[deliverable/linux.git] / drivers / usb / gadget / ci13xxx_udc.h

/*
 * ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Description: MIPS USB IP core family device controller
 *              Structures, registers and logging macros
 */

#ifndef _CI13XXX_h_
#define _CI13XXX_h_

/******************************************************************************
 * DEFINE
 *****************************************************************************/
#define CI13XXX_PAGE_SIZE  4096ul /* page size for TD's */
#define ENDPT_MAX          (32)
#define CTRL_PAYLOAD_MAX   (64)
#define RX        (0)  /* similar to USB_DIR_OUT but can be used as an index */
#define TX        (1)  /* similar to USB_DIR_IN  but can be used as an index */

/******************************************************************************
 * STRUCTURES
 *****************************************************************************/
/* DMA layout of transfer descriptors */
struct ci13xxx_td {
	/* 0 */
	u32 next;
#define TD_TERMINATE          BIT(0)
	/* 1 */
	u32 token;
#define TD_STATUS             (0x00FFUL <<  0)
#define TD_STATUS_TR_ERR      BIT(3)
#define TD_STATUS_DT_ERR      BIT(5)
#define TD_STATUS_HALTED      BIT(6)
#define TD_STATUS_ACTIVE      BIT(7)
#define TD_MULTO              (0x0003UL << 10)
#define TD_IOC                BIT(15)
#define TD_TOTAL_BYTES        (0x7FFFUL << 16)
	/* 2 */
	u32 page[5];
#define TD_CURR_OFFSET        (0x0FFFUL <<  0)
#define TD_FRAME_NUM          (0x07FFUL <<  0)
#define TD_RESERVED_MASK      (0x0FFFUL <<  0)
} __attribute__ ((packed));

/* DMA layout of queue heads */
struct ci13xxx_qh {
	/* 0 */
	u32 cap;
#define QH_IOS                BIT(15)
#define QH_MAX_PKT            (0x07FFUL << 16)
#define QH_ZLT                BIT(29)
#define QH_MULT               (0x0003UL << 30)
	/* 1 */
	u32 curr;
	/* 2 - 8 */
	struct ci13xxx_td        td;
	/* 9 */
	u32 RESERVED;
	struct usb_ctrlrequest   setup;
} __attribute__ ((packed));

/* Extension of usb_request */
struct ci13xxx_req {
	struct usb_request   req;
	unsigned             map;
	struct list_head     queue;
	struct ci13xxx_td   *ptr;
	dma_addr_t           dma;
};

/* Extension of usb_ep */
struct ci13xxx_ep {
	struct usb_ep                          ep;
	const struct usb_endpoint_descriptor  *desc;
	u8                                     dir;
	u8                                     num;
	u8                                     type;
	char                                   name[16];
	struct {
		struct list_head   queue;
		struct ci13xxx_qh *ptr;
		dma_addr_t         dma;
	}                                      qh;
	int                                    wedge;

	/* global resources */
	spinlock_t                            *lock;
	struct device                         *device;
	struct dma_pool                       *td_pool;
};

struct ci13xxx;
struct ci13xxx_udc_driver {
	const char	*name;
	unsigned long	 flags;
#define CI13XXX_REGS_SHARED		BIT(0)
#define CI13XXX_REQUIRE_TRANSCEIVER	BIT(1)
#define CI13XXX_PULLUP_ON_VBUS		BIT(2)
#define CI13XXX_DISABLE_STREAMING	BIT(3)

#define CI13XXX_CONTROLLER_RESET_EVENT		0
#define CI13XXX_CONTROLLER_STOPPED_EVENT	1
	void	(*notify_event) (struct ci13xxx *udc, unsigned event);
};

/* CI13XXX UDC descriptor & global resources */
struct ci13xxx {
	spinlock_t		  *lock;      /* ctrl register bank access */
	void __iomem              *regs;      /* registers address space */

	struct dma_pool           *qh_pool;   /* DMA pool for queue heads */
	struct dma_pool           *td_pool;   /* DMA pool for transfer descs */
	struct usb_request        *status;    /* ep0 status request */

	struct usb_gadget          gadget;     /* USB slave device */
	struct ci13xxx_ep          ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
	u32                        ep0_dir;    /* ep0 direction */
#define ep0out ci13xxx_ep[0]
#define ep0in  ci13xxx_ep[16]

	struct usb_gadget_driver  *driver;     /* 3rd party gadget driver */
	struct ci13xxx_udc_driver *udc_driver; /* device controller driver */
	int                        vbus_active; /* is VBUS active */
	struct otg_transceiver    *transceiver; /* Transceiver struct */
};

/******************************************************************************
 * REGISTERS
 *****************************************************************************/
/* register size */
#define REG_BITS   (32)

/* HCCPARAMS */
#define HCCPARAMS_LEN         BIT(17)

/* DCCPARAMS */
#define DCCPARAMS_DEN         (0x1F << 0)
#define DCCPARAMS_DC          BIT(7)

/* TESTMODE */
#define TESTMODE_FORCE        BIT(0)

/* USBCMD */
#define USBCMD_RS             BIT(0)
#define USBCMD_RST            BIT(1)
#define USBCMD_SUTW           BIT(13)

/* USBSTS & USBINTR */
#define USBi_UI               BIT(0)
#define USBi_UEI              BIT(1)
#define USBi_PCI              BIT(2)
#define USBi_URI              BIT(6)
#define USBi_SLI              BIT(8)

/* DEVICEADDR */
#define DEVICEADDR_USBADRA    BIT(24)
#define DEVICEADDR_USBADR     (0x7FUL << 25)

/* PORTSC */
#define PORTSC_SUSP           BIT(7)
#define PORTSC_HSP            BIT(9)
#define PORTSC_PTC            (0x0FUL << 16)

/* DEVLC */
#define DEVLC_PSPD            (0x03UL << 25)
#define    DEVLC_PSPD_HS      (0x02UL << 25)

/* USBMODE */
#define USBMODE_CM            (0x03UL <<  0)
#define    USBMODE_CM_IDLE    (0x00UL <<  0)
#define    USBMODE_CM_DEVICE  (0x02UL <<  0)
#define    USBMODE_CM_HOST    (0x03UL <<  0)
#define USBMODE_SLOM          BIT(3)
#define USBMODE_SDIS          BIT(4)

/* ENDPTCTRL */
#define ENDPTCTRL_RXS         BIT(0)
#define ENDPTCTRL_RXT         (0x03UL <<  2)
#define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
#define ENDPTCTRL_RXE         BIT(7)
#define ENDPTCTRL_TXS         BIT(16)
#define ENDPTCTRL_TXT         (0x03UL << 18)
#define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
#define ENDPTCTRL_TXE         BIT(23)

/******************************************************************************
 * LOGGING
 *****************************************************************************/
#define ci13xxx_printk(level, format, args...) \
do { \
	if (_udc == NULL) \
		printk(level "[%s] " format "\n", __func__, ## args); \
	else \
		dev_printk(level, _udc->gadget.dev.parent, \
			   "[%s] " format "\n", __func__, ## args); \
} while (0)

#define err(format, args...)    ci13xxx_printk(KERN_ERR, format, ## args)
#define warn(format, args...)   ci13xxx_printk(KERN_WARNING, format, ## args)
#define info(format, args...)   ci13xxx_printk(KERN_INFO, format, ## args)

#ifdef TRACE
#define trace(format, args...)      ci13xxx_printk(KERN_DEBUG, format, ## args)
#define dbg_trace(format, args...)  dev_dbg(dev, format, ##args)
#else
#define trace(format, args...)      do {} while (0)
#define dbg_trace(format, args...)  do {} while (0)
#endif

#endif	/* _CI13XXX_h_ */
Commit	Line	Data
aa69a809 DL	1	/*
	2	* ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* Description: MIPS USB IP core family device controller
	13	* Structures, registers and logging macros
	14	*/
	15
	16	#ifndef _CI13XXX_h_
	17	#define _CI13XXX_h_
	18
	19	/******************************************************************************
	20	* DEFINE
	21	*****************************************************************************/
0a313c4d	22	#define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
ca9cfea0	23	#define ENDPT_MAX (32)
aa69a809 DL	24	#define CTRL_PAYLOAD_MAX (64)
	25	#define RX (0) /* similar to USB_DIR_OUT but can be used as an index */
	26	#define TX (1) /* similar to USB_DIR_IN but can be used as an index */
	27
	28	/******************************************************************************
	29	* STRUCTURES
	30	*****************************************************************************/
	31	/* DMA layout of transfer descriptors */
	32	struct ci13xxx_td {
	33	/* 0 */
	34	u32 next;
	35	#define TD_TERMINATE BIT(0)
	36	/* 1 */
	37	u32 token;
	38	#define TD_STATUS (0x00FFUL << 0)
	39	#define TD_STATUS_TR_ERR BIT(3)
	40	#define TD_STATUS_DT_ERR BIT(5)
	41	#define TD_STATUS_HALTED BIT(6)
	42	#define TD_STATUS_ACTIVE BIT(7)
	43	#define TD_MULTO (0x0003UL << 10)
	44	#define TD_IOC BIT(15)
	45	#define TD_TOTAL_BYTES (0x7FFFUL << 16)
	46	/* 2 */
	47	u32 page[5];
	48	#define TD_CURR_OFFSET (0x0FFFUL << 0)
	49	#define TD_FRAME_NUM (0x07FFUL << 0)
	50	#define TD_RESERVED_MASK (0x0FFFUL << 0)
	51	} __attribute__ ((packed));
	52
	53	/* DMA layout of queue heads */
	54	struct ci13xxx_qh {
	55	/* 0 */
	56	u32 cap;
	57	#define QH_IOS BIT(15)
	58	#define QH_MAX_PKT (0x07FFUL << 16)
	59	#define QH_ZLT BIT(29)
	60	#define QH_MULT (0x0003UL << 30)
	61	/* 1 */
	62	u32 curr;
	63	/* 2 - 8 */
	64	struct ci13xxx_td td;
	65	/* 9 */
	66	u32 RESERVED;
	67	struct usb_ctrlrequest setup;
	68	} __attribute__ ((packed));
	69
	70	/* Extension of usb_request */
	71	struct ci13xxx_req {
	72	struct usb_request req;
	73	unsigned map;
	74	struct list_head queue;
	75	struct ci13xxx_td *ptr;
	76	dma_addr_t dma;
	77	};
	78
	79	/* Extension of usb_ep */
	80	struct ci13xxx_ep {
	81	struct usb_ep ep;
	82	const struct usb_endpoint_descriptor *desc;
	83	u8 dir;
	84	u8 num;
	85	u8 type;
	86	char name[16];
	87	struct {
88	struct list_head queue;
89	struct ci13xxx_qh *ptr;
90	dma_addr_t dma;
ca9cfea0	91	} qh;
aa69a809 DL	92	int wedge;
	93
	94	/* global resources */
	95	spinlock_t *lock;
	96	struct device *device;
	97	struct dma_pool *td_pool;
	98	};
	99
f01ef574 PK	100	struct ci13xxx;
	101	struct ci13xxx_udc_driver {
	102	const char *name;
	103	unsigned long flags;
	104	#define CI13XXX_REGS_SHARED BIT(0)
	105	#define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)
	106	#define CI13XXX_PULLUP_ON_VBUS BIT(2)
	107	#define CI13XXX_DISABLE_STREAMING BIT(3)
	108
	109	#define CI13XXX_CONTROLLER_RESET_EVENT 0
	110	#define CI13XXX_CONTROLLER_STOPPED_EVENT 1
	111	void (notify_event) (struct ci13xxx udc, unsigned event);
	112	};
	113
aa69a809 DL	114	/* CI13XXX UDC descriptor & global resources */
	115	struct ci13xxx {
	116	spinlock_t lock; / ctrl register bank access */
f01ef574	117	void __iomem regs; / registers address space */
aa69a809 DL	118
	119	struct dma_pool qh_pool; / DMA pool for queue heads */
	120	struct dma_pool td_pool; / DMA pool for transfer descs */
ca9cfea0	121	struct usb_request status; / ep0 status request */
aa69a809 DL	122
	123	struct usb_gadget gadget; /* USB slave device */
	124	struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
ca9cfea0 PK	125	u32 ep0_dir; /* ep0 direction */
	126	#define ep0out ci13xxx_ep[0]
	127	#define ep0in ci13xxx_ep[16]
aa69a809 DL	128
aa69a809 DL	129	struct usb_gadget_driver driver; / 3rd party gadget driver */
f01ef574 PK	130	struct ci13xxx_udc_driver udc_driver; / device controller driver */
	131	int vbus_active; /* is VBUS active */
	132	struct otg_transceiver transceiver; / Transceiver struct */
aa69a809 DL	133	};
	134
	135	/******************************************************************************
	136	* REGISTERS
	137	*****************************************************************************/
	138	/* register size */
	139	#define REG_BITS (32)
	140
	141	/* HCCPARAMS */
	142	#define HCCPARAMS_LEN BIT(17)
	143
	144	/* DCCPARAMS */
	145	#define DCCPARAMS_DEN (0x1F << 0)
	146	#define DCCPARAMS_DC BIT(7)
	147
	148	/* TESTMODE */
	149	#define TESTMODE_FORCE BIT(0)
	150
	151	/* USBCMD */
	152	#define USBCMD_RS BIT(0)
	153	#define USBCMD_RST BIT(1)
	154	#define USBCMD_SUTW BIT(13)
	155
	156	/* USBSTS & USBINTR */
	157	#define USBi_UI BIT(0)
	158	#define USBi_UEI BIT(1)
	159	#define USBi_PCI BIT(2)
	160	#define USBi_URI BIT(6)
	161	#define USBi_SLI BIT(8)
	162
	163	/* DEVICEADDR */
	164	#define DEVICEADDR_USBADRA BIT(24)
	165	#define DEVICEADDR_USBADR (0x7FUL << 25)
	166
	167	/* PORTSC */
	168	#define PORTSC_SUSP BIT(7)
	169	#define PORTSC_HSP BIT(9)
	170	#define PORTSC_PTC (0x0FUL << 16)
	171
	172	/* DEVLC */
	173	#define DEVLC_PSPD (0x03UL << 25)
	174	#define DEVLC_PSPD_HS (0x02UL << 25)
	175
	176	/* USBMODE */
	177	#define USBMODE_CM (0x03UL << 0)
	178	#define USBMODE_CM_IDLE (0x00UL << 0)
	179	#define USBMODE_CM_DEVICE (0x02UL << 0)
	180	#define USBMODE_CM_HOST (0x03UL << 0)
	181	#define USBMODE_SLOM BIT(3)
f01ef574	182	#define USBMODE_SDIS BIT(4)
aa69a809 DL	183
	184	/* ENDPTCTRL */
	185	#define ENDPTCTRL_RXS BIT(0)
	186	#define ENDPTCTRL_RXT (0x03UL << 2)
	187	#define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
	188	#define ENDPTCTRL_RXE BIT(7)
	189	#define ENDPTCTRL_TXS BIT(16)
	190	#define ENDPTCTRL_TXT (0x03UL << 18)
	191	#define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
	192	#define ENDPTCTRL_TXE BIT(23)
	193
	194	/******************************************************************************
	195	* LOGGING
	196	*****************************************************************************/
	197	#define ci13xxx_printk(level, format, args...) \
	198	do { \
	199	if (_udc == NULL) \
	200	printk(level "[%s] " format "\n", __func__, ## args); \
	201	else \
	202	dev_printk(level, _udc->gadget.dev.parent, \
	203	"[%s] " format "\n", __func__, ## args); \
	204	} while (0)
	205
	206	#define err(format, args...) ci13xxx_printk(KERN_ERR, format, ## args)
	207	#define warn(format, args...) ci13xxx_printk(KERN_WARNING, format, ## args)
	208	#define info(format, args...) ci13xxx_printk(KERN_INFO, format, ## args)
	209
	210	#ifdef TRACE
	211	#define trace(format, args...) ci13xxx_printk(KERN_DEBUG, format, ## args)
	212	#define dbg_trace(format, args...) dev_dbg(dev, format, ##args)
	213	#else
	214	#define trace(format, args...) do {} while (0)
	215	#define dbg_trace(format, args...) do {} while (0)
	216	#endif
	217
	218	#endif /* _CI13XXX_h_ */