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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/nab/target...
[deliverable/linux.git] / drivers / usb / gadget / fsl_udc_core.c
CommitLineData
b504882d 1/*
58c559e6 2 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
ea437f39 3 * All rights reserved.
b504882d
LY		 4 *
5 * Author: Li Yang <leoli@freescale.com>
6 * Jiang Bo <tanya.jiang@freescale.com>
7 *
8 * Description:
9 * Freescale high-speed USB SOC DR module device controller driver.
2ea6698d 10 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
b504882d
LY		 11 * The driver is previously named as mpc_udc. Based on bare board
12 * code from Dave Liu and Shlomi Gridish.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 */
19
20#undef VERBOSE
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/ioport.h>
25#include <linux/types.h>
26#include <linux/errno.h>
ded017ee 27#include <linux/err.h>
b504882d
LY		 28#include <linux/slab.h>
29#include <linux/init.h>
b504882d
LY		 30#include <linux/list.h>
31#include <linux/interrupt.h>
32#include <linux/proc_fs.h>
33#include <linux/mm.h>
34#include <linux/moduleparam.h>
35#include <linux/device.h>
36#include <linux/usb/ch9.h>
9454a57a 37#include <linux/usb/gadget.h>
b504882d
LY		 38#include <linux/usb/otg.h>
39#include <linux/dma-mapping.h>
40#include <linux/platform_device.h>
41#include <linux/fsl_devices.h>
42#include <linux/dmapool.h>
54e4026b 43#include <linux/delay.h>
f0ea8834 44#include <linux/of_device.h>
b504882d
LY		 45
46#include <asm/byteorder.h>
47#include <asm/io.h>
b504882d
LY		 48#include <asm/unaligned.h>
49#include <asm/dma.h>
b504882d
LY		 50
51#include "fsl_usb2_udc.h"
52
53#define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
54#define DRIVER_AUTHOR "Li Yang/Jiang Bo"
55#define DRIVER_VERSION "Apr 20, 2007"
56
57#define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59static const char driver_name[] = "fsl-usb2-udc";
60static const char driver_desc[] = DRIVER_DESC;
61
7483cff8 62static struct usb_dr_device *dr_regs;
58c559e6 63
7483cff8 64static struct usb_sys_interface *usb_sys_regs;
b504882d
LY		 65
66/* it is initialized in probe() */
67static struct fsl_udc *udc_controller = NULL;
68
69static const struct usb_endpoint_descriptor
70fsl_ep0_desc = {
71 .bLength = USB_DT_ENDPOINT_SIZE,
72 .bDescriptorType = USB_DT_ENDPOINT,
73 .bEndpointAddress = 0,
74 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
75 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
76};
77
b504882d
LY		 78static void fsl_ep_fifo_flush(struct usb_ep *_ep);
79
80#ifdef CONFIG_PPC32
09ba0def
AG		 81/*
82 * On some SoCs, the USB controller registers can be big or little endian,
83 * depending on the version of the chip. In order to be able to run the
84 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
85 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
86 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
87 * call through those pointers. Platform code for SoCs that have BE USB
88 * registers should set pdata->big_endian_mmio flag.
89 *
90 * This also applies to controller-to-cpu accessors for the USB descriptors,
91 * since their endianness is also SoC dependant. Platform code for SoCs that
92 * have BE USB descriptors should set pdata->big_endian_desc flag.
93 */
94static u32 _fsl_readl_be(const unsigned __iomem *p)
95{
96 return in_be32(p);
97}
98
99static u32 _fsl_readl_le(const unsigned __iomem *p)
100{
101 return in_le32(p);
102}
103
104static void _fsl_writel_be(u32 v, unsigned __iomem *p)
105{
106 out_be32(p, v);
107}
108
109static void _fsl_writel_le(u32 v, unsigned __iomem *p)
110{
111 out_le32(p, v);
112}
113
114static u32 (*_fsl_readl)(const unsigned __iomem *p);
115static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
116
117#define fsl_readl(p) (*_fsl_readl)((p))
118#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
119
3140d5b2
AG		 120static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
121{
122 if (pdata->big_endian_mmio) {
123 _fsl_readl = _fsl_readl_be;
124 _fsl_writel = _fsl_writel_be;
125 } else {
126 _fsl_readl = _fsl_readl_le;
127 _fsl_writel = _fsl_writel_le;
128 }
129}
130
09ba0def
AG		 131static inline u32 cpu_to_hc32(const u32 x)
132{
133 return udc_controller->pdata->big_endian_desc
134 ? (__force u32)cpu_to_be32(x)
135 : (__force u32)cpu_to_le32(x);
136}
137
138static inline u32 hc32_to_cpu(const u32 x)
139{
140 return udc_controller->pdata->big_endian_desc
141 ? be32_to_cpu((__force __be32)x)
142 : le32_to_cpu((__force __le32)x);
143}
144#else /* !CONFIG_PPC32 */
3140d5b2
AG		 145static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
146
b504882d 147#define fsl_readl(addr) readl(addr)
c93eebbe 148#define fsl_writel(val32, addr) writel(val32, addr)
09ba0def
AG		 149#define cpu_to_hc32(x) cpu_to_le32(x)
150#define hc32_to_cpu(x) le32_to_cpu(x)
151#endif /* CONFIG_PPC32 */
b504882d
LY		 152
153/********************************************************************
154 * Internal Used Function
155********************************************************************/
156/*-----------------------------------------------------------------
157 * done() - retire a request; caller blocked irqs
158 * @status : request status to be set, only works when
159 * request is still in progress.
160 *--------------------------------------------------------------*/
161static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
162{
163 struct fsl_udc *udc = NULL;
164 unsigned char stopped = ep->stopped;
165 struct ep_td_struct *curr_td, *next_td;
166 int j;
167
168 udc = (struct fsl_udc *)ep->udc;
169 /* Removed the req from fsl_ep->queue */
170 list_del_init(&req->queue);
171
172 /* req.status should be set as -EINPROGRESS in ep_queue() */
173 if (req->req.status == -EINPROGRESS)
174 req->req.status = status;
175 else
176 status = req->req.status;
177
178 /* Free dtd for the request */
179 next_td = req->head;
180 for (j = 0; j < req->dtd_count; j++) {
181 curr_td = next_td;
182 if (j != req->dtd_count - 1) {
183 next_td = curr_td->next_td_virt;
184 }
185 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
186 }
187
188 if (req->mapped) {
189 dma_unmap_single(ep->udc->gadget.dev.parent,
190 req->req.dma, req->req.length,
191 ep_is_in(ep)
192 ? DMA_TO_DEVICE
193 : DMA_FROM_DEVICE);
194 req->req.dma = DMA_ADDR_INVALID;
195 req->mapped = 0;
196 } else
197 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
198 req->req.dma, req->req.length,
199 ep_is_in(ep)
200 ? DMA_TO_DEVICE
201 : DMA_FROM_DEVICE);
202
203 if (status && (status != -ESHUTDOWN))
204 VDBG("complete %s req %p stat %d len %u/%u",
205 ep->ep.name, &req->req, status,
206 req->req.actual, req->req.length);
207
208 ep->stopped = 1;
209
210 spin_unlock(&ep->udc->lock);
211 /* complete() is from gadget layer,
212 * eg fsg->bulk_in_complete() */
213 if (req->req.complete)
214 req->req.complete(&ep->ep, &req->req);
215
216 spin_lock(&ep->udc->lock);
217 ep->stopped = stopped;
218}
219
220/*-----------------------------------------------------------------
221 * nuke(): delete all requests related to this ep
222 * called with spinlock held
223 *--------------------------------------------------------------*/
224static void nuke(struct fsl_ep *ep, int status)
225{
226 ep->stopped = 1;
227
228 /* Flush fifo */
229 fsl_ep_fifo_flush(&ep->ep);
230
231 /* Whether this eq has request linked */
232 while (!list_empty(&ep->queue)) {
233 struct fsl_req *req = NULL;
234
235 req = list_entry(ep->queue.next, struct fsl_req, queue);
236 done(ep, req, status);
237 }
238}
239
240/*------------------------------------------------------------------
241 Internal Hardware related function
242 ------------------------------------------------------------------*/
243
244static int dr_controller_setup(struct fsl_udc *udc)
245{
ea437f39
RM		 246 unsigned int tmp, portctrl, ep_num;
247 unsigned int max_no_of_ep;
54e4026b 248 unsigned int ctrl;
b504882d 249 unsigned long timeout;
58c559e6 250
b504882d
LY		 251#define FSL_UDC_RESET_TIMEOUT 1000
252
54e4026b
GL		 253 /* Config PHY interface */
254 portctrl = fsl_readl(&dr_regs->portsc1);
255 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
256 switch (udc->phy_mode) {
257 case FSL_USB2_PHY_ULPI:
58c559e6
RM		 258 if (udc->pdata->have_sysif_regs) {
259 if (udc->pdata->controller_ver) {
260 /* controller version 1.6 or above */
261 ctrl = __raw_readl(&usb_sys_regs->control);
262 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
263 ctrl |= USB_CTRL_USB_EN;
264 __raw_writel(ctrl, &usb_sys_regs->control);
265 }
266 }
54e4026b
GL		 267 portctrl |= PORTSCX_PTS_ULPI;
268 break;
269 case FSL_USB2_PHY_UTMI_WIDE:
270 portctrl |= PORTSCX_PTW_16BIT;
271 /* fall through */
272 case FSL_USB2_PHY_UTMI:
58c559e6
RM		 273 if (udc->pdata->have_sysif_regs) {
274 if (udc->pdata->controller_ver) {
275 /* controller version 1.6 or above */
276 ctrl = __raw_readl(&usb_sys_regs->control);
277 ctrl |= (USB_CTRL_UTMI_PHY_EN |
278 USB_CTRL_USB_EN);
279 __raw_writel(ctrl, &usb_sys_regs->control);
280 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
281 PHY CLK to become stable - 10ms*/
282 }
283 }
54e4026b
GL		 284 portctrl |= PORTSCX_PTS_UTMI;
285 break;
286 case FSL_USB2_PHY_SERIAL:
287 portctrl |= PORTSCX_PTS_FSLS;
288 break;
289 default:
290 return -EINVAL;
291 }
292 fsl_writel(portctrl, &dr_regs->portsc1);
293
b504882d
LY		 294 /* Stop and reset the usb controller */
295 tmp = fsl_readl(&dr_regs->usbcmd);
296 tmp &= ~USB_CMD_RUN_STOP;
297 fsl_writel(tmp, &dr_regs->usbcmd);
298
299 tmp = fsl_readl(&dr_regs->usbcmd);
300 tmp |= USB_CMD_CTRL_RESET;
301 fsl_writel(tmp, &dr_regs->usbcmd);
302
303 /* Wait for reset to complete */
304 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
305 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
306 if (time_after(jiffies, timeout)) {
bf7409a2 307 ERR("udc reset timeout!\n");
b504882d
LY		 308 return -ETIMEDOUT;
309 }
310 cpu_relax();
311 }
312
313 /* Set the controller as device mode */
314 tmp = fsl_readl(&dr_regs->usbmode);
2ea6698d 315 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
b504882d
LY		 316 tmp |= USB_MODE_CTRL_MODE_DEVICE;
317 /* Disable Setup Lockout */
318 tmp |= USB_MODE_SETUP_LOCK_OFF;
2ea6698d
AG		 319 if (udc->pdata->es)
320 tmp |= USB_MODE_ES;
b504882d
LY		 321 fsl_writel(tmp, &dr_regs->usbmode);
322
323 /* Clear the setup status */
324 fsl_writel(0, &dr_regs->usbsts);
325
326 tmp = udc->ep_qh_dma;
327 tmp &= USB_EP_LIST_ADDRESS_MASK;
328 fsl_writel(tmp, &dr_regs->endpointlistaddr);
329
330 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
6ef65a7f 331 udc->ep_qh, (int)tmp,
b504882d
LY		 332 fsl_readl(&dr_regs->endpointlistaddr));
333
ea437f39
RM		 334 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
335 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
336 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
337 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
338 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
339 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
340 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
341 }
b504882d 342 /* Config control enable i/o output, cpu endian register */
54e4026b 343#ifndef CONFIG_ARCH_MXC
2ea6698d
AG		 344 if (udc->pdata->have_sysif_regs) {
345 ctrl = __raw_readl(&usb_sys_regs->control);
346 ctrl |= USB_CTRL_IOENB;
347 __raw_writel(ctrl, &usb_sys_regs->control);
348 }
54e4026b 349#endif
b504882d
LY		 350
351#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
352 /* Turn on cache snooping hardware, since some PowerPC platforms
353 * wholly rely on hardware to deal with cache coherent. */
354
2ea6698d
AG		 355 if (udc->pdata->have_sysif_regs) {
356 /* Setup Snooping for all the 4GB space */
357 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
358 __raw_writel(tmp, &usb_sys_regs->snoop1);
359 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
360 __raw_writel(tmp, &usb_sys_regs->snoop2);
361 }
b504882d
LY		 362#endif
363
364 return 0;
365}
366
367/* Enable DR irq and set controller to run state */
368static void dr_controller_run(struct fsl_udc *udc)
369{
370 u32 temp;
371
372 /* Enable DR irq reg */
373 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
374 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
375 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
376
377 fsl_writel(temp, &dr_regs->usbintr);
378
379 /* Clear stopped bit */
380 udc->stopped = 0;
381
382 /* Set the controller as device mode */
383 temp = fsl_readl(&dr_regs->usbmode);
384 temp |= USB_MODE_CTRL_MODE_DEVICE;
385 fsl_writel(temp, &dr_regs->usbmode);
386
387 /* Set controller to Run */
388 temp = fsl_readl(&dr_regs->usbcmd);
389 temp |= USB_CMD_RUN_STOP;
390 fsl_writel(temp, &dr_regs->usbcmd);
b504882d
LY		 391}
392
393static void dr_controller_stop(struct fsl_udc *udc)
394{
395 unsigned int tmp;
396
83722bc9
AG		 397 pr_debug("%s\n", __func__);
398
399 /* if we're in OTG mode, and the Host is currently using the port,
400 * stop now and don't rip the controller out from under the
401 * ehci driver
402 */
403 if (udc->gadget.is_otg) {
404 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
405 pr_debug("udc: Leaving early\n");
406 return;
407 }
408 }
409
b504882d
LY		 410 /* disable all INTR */
411 fsl_writel(0, &dr_regs->usbintr);
412
413 /* Set stopped bit for isr */
414 udc->stopped = 1;
415
416 /* disable IO output */
417/* usb_sys_regs->control = 0; */
418
419 /* set controller to Stop */
420 tmp = fsl_readl(&dr_regs->usbcmd);
421 tmp &= ~USB_CMD_RUN_STOP;
422 fsl_writel(tmp, &dr_regs->usbcmd);
b504882d
LY		 423}
424
9c94155e
WN		 425static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
426 unsigned char ep_type)
b504882d
LY		 427{
428 unsigned int tmp_epctrl = 0;
429
430 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
431 if (dir) {
432 if (ep_num)
433 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
434 tmp_epctrl |= EPCTRL_TX_ENABLE;
ea437f39 435 tmp_epctrl &= ~EPCTRL_TX_TYPE;
b504882d
LY		 436 tmp_epctrl |= ((unsigned int)(ep_type)
437 << EPCTRL_TX_EP_TYPE_SHIFT);
438 } else {
439 if (ep_num)
440 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
441 tmp_epctrl |= EPCTRL_RX_ENABLE;
ea437f39 442 tmp_epctrl &= ~EPCTRL_RX_TYPE;
b504882d
LY		 443 tmp_epctrl |= ((unsigned int)(ep_type)
444 << EPCTRL_RX_EP_TYPE_SHIFT);
445 }
446
447 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
448}
449
450static void
451dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
452{
453 u32 tmp_epctrl = 0;
454
455 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
456
457 if (value) {
458 /* set the stall bit */
459 if (dir)
460 tmp_epctrl |= EPCTRL_TX_EP_STALL;
461 else
462 tmp_epctrl |= EPCTRL_RX_EP_STALL;
463 } else {
464 /* clear the stall bit and reset data toggle */
465 if (dir) {
466 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
467 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
468 } else {
469 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
470 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
471 }
472 }
473 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
474}
475
476/* Get stall status of a specific ep
477 Return: 0: not stalled; 1:stalled */
478static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
479{
480 u32 epctrl;
481
482 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
483 if (dir)
484 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
485 else
486 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
487}
488
489/********************************************************************
490 Internal Structure Build up functions
491********************************************************************/
492
493/*------------------------------------------------------------------
494* struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
495 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
496 * @mult: Mult field
497 ------------------------------------------------------------------*/
498static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
499 unsigned char dir, unsigned char ep_type,
500 unsigned int max_pkt_len,
501 unsigned int zlt, unsigned char mult)
502{
503 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
504 unsigned int tmp = 0;
505
506 /* set the Endpoint Capabilites in QH */
507 switch (ep_type) {
508 case USB_ENDPOINT_XFER_CONTROL:
509 /* Interrupt On Setup (IOS). for control ep */
510 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
511 | EP_QUEUE_HEAD_IOS;
512 break;
513 case USB_ENDPOINT_XFER_ISOC:
514 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
515 | (mult << EP_QUEUE_HEAD_MULT_POS);
516 break;
517 case USB_ENDPOINT_XFER_BULK:
518 case USB_ENDPOINT_XFER_INT:
519 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
520 break;
521 default:
522 VDBG("error ep type is %d", ep_type);
523 return;
524 }
525 if (zlt)
526 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
9a6e184c 527
09ba0def 528 p_QH->max_pkt_length = cpu_to_hc32(tmp);
9a6e184c
LY		 529 p_QH->next_dtd_ptr = 1;
530 p_QH->size_ioc_int_sts = 0;
b504882d
LY		 531}
532
533/* Setup qh structure and ep register for ep0. */
534static void ep0_setup(struct fsl_udc *udc)
535{
536 /* the intialization of an ep includes: fields in QH, Regs,
537 * fsl_ep struct */
538 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
539 USB_MAX_CTRL_PAYLOAD, 0, 0);
540 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
541 USB_MAX_CTRL_PAYLOAD, 0, 0);
542 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
543 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
544
545 return;
546
547}
548
549/***********************************************************************
550 Endpoint Management Functions
551***********************************************************************/
552
553/*-------------------------------------------------------------------------
554 * when configurations are set, or when interface settings change
555 * for example the do_set_interface() in gadget layer,
556 * the driver will enable or disable the relevant endpoints
557 * ep0 doesn't use this routine. It is always enabled.
558-------------------------------------------------------------------------*/
559static int fsl_ep_enable(struct usb_ep *_ep,
560 const struct usb_endpoint_descriptor *desc)
561{
562 struct fsl_udc *udc = NULL;
563 struct fsl_ep *ep = NULL;
564 unsigned short max = 0;
565 unsigned char mult = 0, zlt;
566 int retval = -EINVAL;
567 unsigned long flags = 0;
568
569 ep = container_of(_ep, struct fsl_ep, ep);
570
571 /* catch various bogus parameters */
1fa75972 572 if (!_ep || !desc
b504882d
LY		 573 || (desc->bDescriptorType != USB_DT_ENDPOINT))
574 return -EINVAL;
575
576 udc = ep->udc;
577
578 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
579 return -ESHUTDOWN;
580
29cc8897 581 max = usb_endpoint_maxp(desc);
b504882d 582
25985edc 583 /* Disable automatic zlp generation. Driver is responsible to indicate
b504882d
LY		 584 * explicitly through req->req.zero. This is needed to enable multi-td
585 * request. */
586 zlt = 1;
587
588 /* Assume the max packet size from gadget is always correct */
589 switch (desc->bmAttributes & 0x03) {
590 case USB_ENDPOINT_XFER_CONTROL:
591 case USB_ENDPOINT_XFER_BULK:
592 case USB_ENDPOINT_XFER_INT:
593 /* mult = 0. Execute N Transactions as demonstrated by
594 * the USB variable length packet protocol where N is
595 * computed using the Maximum Packet Length (dQH) and
596 * the Total Bytes field (dTD) */
597 mult = 0;
598 break;
599 case USB_ENDPOINT_XFER_ISOC:
600 /* Calculate transactions needed for high bandwidth iso */
601 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
88e3b59b 602 max = max & 0x7ff; /* bit 0~10 */
b504882d
LY		 603 /* 3 transactions at most */
604 if (mult > 3)
605 goto en_done;
606 break;
607 default:
608 goto en_done;
609 }
610
611 spin_lock_irqsave(&udc->lock, flags);
612 ep->ep.maxpacket = max;
79149b8b 613 ep->ep.desc = desc;
b504882d
LY		 614 ep->stopped = 0;
615
616 /* Controller related setup */
617 /* Init EPx Queue Head (Ep Capabilites field in QH
618 * according to max, zlt, mult) */
619 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
620 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
621 ? USB_SEND : USB_RECV),
622 (unsigned char) (desc->bmAttributes
623 & USB_ENDPOINT_XFERTYPE_MASK),
624 max, zlt, mult);
625
626 /* Init endpoint ctrl register */
627 dr_ep_setup((unsigned char) ep_index(ep),
628 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
629 ? USB_SEND : USB_RECV),
630 (unsigned char) (desc->bmAttributes
631 & USB_ENDPOINT_XFERTYPE_MASK));
632
633 spin_unlock_irqrestore(&udc->lock, flags);
634 retval = 0;
635
636 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
79149b8b 637 ep->ep.desc->bEndpointAddress & 0x0f,
b504882d
LY		 638 (desc->bEndpointAddress & USB_DIR_IN)
639 ? "in" : "out", max);
640en_done:
641 return retval;
642}
643
644/*---------------------------------------------------------------------
645 * @ep : the ep being unconfigured. May not be ep0
646 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
647*---------------------------------------------------------------------*/
648static int fsl_ep_disable(struct usb_ep *_ep)
649{
650 struct fsl_udc *udc = NULL;
651 struct fsl_ep *ep = NULL;
652 unsigned long flags = 0;
653 u32 epctrl;
654 int ep_num;
655
656 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 657 if (!_ep || !ep->ep.desc) {
b504882d
LY		 658 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
659 return -EINVAL;
660 }
661
662 /* disable ep on controller */
663 ep_num = ep_index(ep);
664 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
ea437f39
RM		 665 if (ep_is_in(ep)) {
666 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
667 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
668 } else {
669 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
670 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
671 }
b504882d
LY		 672 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
673
674 udc = (struct fsl_udc *)ep->udc;
675 spin_lock_irqsave(&udc->lock, flags);
676
677 /* nuke all pending requests (does flush) */
678 nuke(ep, -ESHUTDOWN);
679
f9c56cdd 680 ep->ep.desc = NULL;
b504882d
LY		 681 ep->stopped = 1;
682 spin_unlock_irqrestore(&udc->lock, flags);
683
684 VDBG("disabled %s OK", _ep->name);
685 return 0;
686}
687
688/*---------------------------------------------------------------------
689 * allocate a request object used by this endpoint
690 * the main operation is to insert the req->queue to the eq->queue
691 * Returns the request, or null if one could not be allocated
692*---------------------------------------------------------------------*/
693static struct usb_request *
694fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
695{
696 struct fsl_req *req = NULL;
697
698 req = kzalloc(sizeof *req, gfp_flags);
699 if (!req)
700 return NULL;
701
702 req->req.dma = DMA_ADDR_INVALID;
703 INIT_LIST_HEAD(&req->queue);
704
705 return &req->req;
706}
707
708static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
709{
710 struct fsl_req *req = NULL;
711
712 req = container_of(_req, struct fsl_req, req);
713
714 if (_req)
715 kfree(req);
716}
717
6414e94c
LY		 718/* Actually add a dTD chain to an empty dQH and let go */
719static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
720{
721 struct ep_queue_head *qh = get_qh_by_ep(ep);
722
723 /* Write dQH next pointer and terminate bit to 0 */
724 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
725 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
726
727 /* Clear active and halt bit */
728 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
729 | EP_QUEUE_HEAD_STATUS_HALT));
730
731 /* Ensure that updates to the QH will occur before priming. */
732 wmb();
733
734 /* Prime endpoint by writing correct bit to ENDPTPRIME */
735 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
736 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
737}
738
739/* Add dTD chain to the dQH of an EP */
224b5039 740static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
b504882d 741{
b504882d 742 u32 temp, bitmask, tmp_stat;
b504882d
LY		 743
744 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
745 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
746
747 bitmask = ep_is_in(ep)
748 ? (1 << (ep_index(ep) + 16))
749 : (1 << (ep_index(ep)));
750
751 /* check if the pipe is empty */
f79a60b8 752 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
b504882d
LY		 753 /* Add td to the end */
754 struct fsl_req *lastreq;
755 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
756 lastreq->tail->next_td_ptr =
09ba0def 757 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
4d0947de
PC		 758 /* Ensure dTD's next dtd pointer to be updated */
759 wmb();
b504882d
LY		 760 /* Read prime bit, if 1 goto done */
761 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
6414e94c 762 return;
b504882d
LY		 763
764 do {
765 /* Set ATDTW bit in USBCMD */
766 temp = fsl_readl(&dr_regs->usbcmd);
767 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
768
769 /* Read correct status bit */
770 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
771
772 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
773
774 /* Write ATDTW bit to 0 */
775 temp = fsl_readl(&dr_regs->usbcmd);
776 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
777
778 if (tmp_stat)
6414e94c 779 return;
b504882d
LY		 780 }
781
6414e94c 782 fsl_prime_ep(ep, req->head);
b504882d
LY		 783}
784
785/* Fill in the dTD structure
786 * @req: request that the transfer belongs to
787 * @length: return actually data length of the dTD
788 * @dma: return dma address of the dTD
789 * @is_last: return flag if it is the last dTD of the request
790 * return: pointer to the built dTD */
791static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
c5cc5ed8 792 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
b504882d
LY		 793{
794 u32 swap_temp;
795 struct ep_td_struct *dtd;
796
797 /* how big will this transfer be? */
798 *length = min(req->req.length - req->req.actual,
799 (unsigned)EP_MAX_LENGTH_TRANSFER);
800
c5cc5ed8 801 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
b504882d
LY		 802 if (dtd == NULL)
803 return dtd;
804
805 dtd->td_dma = *dma;
806 /* Clear reserved field */
09ba0def 807 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
b504882d 808 swap_temp &= ~DTD_RESERVED_FIELDS;
09ba0def 809 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
b504882d
LY		 810
811 /* Init all of buffer page pointers */
812 swap_temp = (u32) (req->req.dma + req->req.actual);
09ba0def
AG		 813 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
814 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
815 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
816 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
817 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
b504882d
LY		 818
819 req->req.actual += *length;
820
821 /* zlp is needed if req->req.zero is set */
822 if (req->req.zero) {
823 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
824 *is_last = 1;
825 else
826 *is_last = 0;
827 } else if (req->req.length == req->req.actual)
828 *is_last = 1;
829 else
830 *is_last = 0;
831
832 if ((*is_last) == 0)
bf7409a2 833 VDBG("multi-dtd request!");
b504882d
LY		 834 /* Fill in the transfer size; set active bit */
835 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
836
837 /* Enable interrupt for the last dtd of a request */
838 if (*is_last && !req->req.no_interrupt)
839 swap_temp |= DTD_IOC;
840
09ba0def 841 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
b504882d
LY		 842
843 mb();
844
845 VDBG("length = %d address= 0x%x", *length, (int)*dma);
846
847 return dtd;
848}
849
850/* Generate dtd chain for a request */
c5cc5ed8 851static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
b504882d
LY		 852{
853 unsigned count;
854 int is_last;
855 int is_first =1;
856 struct ep_td_struct *last_dtd = NULL, *dtd;
857 dma_addr_t dma;
858
859 do {
c5cc5ed8 860 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
b504882d
LY		 861 if (dtd == NULL)
862 return -ENOMEM;
863
864 if (is_first) {
865 is_first = 0;
866 req->head = dtd;
867 } else {
09ba0def 868 last_dtd->next_td_ptr = cpu_to_hc32(dma);
b504882d
LY		 869 last_dtd->next_td_virt = dtd;
870 }
871 last_dtd = dtd;
872
873 req->dtd_count++;
874 } while (!is_last);
875
09ba0def 876 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
b504882d
LY		 877
878 req->tail = dtd;
879
880 return 0;
881}
882
883/* queues (submits) an I/O request to an endpoint */
884static int
885fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
886{
887 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
888 struct fsl_req *req = container_of(_req, struct fsl_req, req);
889 struct fsl_udc *udc;
890 unsigned long flags;
b504882d
LY		 891
892 /* catch various bogus parameters */
893 if (!_req || !req->req.complete || !req->req.buf
894 || !list_empty(&req->queue)) {
bf7409a2 895 VDBG("%s, bad params", __func__);
b504882d
LY		 896 return -EINVAL;
897 }
79149b8b 898 if (unlikely(!_ep || !ep->ep.desc)) {
bf7409a2 899 VDBG("%s, bad ep", __func__);
b504882d
LY		 900 return -EINVAL;
901 }
79149b8b 902 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
b504882d
LY		 903 if (req->req.length > ep->ep.maxpacket)
904 return -EMSGSIZE;
b504882d
LY		 905 }
906
907 udc = ep->udc;
908 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
909 return -ESHUTDOWN;
910
911 req->ep = ep;
912
913 /* map virtual address to hardware */
914 if (req->req.dma == DMA_ADDR_INVALID) {
915 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
916 req->req.buf,
917 req->req.length, ep_is_in(ep)
918 ? DMA_TO_DEVICE
919 : DMA_FROM_DEVICE);
920 req->mapped = 1;
921 } else {
922 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
923 req->req.dma, req->req.length,
924 ep_is_in(ep)
925 ? DMA_TO_DEVICE
926 : DMA_FROM_DEVICE);
927 req->mapped = 0;
928 }
929
930 req->req.status = -EINPROGRESS;
931 req->req.actual = 0;
932 req->dtd_count = 0;
933
b504882d 934 /* build dtds and push them to device queue */
c5cc5ed8
PC		 935 if (!fsl_req_to_dtd(req, gfp_flags)) {
936 spin_lock_irqsave(&udc->lock, flags);
b504882d
LY		 937 fsl_queue_td(ep, req);
938 } else {
b504882d
LY		 939 return -ENOMEM;
940 }
941
b504882d
LY		 942 /* irq handler advances the queue */
943 if (req != NULL)
944 list_add_tail(&req->queue, &ep->queue);
945 spin_unlock_irqrestore(&udc->lock, flags);
946
947 return 0;
948}
949
950/* dequeues (cancels, unlinks) an I/O request from an endpoint */
951static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
952{
953 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
954 struct fsl_req *req;
955 unsigned long flags;
956 int ep_num, stopped, ret = 0;
957 u32 epctrl;
958
959 if (!_ep || !_req)
960 return -EINVAL;
961
962 spin_lock_irqsave(&ep->udc->lock, flags);
963 stopped = ep->stopped;
964
965 /* Stop the ep before we deal with the queue */
966 ep->stopped = 1;
967 ep_num = ep_index(ep);
968 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
969 if (ep_is_in(ep))
970 epctrl &= ~EPCTRL_TX_ENABLE;
971 else
972 epctrl &= ~EPCTRL_RX_ENABLE;
973 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
974
975 /* make sure it's actually queued on this endpoint */
976 list_for_each_entry(req, &ep->queue, queue) {
977 if (&req->req == _req)
978 break;
979 }
980 if (&req->req != _req) {
981 ret = -EINVAL;
982 goto out;
983 }
984
985 /* The request is in progress, or completed but not dequeued */
986 if (ep->queue.next == &req->queue) {
987 _req->status = -ECONNRESET;
988 fsl_ep_fifo_flush(_ep); /* flush current transfer */
989
990 /* The request isn't the last request in this ep queue */
991 if (req->queue.next != &ep->queue) {
b504882d
LY		 992 struct fsl_req *next_req;
993
b504882d
LY		 994 next_req = list_entry(req->queue.next, struct fsl_req,
995 queue);
996
6414e94c
LY		 997 /* prime with dTD of next request */
998 fsl_prime_ep(ep, next_req->head);
b504882d 999 }
6414e94c 1000 /* The request hasn't been processed, patch up the TD chain */
b504882d
LY		 1001 } else {
1002 struct fsl_req *prev_req;
1003
1004 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
6414e94c 1005 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
b504882d
LY		 1006 }
1007
1008 done(ep, req, -ECONNRESET);
1009
1010 /* Enable EP */
1011out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1012 if (ep_is_in(ep))
1013 epctrl |= EPCTRL_TX_ENABLE;
1014 else
1015 epctrl |= EPCTRL_RX_ENABLE;
1016 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1017 ep->stopped = stopped;
1018
1019 spin_unlock_irqrestore(&ep->udc->lock, flags);
1020 return ret;
1021}
1022
1023/*-------------------------------------------------------------------------*/
1024
1025/*-----------------------------------------------------------------
1026 * modify the endpoint halt feature
1027 * @ep: the non-isochronous endpoint being stalled
1028 * @value: 1--set halt 0--clear halt
1029 * Returns zero, or a negative error code.
1030*----------------------------------------------------------------*/
1031static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1032{
1033 struct fsl_ep *ep = NULL;
1034 unsigned long flags = 0;
1035 int status = -EOPNOTSUPP; /* operation not supported */
1036 unsigned char ep_dir = 0, ep_num = 0;
1037 struct fsl_udc *udc = NULL;
1038
1039 ep = container_of(_ep, struct fsl_ep, ep);
1040 udc = ep->udc;
79149b8b 1041 if (!_ep || !ep->ep.desc) {
b504882d
LY		 1042 status = -EINVAL;
1043 goto out;
1044 }
1045
79149b8b 1046 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
b504882d
LY		 1047 status = -EOPNOTSUPP;
1048 goto out;
1049 }
1050
1051 /* Attempt to halt IN ep will fail if any transfer requests
1052 * are still queue */
1053 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1054 status = -EAGAIN;
1055 goto out;
1056 }
1057
1058 status = 0;
1059 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1060 ep_num = (unsigned char)(ep_index(ep));
1061 spin_lock_irqsave(&ep->udc->lock, flags);
1062 dr_ep_change_stall(ep_num, ep_dir, value);
1063 spin_unlock_irqrestore(&ep->udc->lock, flags);
1064
1065 if (ep_index(ep) == 0) {
1066 udc->ep0_state = WAIT_FOR_SETUP;
1067 udc->ep0_dir = 0;
1068 }
1069out:
1070 VDBG(" %s %s halt stat %d", ep->ep.name,
1071 value ? "set" : "clear", status);
1072
1073 return status;
1074}
1075
2ea6698d
AG		 1076static int fsl_ep_fifo_status(struct usb_ep *_ep)
1077{
1078 struct fsl_ep *ep;
1079 struct fsl_udc *udc;
1080 int size = 0;
1081 u32 bitmask;
6414e94c 1082 struct ep_queue_head *qh;
2ea6698d
AG		 1083
1084 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 1085 if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
2ea6698d
AG		 1086 return -ENODEV;
1087
1088 udc = (struct fsl_udc *)ep->udc;
1089
1090 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1091 return -ESHUTDOWN;
1092
6414e94c 1093 qh = get_qh_by_ep(ep);
2ea6698d
AG		 1094
1095 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1096 (1 << (ep_index(ep)));
1097
1098 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
6414e94c 1099 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
2ea6698d
AG		 1100 >> DTD_LENGTH_BIT_POS;
1101
1102 pr_debug("%s %u\n", __func__, size);
1103 return size;
1104}
1105
b504882d
LY		 1106static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1107{
1108 struct fsl_ep *ep;
1109 int ep_num, ep_dir;
1110 u32 bits;
1111 unsigned long timeout;
1112#define FSL_UDC_FLUSH_TIMEOUT 1000
1113
1114 if (!_ep) {
1115 return;
1116 } else {
1117 ep = container_of(_ep, struct fsl_ep, ep);
79149b8b 1118 if (!ep->ep.desc)
b504882d
LY		 1119 return;
1120 }
1121 ep_num = ep_index(ep);
1122 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1123
1124 if (ep_num == 0)
1125 bits = (1 << 16) | 1;
1126 else if (ep_dir == USB_SEND)
1127 bits = 1 << (16 + ep_num);
1128 else
1129 bits = 1 << ep_num;
1130
1131 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1132 do {
1133 fsl_writel(bits, &dr_regs->endptflush);
1134
1135 /* Wait until flush complete */
1136 while (fsl_readl(&dr_regs->endptflush)) {
1137 if (time_after(jiffies, timeout)) {
1138 ERR("ep flush timeout\n");
1139 return;
1140 }
1141 cpu_relax();
1142 }
1143 /* See if we need to flush again */
1144 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1145}
1146
1147static struct usb_ep_ops fsl_ep_ops = {
1148 .enable = fsl_ep_enable,
1149 .disable = fsl_ep_disable,
1150
1151 .alloc_request = fsl_alloc_request,
1152 .free_request = fsl_free_request,
1153
b504882d
LY		 1154 .queue = fsl_ep_queue,
1155 .dequeue = fsl_ep_dequeue,
1156
1157 .set_halt = fsl_ep_set_halt,
2ea6698d 1158 .fifo_status = fsl_ep_fifo_status,
b504882d
LY		 1159 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1160};
1161
1162/*-------------------------------------------------------------------------
1163 Gadget Driver Layer Operations
1164-------------------------------------------------------------------------*/
1165
1166/*----------------------------------------------------------------------
1167 * Get the current frame number (from DR frame_index Reg )
1168 *----------------------------------------------------------------------*/
1169static int fsl_get_frame(struct usb_gadget *gadget)
1170{
1171 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1172}
1173
1174/*-----------------------------------------------------------------------
1175 * Tries to wake up the host connected to this gadget
1176 -----------------------------------------------------------------------*/
1177static int fsl_wakeup(struct usb_gadget *gadget)
1178{
1179 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1180 u32 portsc;
1181
1182 /* Remote wakeup feature not enabled by host */
1183 if (!udc->remote_wakeup)
1184 return -ENOTSUPP;
1185
1186 portsc = fsl_readl(&dr_regs->portsc1);
1187 /* not suspended? */
1188 if (!(portsc & PORTSCX_PORT_SUSPEND))
1189 return 0;
1190 /* trigger force resume */
1191 portsc |= PORTSCX_PORT_FORCE_RESUME;
1192 fsl_writel(portsc, &dr_regs->portsc1);
1193 return 0;
1194}
1195
1196static int can_pullup(struct fsl_udc *udc)
1197{
1198 return udc->driver && udc->softconnect && udc->vbus_active;
1199}
1200
1201/* Notify controller that VBUS is powered, Called by whatever
1202 detects VBUS sessions */
1203static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1204{
1205 struct fsl_udc *udc;
1206 unsigned long flags;
1207
1208 udc = container_of(gadget, struct fsl_udc, gadget);
1209 spin_lock_irqsave(&udc->lock, flags);
bf7409a2 1210 VDBG("VBUS %s", is_active ? "on" : "off");
b504882d
LY		 1211 udc->vbus_active = (is_active != 0);
1212 if (can_pullup(udc))
1213 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1214 &dr_regs->usbcmd);
1215 else
1216 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1217 &dr_regs->usbcmd);
1218 spin_unlock_irqrestore(&udc->lock, flags);
1219 return 0;
1220}
1221
1222/* constrain controller's VBUS power usage
1223 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1224 * reporting how much power the device may consume. For example, this
1225 * could affect how quickly batteries are recharged.
1226 *
1227 * Returns zero on success, else negative errno.
1228 */
1229static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1230{
b504882d
LY		 1231 struct fsl_udc *udc;
1232
1233 udc = container_of(gadget, struct fsl_udc, gadget);
ded017ee 1234 if (!IS_ERR_OR_NULL(udc->transceiver))
b96d3b08 1235 return usb_phy_set_power(udc->transceiver, mA);
b504882d
LY		 1236 return -ENOTSUPP;
1237}
1238
1239/* Change Data+ pullup status
1240 * this func is used by usb_gadget_connect/disconnet
1241 */
1242static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1243{
1244 struct fsl_udc *udc;
1245
1246 udc = container_of(gadget, struct fsl_udc, gadget);
1247 udc->softconnect = (is_on != 0);
1248 if (can_pullup(udc))
1249 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1250 &dr_regs->usbcmd);
1251 else
1252 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1253 &dr_regs->usbcmd);
1254
1255 return 0;
1256}
1257
eb65796e
FB		 1258static int fsl_udc_start(struct usb_gadget *g,
1259 struct usb_gadget_driver *driver);
1260static int fsl_udc_stop(struct usb_gadget *g,
1261 struct usb_gadget_driver *driver);
9454a57a 1262/* defined in gadget.h */
eeef4587 1263static const struct usb_gadget_ops fsl_gadget_ops = {
b504882d
LY		 1264 .get_frame = fsl_get_frame,
1265 .wakeup = fsl_wakeup,
1266/* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1267 .vbus_session = fsl_vbus_session,
1268 .vbus_draw = fsl_vbus_draw,
1269 .pullup = fsl_pullup,
eb65796e
FB		 1270 .udc_start = fsl_udc_start,
1271 .udc_stop = fsl_udc_stop,
b504882d
LY		 1272};
1273
1274/* Set protocol stall on ep0, protocol stall will automatically be cleared
1275 on new transaction */
1276static void ep0stall(struct fsl_udc *udc)
1277{
1278 u32 tmp;
1279
1280 /* must set tx and rx to stall at the same time */
1281 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1282 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1283 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1284 udc->ep0_state = WAIT_FOR_SETUP;
1285 udc->ep0_dir = 0;
1286}
1287
1288/* Prime a status phase for ep0 */
1289static int ep0_prime_status(struct fsl_udc *udc, int direction)
1290{
1291 struct fsl_req *req = udc->status_req;
1292 struct fsl_ep *ep;
b504882d
LY		 1293
1294 if (direction == EP_DIR_IN)
1295 udc->ep0_dir = USB_DIR_IN;
1296 else
1297 udc->ep0_dir = USB_DIR_OUT;
1298
1299 ep = &udc->eps[0];
f79a60b8
PC		 1300 if (udc->ep0_state != DATA_STATE_XMIT)
1301 udc->ep0_state = WAIT_FOR_OUT_STATUS;
b504882d
LY		 1302
1303 req->ep = ep;
1304 req->req.length = 0;
1305 req->req.status = -EINPROGRESS;
1306 req->req.actual = 0;
1307 req->req.complete = NULL;
1308 req->dtd_count = 0;
1309
3140d5b2
AG		 1310 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1311 req->req.buf, req->req.length,
1312 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1313 req->mapped = 1;
1314
c5cc5ed8 1315 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
224b5039 1316 fsl_queue_td(ep, req);
b504882d
LY		 1317 else
1318 return -ENOMEM;
1319
b504882d
LY		 1320 list_add_tail(&req->queue, &ep->queue);
1321
224b5039 1322 return 0;
b504882d
LY		 1323}
1324
825bee3a 1325static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
b504882d
LY		 1326{
1327 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1328
825bee3a
WN		 1329 if (ep->name)
1330 nuke(ep, -ESHUTDOWN);
b504882d
LY		 1331}
1332
1333/*
1334 * ch9 Set address
1335 */
1336static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1337{
1338 /* Save the new address to device struct */
1339 udc->device_address = (u8) value;
1340 /* Update usb state */
1341 udc->usb_state = USB_STATE_ADDRESS;
1342 /* Status phase */
1343 if (ep0_prime_status(udc, EP_DIR_IN))
1344 ep0stall(udc);
1345}
1346
1347/*
1348 * ch9 Get status
1349 */
1350static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1351 u16 index, u16 length)
1352{
1353 u16 tmp = 0; /* Status, cpu endian */
b504882d
LY		 1354 struct fsl_req *req;
1355 struct fsl_ep *ep;
b504882d
LY		 1356
1357 ep = &udc->eps[0];
1358
1359 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1360 /* Get device status */
1361 tmp = 1 << USB_DEVICE_SELF_POWERED;
1362 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1363 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1364 /* Get interface status */
1365 /* We don't have interface information in udc driver */
1366 tmp = 0;
1367 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1368 /* Get endpoint status */
1369 struct fsl_ep *target_ep;
1370
1371 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1372
1373 /* stall if endpoint doesn't exist */
79149b8b 1374 if (!target_ep->ep.desc)
b504882d
LY		 1375 goto stall;
1376 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1377 << USB_ENDPOINT_HALT;
1378 }
1379
1380 udc->ep0_dir = USB_DIR_IN;
1381 /* Borrow the per device status_req */
1382 req = udc->status_req;
1383 /* Fill in the reqest structure */
1384 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
2ea6698d 1385
b504882d
LY		 1386 req->ep = ep;
1387 req->req.length = 2;
1388 req->req.status = -EINPROGRESS;
1389 req->req.actual = 0;
1390 req->req.complete = NULL;
1391 req->dtd_count = 0;
1392
3140d5b2
AG		 1393 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1394 req->req.buf, req->req.length,
1395 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1396 req->mapped = 1;
1397
b504882d 1398 /* prime the data phase */
c5cc5ed8 1399 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
224b5039 1400 fsl_queue_td(ep, req);
b504882d
LY		 1401 else /* no mem */
1402 goto stall;
1403
b504882d
LY		 1404 list_add_tail(&req->queue, &ep->queue);
1405 udc->ep0_state = DATA_STATE_XMIT;
f79a60b8
PC		 1406 if (ep0_prime_status(udc, EP_DIR_OUT))
1407 ep0stall(udc);
1408
b504882d
LY		 1409 return;
1410stall:
1411 ep0stall(udc);
1412}
1413
1414static void setup_received_irq(struct fsl_udc *udc,
1415 struct usb_ctrlrequest *setup)
1416{
1417 u16 wValue = le16_to_cpu(setup->wValue);
1418 u16 wIndex = le16_to_cpu(setup->wIndex);
1419 u16 wLength = le16_to_cpu(setup->wLength);
1420
1421 udc_reset_ep_queue(udc, 0);
1422
39d1f8c9 1423 /* We process some stardard setup requests here */
b504882d 1424 switch (setup->bRequest) {
b504882d 1425 case USB_REQ_GET_STATUS:
39d1f8c9
LY		 1426 /* Data+Status phase from udc */
1427 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
b504882d
LY		 1428 != (USB_DIR_IN | USB_TYPE_STANDARD))
1429 break;
1430 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
39d1f8c9 1431 return;
b504882d 1432
b504882d 1433 case USB_REQ_SET_ADDRESS:
39d1f8c9 1434 /* Status phase from udc */
b504882d
LY		 1435 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1436 | USB_RECIP_DEVICE))
1437 break;
1438 ch9setaddress(udc, wValue, wIndex, wLength);
39d1f8c9 1439 return;
b504882d 1440
b504882d
LY		 1441 case USB_REQ_CLEAR_FEATURE:
1442 case USB_REQ_SET_FEATURE:
39d1f8c9
LY		 1443 /* Status phase from udc */
1444 {
b504882d 1445 int rc = -EOPNOTSUPP;
2ea6698d 1446 u16 ptc = 0;
b504882d 1447
39d1f8c9
LY		 1448 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1449 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
b504882d
LY		 1450 int pipe = get_pipe_by_windex(wIndex);
1451 struct fsl_ep *ep;
1452
118d63f7 1453 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
b504882d
LY		 1454 break;
1455 ep = get_ep_by_pipe(udc, pipe);
1456
1457 spin_unlock(&udc->lock);
1458 rc = fsl_ep_set_halt(&ep->ep,
1459 (setup->bRequest == USB_REQ_SET_FEATURE)
1460 ? 1 : 0);
1461 spin_lock(&udc->lock);
1462
39d1f8c9
LY		 1463 } else if ((setup->bRequestType & (USB_RECIP_MASK
1464 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1465 | USB_TYPE_STANDARD)) {
b504882d
LY		 1466 /* Note: The driver has not include OTG support yet.
1467 * This will be set when OTG support is added */
2ea6698d
AG		 1468 if (wValue == USB_DEVICE_TEST_MODE)
1469 ptc = wIndex >> 8;
1470 else if (gadget_is_otg(&udc->gadget)) {
1471 if (setup->bRequest ==
1472 USB_DEVICE_B_HNP_ENABLE)
1473 udc->gadget.b_hnp_enable = 1;
1474 else if (setup->bRequest ==
1475 USB_DEVICE_A_HNP_SUPPORT)
1476 udc->gadget.a_hnp_support = 1;
1477 else if (setup->bRequest ==
1478 USB_DEVICE_A_ALT_HNP_SUPPORT)
1479 udc->gadget.a_alt_hnp_support = 1;
1480 }
b504882d 1481 rc = 0;
39d1f8c9
LY		 1482 } else
1483 break;
1484
b504882d
LY		 1485 if (rc == 0) {
1486 if (ep0_prime_status(udc, EP_DIR_IN))
1487 ep0stall(udc);
1488 }
2ea6698d
AG		 1489 if (ptc) {
1490 u32 tmp;
1491
1492 mdelay(10);
1493 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1494 fsl_writel(tmp, &dr_regs->portsc1);
1495 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1496 }
1497
39d1f8c9 1498 return;
b504882d 1499 }
b504882d 1500
39d1f8c9 1501 default:
b504882d
LY		 1502 break;
1503 }
39d1f8c9
LY		 1504
1505 /* Requests handled by gadget */
1506 if (wLength) {
1507 /* Data phase from gadget, status phase from udc */
1508 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1509 ? USB_DIR_IN : USB_DIR_OUT;
1510 spin_unlock(&udc->lock);
1511 if (udc->driver->setup(&udc->gadget,
1512 &udc->local_setup_buff) < 0)
1513 ep0stall(udc);
1514 spin_lock(&udc->lock);
1515 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1516 ? DATA_STATE_XMIT : DATA_STATE_RECV;
f79a60b8
PC		 1517 /*
1518 * If the data stage is IN, send status prime immediately.
1519 * See 2.0 Spec chapter 8.5.3.3 for detail.
1520 */
1521 if (udc->ep0_state == DATA_STATE_XMIT)
1522 if (ep0_prime_status(udc, EP_DIR_OUT))
1523 ep0stall(udc);
1524
39d1f8c9
LY		 1525 } else {
1526 /* No data phase, IN status from gadget */
1527 udc->ep0_dir = USB_DIR_IN;
1528 spin_unlock(&udc->lock);
1529 if (udc->driver->setup(&udc->gadget,
1530 &udc->local_setup_buff) < 0)
1531 ep0stall(udc);
1532 spin_lock(&udc->lock);
1533 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1534 }
b504882d
LY		 1535}
1536
1537/* Process request for Data or Status phase of ep0
1538 * prime status phase if needed */
1539static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1540 struct fsl_req *req)
1541{
1542 if (udc->usb_state == USB_STATE_ADDRESS) {
1543 /* Set the new address */
1544 u32 new_address = (u32) udc->device_address;
1545 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1546 &dr_regs->deviceaddr);
1547 }
1548
1549 done(ep0, req, 0);
1550
1551 switch (udc->ep0_state) {
1552 case DATA_STATE_XMIT:
f79a60b8
PC		 1553 /* already primed at setup_received_irq */
1554 udc->ep0_state = WAIT_FOR_OUT_STATUS;
b504882d
LY		 1555 break;
1556 case DATA_STATE_RECV:
1557 /* send status phase */
1558 if (ep0_prime_status(udc, EP_DIR_IN))
1559 ep0stall(udc);
1560 break;
1561 case WAIT_FOR_OUT_STATUS:
1562 udc->ep0_state = WAIT_FOR_SETUP;
1563 break;
1564 case WAIT_FOR_SETUP:
bf7409a2 1565 ERR("Unexpect ep0 packets\n");
b504882d
LY		 1566 break;
1567 default:
1568 ep0stall(udc);
1569 break;
1570 }
1571}
1572
1573/* Tripwire mechanism to ensure a setup packet payload is extracted without
1574 * being corrupted by another incoming setup packet */
1575static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1576{
1577 u32 temp;
1578 struct ep_queue_head *qh;
09ba0def 1579 struct fsl_usb2_platform_data *pdata = udc->pdata;
b504882d
LY		 1580
1581 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1582
1583 /* Clear bit in ENDPTSETUPSTAT */
1584 temp = fsl_readl(&dr_regs->endptsetupstat);
1585 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1586
1587 /* while a hazard exists when setup package arrives */
1588 do {
1589 /* Set Setup Tripwire */
1590 temp = fsl_readl(&dr_regs->usbcmd);
1591 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1592
1593 /* Copy the setup packet to local buffer */
09ba0def
AG		 1594 if (pdata->le_setup_buf) {
1595 u32 *p = (u32 *)buffer_ptr;
1596 u32 *s = (u32 *)qh->setup_buffer;
1597
1598 /* Convert little endian setup buffer to CPU endian */
1599 *p++ = le32_to_cpu(*s++);
1600 *p = le32_to_cpu(*s);
1601 } else {
1602 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1603 }
b504882d
LY		 1604 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1605
1606 /* Clear Setup Tripwire */
1607 temp = fsl_readl(&dr_regs->usbcmd);
1608 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1609}
1610
1611/* process-ep_req(): free the completed Tds for this req */
1612static int process_ep_req(struct fsl_udc *udc, int pipe,
1613 struct fsl_req *curr_req)
1614{
1615 struct ep_td_struct *curr_td;
1616 int td_complete, actual, remaining_length, j, tmp;
1617 int status = 0;
1618 int errors = 0;
1619 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1620 int direction = pipe % 2;
1621
1622 curr_td = curr_req->head;
1623 td_complete = 0;
1624 actual = curr_req->req.length;
1625
1626 for (j = 0; j < curr_req->dtd_count; j++) {
09ba0def 1627 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
b504882d
LY		 1628 & DTD_PACKET_SIZE)
1629 >> DTD_LENGTH_BIT_POS;
1630 actual -= remaining_length;
1631
09ba0def
AG		 1632 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1633 if (errors & DTD_ERROR_MASK) {
b504882d
LY		 1634 if (errors & DTD_STATUS_HALTED) {
1635 ERR("dTD error %08x QH=%d\n", errors, pipe);
1636 /* Clear the errors and Halt condition */
09ba0def 1637 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
b504882d 1638 tmp &= ~errors;
09ba0def 1639 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
b504882d
LY		 1640 status = -EPIPE;
1641 /* FIXME: continue with next queued TD? */
1642
1643 break;
1644 }
1645 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1646 VDBG("Transfer overflow");
1647 status = -EPROTO;
1648 break;
1649 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1650 VDBG("ISO error");
1651 status = -EILSEQ;
1652 break;
1653 } else
25985edc 1654 ERR("Unknown error has occurred (0x%x)!\n",
b504882d
LY		 1655 errors);
1656
09ba0def 1657 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
b504882d
LY		 1658 & DTD_STATUS_ACTIVE) {
1659 VDBG("Request not complete");
1660 status = REQ_UNCOMPLETE;
1661 return status;
1662 } else if (remaining_length) {
1663 if (direction) {
1664 VDBG("Transmit dTD remaining length not zero");
1665 status = -EPROTO;
1666 break;
1667 } else {
1668 td_complete++;
1669 break;
1670 }
1671 } else {
1672 td_complete++;
bf7409a2 1673 VDBG("dTD transmitted successful");
b504882d
LY		 1674 }
1675
1676 if (j != curr_req->dtd_count - 1)
1677 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1678 }
1679
1680 if (status)
1681 return status;
1682
1683 curr_req->req.actual = actual;
1684
1685 return 0;
1686}
1687
1688/* Process a DTD completion interrupt */
1689static void dtd_complete_irq(struct fsl_udc *udc)
1690{
1691 u32 bit_pos;
1692 int i, ep_num, direction, bit_mask, status;
1693 struct fsl_ep *curr_ep;
1694 struct fsl_req *curr_req, *temp_req;
1695
1696 /* Clear the bits in the register */
1697 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1698 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1699
1700 if (!bit_pos)
1701 return;
1702
118d63f7 1703 for (i = 0; i < udc->max_ep; i++) {
b504882d
LY		 1704 ep_num = i >> 1;
1705 direction = i % 2;
1706
1707 bit_mask = 1 << (ep_num + 16 * direction);
1708
1709 if (!(bit_pos & bit_mask))
1710 continue;
1711
1712 curr_ep = get_ep_by_pipe(udc, i);
1713
1714 /* If the ep is configured */
1715 if (curr_ep->name == NULL) {
b6c63937 1716 WARNING("Invalid EP?");
b504882d
LY		 1717 continue;
1718 }
1719
1720 /* process the req queue until an uncomplete request */
1721 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1722 queue) {
1723 status = process_ep_req(udc, i, curr_req);
1724
1725 VDBG("status of process_ep_req= %d, ep = %d",
1726 status, ep_num);
1727 if (status == REQ_UNCOMPLETE)
1728 break;
1729 /* write back status to req */
1730 curr_req->req.status = status;
1731
1732 if (ep_num == 0) {
1733 ep0_req_complete(udc, curr_ep, curr_req);
1734 break;
1735 } else
1736 done(curr_ep, curr_req, status);
1737 }
1738 }
1739}
1740
e538dfda
MN		 1741static inline enum usb_device_speed portscx_device_speed(u32 reg)
1742{
0e042be3 1743 switch (reg & PORTSCX_PORT_SPEED_MASK) {
e538dfda
MN		 1744 case PORTSCX_PORT_SPEED_HIGH:
1745 return USB_SPEED_HIGH;
1746 case PORTSCX_PORT_SPEED_FULL:
1747 return USB_SPEED_FULL;
1748 case PORTSCX_PORT_SPEED_LOW:
1749 return USB_SPEED_LOW;
1750 default:
1751 return USB_SPEED_UNKNOWN;
1752 }
1753}
1754
b504882d
LY		 1755/* Process a port change interrupt */
1756static void port_change_irq(struct fsl_udc *udc)
1757{
83722bc9
AG		 1758 if (udc->bus_reset)
1759 udc->bus_reset = 0;
1760
b504882d 1761 /* Bus resetting is finished */
e538dfda 1762 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
b504882d 1763 /* Get the speed */
e538dfda
MN		 1764 udc->gadget.speed =
1765 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
b504882d
LY		 1766
1767 /* Update USB state */
1768 if (!udc->resume_state)
1769 udc->usb_state = USB_STATE_DEFAULT;
1770}
1771
1772/* Process suspend interrupt */
1773static void suspend_irq(struct fsl_udc *udc)
1774{
1775 udc->resume_state = udc->usb_state;
1776 udc->usb_state = USB_STATE_SUSPENDED;
1777
1778 /* report suspend to the driver, serial.c does not support this */
1779 if (udc->driver->suspend)
1780 udc->driver->suspend(&udc->gadget);
1781}
1782
1783static void bus_resume(struct fsl_udc *udc)
1784{
1785 udc->usb_state = udc->resume_state;
1786 udc->resume_state = 0;
1787
1788 /* report resume to the driver, serial.c does not support this */
1789 if (udc->driver->resume)
1790 udc->driver->resume(&udc->gadget);
1791}
1792
1793/* Clear up all ep queues */
1794static int reset_queues(struct fsl_udc *udc)
1795{
1796 u8 pipe;
1797
1798 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1799 udc_reset_ep_queue(udc, pipe);
1800
1801 /* report disconnect; the driver is already quiesced */
185e3dea 1802 spin_unlock(&udc->lock);
b504882d 1803 udc->driver->disconnect(&udc->gadget);
185e3dea 1804 spin_lock(&udc->lock);
b504882d
LY		 1805
1806 return 0;
1807}
1808
1809/* Process reset interrupt */
1810static void reset_irq(struct fsl_udc *udc)
1811{
1812 u32 temp;
1813 unsigned long timeout;
1814
1815 /* Clear the device address */
1816 temp = fsl_readl(&dr_regs->deviceaddr);
1817 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1818
1819 udc->device_address = 0;
1820
1821 /* Clear usb state */
1822 udc->resume_state = 0;
1823 udc->ep0_dir = 0;
1824 udc->ep0_state = WAIT_FOR_SETUP;
1825 udc->remote_wakeup = 0; /* default to 0 on reset */
1826 udc->gadget.b_hnp_enable = 0;
1827 udc->gadget.a_hnp_support = 0;
1828 udc->gadget.a_alt_hnp_support = 0;
1829
1830 /* Clear all the setup token semaphores */
1831 temp = fsl_readl(&dr_regs->endptsetupstat);
1832 fsl_writel(temp, &dr_regs->endptsetupstat);
1833
1834 /* Clear all the endpoint complete status bits */
1835 temp = fsl_readl(&dr_regs->endptcomplete);
1836 fsl_writel(temp, &dr_regs->endptcomplete);
1837
1838 timeout = jiffies + 100;
1839 while (fsl_readl(&dr_regs->endpointprime)) {
1840 /* Wait until all endptprime bits cleared */
1841 if (time_after(jiffies, timeout)) {
1842 ERR("Timeout for reset\n");
1843 break;
1844 }
1845 cpu_relax();
1846 }
1847
1848 /* Write 1s to the flush register */
1849 fsl_writel(0xffffffff, &dr_regs->endptflush);
1850
1851 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1852 VDBG("Bus reset");
83722bc9
AG		 1853 /* Bus is reseting */
1854 udc->bus_reset = 1;
b504882d
LY		 1855 /* Reset all the queues, include XD, dTD, EP queue
1856 * head and TR Queue */
1857 reset_queues(udc);
1858 udc->usb_state = USB_STATE_DEFAULT;
1859 } else {
1860 VDBG("Controller reset");
1861 /* initialize usb hw reg except for regs for EP, not
1862 * touch usbintr reg */
1863 dr_controller_setup(udc);
1864
1865 /* Reset all internal used Queues */
1866 reset_queues(udc);
1867
1868 ep0_setup(udc);
1869
1870 /* Enable DR IRQ reg, Set Run bit, change udc state */
1871 dr_controller_run(udc);
1872 udc->usb_state = USB_STATE_ATTACHED;
1873 }
1874}
1875
1876/*
1877 * USB device controller interrupt handler
1878 */
1879static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1880{
1881 struct fsl_udc *udc = _udc;
1882 u32 irq_src;
1883 irqreturn_t status = IRQ_NONE;
1884 unsigned long flags;
1885
1886 /* Disable ISR for OTG host mode */
1887 if (udc->stopped)
1888 return IRQ_NONE;
1889 spin_lock_irqsave(&udc->lock, flags);
1890 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1891 /* Clear notification bits */
1892 fsl_writel(irq_src, &dr_regs->usbsts);
1893
1894 /* VDBG("irq_src [0x%8x]", irq_src); */
1895
1896 /* Need to resume? */
1897 if (udc->usb_state == USB_STATE_SUSPENDED)
1898 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1899 bus_resume(udc);
1900
1901 /* USB Interrupt */
1902 if (irq_src & USB_STS_INT) {
1903 VDBG("Packet int");
1904 /* Setup package, we only support ep0 as control ep */
1905 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1906 tripwire_handler(udc, 0,
1907 (u8 *) (&udc->local_setup_buff));
1908 setup_received_irq(udc, &udc->local_setup_buff);
1909 status = IRQ_HANDLED;
1910 }
1911
1912 /* completion of dtd */
1913 if (fsl_readl(&dr_regs->endptcomplete)) {
1914 dtd_complete_irq(udc);
1915 status = IRQ_HANDLED;
1916 }
1917 }
1918
1919 /* SOF (for ISO transfer) */
1920 if (irq_src & USB_STS_SOF) {
1921 status = IRQ_HANDLED;
1922 }
1923
1924 /* Port Change */
1925 if (irq_src & USB_STS_PORT_CHANGE) {
1926 port_change_irq(udc);
1927 status = IRQ_HANDLED;
1928 }
1929
1930 /* Reset Received */
1931 if (irq_src & USB_STS_RESET) {
83722bc9 1932 VDBG("reset int");
b504882d
LY		 1933 reset_irq(udc);
1934 status = IRQ_HANDLED;
1935 }
1936
1937 /* Sleep Enable (Suspend) */
1938 if (irq_src & USB_STS_SUSPEND) {
1939 suspend_irq(udc);
1940 status = IRQ_HANDLED;
1941 }
1942
1943 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
bf7409a2 1944 VDBG("Error IRQ %x", irq_src);
b504882d
LY		 1945 }
1946
1947 spin_unlock_irqrestore(&udc->lock, flags);
1948 return status;
1949}
1950
1951/*----------------------------------------------------------------*
1952 * Hook to gadget drivers
1953 * Called by initialization code of gadget drivers
1954*----------------------------------------------------------------*/
eb65796e
FB		 1955static int fsl_udc_start(struct usb_gadget *g,
1956 struct usb_gadget_driver *driver)
b504882d 1957{
eb65796e 1958 int retval = 0;
b504882d
LY		 1959 unsigned long flags = 0;
1960
b504882d
LY		 1961 /* lock is needed but whether should use this lock or another */
1962 spin_lock_irqsave(&udc_controller->lock, flags);
1963
7483cff8 1964 driver->driver.bus = NULL;
b504882d
LY		 1965 /* hook up the driver */
1966 udc_controller->driver = driver;
1967 udc_controller->gadget.dev.driver = &driver->driver;
1968 spin_unlock_irqrestore(&udc_controller->lock, flags);
1969
ded017ee 1970 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 1971 /* Suspend the controller until OTG enable it */
1972 udc_controller->stopped = 1;
1973 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1974
1975 /* connect to bus through transceiver */
ded017ee 1976 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
6e13c650
HK		 1977 retval = otg_set_peripheral(
1978 udc_controller->transceiver->otg,
83722bc9
AG		 1979 &udc_controller->gadget);
1980 if (retval < 0) {
1981 ERR("can't bind to transceiver\n");
1982 driver->unbind(&udc_controller->gadget);
1983 udc_controller->gadget.dev.driver = 0;
1984 udc_controller->driver = 0;
1985 return retval;
1986 }
1987 }
1988 } else {
1989 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1990 dr_controller_run(udc_controller);
1991 udc_controller->usb_state = USB_STATE_ATTACHED;
1992 udc_controller->ep0_state = WAIT_FOR_SETUP;
1993 udc_controller->ep0_dir = 0;
1994 }
b504882d 1995
b504882d
LY		 1996 return retval;
1997}
b504882d
LY		 1998
1999/* Disconnect from gadget driver */
eb65796e
FB		 2000static int fsl_udc_stop(struct usb_gadget *g,
2001 struct usb_gadget_driver *driver)
b504882d
LY		 2002{
2003 struct fsl_ep *loop_ep;
2004 unsigned long flags;
2005
ded017ee 2006 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
6e13c650 2007 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
b504882d
LY		 2008
2009 /* stop DR, disable intr */
2010 dr_controller_stop(udc_controller);
2011
2012 /* in fact, no needed */
2013 udc_controller->usb_state = USB_STATE_ATTACHED;
2014 udc_controller->ep0_state = WAIT_FOR_SETUP;
2015 udc_controller->ep0_dir = 0;
2016
2017 /* stand operation */
2018 spin_lock_irqsave(&udc_controller->lock, flags);
2019 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2020 nuke(&udc_controller->eps[0], -ESHUTDOWN);
2021 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2022 ep.ep_list)
2023 nuke(loop_ep, -ESHUTDOWN);
2024 spin_unlock_irqrestore(&udc_controller->lock, flags);
2025
7483cff8
WN		 2026 udc_controller->gadget.dev.driver = NULL;
2027 udc_controller->driver = NULL;
b504882d 2028
b504882d
LY		 2029 return 0;
2030}
b504882d
LY		 2031
2032/*-------------------------------------------------------------------------
2033 PROC File System Support
2034-------------------------------------------------------------------------*/
2035#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2036
2037#include <linux/seq_file.h>
2038
2039static const char proc_filename[] = "driver/fsl_usb2_udc";
2040
2041static int fsl_proc_read(char *page, char **start, off_t off, int count,
2042 int *eof, void *_dev)
2043{
2044 char *buf = page;
2045 char *next = buf;
2046 unsigned size = count;
2047 unsigned long flags;
2048 int t, i;
2049 u32 tmp_reg;
2050 struct fsl_ep *ep = NULL;
2051 struct fsl_req *req;
2052
2053 struct fsl_udc *udc = udc_controller;
2054 if (off != 0)
2055 return 0;
2056
2057 spin_lock_irqsave(&udc->lock, flags);
2058
dc0d5c1e 2059 /* ------basic driver information ---- */
b504882d
LY		 2060 t = scnprintf(next, size,
2061 DRIVER_DESC "\n"
2062 "%s version: %s\n"
2063 "Gadget driver: %s\n\n",
2064 driver_name, DRIVER_VERSION,
2065 udc->driver ? udc->driver->driver.name : "(none)");
2066 size -= t;
2067 next += t;
2068
2069 /* ------ DR Registers ----- */
2070 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2071 t = scnprintf(next, size,
2072 "USBCMD reg:\n"
2073 "SetupTW: %d\n"
2074 "Run/Stop: %s\n\n",
2075 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2076 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2077 size -= t;
2078 next += t;
2079
2080 tmp_reg = fsl_readl(&dr_regs->usbsts);
2081 t = scnprintf(next, size,
2082 "USB Status Reg:\n"
9d9d88c8 2083 "Dr Suspend: %d Reset Received: %d System Error: %s "
b504882d
LY		 2084 "USB Error Interrupt: %s\n\n",
2085 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2086 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2087 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2088 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2089 size -= t;
2090 next += t;
2091
2092 tmp_reg = fsl_readl(&dr_regs->usbintr);
2093 t = scnprintf(next, size,
984e833c 2094 "USB Interrupt Enable Reg:\n"
9d9d88c8 2095 "Sleep Enable: %d SOF Received Enable: %d "
b504882d 2096 "Reset Enable: %d\n"
9d9d88c8 2097 "System Error Enable: %d "
b504882d 2098 "Port Change Dectected Enable: %d\n"
9d9d88c8 2099 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
b504882d
LY		 2100 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2101 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2102 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2103 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2104 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2105 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2106 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2107 size -= t;
2108 next += t;
2109
2110 tmp_reg = fsl_readl(&dr_regs->frindex);
2111 t = scnprintf(next, size,
9d9d88c8 2112 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
b504882d
LY		 2113 (tmp_reg & USB_FRINDEX_MASKS));
2114 size -= t;
2115 next += t;
2116
2117 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2118 t = scnprintf(next, size,
9d9d88c8 2119 "USB Device Address Reg: Device Addr is 0x%x\n\n",
b504882d
LY		 2120 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2121 size -= t;
2122 next += t;
2123
2124 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2125 t = scnprintf(next, size,
9d9d88c8 2126 "USB Endpoint List Address Reg: "
b504882d
LY		 2127 "Device Addr is 0x%x\n\n",
2128 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2129 size -= t;
2130 next += t;
2131
2132 tmp_reg = fsl_readl(&dr_regs->portsc1);
2133 t = scnprintf(next, size,
2134 "USB Port Status&Control Reg:\n"
9d9d88c8
WN		 2135 "Port Transceiver Type : %s Port Speed: %s\n"
2136 "PHY Low Power Suspend: %s Port Reset: %s "
2137 "Port Suspend Mode: %s\n"
2138 "Over-current Change: %s "
b504882d 2139 "Port Enable/Disable Change: %s\n"
9d9d88c8 2140 "Port Enabled/Disabled: %s "
b504882d
LY		 2141 "Current Connect Status: %s\n\n", ( {
2142 char *s;
2143 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2144 case PORTSCX_PTS_UTMI:
2145 s = "UTMI"; break;
2146 case PORTSCX_PTS_ULPI:
2147 s = "ULPI "; break;
2148 case PORTSCX_PTS_FSLS:
2149 s = "FS/LS Serial"; break;
2150 default:
2151 s = "None"; break;
2152 }
e538dfda
MN		 2153 s;} ),
2154 usb_speed_string(portscx_device_speed(tmp_reg)),
b504882d
LY		 2155 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2156 "Normal PHY mode" : "Low power mode",
2157 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2158 "Not in Reset",
2159 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2160 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2161 "No",
2162 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2163 "Not change",
2164 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2165 "Not correct",
2166 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2167 "Attached" : "Not-Att");
2168 size -= t;
2169 next += t;
2170
2171 tmp_reg = fsl_readl(&dr_regs->usbmode);
2172 t = scnprintf(next, size,
9d9d88c8 2173 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
b504882d
LY		 2174 char *s;
2175 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2176 case USB_MODE_CTRL_MODE_IDLE:
2177 s = "Idle"; break;
2178 case USB_MODE_CTRL_MODE_DEVICE:
2179 s = "Device Controller"; break;
2180 case USB_MODE_CTRL_MODE_HOST:
2181 s = "Host Controller"; break;
2182 default:
2183 s = "None"; break;
2184 }
2185 s;
2186 } ));
2187 size -= t;
2188 next += t;
2189
2190 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2191 t = scnprintf(next, size,
9d9d88c8 2192 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
b504882d
LY		 2193 (tmp_reg & EP_SETUP_STATUS_MASK));
2194 size -= t;
2195 next += t;
2196
2197 for (i = 0; i < udc->max_ep / 2; i++) {
2198 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2199 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2200 i, tmp_reg);
2201 size -= t;
2202 next += t;
2203 }
2204 tmp_reg = fsl_readl(&dr_regs->endpointprime);
9d9d88c8 2205 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
b504882d
LY		 2206 size -= t;
2207 next += t;
2208
54e4026b 2209#ifndef CONFIG_ARCH_MXC
2ea6698d
AG		 2210 if (udc->pdata->have_sysif_regs) {
2211 tmp_reg = usb_sys_regs->snoop1;
2212 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2213 size -= t;
2214 next += t;
b504882d 2215
2ea6698d
AG		 2216 tmp_reg = usb_sys_regs->control;
2217 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2218 tmp_reg);
2219 size -= t;
2220 next += t;
2221 }
54e4026b 2222#endif
b504882d
LY		 2223
2224 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2225 ep = &udc->eps[0];
2226 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2227 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2228 size -= t;
2229 next += t;
2230
2231 if (list_empty(&ep->queue)) {
2232 t = scnprintf(next, size, "its req queue is empty\n\n");
2233 size -= t;
2234 next += t;
2235 } else {
2236 list_for_each_entry(req, &ep->queue, queue) {
2237 t = scnprintf(next, size,
9d9d88c8 2238 "req %p actual 0x%x length 0x%x buf %p\n",
b504882d
LY		 2239 &req->req, req->req.actual,
2240 req->req.length, req->req.buf);
2241 size -= t;
2242 next += t;
2243 }
2244 }
2245 /* other gadget->eplist ep */
2246 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
79149b8b 2247 if (ep->ep.desc) {
b504882d
LY		 2248 t = scnprintf(next, size,
2249 "\nFor %s Maxpkt is 0x%x "
2250 "index is 0x%x\n",
2251 ep->ep.name, ep_maxpacket(ep),
2252 ep_index(ep));
2253 size -= t;
2254 next += t;
2255
2256 if (list_empty(&ep->queue)) {
2257 t = scnprintf(next, size,
2258 "its req queue is empty\n\n");
2259 size -= t;
2260 next += t;
2261 } else {
2262 list_for_each_entry(req, &ep->queue, queue) {
2263 t = scnprintf(next, size,
9d9d88c8 2264 "req %p actual 0x%x length "
b504882d
LY		 2265 "0x%x buf %p\n",
2266 &req->req, req->req.actual,
2267 req->req.length, req->req.buf);
2268 size -= t;
2269 next += t;
2270 } /* end for each_entry of ep req */
2271 } /* end for else */
2272 } /* end for if(ep->queue) */
2273 } /* end (ep->desc) */
2274
2275 spin_unlock_irqrestore(&udc->lock, flags);
2276
2277 *eof = 1;
2278 return count - size;
2279}
2280
2281#define create_proc_file() create_proc_read_entry(proc_filename, \
2282 0, NULL, fsl_proc_read, NULL)
2283
2284#define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2285
2286#else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2287
2288#define create_proc_file() do {} while (0)
2289#define remove_proc_file() do {} while (0)
2290
2291#endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2292
2293/*-------------------------------------------------------------------------*/
2294
2295/* Release udc structures */
2296static void fsl_udc_release(struct device *dev)
2297{
2298 complete(udc_controller->done);
37c4fd8c 2299 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
b504882d
LY		 2300 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2301 kfree(udc_controller);
2302}
2303
2304/******************************************************************
2305 Internal structure setup functions
2306*******************************************************************/
2307/*------------------------------------------------------------------
2308 * init resource for globle controller
2309 * Return the udc handle on success or NULL on failure
2310 ------------------------------------------------------------------*/
4365831d
LY		 2311static int __init struct_udc_setup(struct fsl_udc *udc,
2312 struct platform_device *pdev)
b504882d 2313{
b504882d
LY		 2314 struct fsl_usb2_platform_data *pdata;
2315 size_t size;
2316
b504882d
LY		 2317 pdata = pdev->dev.platform_data;
2318 udc->phy_mode = pdata->phy_mode;
b504882d
LY		 2319
2320 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2321 if (!udc->eps) {
2322 ERR("malloc fsl_ep failed\n");
4365831d 2323 return -1;
b504882d
LY		 2324 }
2325
2326 /* initialized QHs, take care of alignment */
2327 size = udc->max_ep * sizeof(struct ep_queue_head);
2328 if (size < QH_ALIGNMENT)
2329 size = QH_ALIGNMENT;
2330 else if ((size % QH_ALIGNMENT) != 0) {
2331 size += QH_ALIGNMENT + 1;
2332 size &= ~(QH_ALIGNMENT - 1);
2333 }
2334 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2335 &udc->ep_qh_dma, GFP_KERNEL);
2336 if (!udc->ep_qh) {
2337 ERR("malloc QHs for udc failed\n");
2338 kfree(udc->eps);
4365831d 2339 return -1;
b504882d
LY		 2340 }
2341
2342 udc->ep_qh_size = size;
2343
2344 /* Initialize ep0 status request structure */
2345 /* FIXME: fsl_alloc_request() ignores ep argument */
2346 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2347 struct fsl_req, req);
2348 /* allocate a small amount of memory to get valid address */
2349 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
b504882d
LY		 2350
2351 udc->resume_state = USB_STATE_NOTATTACHED;
2352 udc->usb_state = USB_STATE_POWERED;
2353 udc->ep0_dir = 0;
2354 udc->remote_wakeup = 0; /* default to 0 on reset */
b504882d 2355
4365831d 2356 return 0;
b504882d
LY		 2357}
2358
2359/*----------------------------------------------------------------
2360 * Setup the fsl_ep struct for eps
2361 * Link fsl_ep->ep to gadget->ep_list
2362 * ep0out is not used so do nothing here
2363 * ep0in should be taken care
2364 *--------------------------------------------------------------*/
2365static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2366 char *name, int link)
2367{
2368 struct fsl_ep *ep = &udc->eps[index];
2369
2370 ep->udc = udc;
2371 strcpy(ep->name, name);
2372 ep->ep.name = ep->name;
2373
2374 ep->ep.ops = &fsl_ep_ops;
2375 ep->stopped = 0;
2376
2377 /* for ep0: maxP defined in desc
2378 * for other eps, maxP is set by epautoconfig() called by gadget layer
2379 */
2380 ep->ep.maxpacket = (unsigned short) ~0;
2381
2382 /* the queue lists any req for this ep */
2383 INIT_LIST_HEAD(&ep->queue);
2384
2385 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2386 if (link)
2387 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2388 ep->gadget = &udc->gadget;
2389 ep->qh = &udc->ep_qh[index];
2390
2391 return 0;
2392}
2393
2394/* Driver probe function
4365831d
LY		 2395 * all intialization operations implemented here except enabling usb_intr reg
2396 * board setup should have been done in the platform code
b504882d
LY		 2397 */
2398static int __init fsl_udc_probe(struct platform_device *pdev)
2399{
09ba0def 2400 struct fsl_usb2_platform_data *pdata;
b504882d
LY		 2401 struct resource *res;
2402 int ret = -ENODEV;
2403 unsigned int i;
4365831d 2404 u32 dccparams;
b504882d 2405
4365831d
LY		 2406 udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2407 if (udc_controller == NULL) {
2408 ERR("malloc udc failed\n");
b504882d
LY		 2409 return -ENOMEM;
2410 }
2411
09ba0def
AG		 2412 pdata = pdev->dev.platform_data;
2413 udc_controller->pdata = pdata;
e06da9a8
WN		 2414 spin_lock_init(&udc_controller->lock);
2415 udc_controller->stopped = 1;
2416
83722bc9
AG		 2417#ifdef CONFIG_USB_OTG
2418 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
662dca54 2419 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee 2420 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 2421 ERR("Can't find OTG driver!\n");
2422 ret = -ENODEV;
2423 goto err_kfree;
2424 }
2425 }
2426#endif
2427
b504882d 2428 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4365831d 2429 if (!res) {
23d7cd04
WN		 2430 ret = -ENXIO;
2431 goto err_kfree;
4365831d 2432 }
b504882d 2433
83722bc9 2434 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
28f65c11 2435 if (!request_mem_region(res->start, resource_size(res),
83722bc9
AG		 2436 driver_name)) {
2437 ERR("request mem region for %s failed\n", pdev->name);
2438 ret = -EBUSY;
2439 goto err_kfree;
2440 }
b504882d
LY		 2441 }
2442
54e4026b 2443 dr_regs = ioremap(res->start, resource_size(res));
b504882d
LY		 2444 if (!dr_regs) {
2445 ret = -ENOMEM;
23d7cd04 2446 goto err_release_mem_region;
b504882d
LY		 2447 }
2448
2ea6698d
AG		 2449 pdata->regs = (void *)dr_regs;
2450
2451 /*
2452 * do platform specific init: check the clock, grab/config pins, etc.
2453 */
2454 if (pdata->init && pdata->init(pdev)) {
2455 ret = -ENODEV;
2456 goto err_iounmap_noclk;
2457 }
2458
2459 /* Set accessors only after pdata->init() ! */
3140d5b2 2460 fsl_set_accessors(pdata);
09ba0def 2461
54e4026b 2462#ifndef CONFIG_ARCH_MXC
2ea6698d 2463 if (pdata->have_sysif_regs)
8981d76a 2464 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
54e4026b
GL		 2465#endif
2466
2467 /* Initialize USB clocks */
2468 ret = fsl_udc_clk_init(pdev);
2469 if (ret < 0)
2470 goto err_iounmap_noclk;
b504882d 2471
4365831d
LY		 2472 /* Read Device Controller Capability Parameters register */
2473 dccparams = fsl_readl(&dr_regs->dccparams);
2474 if (!(dccparams & DCCPARAMS_DC)) {
2475 ERR("This SOC doesn't support device role\n");
2476 ret = -ENODEV;
23d7cd04 2477 goto err_iounmap;
4365831d
LY		 2478 }
2479 /* Get max device endpoints */
2480 /* DEN is bidirectional ep number, max_ep doubles the number */
2481 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2482
b504882d
LY		 2483 udc_controller->irq = platform_get_irq(pdev, 0);
2484 if (!udc_controller->irq) {
2485 ret = -ENODEV;
23d7cd04 2486 goto err_iounmap;
b504882d
LY		 2487 }
2488
37b5453d 2489 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
b504882d
LY		 2490 driver_name, udc_controller);
2491 if (ret != 0) {
bf7409a2 2492 ERR("cannot request irq %d err %d\n",
b504882d 2493 udc_controller->irq, ret);
23d7cd04 2494 goto err_iounmap;
b504882d
LY		 2495 }
2496
4365831d
LY		 2497 /* Initialize the udc structure including QH member and other member */
2498 if (struct_udc_setup(udc_controller, pdev)) {
2499 ERR("Can't initialize udc data structure\n");
2500 ret = -ENOMEM;
23d7cd04 2501 goto err_free_irq;
4365831d
LY		 2502 }
2503
ded017ee 2504 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
83722bc9
AG		 2505 /* initialize usb hw reg except for regs for EP,
2506 * leave usbintr reg untouched */
2507 dr_controller_setup(udc_controller);
2508 }
b504882d 2509
c2c9caa9
PC		 2510 ret = fsl_udc_clk_finalize(pdev);
2511 if (ret)
2512 goto err_free_irq;
54e4026b 2513
b504882d
LY		 2514 /* Setup gadget structure */
2515 udc_controller->gadget.ops = &fsl_gadget_ops;
d327ab5b 2516 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
b504882d
LY		 2517 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2518 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2519 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2520 udc_controller->gadget.name = driver_name;
2521
2522 /* Setup gadget.dev and register with kernel */
0031a06e 2523 dev_set_name(&udc_controller->gadget.dev, "gadget");
b504882d
LY		 2524 udc_controller->gadget.dev.release = fsl_udc_release;
2525 udc_controller->gadget.dev.parent = &pdev->dev;
cb4baf10 2526 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
b504882d
LY		 2527 ret = device_register(&udc_controller->gadget.dev);
2528 if (ret < 0)
23d7cd04 2529 goto err_free_irq;
b504882d 2530
ded017ee 2531 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
83722bc9
AG		 2532 udc_controller->gadget.is_otg = 1;
2533
b504882d
LY		 2534 /* setup QH and epctrl for ep0 */
2535 ep0_setup(udc_controller);
2536
2537 /* setup udc->eps[] for ep0 */
2538 struct_ep_setup(udc_controller, 0, "ep0", 0);
2539 /* for ep0: the desc defined here;
2540 * for other eps, gadget layer called ep_enable with defined desc
2541 */
80e91fd5 2542 udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
b504882d
LY		 2543 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2544
2545 /* setup the udc->eps[] for non-control endpoints and link
2546 * to gadget.ep_list */
2547 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2548 char name[14];
2549
2550 sprintf(name, "ep%dout", i);
2551 struct_ep_setup(udc_controller, i * 2, name, 1);
2552 sprintf(name, "ep%din", i);
2553 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2554 }
2555
2556 /* use dma_pool for TD management */
2557 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2558 sizeof(struct ep_td_struct),
2559 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2560 if (udc_controller->td_pool == NULL) {
2561 ret = -ENOMEM;
23d7cd04 2562 goto err_unregister;
b504882d 2563 }
0f91349b
SAS		 2564
2565 ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2566 if (ret)
2567 goto err_del_udc;
2568
b504882d
LY		 2569 create_proc_file();
2570 return 0;
2571
0f91349b
SAS		 2572err_del_udc:
2573 dma_pool_destroy(udc_controller->td_pool);
23d7cd04 2574err_unregister:
b504882d 2575 device_unregister(&udc_controller->gadget.dev);
23d7cd04 2576err_free_irq:
b504882d 2577 free_irq(udc_controller->irq, udc_controller);
23d7cd04 2578err_iounmap:
2ea6698d
AG		 2579 if (pdata->exit)
2580 pdata->exit(pdev);
54e4026b
GL		 2581 fsl_udc_clk_release();
2582err_iounmap_noclk:
b504882d 2583 iounmap(dr_regs);
23d7cd04 2584err_release_mem_region:
83722bc9 2585 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
28f65c11 2586 release_mem_region(res->start, resource_size(res));
23d7cd04 2587err_kfree:
4365831d 2588 kfree(udc_controller);
23d7cd04 2589 udc_controller = NULL;
b504882d
LY		 2590 return ret;
2591}
2592
2593/* Driver removal function
2594 * Free resources and finish pending transactions
2595 */
2596static int __exit fsl_udc_remove(struct platform_device *pdev)
2597{
2598 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2ea6698d 2599 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
b504882d
LY		 2600
2601 DECLARE_COMPLETION(done);
2602
2603 if (!udc_controller)
2604 return -ENODEV;
0f91349b
SAS		 2605
2606 usb_del_gadget_udc(&udc_controller->gadget);
b504882d
LY		 2607 udc_controller->done = &done;
2608
54e4026b
GL		 2609 fsl_udc_clk_release();
2610
b504882d
LY		 2611 /* DR has been stopped in usb_gadget_unregister_driver() */
2612 remove_proc_file();
2613
2614 /* Free allocated memory */
2615 kfree(udc_controller->status_req->req.buf);
2616 kfree(udc_controller->status_req);
2617 kfree(udc_controller->eps);
2618
2619 dma_pool_destroy(udc_controller->td_pool);
2620 free_irq(udc_controller->irq, udc_controller);
2621 iounmap(dr_regs);
83722bc9 2622 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
28f65c11 2623 release_mem_region(res->start, resource_size(res));
b504882d
LY		 2624
2625 device_unregister(&udc_controller->gadget.dev);
2626 /* free udc --wait for the release() finished */
2627 wait_for_completion(&done);
2628
2ea6698d
AG		 2629 /*
2630 * do platform specific un-initialization:
2631 * release iomux pins, etc.
2632 */
2633 if (pdata->exit)
2634 pdata->exit(pdev);
2635
b504882d
LY		 2636 return 0;
2637}
2638
2639/*-----------------------------------------------------------------
2640 * Modify Power management attributes
2641 * Used by OTG statemachine to disable gadget temporarily
2642 -----------------------------------------------------------------*/
2643static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2644{
2645 dr_controller_stop(udc_controller);
2646 return 0;
2647}
2648
2649/*-----------------------------------------------------------------
2650 * Invoked on USB resume. May be called in_interrupt.
2651 * Here we start the DR controller and enable the irq
2652 *-----------------------------------------------------------------*/
2653static int fsl_udc_resume(struct platform_device *pdev)
2654{
2655 /* Enable DR irq reg and set controller Run */
2656 if (udc_controller->stopped) {
2657 dr_controller_setup(udc_controller);
2658 dr_controller_run(udc_controller);
2659 }
2660 udc_controller->usb_state = USB_STATE_ATTACHED;
2661 udc_controller->ep0_state = WAIT_FOR_SETUP;
2662 udc_controller->ep0_dir = 0;
2663 return 0;
2664}
2665
83722bc9
AG		 2666static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2667{
2668 struct fsl_udc *udc = udc_controller;
2669 u32 mode, usbcmd;
2670
2671 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2672
2673 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2674
2675 /*
2676 * If the controller is already stopped, then this must be a
2677 * PM suspend. Remember this fact, so that we will leave the
2678 * controller stopped at PM resume time.
2679 */
2680 if (udc->stopped) {
2681 pr_debug("gadget already stopped, leaving early\n");
2682 udc->already_stopped = 1;
2683 return 0;
2684 }
2685
2686 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2687 pr_debug("gadget not in device mode, leaving early\n");
2688 return 0;
2689 }
2690
2691 /* stop the controller */
2692 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2693 fsl_writel(usbcmd, &dr_regs->usbcmd);
2694
2695 udc->stopped = 1;
2696
2697 pr_info("USB Gadget suspended\n");
2698
2699 return 0;
2700}
2701
2702static int fsl_udc_otg_resume(struct device *dev)
2703{
2704 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2705 udc_controller->stopped, udc_controller->already_stopped);
2706
2707 /*
2708 * If the controller was stopped at suspend time, then
2709 * don't resume it now.
2710 */
2711 if (udc_controller->already_stopped) {
2712 udc_controller->already_stopped = 0;
2713 pr_debug("gadget was already stopped, leaving early\n");
2714 return 0;
2715 }
2716
2717 pr_info("USB Gadget resume\n");
2718
2719 return fsl_udc_resume(NULL);
2720}
b504882d
LY		 2721/*-------------------------------------------------------------------------
2722 Register entry point for the peripheral controller driver
2723--------------------------------------------------------------------------*/
f0ea8834
PC		 2724static const struct platform_device_id fsl_udc_devtype[] = {
2725 {
2726 .name = "imx-udc-mx27",
2727 }, {
2728 .name = "imx-udc-mx51",
2729 }, {
2730 /* sentinel */
2731 }
2732};
2733MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
b504882d 2734static struct platform_driver udc_driver = {
f0ea8834
PC		 2735 .remove = __exit_p(fsl_udc_remove),
2736 /* Just for FSL i.mx SoC currently */
2737 .id_table = fsl_udc_devtype,
b504882d 2738 /* these suspend and resume are not usb suspend and resume */
f0ea8834
PC		 2739 .suspend = fsl_udc_suspend,
2740 .resume = fsl_udc_resume,
2741 .driver = {
2742 .name = (char *)driver_name,
2743 .owner = THIS_MODULE,
2744 /* udc suspend/resume called from OTG driver */
2745 .suspend = fsl_udc_otg_suspend,
2746 .resume = fsl_udc_otg_resume,
b504882d
LY		 2747 },
2748};
2749
2750static int __init udc_init(void)
2751{
2752 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2753 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2754}
2755
2756module_init(udc_init);
2757
2758static void __exit udc_exit(void)
2759{
2760 platform_driver_unregister(&udc_driver);
6f8aa65b 2761 printk(KERN_WARNING "%s unregistered\n", driver_desc);
b504882d
LY		 2762}
2763
2764module_exit(udc_exit);
2765
2766MODULE_DESCRIPTION(DRIVER_DESC);
2767MODULE_AUTHOR(DRIVER_AUTHOR);
2768MODULE_LICENSE("GPL");
f34c32f1 2769MODULE_ALIAS("platform:fsl-usb2-udc");
Linux kernel - Deliverables
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