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0fe6f1d1 YHC |
1 | /* |
2 | * Fusb300 UDC (USB gadget) | |
3 | * | |
4 | * Copyright (C) 2010 Faraday Technology Corp. | |
5 | * | |
6 | * Author : Yuan-hsin Chen <yhchen@faraday-tech.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
0fe6f1d1 YHC |
11 | */ |
12 | ||
13 | ||
14 | #ifndef __FUSB300_UDC_H__ | |
15 | #define __FUSB300_UDC_H_ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | ||
19 | #define FUSB300_OFFSET_GCR 0x00 | |
20 | #define FUSB300_OFFSET_GTM 0x04 | |
21 | #define FUSB300_OFFSET_DAR 0x08 | |
22 | #define FUSB300_OFFSET_CSR 0x0C | |
23 | #define FUSB300_OFFSET_CXPORT 0x10 | |
24 | #define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30) | |
25 | #define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30) | |
26 | #define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30) | |
27 | #define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30) | |
28 | #define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30) | |
29 | #define FUSB300_OFFSET_HSPTM 0x300 | |
30 | #define FUSB300_OFFSET_HSCR 0x304 | |
31 | #define FUSB300_OFFSET_SSCR0 0x308 | |
32 | #define FUSB300_OFFSET_SSCR1 0x30C | |
33 | #define FUSB300_OFFSET_TT 0x310 | |
34 | #define FUSB300_OFFSET_DEVNOTF 0x314 | |
35 | #define FUSB300_OFFSET_DNC1 0x318 | |
36 | #define FUSB300_OFFSET_CS 0x31C | |
37 | #define FUSB300_OFFSET_SOF 0x324 | |
38 | #define FUSB300_OFFSET_EFCS 0x328 | |
39 | #define FUSB300_OFFSET_IGR0 0x400 | |
40 | #define FUSB300_OFFSET_IGR1 0x404 | |
41 | #define FUSB300_OFFSET_IGR2 0x408 | |
42 | #define FUSB300_OFFSET_IGR3 0x40C | |
43 | #define FUSB300_OFFSET_IGR4 0x410 | |
44 | #define FUSB300_OFFSET_IGR5 0x414 | |
45 | #define FUSB300_OFFSET_IGER0 0x420 | |
46 | #define FUSB300_OFFSET_IGER1 0x424 | |
47 | #define FUSB300_OFFSET_IGER2 0x428 | |
48 | #define FUSB300_OFFSET_IGER3 0x42C | |
49 | #define FUSB300_OFFSET_IGER4 0x430 | |
50 | #define FUSB300_OFFSET_IGER5 0x434 | |
51 | #define FUSB300_OFFSET_DMAHMER 0x500 | |
52 | #define FUSB300_OFFSET_EPPRDRDY 0x504 | |
53 | #define FUSB300_OFFSET_DMAEPMR 0x508 | |
54 | #define FUSB300_OFFSET_DMAENR 0x50C | |
55 | #define FUSB300_OFFSET_DMAAPR 0x510 | |
56 | #define FUSB300_OFFSET_AHBCR 0x514 | |
57 | #define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10) | |
58 | #define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10) | |
59 | #define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10) | |
60 | #define FUSB300_OFFSET_EPRD_PTR(n) (0x52C + (n - 1) * 0x10) | |
61 | #define FUSB300_OFFSET_BUFDBG_START 0x800 | |
62 | #define FUSB300_OFFSET_BUFDBG_END 0xBFC | |
63 | #define FUSB300_OFFSET_EPPORT(n) (0x1010 + (n - 1) * 0x10) | |
64 | ||
65 | /* | |
66 | * * Global Control Register (offset = 000H) | |
67 | * */ | |
68 | #define FUSB300_GCR_SF_RST (1 << 8) | |
69 | #define FUSB300_GCR_VBUS_STATUS (1 << 7) | |
70 | #define FUSB300_GCR_FORCE_HS_SUSP (1 << 6) | |
71 | #define FUSB300_GCR_SYNC_FIFO1_CLR (1 << 5) | |
72 | #define FUSB300_GCR_SYNC_FIFO0_CLR (1 << 4) | |
73 | #define FUSB300_GCR_FIFOCLR (1 << 3) | |
74 | #define FUSB300_GCR_GLINTEN (1 << 2) | |
75 | #define FUSB300_GCR_DEVEN_FS 0x3 | |
76 | #define FUSB300_GCR_DEVEN_HS 0x2 | |
77 | #define FUSB300_GCR_DEVEN_SS 0x1 | |
78 | #define FUSB300_GCR_DEVDIS 0x0 | |
79 | #define FUSB300_GCR_DEVEN_MSK 0x3 | |
80 | ||
81 | ||
82 | /* | |
83 | * *Global Test Mode (offset = 004H) | |
84 | * */ | |
85 | #define FUSB300_GTM_TST_DIS_SOFGEN (1 << 16) | |
86 | #define FUSB300_GTM_TST_CUR_EP_ENTRY(n) ((n & 0xF) << 12) | |
87 | #define FUSB300_GTM_TST_EP_ENTRY(n) ((n & 0xF) << 8) | |
88 | #define FUSB300_GTM_TST_EP_NUM(n) ((n & 0xF) << 4) | |
89 | #define FUSB300_GTM_TST_FIFO_DEG (1 << 1) | |
90 | #define FUSB300_GTM_TSTMODE (1 << 0) | |
91 | ||
92 | /* | |
93 | * * Device Address Register (offset = 008H) | |
94 | * */ | |
95 | #define FUSB300_DAR_SETCONFG (1 << 7) | |
96 | #define FUSB300_DAR_DRVADDR(x) (x & 0x7F) | |
97 | #define FUSB300_DAR_DRVADDR_MSK 0x7F | |
98 | ||
99 | /* | |
100 | * *Control Transfer Configuration and Status Register | |
101 | * (CX_Config_Status, offset = 00CH) | |
102 | * */ | |
103 | #define FUSB300_CSR_LEN(x) ((x & 0xFFFF) << 8) | |
104 | #define FUSB300_CSR_LEN_MSK (0xFFFF << 8) | |
105 | #define FUSB300_CSR_EMP (1 << 4) | |
106 | #define FUSB300_CSR_FUL (1 << 3) | |
107 | #define FUSB300_CSR_CLR (1 << 2) | |
108 | #define FUSB300_CSR_STL (1 << 1) | |
109 | #define FUSB300_CSR_DONE (1 << 0) | |
110 | ||
111 | /* | |
112 | * * EPn Setting 0 (EPn_SET0, offset = 020H+(n-1)*30H, n=1~15 ) | |
113 | * */ | |
114 | #define FUSB300_EPSET0_CLRSEQNUM (1 << 2) | |
115 | #define FUSB300_EPSET0_EPn_TX0BYTE (1 << 1) | |
116 | #define FUSB300_EPSET0_STL (1 << 0) | |
117 | ||
118 | /* | |
119 | * * EPn Setting 1 (EPn_SET1, offset = 024H+(n-1)*30H, n=1~15) | |
120 | * */ | |
121 | #define FUSB300_EPSET1_START_ENTRY(x) ((x & 0xFF) << 24) | |
122 | #define FUSB300_EPSET1_START_ENTRY_MSK (0xFF << 24) | |
123 | #define FUSB300_EPSET1_FIFOENTRY(x) ((x & 0x1F) << 12) | |
124 | #define FUSB300_EPSET1_FIFOENTRY_MSK (0x1f << 12) | |
125 | #define FUSB300_EPSET1_INTERVAL(x) ((x & 0x7) << 6) | |
126 | #define FUSB300_EPSET1_BWNUM(x) ((x & 0x3) << 4) | |
127 | #define FUSB300_EPSET1_TYPEISO (1 << 2) | |
128 | #define FUSB300_EPSET1_TYPEBLK (2 << 2) | |
129 | #define FUSB300_EPSET1_TYPEINT (3 << 2) | |
130 | #define FUSB300_EPSET1_TYPE(x) ((x & 0x3) << 2) | |
131 | #define FUSB300_EPSET1_TYPE_MSK (0x3 << 2) | |
132 | #define FUSB300_EPSET1_DIROUT (0 << 1) | |
133 | #define FUSB300_EPSET1_DIRIN (1 << 1) | |
134 | #define FUSB300_EPSET1_DIR(x) ((x & 0x1) << 1) | |
135 | #define FUSB300_EPSET1_DIRIN (1 << 1) | |
136 | #define FUSB300_EPSET1_DIR_MSK ((0x1) << 1) | |
137 | #define FUSB300_EPSET1_ACTDIS 0 | |
138 | #define FUSB300_EPSET1_ACTEN 1 | |
139 | ||
140 | /* | |
141 | * *EPn Setting 2 (EPn_SET2, offset = 028H+(n-1)*30H, n=1~15) | |
142 | * */ | |
143 | #define FUSB300_EPSET2_ADDROFS(x) ((x & 0x7FFF) << 16) | |
144 | #define FUSB300_EPSET2_ADDROFS_MSK (0x7fff << 16) | |
145 | #define FUSB300_EPSET2_MPS(x) (x & 0x7FF) | |
146 | #define FUSB300_EPSET2_MPS_MSK 0x7FF | |
147 | ||
148 | /* | |
149 | * * EPn FIFO Register (offset = 2cH+(n-1)*30H) | |
150 | * */ | |
151 | #define FUSB300_FFR_RST (1 << 31) | |
152 | #define FUSB300_FF_FUL (1 << 30) | |
153 | #define FUSB300_FF_EMPTY (1 << 29) | |
154 | #define FUSB300_FFR_BYCNT 0x1FFFF | |
155 | ||
156 | /* | |
157 | * *EPn Stream ID (EPn_STR_ID, offset = 040H+(n-1)*30H, n=1~15) | |
158 | * */ | |
159 | #define FUSB300_STRID_STREN (1 << 16) | |
160 | #define FUSB300_STRID_STRID(x) (x & 0xFFFF) | |
161 | ||
162 | /* | |
163 | * *HS PHY Test Mode (offset = 300H) | |
164 | * */ | |
165 | #define FUSB300_HSPTM_TSTPKDONE (1 << 4) | |
166 | #define FUSB300_HSPTM_TSTPKT (1 << 3) | |
167 | #define FUSB300_HSPTM_TSTSET0NAK (1 << 2) | |
168 | #define FUSB300_HSPTM_TSTKSTA (1 << 1) | |
169 | #define FUSB300_HSPTM_TSTJSTA (1 << 0) | |
170 | ||
171 | /* | |
172 | * *HS Control Register (offset = 304H) | |
173 | * */ | |
174 | #define FUSB300_HSCR_HS_LPM_PERMIT (1 << 8) | |
175 | #define FUSB300_HSCR_HS_LPM_RMWKUP (1 << 7) | |
176 | #define FUSB300_HSCR_CAP_LPM_RMWKUP (1 << 6) | |
177 | #define FUSB300_HSCR_HS_GOSUSP (1 << 5) | |
178 | #define FUSB300_HSCR_HS_GORMWKU (1 << 4) | |
179 | #define FUSB300_HSCR_CAP_RMWKUP (1 << 3) | |
180 | #define FUSB300_HSCR_IDLECNT_0MS 0 | |
181 | #define FUSB300_HSCR_IDLECNT_1MS 1 | |
182 | #define FUSB300_HSCR_IDLECNT_2MS 2 | |
183 | #define FUSB300_HSCR_IDLECNT_3MS 3 | |
184 | #define FUSB300_HSCR_IDLECNT_4MS 4 | |
185 | #define FUSB300_HSCR_IDLECNT_5MS 5 | |
186 | #define FUSB300_HSCR_IDLECNT_6MS 6 | |
187 | #define FUSB300_HSCR_IDLECNT_7MS 7 | |
188 | ||
189 | /* | |
190 | * * SS Controller Register 0 (offset = 308H) | |
191 | * */ | |
192 | #define FUSB300_SSCR0_MAX_INTERVAL(x) ((x & 0x7) << 4) | |
193 | #define FUSB300_SSCR0_U2_FUN_EN (1 << 1) | |
194 | #define FUSB300_SSCR0_U1_FUN_EN (1 << 0) | |
195 | ||
196 | /* | |
197 | * * SS Controller Register 1 (offset = 30CH) | |
198 | * */ | |
199 | #define FUSB300_SSCR1_GO_U3_DONE (1 << 8) | |
200 | #define FUSB300_SSCR1_TXDEEMPH_LEVEL (1 << 7) | |
201 | #define FUSB300_SSCR1_DIS_SCRMB (1 << 6) | |
202 | #define FUSB300_SSCR1_FORCE_RECOVERY (1 << 5) | |
203 | #define FUSB300_SSCR1_U3_WAKEUP_EN (1 << 4) | |
204 | #define FUSB300_SSCR1_U2_EXIT_EN (1 << 3) | |
205 | #define FUSB300_SSCR1_U1_EXIT_EN (1 << 2) | |
206 | #define FUSB300_SSCR1_U2_ENTRY_EN (1 << 1) | |
207 | #define FUSB300_SSCR1_U1_ENTRY_EN (1 << 0) | |
208 | ||
209 | /* | |
210 | * *SS Controller Register 2 (offset = 310H) | |
211 | * */ | |
212 | #define FUSB300_SSCR2_SS_TX_SWING (1 << 25) | |
213 | #define FUSB300_SSCR2_FORCE_LINKPM_ACCEPT (1 << 24) | |
214 | #define FUSB300_SSCR2_U2_INACT_TIMEOUT(x) ((x & 0xFF) << 16) | |
215 | #define FUSB300_SSCR2_U1TIMEOUT(x) ((x & 0xFF) << 8) | |
216 | #define FUSB300_SSCR2_U2TIMEOUT(x) (x & 0xFF) | |
217 | ||
218 | /* | |
219 | * *SS Device Notification Control (DEV_NOTF, offset = 314H) | |
220 | * */ | |
221 | #define FUSB300_DEVNOTF_CONTEXT0(x) ((x & 0xFFFFFF) << 8) | |
222 | #define FUSB300_DEVNOTF_TYPE_DIS 0 | |
223 | #define FUSB300_DEVNOTF_TYPE_FUNCWAKE 1 | |
224 | #define FUSB300_DEVNOTF_TYPE_LTM 2 | |
225 | #define FUSB300_DEVNOTF_TYPE_BUSINT_ADJMSG 3 | |
226 | ||
227 | /* | |
228 | * *BFM Arbiter Priority Register (BFM_ARB offset = 31CH) | |
229 | * */ | |
230 | #define FUSB300_BFMARB_ARB_M1 (1 << 3) | |
231 | #define FUSB300_BFMARB_ARB_M0 (1 << 2) | |
232 | #define FUSB300_BFMARB_ARB_S1 (1 << 1) | |
233 | #define FUSB300_BFMARB_ARB_S0 1 | |
234 | ||
235 | /* | |
236 | * *Vendor Specific IO Control Register (offset = 320H) | |
237 | * */ | |
238 | #define FUSB300_VSIC_VCTLOAD_N (1 << 8) | |
239 | #define FUSB300_VSIC_VCTL(x) (x & 0x3F) | |
240 | ||
241 | /* | |
242 | * *SOF Mask Timer (offset = 324H) | |
243 | * */ | |
244 | #define FUSB300_SOF_MASK_TIMER_HS 0x044c | |
245 | #define FUSB300_SOF_MASK_TIMER_FS 0x2710 | |
246 | ||
247 | /* | |
248 | * *Error Flag and Control Status (offset = 328H) | |
249 | * */ | |
250 | #define FUSB300_EFCS_PM_STATE_U3 3 | |
251 | #define FUSB300_EFCS_PM_STATE_U2 2 | |
252 | #define FUSB300_EFCS_PM_STATE_U1 1 | |
253 | #define FUSB300_EFCS_PM_STATE_U0 0 | |
254 | ||
255 | /* | |
256 | * *Interrupt Group 0 Register (offset = 400H) | |
257 | * */ | |
258 | #define FUSB300_IGR0_EP15_PRD_INT (1 << 31) | |
259 | #define FUSB300_IGR0_EP14_PRD_INT (1 << 30) | |
260 | #define FUSB300_IGR0_EP13_PRD_INT (1 << 29) | |
261 | #define FUSB300_IGR0_EP12_PRD_INT (1 << 28) | |
262 | #define FUSB300_IGR0_EP11_PRD_INT (1 << 27) | |
263 | #define FUSB300_IGR0_EP10_PRD_INT (1 << 26) | |
264 | #define FUSB300_IGR0_EP9_PRD_INT (1 << 25) | |
265 | #define FUSB300_IGR0_EP8_PRD_INT (1 << 24) | |
266 | #define FUSB300_IGR0_EP7_PRD_INT (1 << 23) | |
267 | #define FUSB300_IGR0_EP6_PRD_INT (1 << 22) | |
268 | #define FUSB300_IGR0_EP5_PRD_INT (1 << 21) | |
269 | #define FUSB300_IGR0_EP4_PRD_INT (1 << 20) | |
270 | #define FUSB300_IGR0_EP3_PRD_INT (1 << 19) | |
271 | #define FUSB300_IGR0_EP2_PRD_INT (1 << 18) | |
272 | #define FUSB300_IGR0_EP1_PRD_INT (1 << 17) | |
273 | #define FUSB300_IGR0_EPn_PRD_INT(n) (1 << (n + 16)) | |
274 | ||
275 | #define FUSB300_IGR0_EP15_FIFO_INT (1 << 15) | |
276 | #define FUSB300_IGR0_EP14_FIFO_INT (1 << 14) | |
277 | #define FUSB300_IGR0_EP13_FIFO_INT (1 << 13) | |
278 | #define FUSB300_IGR0_EP12_FIFO_INT (1 << 12) | |
279 | #define FUSB300_IGR0_EP11_FIFO_INT (1 << 11) | |
280 | #define FUSB300_IGR0_EP10_FIFO_INT (1 << 10) | |
281 | #define FUSB300_IGR0_EP9_FIFO_INT (1 << 9) | |
282 | #define FUSB300_IGR0_EP8_FIFO_INT (1 << 8) | |
283 | #define FUSB300_IGR0_EP7_FIFO_INT (1 << 7) | |
284 | #define FUSB300_IGR0_EP6_FIFO_INT (1 << 6) | |
285 | #define FUSB300_IGR0_EP5_FIFO_INT (1 << 5) | |
286 | #define FUSB300_IGR0_EP4_FIFO_INT (1 << 4) | |
287 | #define FUSB300_IGR0_EP3_FIFO_INT (1 << 3) | |
288 | #define FUSB300_IGR0_EP2_FIFO_INT (1 << 2) | |
289 | #define FUSB300_IGR0_EP1_FIFO_INT (1 << 1) | |
290 | #define FUSB300_IGR0_EPn_FIFO_INT(n) (1 << n) | |
291 | ||
292 | /* | |
293 | * *Interrupt Group 1 Register (offset = 404H) | |
294 | * */ | |
295 | #define FUSB300_IGR1_INTGRP5 (1 << 31) | |
296 | #define FUSB300_IGR1_VBUS_CHG_INT (1 << 30) | |
297 | #define FUSB300_IGR1_SYNF1_EMPTY_INT (1 << 29) | |
298 | #define FUSB300_IGR1_SYNF0_EMPTY_INT (1 << 28) | |
299 | #define FUSB300_IGR1_U3_EXIT_FAIL_INT (1 << 27) | |
300 | #define FUSB300_IGR1_U2_EXIT_FAIL_INT (1 << 26) | |
301 | #define FUSB300_IGR1_U1_EXIT_FAIL_INT (1 << 25) | |
302 | #define FUSB300_IGR1_U2_ENTRY_FAIL_INT (1 << 24) | |
303 | #define FUSB300_IGR1_U1_ENTRY_FAIL_INT (1 << 23) | |
304 | #define FUSB300_IGR1_U3_EXIT_INT (1 << 22) | |
305 | #define FUSB300_IGR1_U2_EXIT_INT (1 << 21) | |
306 | #define FUSB300_IGR1_U1_EXIT_INT (1 << 20) | |
307 | #define FUSB300_IGR1_U3_ENTRY_INT (1 << 19) | |
308 | #define FUSB300_IGR1_U2_ENTRY_INT (1 << 18) | |
309 | #define FUSB300_IGR1_U1_ENTRY_INT (1 << 17) | |
310 | #define FUSB300_IGR1_HOT_RST_INT (1 << 16) | |
311 | #define FUSB300_IGR1_WARM_RST_INT (1 << 15) | |
312 | #define FUSB300_IGR1_RESM_INT (1 << 14) | |
313 | #define FUSB300_IGR1_SUSP_INT (1 << 13) | |
314 | #define FUSB300_IGR1_HS_LPM_INT (1 << 12) | |
315 | #define FUSB300_IGR1_USBRST_INT (1 << 11) | |
316 | #define FUSB300_IGR1_DEV_MODE_CHG_INT (1 << 9) | |
317 | #define FUSB300_IGR1_CX_COMABT_INT (1 << 8) | |
318 | #define FUSB300_IGR1_CX_COMFAIL_INT (1 << 7) | |
319 | #define FUSB300_IGR1_CX_CMDEND_INT (1 << 6) | |
320 | #define FUSB300_IGR1_CX_OUT_INT (1 << 5) | |
321 | #define FUSB300_IGR1_CX_IN_INT (1 << 4) | |
322 | #define FUSB300_IGR1_CX_SETUP_INT (1 << 3) | |
323 | #define FUSB300_IGR1_INTGRP4 (1 << 2) | |
324 | #define FUSB300_IGR1_INTGRP3 (1 << 1) | |
325 | #define FUSB300_IGR1_INTGRP2 (1 << 0) | |
326 | ||
327 | /* | |
328 | * *Interrupt Group 2 Register (offset = 408H) | |
329 | * */ | |
330 | #define FUSB300_IGR2_EP6_STR_ACCEPT_INT (1 << 29) | |
331 | #define FUSB300_IGR2_EP6_STR_RESUME_INT (1 << 28) | |
332 | #define FUSB300_IGR2_EP6_STR_REQ_INT (1 << 27) | |
333 | #define FUSB300_IGR2_EP6_STR_NOTRDY_INT (1 << 26) | |
334 | #define FUSB300_IGR2_EP6_STR_PRIME_INT (1 << 25) | |
335 | #define FUSB300_IGR2_EP5_STR_ACCEPT_INT (1 << 24) | |
336 | #define FUSB300_IGR2_EP5_STR_RESUME_INT (1 << 23) | |
337 | #define FUSB300_IGR2_EP5_STR_REQ_INT (1 << 22) | |
338 | #define FUSB300_IGR2_EP5_STR_NOTRDY_INT (1 << 21) | |
339 | #define FUSB300_IGR2_EP5_STR_PRIME_INT (1 << 20) | |
340 | #define FUSB300_IGR2_EP4_STR_ACCEPT_INT (1 << 19) | |
341 | #define FUSB300_IGR2_EP4_STR_RESUME_INT (1 << 18) | |
342 | #define FUSB300_IGR2_EP4_STR_REQ_INT (1 << 17) | |
343 | #define FUSB300_IGR2_EP4_STR_NOTRDY_INT (1 << 16) | |
344 | #define FUSB300_IGR2_EP4_STR_PRIME_INT (1 << 15) | |
345 | #define FUSB300_IGR2_EP3_STR_ACCEPT_INT (1 << 14) | |
346 | #define FUSB300_IGR2_EP3_STR_RESUME_INT (1 << 13) | |
347 | #define FUSB300_IGR2_EP3_STR_REQ_INT (1 << 12) | |
348 | #define FUSB300_IGR2_EP3_STR_NOTRDY_INT (1 << 11) | |
349 | #define FUSB300_IGR2_EP3_STR_PRIME_INT (1 << 10) | |
350 | #define FUSB300_IGR2_EP2_STR_ACCEPT_INT (1 << 9) | |
351 | #define FUSB300_IGR2_EP2_STR_RESUME_INT (1 << 8) | |
352 | #define FUSB300_IGR2_EP2_STR_REQ_INT (1 << 7) | |
353 | #define FUSB300_IGR2_EP2_STR_NOTRDY_INT (1 << 6) | |
354 | #define FUSB300_IGR2_EP2_STR_PRIME_INT (1 << 5) | |
355 | #define FUSB300_IGR2_EP1_STR_ACCEPT_INT (1 << 4) | |
356 | #define FUSB300_IGR2_EP1_STR_RESUME_INT (1 << 3) | |
357 | #define FUSB300_IGR2_EP1_STR_REQ_INT (1 << 2) | |
358 | #define FUSB300_IGR2_EP1_STR_NOTRDY_INT (1 << 1) | |
359 | #define FUSB300_IGR2_EP1_STR_PRIME_INT (1 << 0) | |
360 | ||
361 | #define FUSB300_IGR2_EP_STR_ACCEPT_INT(n) (1 << (5 * n - 1)) | |
362 | #define FUSB300_IGR2_EP_STR_RESUME_INT(n) (1 << (5 * n - 2)) | |
363 | #define FUSB300_IGR2_EP_STR_REQ_INT(n) (1 << (5 * n - 3)) | |
364 | #define FUSB300_IGR2_EP_STR_NOTRDY_INT(n) (1 << (5 * n - 4)) | |
365 | #define FUSB300_IGR2_EP_STR_PRIME_INT(n) (1 << (5 * n - 5)) | |
366 | ||
367 | /* | |
368 | * *Interrupt Group 3 Register (offset = 40CH) | |
369 | * */ | |
370 | #define FUSB300_IGR3_EP12_STR_ACCEPT_INT (1 << 29) | |
371 | #define FUSB300_IGR3_EP12_STR_RESUME_INT (1 << 28) | |
372 | #define FUSB300_IGR3_EP12_STR_REQ_INT (1 << 27) | |
373 | #define FUSB300_IGR3_EP12_STR_NOTRDY_INT (1 << 26) | |
374 | #define FUSB300_IGR3_EP12_STR_PRIME_INT (1 << 25) | |
375 | #define FUSB300_IGR3_EP11_STR_ACCEPT_INT (1 << 24) | |
376 | #define FUSB300_IGR3_EP11_STR_RESUME_INT (1 << 23) | |
377 | #define FUSB300_IGR3_EP11_STR_REQ_INT (1 << 22) | |
378 | #define FUSB300_IGR3_EP11_STR_NOTRDY_INT (1 << 21) | |
379 | #define FUSB300_IGR3_EP11_STR_PRIME_INT (1 << 20) | |
380 | #define FUSB300_IGR3_EP10_STR_ACCEPT_INT (1 << 19) | |
381 | #define FUSB300_IGR3_EP10_STR_RESUME_INT (1 << 18) | |
382 | #define FUSB300_IGR3_EP10_STR_REQ_INT (1 << 17) | |
383 | #define FUSB300_IGR3_EP10_STR_NOTRDY_INT (1 << 16) | |
384 | #define FUSB300_IGR3_EP10_STR_PRIME_INT (1 << 15) | |
385 | #define FUSB300_IGR3_EP9_STR_ACCEPT_INT (1 << 14) | |
386 | #define FUSB300_IGR3_EP9_STR_RESUME_INT (1 << 13) | |
387 | #define FUSB300_IGR3_EP9_STR_REQ_INT (1 << 12) | |
388 | #define FUSB300_IGR3_EP9_STR_NOTRDY_INT (1 << 11) | |
389 | #define FUSB300_IGR3_EP9_STR_PRIME_INT (1 << 10) | |
390 | #define FUSB300_IGR3_EP8_STR_ACCEPT_INT (1 << 9) | |
391 | #define FUSB300_IGR3_EP8_STR_RESUME_INT (1 << 8) | |
392 | #define FUSB300_IGR3_EP8_STR_REQ_INT (1 << 7) | |
393 | #define FUSB300_IGR3_EP8_STR_NOTRDY_INT (1 << 6) | |
394 | #define FUSB300_IGR3_EP8_STR_PRIME_INT (1 << 5) | |
395 | #define FUSB300_IGR3_EP7_STR_ACCEPT_INT (1 << 4) | |
396 | #define FUSB300_IGR3_EP7_STR_RESUME_INT (1 << 3) | |
397 | #define FUSB300_IGR3_EP7_STR_REQ_INT (1 << 2) | |
398 | #define FUSB300_IGR3_EP7_STR_NOTRDY_INT (1 << 1) | |
399 | #define FUSB300_IGR3_EP7_STR_PRIME_INT (1 << 0) | |
400 | ||
401 | #define FUSB300_IGR3_EP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1)) | |
402 | #define FUSB300_IGR3_EP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2)) | |
403 | #define FUSB300_IGR3_EP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3)) | |
404 | #define FUSB300_IGR3_EP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4)) | |
405 | #define FUSB300_IGR3_EP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5)) | |
406 | ||
407 | /* | |
408 | * *Interrupt Group 4 Register (offset = 410H) | |
409 | * */ | |
410 | #define FUSB300_IGR4_EP15_RX0_INT (1 << 31) | |
411 | #define FUSB300_IGR4_EP14_RX0_INT (1 << 30) | |
412 | #define FUSB300_IGR4_EP13_RX0_INT (1 << 29) | |
413 | #define FUSB300_IGR4_EP12_RX0_INT (1 << 28) | |
414 | #define FUSB300_IGR4_EP11_RX0_INT (1 << 27) | |
415 | #define FUSB300_IGR4_EP10_RX0_INT (1 << 26) | |
416 | #define FUSB300_IGR4_EP9_RX0_INT (1 << 25) | |
417 | #define FUSB300_IGR4_EP8_RX0_INT (1 << 24) | |
418 | #define FUSB300_IGR4_EP7_RX0_INT (1 << 23) | |
419 | #define FUSB300_IGR4_EP6_RX0_INT (1 << 22) | |
420 | #define FUSB300_IGR4_EP5_RX0_INT (1 << 21) | |
421 | #define FUSB300_IGR4_EP4_RX0_INT (1 << 20) | |
422 | #define FUSB300_IGR4_EP3_RX0_INT (1 << 19) | |
423 | #define FUSB300_IGR4_EP2_RX0_INT (1 << 18) | |
424 | #define FUSB300_IGR4_EP1_RX0_INT (1 << 17) | |
425 | #define FUSB300_IGR4_EP_RX0_INT(x) (1 << (x + 16)) | |
426 | #define FUSB300_IGR4_EP15_STR_ACCEPT_INT (1 << 14) | |
427 | #define FUSB300_IGR4_EP15_STR_RESUME_INT (1 << 13) | |
428 | #define FUSB300_IGR4_EP15_STR_REQ_INT (1 << 12) | |
429 | #define FUSB300_IGR4_EP15_STR_NOTRDY_INT (1 << 11) | |
430 | #define FUSB300_IGR4_EP15_STR_PRIME_INT (1 << 10) | |
431 | #define FUSB300_IGR4_EP14_STR_ACCEPT_INT (1 << 9) | |
432 | #define FUSB300_IGR4_EP14_STR_RESUME_INT (1 << 8) | |
433 | #define FUSB300_IGR4_EP14_STR_REQ_INT (1 << 7) | |
434 | #define FUSB300_IGR4_EP14_STR_NOTRDY_INT (1 << 6) | |
435 | #define FUSB300_IGR4_EP14_STR_PRIME_INT (1 << 5) | |
436 | #define FUSB300_IGR4_EP13_STR_ACCEPT_INT (1 << 4) | |
437 | #define FUSB300_IGR4_EP13_STR_RESUME_INT (1 << 3) | |
438 | #define FUSB300_IGR4_EP13_STR_REQ_INT (1 << 2) | |
439 | #define FUSB300_IGR4_EP13_STR_NOTRDY_INT (1 << 1) | |
440 | #define FUSB300_IGR4_EP13_STR_PRIME_INT (1 << 0) | |
441 | ||
442 | #define FUSB300_IGR4_EP_STR_ACCEPT_INT(n) (1 << (5 * (n - 12) - 1)) | |
443 | #define FUSB300_IGR4_EP_STR_RESUME_INT(n) (1 << (5 * (n - 12) - 2)) | |
444 | #define FUSB300_IGR4_EP_STR_REQ_INT(n) (1 << (5 * (n - 12) - 3)) | |
445 | #define FUSB300_IGR4_EP_STR_NOTRDY_INT(n) (1 << (5 * (n - 12) - 4)) | |
446 | #define FUSB300_IGR4_EP_STR_PRIME_INT(n) (1 << (5 * (n - 12) - 5)) | |
447 | ||
448 | /* | |
449 | * *Interrupt Group 5 Register (offset = 414H) | |
450 | * */ | |
451 | #define FUSB300_IGR5_EP_STL_INT(n) (1 << n) | |
452 | ||
453 | /* | |
454 | * *Interrupt Enable Group 0 Register (offset = 420H) | |
455 | * */ | |
456 | #define FUSB300_IGER0_EEP15_PRD_INT (1 << 31) | |
457 | #define FUSB300_IGER0_EEP14_PRD_INT (1 << 30) | |
458 | #define FUSB300_IGER0_EEP13_PRD_INT (1 << 29) | |
459 | #define FUSB300_IGER0_EEP12_PRD_INT (1 << 28) | |
460 | #define FUSB300_IGER0_EEP11_PRD_INT (1 << 27) | |
461 | #define FUSB300_IGER0_EEP10_PRD_INT (1 << 26) | |
462 | #define FUSB300_IGER0_EEP9_PRD_INT (1 << 25) | |
463 | #define FUSB300_IGER0_EP8_PRD_INT (1 << 24) | |
464 | #define FUSB300_IGER0_EEP7_PRD_INT (1 << 23) | |
465 | #define FUSB300_IGER0_EEP6_PRD_INT (1 << 22) | |
466 | #define FUSB300_IGER0_EEP5_PRD_INT (1 << 21) | |
467 | #define FUSB300_IGER0_EEP4_PRD_INT (1 << 20) | |
468 | #define FUSB300_IGER0_EEP3_PRD_INT (1 << 19) | |
469 | #define FUSB300_IGER0_EEP2_PRD_INT (1 << 18) | |
470 | #define FUSB300_IGER0_EEP1_PRD_INT (1 << 17) | |
471 | #define FUSB300_IGER0_EEPn_PRD_INT(n) (1 << (n + 16)) | |
472 | ||
473 | #define FUSB300_IGER0_EEP15_FIFO_INT (1 << 15) | |
474 | #define FUSB300_IGER0_EEP14_FIFO_INT (1 << 14) | |
475 | #define FUSB300_IGER0_EEP13_FIFO_INT (1 << 13) | |
476 | #define FUSB300_IGER0_EEP12_FIFO_INT (1 << 12) | |
477 | #define FUSB300_IGER0_EEP11_FIFO_INT (1 << 11) | |
478 | #define FUSB300_IGER0_EEP10_FIFO_INT (1 << 10) | |
479 | #define FUSB300_IGER0_EEP9_FIFO_INT (1 << 9) | |
480 | #define FUSB300_IGER0_EEP8_FIFO_INT (1 << 8) | |
481 | #define FUSB300_IGER0_EEP7_FIFO_INT (1 << 7) | |
482 | #define FUSB300_IGER0_EEP6_FIFO_INT (1 << 6) | |
483 | #define FUSB300_IGER0_EEP5_FIFO_INT (1 << 5) | |
484 | #define FUSB300_IGER0_EEP4_FIFO_INT (1 << 4) | |
485 | #define FUSB300_IGER0_EEP3_FIFO_INT (1 << 3) | |
486 | #define FUSB300_IGER0_EEP2_FIFO_INT (1 << 2) | |
487 | #define FUSB300_IGER0_EEP1_FIFO_INT (1 << 1) | |
488 | #define FUSB300_IGER0_EEPn_FIFO_INT(n) (1 << n) | |
489 | ||
490 | /* | |
491 | * *Interrupt Enable Group 1 Register (offset = 424H) | |
492 | * */ | |
493 | #define FUSB300_IGER1_EINT_GRP5 (1 << 31) | |
494 | #define FUSB300_IGER1_VBUS_CHG_INT (1 << 30) | |
495 | #define FUSB300_IGER1_SYNF1_EMPTY_INT (1 << 29) | |
496 | #define FUSB300_IGER1_SYNF0_EMPTY_INT (1 << 28) | |
497 | #define FUSB300_IGER1_U3_EXIT_FAIL_INT (1 << 27) | |
498 | #define FUSB300_IGER1_U2_EXIT_FAIL_INT (1 << 26) | |
499 | #define FUSB300_IGER1_U1_EXIT_FAIL_INT (1 << 25) | |
500 | #define FUSB300_IGER1_U2_ENTRY_FAIL_INT (1 << 24) | |
501 | #define FUSB300_IGER1_U1_ENTRY_FAIL_INT (1 << 23) | |
502 | #define FUSB300_IGER1_U3_EXIT_INT (1 << 22) | |
503 | #define FUSB300_IGER1_U2_EXIT_INT (1 << 21) | |
504 | #define FUSB300_IGER1_U1_EXIT_INT (1 << 20) | |
505 | #define FUSB300_IGER1_U3_ENTRY_INT (1 << 19) | |
506 | #define FUSB300_IGER1_U2_ENTRY_INT (1 << 18) | |
507 | #define FUSB300_IGER1_U1_ENTRY_INT (1 << 17) | |
508 | #define FUSB300_IGER1_HOT_RST_INT (1 << 16) | |
509 | #define FUSB300_IGER1_WARM_RST_INT (1 << 15) | |
510 | #define FUSB300_IGER1_RESM_INT (1 << 14) | |
511 | #define FUSB300_IGER1_SUSP_INT (1 << 13) | |
512 | #define FUSB300_IGER1_LPM_INT (1 << 12) | |
513 | #define FUSB300_IGER1_HS_RST_INT (1 << 11) | |
514 | #define FUSB300_IGER1_EDEV_MODE_CHG_INT (1 << 9) | |
515 | #define FUSB300_IGER1_CX_COMABT_INT (1 << 8) | |
516 | #define FUSB300_IGER1_CX_COMFAIL_INT (1 << 7) | |
517 | #define FUSB300_IGER1_CX_CMDEND_INT (1 << 6) | |
518 | #define FUSB300_IGER1_CX_OUT_INT (1 << 5) | |
519 | #define FUSB300_IGER1_CX_IN_INT (1 << 4) | |
520 | #define FUSB300_IGER1_CX_SETUP_INT (1 << 3) | |
521 | #define FUSB300_IGER1_INTGRP4 (1 << 2) | |
522 | #define FUSB300_IGER1_INTGRP3 (1 << 1) | |
523 | #define FUSB300_IGER1_INTGRP2 (1 << 0) | |
524 | ||
525 | /* | |
526 | * *Interrupt Enable Group 2 Register (offset = 428H) | |
527 | * */ | |
528 | #define FUSB300_IGER2_EEP_STR_ACCEPT_INT(n) (1 << (5 * n - 1)) | |
529 | #define FUSB300_IGER2_EEP_STR_RESUME_INT(n) (1 << (5 * n - 2)) | |
530 | #define FUSB300_IGER2_EEP_STR_REQ_INT(n) (1 << (5 * n - 3)) | |
531 | #define FUSB300_IGER2_EEP_STR_NOTRDY_INT(n) (1 << (5 * n - 4)) | |
532 | #define FUSB300_IGER2_EEP_STR_PRIME_INT(n) (1 << (5 * n - 5)) | |
533 | ||
534 | /* | |
535 | * *Interrupt Enable Group 3 Register (offset = 42CH) | |
536 | * */ | |
537 | ||
538 | #define FUSB300_IGER3_EEP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1)) | |
539 | #define FUSB300_IGER3_EEP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2)) | |
540 | #define FUSB300_IGER3_EEP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3)) | |
541 | #define FUSB300_IGER3_EEP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4)) | |
542 | #define FUSB300_IGER3_EEP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5)) | |
543 | ||
544 | /* | |
545 | * *Interrupt Enable Group 4 Register (offset = 430H) | |
546 | * */ | |
547 | ||
548 | #define FUSB300_IGER4_EEP_RX0_INT(n) (1 << (n + 16)) | |
549 | #define FUSB300_IGER4_EEP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1)) | |
550 | #define FUSB300_IGER4_EEP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2)) | |
551 | #define FUSB300_IGER4_EEP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3)) | |
552 | #define FUSB300_IGER4_EEP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4)) | |
553 | #define FUSB300_IGER4_EEP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5)) | |
554 | ||
555 | /* EP PRD Ready (EP_PRD_RDY, offset = 504H) */ | |
556 | ||
557 | #define FUSB300_EPPRDR_EP15_PRD_RDY (1 << 15) | |
558 | #define FUSB300_EPPRDR_EP14_PRD_RDY (1 << 14) | |
559 | #define FUSB300_EPPRDR_EP13_PRD_RDY (1 << 13) | |
560 | #define FUSB300_EPPRDR_EP12_PRD_RDY (1 << 12) | |
561 | #define FUSB300_EPPRDR_EP11_PRD_RDY (1 << 11) | |
562 | #define FUSB300_EPPRDR_EP10_PRD_RDY (1 << 10) | |
563 | #define FUSB300_EPPRDR_EP9_PRD_RDY (1 << 9) | |
564 | #define FUSB300_EPPRDR_EP8_PRD_RDY (1 << 8) | |
565 | #define FUSB300_EPPRDR_EP7_PRD_RDY (1 << 7) | |
566 | #define FUSB300_EPPRDR_EP6_PRD_RDY (1 << 6) | |
567 | #define FUSB300_EPPRDR_EP5_PRD_RDY (1 << 5) | |
568 | #define FUSB300_EPPRDR_EP4_PRD_RDY (1 << 4) | |
569 | #define FUSB300_EPPRDR_EP3_PRD_RDY (1 << 3) | |
570 | #define FUSB300_EPPRDR_EP2_PRD_RDY (1 << 2) | |
571 | #define FUSB300_EPPRDR_EP1_PRD_RDY (1 << 1) | |
572 | #define FUSB300_EPPRDR_EP_PRD_RDY(n) (1 << n) | |
573 | ||
574 | /* AHB Bus Control Register (offset = 514H) */ | |
575 | #define FUSB300_AHBBCR_S1_SPLIT_ON (1 << 17) | |
576 | #define FUSB300_AHBBCR_S0_SPLIT_ON (1 << 16) | |
577 | #define FUSB300_AHBBCR_S1_1entry (0 << 12) | |
578 | #define FUSB300_AHBBCR_S1_4entry (3 << 12) | |
579 | #define FUSB300_AHBBCR_S1_8entry (5 << 12) | |
580 | #define FUSB300_AHBBCR_S1_16entry (7 << 12) | |
581 | #define FUSB300_AHBBCR_S0_1entry (0 << 8) | |
582 | #define FUSB300_AHBBCR_S0_4entry (3 << 8) | |
583 | #define FUSB300_AHBBCR_S0_8entry (5 << 8) | |
584 | #define FUSB300_AHBBCR_S0_16entry (7 << 8) | |
585 | #define FUSB300_AHBBCR_M1_BURST_SINGLE (0 << 4) | |
586 | #define FUSB300_AHBBCR_M1_BURST_INCR (1 << 4) | |
587 | #define FUSB300_AHBBCR_M1_BURST_INCR4 (3 << 4) | |
588 | #define FUSB300_AHBBCR_M1_BURST_INCR8 (5 << 4) | |
589 | #define FUSB300_AHBBCR_M1_BURST_INCR16 (7 << 4) | |
590 | #define FUSB300_AHBBCR_M0_BURST_SINGLE 0 | |
591 | #define FUSB300_AHBBCR_M0_BURST_INCR 1 | |
592 | #define FUSB300_AHBBCR_M0_BURST_INCR4 3 | |
593 | #define FUSB300_AHBBCR_M0_BURST_INCR8 5 | |
594 | #define FUSB300_AHBBCR_M0_BURST_INCR16 7 | |
595 | #define FUSB300_IGER5_EEP_STL_INT(n) (1 << n) | |
596 | ||
597 | /* WORD 0 Data Structure of PRD Table */ | |
598 | #define FUSB300_EPPRD0_M (1 << 30) | |
599 | #define FUSB300_EPPRD0_O (1 << 29) | |
600 | /* The finished prd */ | |
601 | #define FUSB300_EPPRD0_F (1 << 28) | |
602 | #define FUSB300_EPPRD0_I (1 << 27) | |
603 | #define FUSB300_EPPRD0_A (1 << 26) | |
604 | /* To decide HW point to first prd at next time */ | |
605 | #define FUSB300_EPPRD0_L (1 << 25) | |
606 | #define FUSB300_EPPRD0_H (1 << 24) | |
607 | #define FUSB300_EPPRD0_BTC(n) (n & 0xFFFFFF) | |
608 | ||
609 | /*----------------------------------------------------------------------*/ | |
610 | #define FUSB300_MAX_NUM_EP 16 | |
611 | ||
612 | #define FUSB300_FIFO_ENTRY_NUM 8 | |
613 | #define FUSB300_MAX_FIFO_ENTRY 8 | |
614 | ||
615 | #define SS_CTL_MAX_PACKET_SIZE 0x200 | |
616 | #define SS_BULK_MAX_PACKET_SIZE 0x400 | |
617 | #define SS_INT_MAX_PACKET_SIZE 0x400 | |
618 | #define SS_ISO_MAX_PACKET_SIZE 0x400 | |
619 | ||
620 | #define HS_BULK_MAX_PACKET_SIZE 0x200 | |
621 | #define HS_CTL_MAX_PACKET_SIZE 0x40 | |
622 | #define HS_INT_MAX_PACKET_SIZE 0x400 | |
623 | #define HS_ISO_MAX_PACKET_SIZE 0x400 | |
624 | ||
625 | struct fusb300_ep_info { | |
626 | u8 epnum; | |
627 | u8 type; | |
628 | u8 interval; | |
629 | u8 dir_in; | |
630 | u16 maxpacket; | |
631 | u16 addrofs; | |
632 | u16 bw_num; | |
633 | }; | |
634 | ||
635 | struct fusb300_request { | |
636 | ||
637 | struct usb_request req; | |
638 | struct list_head queue; | |
639 | }; | |
640 | ||
641 | ||
642 | struct fusb300_ep { | |
643 | struct usb_ep ep; | |
644 | struct fusb300 *fusb300; | |
645 | ||
646 | struct list_head queue; | |
647 | unsigned stall:1; | |
648 | unsigned wedged:1; | |
649 | unsigned use_dma:1; | |
650 | ||
651 | unsigned char epnum; | |
652 | unsigned char type; | |
0fe6f1d1 YHC |
653 | }; |
654 | ||
655 | struct fusb300 { | |
656 | spinlock_t lock; | |
657 | void __iomem *reg; | |
658 | ||
659 | unsigned long irq_trigger; | |
660 | ||
661 | struct usb_gadget gadget; | |
662 | struct usb_gadget_driver *driver; | |
663 | ||
664 | struct fusb300_ep *ep[FUSB300_MAX_NUM_EP]; | |
665 | ||
666 | struct usb_request *ep0_req; /* for internal request */ | |
667 | __le16 ep0_data; | |
668 | u32 ep0_length; /* for internal request */ | |
669 | u8 ep0_dir; /* 0/0x80 out/in */ | |
670 | ||
671 | u8 fifo_entry_num; /* next start fifo entry */ | |
672 | u32 addrofs; /* next fifo address offset */ | |
673 | u8 reenum; /* if re-enumeration */ | |
674 | }; | |
675 | ||
8de94fff FB |
676 | #define to_fusb300(g) (container_of((g), struct fusb300, gadget)) |
677 | ||
0fe6f1d1 | 678 | #endif |