projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * linux/drivers/usb/gadget/lh7a40x_udc.h | |
| 3 | * Sharp LH7A40x on-chip full speed USB device controllers | |
| 4 | * | |
| 5 | * Copyright (C) 2004 Mikko Lahteenmaki, Nordic ID | |
| 6 | * Copyright (C) 2004 Bo Henriksen, Nordic ID | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License as published by | |
| 10 | * the Free Software Foundation; either version 2 of the License, or | |
| 11 | * (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | * | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef __LH7A40X_H_ | |
| 25 | #define __LH7A40X_H_ | |
| 26 | ||
| 1da177e4 LT |
27 | #include <linux/module.h> |
| 28 | #include <linux/kernel.h> | |
| 29 | #include <linux/ioport.h> | |
| 30 | #include <linux/types.h> | |
| 1da177e4 LT |
31 | #include <linux/errno.h> |
| 32 | #include <linux/delay.h> | |
| 33 | #include <linux/sched.h> | |
| 34 | #include <linux/slab.h> | |
| 35 | #include <linux/init.h> | |
| 36 | #include <linux/timer.h> | |
| 37 | #include <linux/list.h> | |
| 38 | #include <linux/interrupt.h> | |
| 39 | #include <linux/proc_fs.h> | |
| 40 | #include <linux/mm.h> | |
| 41 | #include <linux/device.h> | |
| 42 | #include <linux/dma-mapping.h> | |
| 43 | ||
| 44 | #include <asm/byteorder.h> | |
| 45 | #include <asm/dma.h> | |
| 46 | #include <asm/io.h> | |
| 47 | #include <asm/irq.h> | |
| 48 | #include <asm/system.h> | |
| 49 | #include <asm/unaligned.h> | |
| a09e64fb | 50 | #include <mach/hardware.h> |
| 1da177e4 | 51 | |
| 5f848137 | 52 | #include <linux/usb/ch9.h> |
| 9454a57a | 53 | #include <linux/usb/gadget.h> |
| 1da177e4 LT |
54 | |
| 55 | /* | |
| 56 | * Memory map | |
| 57 | */ | |
| 58 | ||
| 59 | #define USB_FA 0x80000200 // function address register | |
| 60 | #define USB_PM 0x80000204 // power management register | |
| 61 | ||
| 62 | #define USB_IN_INT 0x80000208 // IN interrupt register bank (EP0-EP3) | |
| 63 | #define USB_OUT_INT 0x80000210 // OUT interrupt register bank (EP2) | |
| 64 | #define USB_INT 0x80000218 // interrupt register bank | |
| 65 | ||
| 66 | #define USB_IN_INT_EN 0x8000021C // IN interrupt enable register bank | |
| 67 | #define USB_OUT_INT_EN 0x80000224 // OUT interrupt enable register bank | |
| 68 | #define USB_INT_EN 0x8000022C // USB interrupt enable register bank | |
| 69 | ||
| 70 | #define USB_FRM_NUM1 0x80000230 // Frame number1 register | |
| 71 | #define USB_FRM_NUM2 0x80000234 // Frame number2 register | |
| 72 | #define USB_INDEX 0x80000238 // index register | |
| 73 | ||
| 74 | #define USB_IN_MAXP 0x80000240 // IN MAXP register | |
| 75 | #define USB_IN_CSR1 0x80000244 // IN CSR1 register/EP0 CSR register | |
| 76 | #define USB_EP0_CSR 0x80000244 // IN CSR1 register/EP0 CSR register | |
| 77 | #define USB_IN_CSR2 0x80000248 // IN CSR2 register | |
| 78 | #define USB_OUT_MAXP 0x8000024C // OUT MAXP register | |
| 79 | ||
| 80 | #define USB_OUT_CSR1 0x80000250 // OUT CSR1 register | |
| 81 | #define USB_OUT_CSR2 0x80000254 // OUT CSR2 register | |
| 82 | #define USB_OUT_FIFO_WC1 0x80000258 // OUT FIFO write count1 register | |
| 83 | #define USB_OUT_FIFO_WC2 0x8000025C // OUT FIFO write count2 register | |
| 84 | ||
| 85 | #define USB_RESET 0x8000044C // USB reset register | |
| 86 | ||
| 87 | #define USB_EP0_FIFO 0x80000280 | |
| 88 | #define USB_EP1_FIFO 0x80000284 | |
| 89 | #define USB_EP2_FIFO 0x80000288 | |
| 90 | #define USB_EP3_FIFO 0x8000028c | |
| 91 | ||
| 92 | /* | |
| 93 | * USB reset register | |
| 94 | */ | |
| 95 | #define USB_RESET_APB (1<<1) //resets USB APB control side WRITE | |
| 96 | #define USB_RESET_IO (1<<0) //resets USB IO side WRITE | |
| 97 | ||
| 98 | /* | |
| 99 | * USB function address register | |
| 100 | */ | |
| 101 | #define USB_FA_ADDR_UPDATE (1<<7) | |
| 102 | #define USB_FA_FUNCTION_ADDR (0x7F) | |
| 103 | ||
| 104 | /* | |
| 105 | * Power Management register | |
| 106 | */ | |
| 107 | #define PM_USB_DCP (1<<5) | |
| 108 | #define PM_USB_ENABLE (1<<4) | |
| 109 | #define PM_USB_RESET (1<<3) | |
| 110 | #define PM_UC_RESUME (1<<2) | |
| 111 | #define PM_SUSPEND_MODE (1<<1) | |
| 112 | #define PM_ENABLE_SUSPEND (1<<0) | |
| 113 | ||
| 114 | /* | |
| 115 | * IN interrupt register | |
| 116 | */ | |
| 117 | #define USB_IN_INT_EP3 (1<<3) | |
| 118 | #define USB_IN_INT_EP1 (1<<1) | |
| 119 | #define USB_IN_INT_EP0 (1<<0) | |
| 120 | ||
| 121 | /* | |
| 122 | * OUT interrupt register | |
| 123 | */ | |
| 124 | #define USB_OUT_INT_EP2 (1<<2) | |
| 125 | ||
| 126 | /* | |
| 127 | * USB interrupt register | |
| 128 | */ | |
| 129 | #define USB_INT_RESET_INT (1<<2) | |
| 130 | #define USB_INT_RESUME_INT (1<<1) | |
| 131 | #define USB_INT_SUSPEND_INT (1<<0) | |
| 132 | ||
| 133 | /* | |
| 134 | * USB interrupt enable register | |
| 135 | */ | |
| 136 | #define USB_INT_EN_USB_RESET_INTER (1<<2) | |
| 137 | #define USB_INT_EN_RESUME_INTER (1<<1) | |
| 138 | #define USB_INT_EN_SUSPEND_INTER (1<<0) | |
| 139 | ||
| 140 | /* | |
| 141 | * INCSR1 register | |
| 142 | */ | |
| 143 | #define USB_IN_CSR1_CLR_DATA_TOGGLE (1<<6) | |
| 144 | #define USB_IN_CSR1_SENT_STALL (1<<5) | |
| 145 | #define USB_IN_CSR1_SEND_STALL (1<<4) | |
| 146 | #define USB_IN_CSR1_FIFO_FLUSH (1<<3) | |
| 147 | #define USB_IN_CSR1_FIFO_NOT_EMPTY (1<<1) | |
| 148 | #define USB_IN_CSR1_IN_PKT_RDY (1<<0) | |
| 149 | ||
| 150 | /* | |
| 151 | * INCSR2 register | |
| 152 | */ | |
| 153 | #define USB_IN_CSR2_AUTO_SET (1<<7) | |
| 154 | #define USB_IN_CSR2_USB_DMA_EN (1<<4) | |
| 155 | ||
| 156 | /* | |
| 157 | * OUT CSR1 register | |
| 158 | */ | |
| 159 | #define USB_OUT_CSR1_CLR_DATA_REG (1<<7) | |
| 160 | #define USB_OUT_CSR1_SENT_STALL (1<<6) | |
| 161 | #define USB_OUT_CSR1_SEND_STALL (1<<5) | |
| 162 | #define USB_OUT_CSR1_FIFO_FLUSH (1<<4) | |
| 163 | #define USB_OUT_CSR1_FIFO_FULL (1<<1) | |
| 164 | #define USB_OUT_CSR1_OUT_PKT_RDY (1<<0) | |
| 165 | ||
| 166 | /* | |
| 167 | * OUT CSR2 register | |
| 168 | */ | |
| 169 | #define USB_OUT_CSR2_AUTO_CLR (1<<7) | |
| 170 | #define USB_OUT_CSR2_USB_DMA_EN (1<<4) | |
| 171 | ||
| 172 | /* | |
| 173 | * EP0 CSR | |
| 174 | */ | |
| 175 | #define EP0_CLR_SETUP_END (1<<7) /* Clear "Setup Ends" Bit (w) */ | |
| 176 | #define EP0_CLR_OUT (1<<6) /* Clear "Out packet ready" Bit (w) */ | |
| 177 | #define EP0_SEND_STALL (1<<5) /* Send STALL Handshake (rw) */ | |
| 178 | #define EP0_SETUP_END (1<<4) /* Setup Ends (r) */ | |
| 179 | ||
| 180 | #define EP0_DATA_END (1<<3) /* Data end (rw) */ | |
| 181 | #define EP0_SENT_STALL (1<<2) /* Sent Stall Handshake (r) */ | |
| 182 | #define EP0_IN_PKT_RDY (1<<1) /* In packet ready (rw) */ | |
| 183 | #define EP0_OUT_PKT_RDY (1<<0) /* Out packet ready (r) */ | |
| 184 | ||
| 185 | /* general CSR */ | |
| 186 | #define OUT_PKT_RDY (1<<0) | |
| 187 | #define IN_PKT_RDY (1<<0) | |
| 188 | ||
| 189 | /* | |
| 190 | * IN/OUT MAXP register | |
| 191 | */ | |
| 192 | #define USB_OUT_MAXP_MAXP (0xF) | |
| 193 | #define USB_IN_MAXP_MAXP (0xF) | |
| 194 | ||
| 195 | // Max packet size | |
| 196 | //#define EP0_PACKETSIZE 0x10 | |
| 197 | #define EP0_PACKETSIZE 0x8 | |
| 198 | #define EP0_MAXPACKETSIZE 0x10 | |
| 199 | ||
| 200 | #define UDC_MAX_ENDPOINTS 4 | |
| 201 | ||
| 202 | #define WAIT_FOR_SETUP 0 | |
| 203 | #define DATA_STATE_XMIT 1 | |
| 204 | #define DATA_STATE_NEED_ZLP 2 | |
| 205 | #define WAIT_FOR_OUT_STATUS 3 | |
| 206 | #define DATA_STATE_RECV 4 | |
| 207 | ||
| 208 | /* ********************************************************************************************* */ | |
| 209 | /* IO | |
| 210 | */ | |
| 211 | ||
| 212 | typedef enum ep_type { | |
| 213 | ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt | |
| 214 | } ep_type_t; | |
| 215 | ||
| 216 | struct lh7a40x_ep { | |
| 217 | struct usb_ep ep; | |
| 218 | struct lh7a40x_udc *dev; | |
| 219 | ||
| 220 | const struct usb_endpoint_descriptor *desc; | |
| 221 | struct list_head queue; | |
| 222 | unsigned long pio_irqs; | |
| 223 | ||
| 224 | u8 stopped; | |
| 225 | u8 bEndpointAddress; | |
| 226 | u8 bmAttributes; | |
| 227 | ||
| 228 | ep_type_t ep_type; | |
| 229 | u32 fifo; | |
| 230 | u32 csr1; | |
| 231 | u32 csr2; | |
| 232 | }; | |
| 233 | ||
| 234 | struct lh7a40x_request { | |
| 235 | struct usb_request req; | |
| 236 | struct list_head queue; | |
| 237 | }; | |
| 238 | ||
| 239 | struct lh7a40x_udc { | |
| 240 | struct usb_gadget gadget; | |
| 241 | struct usb_gadget_driver *driver; | |
| 242 | struct device *dev; | |
| 243 | spinlock_t lock; | |
| 244 | ||
| 245 | int ep0state; | |
| 246 | struct lh7a40x_ep ep[UDC_MAX_ENDPOINTS]; | |
| 247 | ||
| 248 | unsigned char usb_address; | |
| 249 | ||
| 250 | unsigned req_pending:1, req_std:1, req_config:1; | |
| 251 | }; | |
| 252 | ||
| 253 | extern struct lh7a40x_udc *the_controller; | |
| 254 | ||
| 255 | #define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN)==USB_DIR_IN) | |
| 256 | #define ep_index(EP) ((EP)->bEndpointAddress&0xF) | |
| 257 | #define ep_maxpacket(EP) ((EP)->ep.maxpacket) | |
| 258 | ||
| 259 | #endif |