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24a28e42 RS |
1 | /* |
2 | * USB Gadget driver for LPC32xx | |
3 | * | |
4 | * Authors: | |
5 | * Kevin Wells <kevin.wells@nxp.com> | |
6 | * Mike James | |
7 | * Roland Stigge <stigge@antcom.de> | |
8 | * | |
9 | * Copyright (C) 2006 Philips Semiconductors | |
10 | * Copyright (C) 2009 NXP Semiconductors | |
11 | * Copyright (C) 2012 Roland Stigge | |
12 | * | |
13 | * Note: This driver is based on original work done by Mike James for | |
14 | * the LPC3180. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/errno.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/list.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/proc_fs.h> | |
42 | #include <linux/clk.h> | |
43 | #include <linux/usb/ch9.h> | |
44 | #include <linux/usb/gadget.h> | |
45 | #include <linux/i2c.h> | |
46 | #include <linux/kthread.h> | |
47 | #include <linux/freezer.h> | |
48 | #include <linux/dma-mapping.h> | |
49 | #include <linux/dmapool.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/of.h> | |
52 | #include <linux/usb/isp1301.h> | |
53 | ||
54 | #include <asm/byteorder.h> | |
55 | #include <mach/hardware.h> | |
56 | #include <linux/io.h> | |
57 | #include <asm/irq.h> | |
58 | #include <asm/system.h> | |
59 | ||
60 | #include <mach/platform.h> | |
61 | #include <mach/irqs.h> | |
62 | #include <mach/board.h> | |
63 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
d7dbdb5e | 64 | #include <linux/debugfs.h> |
24a28e42 RS |
65 | #include <linux/seq_file.h> |
66 | #endif | |
67 | ||
68 | /* | |
69 | * USB device configuration structure | |
70 | */ | |
71 | typedef void (*usc_chg_event)(int); | |
72 | struct lpc32xx_usbd_cfg { | |
73 | int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */ | |
74 | usc_chg_event conn_chgb; /* Connection change event (optional) */ | |
75 | usc_chg_event susp_chgb; /* Suspend/resume event (optional) */ | |
76 | usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */ | |
77 | }; | |
78 | ||
79 | /* | |
80 | * controller driver data structures | |
81 | */ | |
82 | ||
83 | /* 16 endpoints (not to be confused with 32 hardware endpoints) */ | |
84 | #define NUM_ENDPOINTS 16 | |
85 | ||
86 | /* | |
87 | * IRQ indices make reading the code a little easier | |
88 | */ | |
89 | #define IRQ_USB_LP 0 | |
90 | #define IRQ_USB_HP 1 | |
91 | #define IRQ_USB_DEVDMA 2 | |
92 | #define IRQ_USB_ATX 3 | |
93 | ||
94 | #define EP_OUT 0 /* RX (from host) */ | |
95 | #define EP_IN 1 /* TX (to host) */ | |
96 | ||
97 | /* Returns the interrupt mask for the selected hardware endpoint */ | |
98 | #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir)) | |
99 | ||
100 | #define EP_INT_TYPE 0 | |
101 | #define EP_ISO_TYPE 1 | |
102 | #define EP_BLK_TYPE 2 | |
103 | #define EP_CTL_TYPE 3 | |
104 | ||
105 | /* EP0 states */ | |
106 | #define WAIT_FOR_SETUP 0 /* Wait for setup packet */ | |
107 | #define DATA_IN 1 /* Expect dev->host transfer */ | |
108 | #define DATA_OUT 2 /* Expect host->dev transfer */ | |
109 | ||
110 | /* DD (DMA Descriptor) structure, requires word alignment, this is already | |
111 | * defined in the LPC32XX USB device header file, but this version is slightly | |
112 | * modified to tag some work data with each DMA descriptor. */ | |
113 | struct lpc32xx_usbd_dd_gad { | |
114 | u32 dd_next_phy; | |
115 | u32 dd_setup; | |
116 | u32 dd_buffer_addr; | |
117 | u32 dd_status; | |
118 | u32 dd_iso_ps_mem_addr; | |
119 | u32 this_dma; | |
120 | u32 iso_status[6]; /* 5 spare */ | |
121 | u32 dd_next_v; | |
122 | }; | |
123 | ||
124 | /* | |
125 | * Logical endpoint structure | |
126 | */ | |
127 | struct lpc32xx_ep { | |
128 | struct usb_ep ep; | |
129 | struct list_head queue; | |
130 | struct lpc32xx_udc *udc; | |
131 | ||
132 | u32 hwep_num_base; /* Physical hardware EP */ | |
133 | u32 hwep_num; /* Maps to hardware endpoint */ | |
134 | u32 maxpacket; | |
135 | u32 lep; | |
136 | ||
137 | bool is_in; | |
138 | bool req_pending; | |
139 | u32 eptype; | |
140 | ||
141 | u32 totalints; | |
142 | ||
143 | bool wedge; | |
144 | ||
145 | const struct usb_endpoint_descriptor *desc; | |
146 | }; | |
147 | ||
148 | /* | |
149 | * Common UDC structure | |
150 | */ | |
151 | struct lpc32xx_udc { | |
152 | struct usb_gadget gadget; | |
153 | struct usb_gadget_driver *driver; | |
154 | struct platform_device *pdev; | |
155 | struct device *dev; | |
156 | struct dentry *pde; | |
157 | spinlock_t lock; | |
158 | struct i2c_client *isp1301_i2c_client; | |
159 | ||
160 | /* Board and device specific */ | |
161 | struct lpc32xx_usbd_cfg *board; | |
162 | u32 io_p_start; | |
163 | u32 io_p_size; | |
164 | void __iomem *udp_baseaddr; | |
165 | int udp_irq[4]; | |
166 | struct clk *usb_pll_clk; | |
167 | struct clk *usb_slv_clk; | |
168 | ||
169 | /* DMA support */ | |
170 | u32 *udca_v_base; | |
171 | u32 udca_p_base; | |
172 | struct dma_pool *dd_cache; | |
173 | ||
174 | /* Common EP and control data */ | |
175 | u32 enabled_devints; | |
176 | u32 enabled_hwepints; | |
177 | u32 dev_status; | |
178 | u32 realized_eps; | |
179 | ||
180 | /* VBUS detection, pullup, and power flags */ | |
181 | u8 vbus; | |
182 | u8 last_vbus; | |
183 | int pullup; | |
184 | int poweron; | |
185 | ||
186 | /* Work queues related to I2C support */ | |
187 | struct work_struct pullup_job; | |
188 | struct work_struct vbus_job; | |
189 | struct work_struct power_job; | |
190 | ||
191 | /* USB device peripheral - various */ | |
192 | struct lpc32xx_ep ep[NUM_ENDPOINTS]; | |
193 | bool enabled; | |
194 | bool clocked; | |
195 | bool suspended; | |
196 | bool selfpowered; | |
197 | int ep0state; | |
198 | atomic_t enabled_ep_cnt; | |
199 | wait_queue_head_t ep_disable_wait_queue; | |
200 | }; | |
201 | ||
202 | /* | |
203 | * Endpoint request | |
204 | */ | |
205 | struct lpc32xx_request { | |
206 | struct usb_request req; | |
207 | struct list_head queue; | |
208 | struct lpc32xx_usbd_dd_gad *dd_desc_ptr; | |
209 | bool mapped; | |
210 | bool send_zlp; | |
211 | }; | |
212 | ||
213 | static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g) | |
214 | { | |
215 | return container_of(g, struct lpc32xx_udc, gadget); | |
216 | } | |
217 | ||
218 | #define ep_dbg(epp, fmt, arg...) \ | |
219 | dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg) | |
220 | #define ep_err(epp, fmt, arg...) \ | |
221 | dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg) | |
222 | #define ep_info(epp, fmt, arg...) \ | |
223 | dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg) | |
224 | #define ep_warn(epp, fmt, arg...) \ | |
225 | dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg) | |
226 | ||
227 | #define UDCA_BUFF_SIZE (128) | |
228 | ||
229 | /* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will | |
230 | * be replaced with an inremap()ed pointer, see USB_OTG_CLK_CTRL() | |
231 | * */ | |
232 | #define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64) | |
233 | #define USB_CLOCK_MASK (AHB_M_CLOCK_ON | OTG_CLOCK_ON | \ | |
234 | DEV_CLOCK_ON | I2C_CLOCK_ON) | |
235 | ||
236 | /* USB_CTRL bit defines */ | |
237 | #define USB_SLAVE_HCLK_EN (1 << 24) | |
238 | #define USB_HOST_NEED_CLK_EN (1 << 21) | |
239 | #define USB_DEV_NEED_CLK_EN (1 << 22) | |
240 | ||
241 | #define USB_OTG_CLK_CTRL(udc) ((udc)->udp_baseaddr + 0xFF4) | |
242 | #define USB_OTG_CLK_STAT(udc) ((udc)->udp_baseaddr + 0xFF8) | |
243 | ||
244 | /* USB_OTG_CLK_CTRL bit defines */ | |
245 | #define AHB_M_CLOCK_ON (1 << 4) | |
246 | #define OTG_CLOCK_ON (1 << 3) | |
247 | #define I2C_CLOCK_ON (1 << 2) | |
248 | #define DEV_CLOCK_ON (1 << 1) | |
249 | #define HOST_CLOCK_ON (1 << 0) | |
250 | ||
251 | #define USB_OTG_STAT_CONTROL(udc) (udc->udp_baseaddr + 0x110) | |
252 | ||
253 | /* USB_OTG_STAT_CONTROL bit defines */ | |
254 | #define TRANSPARENT_I2C_EN (1 << 7) | |
255 | #define HOST_EN (1 << 0) | |
256 | ||
257 | /********************************************************************** | |
258 | * USB device controller register offsets | |
259 | **********************************************************************/ | |
260 | ||
261 | #define USBD_DEVINTST(x) ((x) + 0x200) | |
262 | #define USBD_DEVINTEN(x) ((x) + 0x204) | |
263 | #define USBD_DEVINTCLR(x) ((x) + 0x208) | |
264 | #define USBD_DEVINTSET(x) ((x) + 0x20C) | |
265 | #define USBD_CMDCODE(x) ((x) + 0x210) | |
266 | #define USBD_CMDDATA(x) ((x) + 0x214) | |
267 | #define USBD_RXDATA(x) ((x) + 0x218) | |
268 | #define USBD_TXDATA(x) ((x) + 0x21C) | |
269 | #define USBD_RXPLEN(x) ((x) + 0x220) | |
270 | #define USBD_TXPLEN(x) ((x) + 0x224) | |
271 | #define USBD_CTRL(x) ((x) + 0x228) | |
272 | #define USBD_DEVINTPRI(x) ((x) + 0x22C) | |
273 | #define USBD_EPINTST(x) ((x) + 0x230) | |
274 | #define USBD_EPINTEN(x) ((x) + 0x234) | |
275 | #define USBD_EPINTCLR(x) ((x) + 0x238) | |
276 | #define USBD_EPINTSET(x) ((x) + 0x23C) | |
277 | #define USBD_EPINTPRI(x) ((x) + 0x240) | |
278 | #define USBD_REEP(x) ((x) + 0x244) | |
279 | #define USBD_EPIND(x) ((x) + 0x248) | |
280 | #define USBD_EPMAXPSIZE(x) ((x) + 0x24C) | |
281 | /* DMA support registers only below */ | |
282 | /* Set, clear, or get enabled state of the DMA request status. If | |
283 | * enabled, an IN or OUT token will start a DMA transfer for the EP */ | |
284 | #define USBD_DMARST(x) ((x) + 0x250) | |
285 | #define USBD_DMARCLR(x) ((x) + 0x254) | |
286 | #define USBD_DMARSET(x) ((x) + 0x258) | |
287 | /* DMA UDCA head pointer */ | |
288 | #define USBD_UDCAH(x) ((x) + 0x280) | |
289 | /* EP DMA status, enable, and disable. This is used to specifically | |
290 | * enabled or disable DMA for a specific EP */ | |
291 | #define USBD_EPDMAST(x) ((x) + 0x284) | |
292 | #define USBD_EPDMAEN(x) ((x) + 0x288) | |
293 | #define USBD_EPDMADIS(x) ((x) + 0x28C) | |
294 | /* DMA master interrupts enable and pending interrupts */ | |
295 | #define USBD_DMAINTST(x) ((x) + 0x290) | |
296 | #define USBD_DMAINTEN(x) ((x) + 0x294) | |
297 | /* DMA end of transfer interrupt enable, disable, status */ | |
298 | #define USBD_EOTINTST(x) ((x) + 0x2A0) | |
299 | #define USBD_EOTINTCLR(x) ((x) + 0x2A4) | |
300 | #define USBD_EOTINTSET(x) ((x) + 0x2A8) | |
301 | /* New DD request interrupt enable, disable, status */ | |
302 | #define USBD_NDDRTINTST(x) ((x) + 0x2AC) | |
303 | #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0) | |
304 | #define USBD_NDDRTINTSET(x) ((x) + 0x2B4) | |
305 | /* DMA error interrupt enable, disable, status */ | |
306 | #define USBD_SYSERRTINTST(x) ((x) + 0x2B8) | |
307 | #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC) | |
308 | #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0) | |
309 | ||
310 | /********************************************************************** | |
311 | * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/ | |
312 | * USBD_DEVINTPRI register definitions | |
313 | **********************************************************************/ | |
314 | #define USBD_ERR_INT (1 << 9) | |
315 | #define USBD_EP_RLZED (1 << 8) | |
316 | #define USBD_TXENDPKT (1 << 7) | |
317 | #define USBD_RXENDPKT (1 << 6) | |
318 | #define USBD_CDFULL (1 << 5) | |
319 | #define USBD_CCEMPTY (1 << 4) | |
320 | #define USBD_DEV_STAT (1 << 3) | |
321 | #define USBD_EP_SLOW (1 << 2) | |
322 | #define USBD_EP_FAST (1 << 1) | |
323 | #define USBD_FRAME (1 << 0) | |
324 | ||
325 | /********************************************************************** | |
326 | * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/ | |
327 | * USBD_EPINTPRI register definitions | |
328 | **********************************************************************/ | |
329 | /* End point selection macro (RX) */ | |
330 | #define USBD_RX_EP_SEL(e) (1 << ((e) << 1)) | |
331 | ||
332 | /* End point selection macro (TX) */ | |
333 | #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1)) | |
334 | ||
335 | /********************************************************************** | |
336 | * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/ | |
337 | * USBD_EPDMAEN/USBD_EPDMADIS/ | |
338 | * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/ | |
339 | * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/ | |
340 | * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET | |
341 | * register definitions | |
342 | **********************************************************************/ | |
343 | /* Endpoint selection macro */ | |
344 | #define USBD_EP_SEL(e) (1 << (e)) | |
345 | ||
346 | /********************************************************************** | |
347 | * SBD_DMAINTST/USBD_DMAINTEN | |
348 | **********************************************************************/ | |
349 | #define USBD_SYS_ERR_INT (1 << 2) | |
350 | #define USBD_NEW_DD_INT (1 << 1) | |
351 | #define USBD_EOT_INT (1 << 0) | |
352 | ||
353 | /********************************************************************** | |
354 | * USBD_RXPLEN register definitions | |
355 | **********************************************************************/ | |
356 | #define USBD_PKT_RDY (1 << 11) | |
357 | #define USBD_DV (1 << 10) | |
358 | #define USBD_PK_LEN_MASK 0x3FF | |
359 | ||
360 | /********************************************************************** | |
361 | * USBD_CTRL register definitions | |
362 | **********************************************************************/ | |
363 | #define USBD_LOG_ENDPOINT(e) ((e) << 2) | |
364 | #define USBD_WR_EN (1 << 1) | |
365 | #define USBD_RD_EN (1 << 0) | |
366 | ||
367 | /********************************************************************** | |
368 | * USBD_CMDCODE register definitions | |
369 | **********************************************************************/ | |
370 | #define USBD_CMD_CODE(c) ((c) << 16) | |
371 | #define USBD_CMD_PHASE(p) ((p) << 8) | |
372 | ||
373 | /********************************************************************** | |
374 | * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions | |
375 | **********************************************************************/ | |
376 | #define USBD_DMAEP(e) (1 << (e)) | |
377 | ||
378 | /* DD (DMA Descriptor) structure, requires word alignment */ | |
379 | struct lpc32xx_usbd_dd { | |
380 | u32 *dd_next; | |
381 | u32 dd_setup; | |
382 | u32 dd_buffer_addr; | |
383 | u32 dd_status; | |
384 | u32 dd_iso_ps_mem_addr; | |
385 | }; | |
386 | ||
387 | /* dd_setup bit defines */ | |
388 | #define DD_SETUP_ATLE_DMA_MODE 0x01 | |
389 | #define DD_SETUP_NEXT_DD_VALID 0x04 | |
390 | #define DD_SETUP_ISO_EP 0x10 | |
391 | #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5) | |
392 | #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16) | |
393 | ||
394 | /* dd_status bit defines */ | |
395 | #define DD_STATUS_DD_RETIRED 0x01 | |
396 | #define DD_STATUS_STS_MASK 0x1E | |
397 | #define DD_STATUS_STS_NS 0x00 /* Not serviced */ | |
398 | #define DD_STATUS_STS_BS 0x02 /* Being serviced */ | |
399 | #define DD_STATUS_STS_NC 0x04 /* Normal completion */ | |
400 | #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */ | |
401 | #define DD_STATUS_STS_DOR 0x08 /* Data overrun */ | |
402 | #define DD_STATUS_STS_SE 0x12 /* System error */ | |
403 | #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */ | |
404 | #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */ | |
405 | #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */ | |
406 | #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F) | |
407 | #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF) | |
408 | ||
409 | /* | |
410 | * | |
411 | * Protocol engine bits below | |
412 | * | |
413 | */ | |
414 | /* Device Interrupt Bit Definitions */ | |
415 | #define FRAME_INT 0x00000001 | |
416 | #define EP_FAST_INT 0x00000002 | |
417 | #define EP_SLOW_INT 0x00000004 | |
418 | #define DEV_STAT_INT 0x00000008 | |
419 | #define CCEMTY_INT 0x00000010 | |
420 | #define CDFULL_INT 0x00000020 | |
421 | #define RxENDPKT_INT 0x00000040 | |
422 | #define TxENDPKT_INT 0x00000080 | |
423 | #define EP_RLZED_INT 0x00000100 | |
424 | #define ERR_INT 0x00000200 | |
425 | ||
426 | /* Rx & Tx Packet Length Definitions */ | |
427 | #define PKT_LNGTH_MASK 0x000003FF | |
428 | #define PKT_DV 0x00000400 | |
429 | #define PKT_RDY 0x00000800 | |
430 | ||
431 | /* USB Control Definitions */ | |
432 | #define CTRL_RD_EN 0x00000001 | |
433 | #define CTRL_WR_EN 0x00000002 | |
434 | ||
435 | /* Command Codes */ | |
436 | #define CMD_SET_ADDR 0x00D00500 | |
437 | #define CMD_CFG_DEV 0x00D80500 | |
438 | #define CMD_SET_MODE 0x00F30500 | |
439 | #define CMD_RD_FRAME 0x00F50500 | |
440 | #define DAT_RD_FRAME 0x00F50200 | |
441 | #define CMD_RD_TEST 0x00FD0500 | |
442 | #define DAT_RD_TEST 0x00FD0200 | |
443 | #define CMD_SET_DEV_STAT 0x00FE0500 | |
444 | #define CMD_GET_DEV_STAT 0x00FE0500 | |
445 | #define DAT_GET_DEV_STAT 0x00FE0200 | |
446 | #define CMD_GET_ERR_CODE 0x00FF0500 | |
447 | #define DAT_GET_ERR_CODE 0x00FF0200 | |
448 | #define CMD_RD_ERR_STAT 0x00FB0500 | |
449 | #define DAT_RD_ERR_STAT 0x00FB0200 | |
450 | #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) | |
451 | #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) | |
452 | #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) | |
453 | #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) | |
454 | #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) | |
455 | #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) | |
456 | #define CMD_CLR_BUF 0x00F20500 | |
457 | #define DAT_CLR_BUF 0x00F20200 | |
458 | #define CMD_VALID_BUF 0x00FA0500 | |
459 | ||
460 | /* Device Address Register Definitions */ | |
461 | #define DEV_ADDR_MASK 0x7F | |
462 | #define DEV_EN 0x80 | |
463 | ||
464 | /* Device Configure Register Definitions */ | |
465 | #define CONF_DVICE 0x01 | |
466 | ||
467 | /* Device Mode Register Definitions */ | |
468 | #define AP_CLK 0x01 | |
469 | #define INAK_CI 0x02 | |
470 | #define INAK_CO 0x04 | |
471 | #define INAK_II 0x08 | |
472 | #define INAK_IO 0x10 | |
473 | #define INAK_BI 0x20 | |
474 | #define INAK_BO 0x40 | |
475 | ||
476 | /* Device Status Register Definitions */ | |
477 | #define DEV_CON 0x01 | |
478 | #define DEV_CON_CH 0x02 | |
479 | #define DEV_SUS 0x04 | |
480 | #define DEV_SUS_CH 0x08 | |
481 | #define DEV_RST 0x10 | |
482 | ||
483 | /* Error Code Register Definitions */ | |
484 | #define ERR_EC_MASK 0x0F | |
485 | #define ERR_EA 0x10 | |
486 | ||
487 | /* Error Status Register Definitions */ | |
488 | #define ERR_PID 0x01 | |
489 | #define ERR_UEPKT 0x02 | |
490 | #define ERR_DCRC 0x04 | |
491 | #define ERR_TIMOUT 0x08 | |
492 | #define ERR_EOP 0x10 | |
493 | #define ERR_B_OVRN 0x20 | |
494 | #define ERR_BTSTF 0x40 | |
495 | #define ERR_TGL 0x80 | |
496 | ||
497 | /* Endpoint Select Register Definitions */ | |
498 | #define EP_SEL_F 0x01 | |
499 | #define EP_SEL_ST 0x02 | |
500 | #define EP_SEL_STP 0x04 | |
501 | #define EP_SEL_PO 0x08 | |
502 | #define EP_SEL_EPN 0x10 | |
503 | #define EP_SEL_B_1_FULL 0x20 | |
504 | #define EP_SEL_B_2_FULL 0x40 | |
505 | ||
506 | /* Endpoint Status Register Definitions */ | |
507 | #define EP_STAT_ST 0x01 | |
508 | #define EP_STAT_DA 0x20 | |
509 | #define EP_STAT_RF_MO 0x40 | |
510 | #define EP_STAT_CND_ST 0x80 | |
511 | ||
512 | /* Clear Buffer Register Definitions */ | |
513 | #define CLR_BUF_PO 0x01 | |
514 | ||
515 | /* DMA Interrupt Bit Definitions */ | |
516 | #define EOT_INT 0x01 | |
517 | #define NDD_REQ_INT 0x02 | |
518 | #define SYS_ERR_INT 0x04 | |
519 | ||
520 | #define DRIVER_VERSION "1.03" | |
521 | static const char driver_name[] = "lpc32xx_udc"; | |
522 | ||
523 | /* | |
524 | * | |
525 | * proc interface support | |
526 | * | |
527 | */ | |
528 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
529 | static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"}; | |
530 | static const char debug_filename[] = "driver/udc"; | |
531 | ||
532 | static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep) | |
533 | { | |
534 | struct lpc32xx_request *req; | |
535 | ||
536 | seq_printf(s, "\n"); | |
537 | seq_printf(s, "%12s, maxpacket %4d %3s", | |
538 | ep->ep.name, ep->ep.maxpacket, | |
539 | ep->is_in ? "in" : "out"); | |
540 | seq_printf(s, " type %4s", epnames[ep->eptype]); | |
541 | seq_printf(s, " ints: %12d", ep->totalints); | |
542 | ||
543 | if (list_empty(&ep->queue)) | |
544 | seq_printf(s, "\t(queue empty)\n"); | |
545 | else { | |
546 | list_for_each_entry(req, &ep->queue, queue) { | |
547 | u32 length = req->req.actual; | |
548 | ||
549 | seq_printf(s, "\treq %p len %d/%d buf %p\n", | |
550 | &req->req, length, | |
551 | req->req.length, req->req.buf); | |
552 | } | |
553 | } | |
554 | } | |
555 | ||
556 | static int proc_udc_show(struct seq_file *s, void *unused) | |
557 | { | |
558 | struct lpc32xx_udc *udc = s->private; | |
559 | struct lpc32xx_ep *ep; | |
560 | unsigned long flags; | |
561 | ||
562 | seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); | |
563 | ||
564 | spin_lock_irqsave(&udc->lock, flags); | |
565 | ||
566 | seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", | |
567 | udc->vbus ? "present" : "off", | |
568 | udc->enabled ? (udc->vbus ? "active" : "enabled") : | |
569 | "disabled", | |
570 | udc->selfpowered ? "self" : "VBUS", | |
571 | udc->suspended ? ", suspended" : "", | |
572 | udc->driver ? udc->driver->driver.name : "(none)"); | |
573 | ||
574 | if (udc->enabled && udc->vbus) { | |
575 | proc_ep_show(s, &udc->ep[0]); | |
576 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { | |
577 | if (ep->desc) | |
578 | proc_ep_show(s, ep); | |
579 | } | |
580 | } | |
581 | ||
582 | spin_unlock_irqrestore(&udc->lock, flags); | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | static int proc_udc_open(struct inode *inode, struct file *file) | |
588 | { | |
589 | return single_open(file, proc_udc_show, PDE(inode)->data); | |
590 | } | |
591 | ||
592 | static const struct file_operations proc_ops = { | |
593 | .owner = THIS_MODULE, | |
594 | .open = proc_udc_open, | |
595 | .read = seq_read, | |
596 | .llseek = seq_lseek, | |
597 | .release = single_release, | |
598 | }; | |
599 | ||
600 | static void create_debug_file(struct lpc32xx_udc *udc) | |
601 | { | |
602 | udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops); | |
603 | } | |
604 | ||
605 | static void remove_debug_file(struct lpc32xx_udc *udc) | |
606 | { | |
607 | if (udc->pde) | |
608 | debugfs_remove(udc->pde); | |
609 | } | |
610 | ||
611 | #else | |
612 | static inline void create_debug_file(struct lpc32xx_udc *udc) {} | |
613 | static inline void remove_debug_file(struct lpc32xx_udc *udc) {} | |
614 | #endif | |
615 | ||
616 | /* Primary initialization sequence for the ISP1301 transceiver */ | |
617 | static void isp1301_udc_configure(struct lpc32xx_udc *udc) | |
618 | { | |
619 | /* LPC32XX only supports DAT_SE0 USB mode */ | |
620 | /* This sequence is important */ | |
621 | ||
622 | /* Disable transparent UART mode first */ | |
623 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
624 | (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), | |
625 | MC1_UART_EN); | |
626 | ||
627 | /* Set full speed and SE0 mode */ | |
628 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
629 | (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); | |
630 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
631 | ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0)); | |
632 | ||
633 | /* | |
634 | * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide | |
635 | */ | |
636 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
637 | (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); | |
638 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
639 | ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL)); | |
640 | ||
641 | /* Driver VBUS_DRV high or low depending on board setup */ | |
642 | if (udc->board->vbus_drv_pol != 0) | |
643 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
644 | ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV); | |
645 | else | |
646 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
647 | ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, | |
648 | OTG1_VBUS_DRV); | |
649 | ||
650 | /* Bi-directional mode with suspend control | |
651 | * Enable both pulldowns for now - the pullup will be enable when VBUS | |
652 | * is detected */ | |
653 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
654 | (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); | |
655 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
656 | ISP1301_I2C_OTG_CONTROL_1, | |
657 | (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); | |
658 | ||
659 | /* Discharge VBUS (just in case) */ | |
660 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
661 | ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); | |
662 | msleep(1); | |
663 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
664 | (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), | |
665 | OTG1_VBUS_DISCHRG); | |
666 | ||
667 | /* Clear and enable VBUS high edge interrupt */ | |
668 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
669 | ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0); | |
670 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
671 | ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); | |
672 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
673 | ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD); | |
674 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
675 | ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); | |
676 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
677 | ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD); | |
678 | ||
679 | /* Enable usb_need_clk clock after transceiver is initialized */ | |
680 | writel((readl(USB_CTRL) | (1 << 22)), USB_CTRL); | |
681 | ||
682 | dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", | |
683 | i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00)); | |
684 | dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", | |
685 | i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02)); | |
686 | dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n", | |
687 | i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14)); | |
688 | } | |
689 | ||
690 | /* Enables or disables the USB device pullup via the ISP1301 transceiver */ | |
691 | static void isp1301_pullup_set(struct lpc32xx_udc *udc) | |
692 | { | |
693 | if (udc->pullup) | |
694 | /* Enable pullup for bus signalling */ | |
695 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
696 | ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP); | |
697 | else | |
698 | /* Enable pullup for bus signalling */ | |
699 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
700 | ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, | |
701 | OTG1_DP_PULLUP); | |
702 | } | |
703 | ||
704 | static void pullup_work(struct work_struct *work) | |
705 | { | |
706 | struct lpc32xx_udc *udc = | |
707 | container_of(work, struct lpc32xx_udc, pullup_job); | |
708 | ||
709 | isp1301_pullup_set(udc); | |
710 | } | |
711 | ||
712 | static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup, | |
713 | int block) | |
714 | { | |
715 | if (en_pullup == udc->pullup) | |
716 | return; | |
717 | ||
718 | udc->pullup = en_pullup; | |
719 | if (block) | |
720 | isp1301_pullup_set(udc); | |
721 | else | |
722 | /* defer slow i2c pull up setting */ | |
723 | schedule_work(&udc->pullup_job); | |
724 | } | |
725 | ||
726 | #ifdef CONFIG_PM | |
727 | /* Powers up or down the ISP1301 transceiver */ | |
728 | static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable) | |
729 | { | |
730 | if (enable != 0) | |
731 | /* Power up ISP1301 - this ISP1301 will automatically wakeup | |
732 | when VBUS is detected */ | |
733 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
734 | ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR, | |
735 | MC2_GLOBAL_PWR_DN); | |
736 | else | |
737 | /* Power down ISP1301 */ | |
738 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
739 | ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); | |
740 | } | |
741 | ||
742 | static void power_work(struct work_struct *work) | |
743 | { | |
744 | struct lpc32xx_udc *udc = | |
745 | container_of(work, struct lpc32xx_udc, power_job); | |
746 | ||
747 | isp1301_set_powerstate(udc, udc->poweron); | |
748 | } | |
749 | #endif | |
750 | ||
751 | /* | |
752 | * | |
753 | * USB protocol engine command/data read/write helper functions | |
754 | * | |
755 | */ | |
756 | /* Issues a single command to the USB device state machine */ | |
757 | static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd) | |
758 | { | |
759 | u32 pass = 0; | |
760 | int to; | |
761 | ||
762 | /* EP may lock on CLRI if this read isn't done */ | |
763 | u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); | |
764 | (void) tmp; | |
765 | ||
766 | while (pass == 0) { | |
767 | writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr)); | |
768 | ||
769 | /* Write command code */ | |
770 | writel(cmd, USBD_CMDCODE(udc->udp_baseaddr)); | |
771 | to = 10000; | |
772 | while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) & | |
773 | USBD_CCEMPTY) == 0) && (to > 0)) { | |
774 | to--; | |
775 | } | |
776 | ||
777 | if (to > 0) | |
778 | pass = 1; | |
779 | ||
780 | cpu_relax(); | |
781 | } | |
782 | } | |
783 | ||
784 | /* Issues 2 commands (or command and data) to the USB device state machine */ | |
785 | static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd, | |
786 | u32 data) | |
787 | { | |
788 | udc_protocol_cmd_w(udc, cmd); | |
789 | udc_protocol_cmd_w(udc, data); | |
790 | } | |
791 | ||
792 | /* Issues a single command to the USB device state machine and reads | |
793 | * response data */ | |
794 | static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd) | |
795 | { | |
796 | u32 tmp; | |
797 | int to = 1000; | |
798 | ||
799 | /* Write a command and read data from the protocol engine */ | |
800 | writel((USBD_CDFULL | USBD_CCEMPTY), | |
801 | USBD_DEVINTCLR(udc->udp_baseaddr)); | |
802 | ||
803 | /* Write command code */ | |
804 | udc_protocol_cmd_w(udc, cmd); | |
805 | ||
806 | tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); | |
807 | while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL)) | |
808 | && (to > 0)) | |
809 | to--; | |
810 | if (!to) | |
811 | dev_dbg(udc->dev, | |
812 | "Protocol engine didn't receive response (CDFULL)\n"); | |
813 | ||
814 | return readl(USBD_CMDDATA(udc->udp_baseaddr)); | |
815 | } | |
816 | ||
817 | /* | |
818 | * | |
819 | * USB device interrupt mask support functions | |
820 | * | |
821 | */ | |
822 | /* Enable one or more USB device interrupts */ | |
823 | static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask) | |
824 | { | |
825 | udc->enabled_devints |= devmask; | |
826 | writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); | |
827 | } | |
828 | ||
829 | /* Disable one or more USB device interrupts */ | |
830 | static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask) | |
831 | { | |
832 | udc->enabled_devints &= ~mask; | |
833 | writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); | |
834 | } | |
835 | ||
836 | /* Clear one or more USB device interrupts */ | |
837 | static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask) | |
838 | { | |
839 | writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr)); | |
840 | } | |
841 | ||
842 | /* | |
843 | * | |
844 | * Endpoint interrupt disable/enable functions | |
845 | * | |
846 | */ | |
847 | /* Enable one or more USB endpoint interrupts */ | |
848 | static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep) | |
849 | { | |
850 | udc->enabled_hwepints |= (1 << hwep); | |
851 | writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); | |
852 | } | |
853 | ||
854 | /* Disable one or more USB endpoint interrupts */ | |
855 | static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep) | |
856 | { | |
857 | udc->enabled_hwepints &= ~(1 << hwep); | |
858 | writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); | |
859 | } | |
860 | ||
861 | /* Clear one or more USB endpoint interrupts */ | |
862 | static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep) | |
863 | { | |
864 | writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr)); | |
865 | } | |
866 | ||
867 | /* Enable DMA for the HW channel */ | |
868 | static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep) | |
869 | { | |
870 | writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr)); | |
871 | } | |
872 | ||
873 | /* Disable DMA for the HW channel */ | |
874 | static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep) | |
875 | { | |
876 | writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr)); | |
877 | } | |
878 | ||
879 | /* | |
880 | * | |
881 | * Endpoint realize/unrealize functions | |
882 | * | |
883 | */ | |
884 | /* Before an endpoint can be used, it needs to be realized | |
885 | * in the USB protocol engine - this realizes the endpoint. | |
886 | * The interrupt (FIFO or DMA) is not enabled with this function */ | |
887 | static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep, | |
888 | u32 maxpacket) | |
889 | { | |
890 | int to = 1000; | |
891 | ||
892 | writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); | |
893 | writel(hwep, USBD_EPIND(udc->udp_baseaddr)); | |
894 | udc->realized_eps |= (1 << hwep); | |
895 | writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); | |
896 | writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr)); | |
897 | ||
898 | /* Wait until endpoint is realized in hardware */ | |
899 | while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & | |
900 | USBD_EP_RLZED)) && (to > 0)) | |
901 | to--; | |
902 | if (!to) | |
903 | dev_dbg(udc->dev, "EP not correctly realized in hardware\n"); | |
904 | ||
905 | writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); | |
906 | } | |
907 | ||
908 | /* Unrealize an EP */ | |
909 | static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep) | |
910 | { | |
911 | udc->realized_eps &= ~(1 << hwep); | |
912 | writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); | |
913 | } | |
914 | ||
915 | /* | |
916 | * | |
917 | * Endpoint support functions | |
918 | * | |
919 | */ | |
920 | /* Select and clear endpoint interrupt */ | |
921 | static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep) | |
922 | { | |
923 | udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep)); | |
924 | return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep)); | |
925 | } | |
926 | ||
927 | /* Disables the endpoint in the USB protocol engine */ | |
928 | static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep) | |
929 | { | |
930 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), | |
931 | DAT_WR_BYTE(EP_STAT_DA)); | |
932 | } | |
933 | ||
934 | /* Stalls the endpoint - endpoint will return STALL */ | |
935 | static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep) | |
936 | { | |
937 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), | |
938 | DAT_WR_BYTE(EP_STAT_ST)); | |
939 | } | |
940 | ||
941 | /* Clear stall or reset endpoint */ | |
942 | static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep) | |
943 | { | |
944 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), | |
945 | DAT_WR_BYTE(0)); | |
946 | } | |
947 | ||
948 | /* Select an endpoint for endpoint status, clear, validate */ | |
949 | static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep) | |
950 | { | |
951 | udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep)); | |
952 | } | |
953 | ||
954 | /* | |
955 | * | |
956 | * Endpoint buffer management functions | |
957 | * | |
958 | */ | |
959 | /* Clear the current endpoint's buffer */ | |
960 | static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) | |
961 | { | |
962 | udc_select_hwep(udc, hwep); | |
963 | udc_protocol_cmd_w(udc, CMD_CLR_BUF); | |
964 | } | |
965 | ||
966 | /* Validate the current endpoint's buffer */ | |
967 | static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) | |
968 | { | |
969 | udc_select_hwep(udc, hwep); | |
970 | udc_protocol_cmd_w(udc, CMD_VALID_BUF); | |
971 | } | |
972 | ||
973 | static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep) | |
974 | { | |
975 | /* Clear EP interrupt */ | |
976 | uda_clear_hwepint(udc, hwep); | |
977 | return udc_selep_clrint(udc, hwep); | |
978 | } | |
979 | ||
980 | /* | |
981 | * | |
982 | * USB EP DMA support | |
983 | * | |
984 | */ | |
985 | /* Allocate a DMA Descriptor */ | |
986 | static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc) | |
987 | { | |
988 | dma_addr_t dma; | |
989 | struct lpc32xx_usbd_dd_gad *dd; | |
990 | ||
991 | dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc( | |
992 | udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma); | |
993 | if (dd) | |
994 | dd->this_dma = dma; | |
995 | ||
996 | return dd; | |
997 | } | |
998 | ||
999 | /* Free a DMA Descriptor */ | |
1000 | static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd) | |
1001 | { | |
1002 | dma_pool_free(udc->dd_cache, dd, dd->this_dma); | |
1003 | } | |
1004 | ||
1005 | /* | |
1006 | * | |
1007 | * USB setup and shutdown functions | |
1008 | * | |
1009 | */ | |
1010 | /* Enables or disables most of the USB system clocks when low power mode is | |
1011 | * needed. Clocks are typically started on a connection event, and disabled | |
1012 | * when a cable is disconnected */ | |
1013 | #define OTGOFF_CLK_MASK (AHB_M_CLOCK_ON | I2C_CLOCK_ON) | |
1014 | static void udc_clk_set(struct lpc32xx_udc *udc, int enable) | |
1015 | { | |
1016 | int to = 1000; | |
1017 | ||
1018 | if (enable != 0) { | |
1019 | if (udc->clocked) | |
1020 | return; | |
1021 | ||
1022 | udc->clocked = 1; | |
1023 | ||
1024 | /* 48MHz PLL up */ | |
1025 | clk_enable(udc->usb_pll_clk); | |
1026 | ||
1027 | /* Enable the USB device clock */ | |
1028 | writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, | |
1029 | USB_CTRL); | |
1030 | ||
1031 | /* Set to enable all needed USB OTG clocks */ | |
1032 | writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL(udc)); | |
1033 | ||
1034 | while (((readl(USB_OTG_CLK_STAT(udc)) & USB_CLOCK_MASK) != | |
1035 | USB_CLOCK_MASK) && (to > 0)) | |
1036 | to--; | |
1037 | if (!to) | |
1038 | dev_dbg(udc->dev, "Cannot enable USB OTG clocking\n"); | |
1039 | } else { | |
1040 | if (!udc->clocked) | |
1041 | return; | |
1042 | ||
1043 | udc->clocked = 0; | |
1044 | ||
1045 | /* Never disable the USB_HCLK during normal operation */ | |
1046 | ||
1047 | /* 48MHz PLL dpwn */ | |
1048 | clk_disable(udc->usb_pll_clk); | |
1049 | ||
1050 | /* Enable the USB device clock */ | |
1051 | writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN, | |
1052 | USB_CTRL); | |
1053 | ||
1054 | /* Set to enable all needed USB OTG clocks */ | |
1055 | writel(OTGOFF_CLK_MASK, USB_OTG_CLK_CTRL(udc)); | |
1056 | ||
1057 | while (((readl(USB_OTG_CLK_STAT(udc)) & | |
1058 | OTGOFF_CLK_MASK) != | |
1059 | OTGOFF_CLK_MASK) && (to > 0)) | |
1060 | to--; | |
1061 | if (!to) | |
1062 | dev_dbg(udc->dev, "Cannot disable USB OTG clocking\n"); | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | /* Set/reset USB device address */ | |
1067 | static void udc_set_address(struct lpc32xx_udc *udc, u32 addr) | |
1068 | { | |
1069 | /* Address will be latched at the end of the status phase, or | |
1070 | latched immediately if function is called twice */ | |
1071 | udc_protocol_cmd_data_w(udc, CMD_SET_ADDR, | |
1072 | DAT_WR_BYTE(DEV_EN | addr)); | |
1073 | } | |
1074 | ||
1075 | /* Setup up a IN request for DMA transfer - this consists of determining the | |
1076 | * list of DMA addresses for the transfer, allocating DMA Descriptors, | |
1077 | * installing the DD into the UDCA, and then enabling the DMA for that EP */ | |
1078 | static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) | |
1079 | { | |
1080 | struct lpc32xx_request *req; | |
1081 | u32 hwep = ep->hwep_num; | |
1082 | ||
1083 | ep->req_pending = 1; | |
1084 | ||
1085 | /* There will always be a request waiting here */ | |
1086 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); | |
1087 | ||
1088 | /* Place the DD Descriptor into the UDCA */ | |
1089 | udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; | |
1090 | ||
1091 | /* Enable DMA and interrupt for the HW EP */ | |
1092 | udc_ep_dma_enable(udc, hwep); | |
1093 | ||
1094 | /* Clear ZLP if last packet is not of MAXP size */ | |
1095 | if (req->req.length % ep->ep.maxpacket) | |
1096 | req->send_zlp = 0; | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | /* Setup up a OUT request for DMA transfer - this consists of determining the | |
1102 | * list of DMA addresses for the transfer, allocating DMA Descriptors, | |
1103 | * installing the DD into the UDCA, and then enabling the DMA for that EP */ | |
1104 | static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) | |
1105 | { | |
1106 | struct lpc32xx_request *req; | |
1107 | u32 hwep = ep->hwep_num; | |
1108 | ||
1109 | ep->req_pending = 1; | |
1110 | ||
1111 | /* There will always be a request waiting here */ | |
1112 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); | |
1113 | ||
1114 | /* Place the DD Descriptor into the UDCA */ | |
1115 | udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; | |
1116 | ||
1117 | /* Enable DMA and interrupt for the HW EP */ | |
1118 | udc_ep_dma_enable(udc, hwep); | |
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | static void udc_disable(struct lpc32xx_udc *udc) | |
1123 | { | |
1124 | u32 i; | |
1125 | ||
1126 | /* Disable device */ | |
1127 | udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); | |
1128 | udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0)); | |
1129 | ||
1130 | /* Disable all device interrupts (including EP0) */ | |
1131 | uda_disable_devint(udc, 0x3FF); | |
1132 | ||
1133 | /* Disable and reset all endpoint interrupts */ | |
1134 | for (i = 0; i < 32; i++) { | |
1135 | uda_disable_hwepint(udc, i); | |
1136 | uda_clear_hwepint(udc, i); | |
1137 | udc_disable_hwep(udc, i); | |
1138 | udc_unrealize_hwep(udc, i); | |
1139 | udc->udca_v_base[i] = 0; | |
1140 | ||
1141 | /* Disable and clear all interrupts and DMA */ | |
1142 | udc_ep_dma_disable(udc, i); | |
1143 | writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr)); | |
1144 | writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr)); | |
1145 | writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr)); | |
1146 | writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr)); | |
1147 | } | |
1148 | ||
1149 | /* Disable DMA interrupts */ | |
1150 | writel(0, USBD_DMAINTEN(udc->udp_baseaddr)); | |
1151 | ||
1152 | writel(0, USBD_UDCAH(udc->udp_baseaddr)); | |
1153 | } | |
1154 | ||
1155 | static void udc_enable(struct lpc32xx_udc *udc) | |
1156 | { | |
1157 | u32 i; | |
1158 | struct lpc32xx_ep *ep = &udc->ep[0]; | |
1159 | ||
1160 | /* Start with known state */ | |
1161 | udc_disable(udc); | |
1162 | ||
1163 | /* Enable device */ | |
1164 | udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); | |
1165 | ||
1166 | /* EP interrupts on high priority, FRAME interrupt on low priority */ | |
1167 | writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr)); | |
1168 | writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr)); | |
1169 | ||
1170 | /* Clear any pending device interrupts */ | |
1171 | writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr)); | |
1172 | ||
1173 | /* Setup UDCA - not yet used (DMA) */ | |
1174 | writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr)); | |
1175 | ||
1176 | /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */ | |
1177 | for (i = 0; i <= 1; i++) { | |
1178 | udc_realize_hwep(udc, i, ep->ep.maxpacket); | |
1179 | uda_enable_hwepint(udc, i); | |
1180 | udc_select_hwep(udc, i); | |
1181 | udc_clrstall_hwep(udc, i); | |
1182 | udc_clr_buffer_hwep(udc, i); | |
1183 | } | |
1184 | ||
1185 | /* Device interrupt setup */ | |
1186 | uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | | |
1187 | USBD_EP_FAST)); | |
1188 | uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | | |
1189 | USBD_EP_FAST)); | |
1190 | ||
1191 | /* Set device address to 0 - called twice to force a latch in the USB | |
1192 | engine without the need of a setup packet status closure */ | |
1193 | udc_set_address(udc, 0); | |
1194 | udc_set_address(udc, 0); | |
1195 | ||
1196 | /* Enable master DMA interrupts */ | |
1197 | writel((USBD_SYS_ERR_INT | USBD_EOT_INT), | |
1198 | USBD_DMAINTEN(udc->udp_baseaddr)); | |
1199 | ||
1200 | udc->dev_status = 0; | |
1201 | } | |
1202 | ||
1203 | /* | |
1204 | * | |
1205 | * USB device board specific events handled via callbacks | |
1206 | * | |
1207 | */ | |
1208 | /* Connection change event - notify board function of change */ | |
1209 | static void uda_power_event(struct lpc32xx_udc *udc, u32 conn) | |
1210 | { | |
1211 | /* Just notify of a connection change event (optional) */ | |
1212 | if (udc->board->conn_chgb != NULL) | |
1213 | udc->board->conn_chgb(conn); | |
1214 | } | |
1215 | ||
1216 | /* Suspend/resume event - notify board function of change */ | |
1217 | static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn) | |
1218 | { | |
1219 | /* Just notify of a Suspend/resume change event (optional) */ | |
1220 | if (udc->board->susp_chgb != NULL) | |
1221 | udc->board->susp_chgb(conn); | |
1222 | ||
1223 | if (conn) | |
1224 | udc->suspended = 0; | |
1225 | else | |
1226 | udc->suspended = 1; | |
1227 | } | |
1228 | ||
1229 | /* Remote wakeup enable/disable - notify board function of change */ | |
1230 | static void uda_remwkp_cgh(struct lpc32xx_udc *udc) | |
1231 | { | |
1232 | if (udc->board->rmwk_chgb != NULL) | |
1233 | udc->board->rmwk_chgb(udc->dev_status & | |
1234 | (1 << USB_DEVICE_REMOTE_WAKEUP)); | |
1235 | } | |
1236 | ||
1237 | /* Reads data from FIFO, adjusts for alignment and data size */ | |
1238 | static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) | |
1239 | { | |
1240 | int n, i, bl; | |
1241 | u16 *p16; | |
1242 | u32 *p32, tmp, cbytes; | |
1243 | ||
1244 | /* Use optimal data transfer method based on source address and size */ | |
1245 | switch (((u32) data) & 0x3) { | |
1246 | case 0: /* 32-bit aligned */ | |
1247 | p32 = (u32 *) data; | |
1248 | cbytes = (bytes & ~0x3); | |
1249 | ||
1250 | /* Copy 32-bit aligned data first */ | |
1251 | for (n = 0; n < cbytes; n += 4) | |
1252 | *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr)); | |
1253 | ||
1254 | /* Handle any remaining bytes */ | |
1255 | bl = bytes - cbytes; | |
1256 | if (bl) { | |
1257 | tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); | |
1258 | for (n = 0; n < bl; n++) | |
1259 | data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); | |
1260 | ||
1261 | } | |
1262 | break; | |
1263 | ||
1264 | case 1: /* 8-bit aligned */ | |
1265 | case 3: | |
1266 | /* Each byte has to be handled independently */ | |
1267 | for (n = 0; n < bytes; n += 4) { | |
1268 | tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); | |
1269 | ||
1270 | bl = bytes - n; | |
1271 | if (bl > 3) | |
1272 | bl = 3; | |
1273 | ||
1274 | for (i = 0; i < bl; i++) | |
1275 | data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF); | |
1276 | } | |
1277 | break; | |
1278 | ||
1279 | case 2: /* 16-bit aligned */ | |
1280 | p16 = (u16 *) data; | |
1281 | cbytes = (bytes & ~0x3); | |
1282 | ||
1283 | /* Copy 32-bit sized objects first with 16-bit alignment */ | |
1284 | for (n = 0; n < cbytes; n += 4) { | |
1285 | tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); | |
1286 | *p16++ = (u16)(tmp & 0xFFFF); | |
1287 | *p16++ = (u16)((tmp >> 16) & 0xFFFF); | |
1288 | } | |
1289 | ||
1290 | /* Handle any remaining bytes */ | |
1291 | bl = bytes - cbytes; | |
1292 | if (bl) { | |
1293 | tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); | |
1294 | for (n = 0; n < bl; n++) | |
1295 | data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); | |
1296 | } | |
1297 | break; | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | /* Read data from the FIFO for an endpoint. This function is for endpoints (such | |
1302 | * as EP0) that don't use DMA. This function should only be called if a packet | |
1303 | * is known to be ready to read for the endpoint. Note that the endpoint must | |
1304 | * be selected in the protocol engine prior to this call. */ | |
1305 | static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, | |
1306 | u32 bytes) | |
1307 | { | |
1308 | u32 tmpv; | |
1309 | int to = 1000; | |
1310 | u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN; | |
1311 | ||
1312 | /* Setup read of endpoint */ | |
1313 | writel(hwrep, USBD_CTRL(udc->udp_baseaddr)); | |
1314 | ||
1315 | /* Wait until packet is ready */ | |
1316 | while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) & | |
1317 | PKT_RDY) == 0) && (to > 0)) | |
1318 | to--; | |
1319 | if (!to) | |
1320 | dev_dbg(udc->dev, "No packet ready on FIFO EP read\n"); | |
1321 | ||
1322 | /* Mask out count */ | |
1323 | tmp = tmpv & PKT_LNGTH_MASK; | |
1324 | if (bytes < tmp) | |
1325 | tmp = bytes; | |
1326 | ||
1327 | if ((tmp > 0) && (data != NULL)) | |
1328 | udc_pop_fifo(udc, (u8 *) data, tmp); | |
1329 | ||
1330 | writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); | |
1331 | ||
1332 | /* Clear the buffer */ | |
1333 | udc_clr_buffer_hwep(udc, hwep); | |
1334 | ||
1335 | return tmp; | |
1336 | } | |
1337 | ||
1338 | /* Stuffs data into the FIFO, adjusts for alignment and data size */ | |
1339 | static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) | |
1340 | { | |
1341 | int n, i, bl; | |
1342 | u16 *p16; | |
1343 | u32 *p32, tmp, cbytes; | |
1344 | ||
1345 | /* Use optimal data transfer method based on source address and size */ | |
1346 | switch (((u32) data) & 0x3) { | |
1347 | case 0: /* 32-bit aligned */ | |
1348 | p32 = (u32 *) data; | |
1349 | cbytes = (bytes & ~0x3); | |
1350 | ||
1351 | /* Copy 32-bit aligned data first */ | |
1352 | for (n = 0; n < cbytes; n += 4) | |
1353 | writel(*p32++, USBD_TXDATA(udc->udp_baseaddr)); | |
1354 | ||
1355 | /* Handle any remaining bytes */ | |
1356 | bl = bytes - cbytes; | |
1357 | if (bl) { | |
1358 | tmp = 0; | |
1359 | for (n = 0; n < bl; n++) | |
1360 | tmp |= data[cbytes + n] << (n * 8); | |
1361 | ||
1362 | writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); | |
1363 | } | |
1364 | break; | |
1365 | ||
1366 | case 1: /* 8-bit aligned */ | |
1367 | case 3: | |
1368 | /* Each byte has to be handled independently */ | |
1369 | for (n = 0; n < bytes; n += 4) { | |
1370 | bl = bytes - n; | |
1371 | if (bl > 4) | |
1372 | bl = 4; | |
1373 | ||
1374 | tmp = 0; | |
1375 | for (i = 0; i < bl; i++) | |
1376 | tmp |= data[n + i] << (i * 8); | |
1377 | ||
1378 | writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); | |
1379 | } | |
1380 | break; | |
1381 | ||
1382 | case 2: /* 16-bit aligned */ | |
1383 | p16 = (u16 *) data; | |
1384 | cbytes = (bytes & ~0x3); | |
1385 | ||
1386 | /* Copy 32-bit aligned data first */ | |
1387 | for (n = 0; n < cbytes; n += 4) { | |
1388 | tmp = *p16++ & 0xFFFF; | |
1389 | tmp |= (*p16++ & 0xFFFF) << 16; | |
1390 | writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); | |
1391 | } | |
1392 | ||
1393 | /* Handle any remaining bytes */ | |
1394 | bl = bytes - cbytes; | |
1395 | if (bl) { | |
1396 | tmp = 0; | |
1397 | for (n = 0; n < bl; n++) | |
1398 | tmp |= data[cbytes + n] << (n * 8); | |
1399 | ||
1400 | writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); | |
1401 | } | |
1402 | break; | |
1403 | } | |
1404 | } | |
1405 | ||
1406 | /* Write data to the FIFO for an endpoint. This function is for endpoints (such | |
1407 | * as EP0) that don't use DMA. Note that the endpoint must be selected in the | |
1408 | * protocol engine prior to this call. */ | |
1409 | static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, | |
1410 | u32 bytes) | |
1411 | { | |
1412 | u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN; | |
1413 | ||
1414 | if ((bytes > 0) && (data == NULL)) | |
1415 | return; | |
1416 | ||
1417 | /* Setup write of endpoint */ | |
1418 | writel(hwwep, USBD_CTRL(udc->udp_baseaddr)); | |
1419 | ||
1420 | writel(bytes, USBD_TXPLEN(udc->udp_baseaddr)); | |
1421 | ||
1422 | /* Need at least 1 byte to trigger TX */ | |
1423 | if (bytes == 0) | |
1424 | writel(0, USBD_TXDATA(udc->udp_baseaddr)); | |
1425 | else | |
1426 | udc_stuff_fifo(udc, (u8 *) data, bytes); | |
1427 | ||
1428 | writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); | |
1429 | ||
1430 | udc_val_buffer_hwep(udc, hwep); | |
1431 | } | |
1432 | ||
1433 | /* USB device reset - resets USB to a default state with just EP0 | |
1434 | enabled */ | |
1435 | static void uda_usb_reset(struct lpc32xx_udc *udc) | |
1436 | { | |
1437 | u32 i = 0; | |
1438 | /* Re-init device controller and EP0 */ | |
1439 | udc_enable(udc); | |
1440 | udc->gadget.speed = USB_SPEED_FULL; | |
1441 | ||
1442 | for (i = 1; i < NUM_ENDPOINTS; i++) { | |
1443 | struct lpc32xx_ep *ep = &udc->ep[i]; | |
1444 | ep->req_pending = 0; | |
1445 | } | |
1446 | } | |
1447 | ||
1448 | /* Send a ZLP on EP0 */ | |
1449 | static void udc_ep0_send_zlp(struct lpc32xx_udc *udc) | |
1450 | { | |
1451 | udc_write_hwep(udc, EP_IN, NULL, 0); | |
1452 | } | |
1453 | ||
1454 | /* Get current frame number */ | |
1455 | static u16 udc_get_current_frame(struct lpc32xx_udc *udc) | |
1456 | { | |
1457 | u16 flo, fhi; | |
1458 | ||
1459 | udc_protocol_cmd_w(udc, CMD_RD_FRAME); | |
1460 | flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); | |
1461 | fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); | |
1462 | ||
1463 | return (fhi << 8) | flo; | |
1464 | } | |
1465 | ||
1466 | /* Set the device as configured - enables all endpoints */ | |
1467 | static inline void udc_set_device_configured(struct lpc32xx_udc *udc) | |
1468 | { | |
1469 | udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE)); | |
1470 | } | |
1471 | ||
1472 | /* Set the device as unconfigured - disables all endpoints */ | |
1473 | static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc) | |
1474 | { | |
1475 | udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); | |
1476 | } | |
1477 | ||
1478 | /* reinit == restore initial software state */ | |
1479 | static void udc_reinit(struct lpc32xx_udc *udc) | |
1480 | { | |
1481 | u32 i; | |
1482 | ||
1483 | INIT_LIST_HEAD(&udc->gadget.ep_list); | |
1484 | INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); | |
1485 | ||
1486 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
1487 | struct lpc32xx_ep *ep = &udc->ep[i]; | |
1488 | ||
1489 | if (i != 0) | |
1490 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); | |
1491 | ep->desc = NULL; | |
1492 | ep->ep.maxpacket = ep->maxpacket; | |
1493 | INIT_LIST_HEAD(&ep->queue); | |
1494 | ep->req_pending = 0; | |
1495 | } | |
1496 | ||
1497 | udc->ep0state = WAIT_FOR_SETUP; | |
1498 | } | |
1499 | ||
1500 | /* Must be called with lock */ | |
1501 | static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status) | |
1502 | { | |
1503 | struct lpc32xx_udc *udc = ep->udc; | |
1504 | ||
1505 | list_del_init(&req->queue); | |
1506 | if (req->req.status == -EINPROGRESS) | |
1507 | req->req.status = status; | |
1508 | else | |
1509 | status = req->req.status; | |
1510 | ||
1511 | if (ep->lep) { | |
1512 | enum dma_data_direction direction; | |
1513 | ||
1514 | if (ep->is_in) | |
1515 | direction = DMA_TO_DEVICE; | |
1516 | else | |
1517 | direction = DMA_FROM_DEVICE; | |
1518 | ||
1519 | if (req->mapped) { | |
1520 | dma_unmap_single(ep->udc->gadget.dev.parent, | |
1521 | req->req.dma, req->req.length, | |
1522 | direction); | |
1523 | req->req.dma = 0; | |
1524 | req->mapped = 0; | |
1525 | } else | |
1526 | dma_sync_single_for_cpu(ep->udc->gadget.dev.parent, | |
1527 | req->req.dma, req->req.length, | |
1528 | direction); | |
1529 | ||
1530 | /* Free DDs */ | |
1531 | udc_dd_free(udc, req->dd_desc_ptr); | |
1532 | } | |
1533 | ||
1534 | if (status && status != -ESHUTDOWN) | |
1535 | ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status); | |
1536 | ||
1537 | ep->req_pending = 0; | |
1538 | spin_unlock(&udc->lock); | |
1539 | req->req.complete(&ep->ep, &req->req); | |
1540 | spin_lock(&udc->lock); | |
1541 | } | |
1542 | ||
1543 | /* Must be called with lock */ | |
1544 | static void nuke(struct lpc32xx_ep *ep, int status) | |
1545 | { | |
1546 | struct lpc32xx_request *req; | |
1547 | ||
1548 | while (!list_empty(&ep->queue)) { | |
1549 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); | |
1550 | done(ep, req, status); | |
1551 | } | |
1552 | ||
1553 | if (ep->desc && status == -ESHUTDOWN) { | |
1554 | uda_disable_hwepint(ep->udc, ep->hwep_num); | |
1555 | udc_disable_hwep(ep->udc, ep->hwep_num); | |
1556 | } | |
1557 | } | |
1558 | ||
1559 | /* IN endpoint 0 transfer */ | |
1560 | static int udc_ep0_in_req(struct lpc32xx_udc *udc) | |
1561 | { | |
1562 | struct lpc32xx_request *req; | |
1563 | struct lpc32xx_ep *ep0 = &udc->ep[0]; | |
1564 | u32 tsend, ts = 0; | |
1565 | ||
1566 | if (list_empty(&ep0->queue)) | |
1567 | /* Nothing to send */ | |
1568 | return 0; | |
1569 | else | |
1570 | req = list_entry(ep0->queue.next, struct lpc32xx_request, | |
1571 | queue); | |
1572 | ||
1573 | tsend = ts = req->req.length - req->req.actual; | |
1574 | if (ts == 0) { | |
1575 | /* Send a ZLP */ | |
1576 | udc_ep0_send_zlp(udc); | |
1577 | done(ep0, req, 0); | |
1578 | return 1; | |
1579 | } else if (ts > ep0->ep.maxpacket) | |
1580 | ts = ep0->ep.maxpacket; /* Just send what we can */ | |
1581 | ||
1582 | /* Write data to the EP0 FIFO and start transfer */ | |
1583 | udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts); | |
1584 | ||
1585 | /* Increment data pointer */ | |
1586 | req->req.actual += ts; | |
1587 | ||
1588 | if (tsend >= ep0->ep.maxpacket) | |
1589 | return 0; /* Stay in data transfer state */ | |
1590 | ||
1591 | /* Transfer request is complete */ | |
1592 | udc->ep0state = WAIT_FOR_SETUP; | |
1593 | done(ep0, req, 0); | |
1594 | return 1; | |
1595 | } | |
1596 | ||
1597 | /* OUT endpoint 0 transfer */ | |
1598 | static int udc_ep0_out_req(struct lpc32xx_udc *udc) | |
1599 | { | |
1600 | struct lpc32xx_request *req; | |
1601 | struct lpc32xx_ep *ep0 = &udc->ep[0]; | |
1602 | u32 tr, bufferspace; | |
1603 | ||
1604 | if (list_empty(&ep0->queue)) | |
1605 | return 0; | |
1606 | else | |
1607 | req = list_entry(ep0->queue.next, struct lpc32xx_request, | |
1608 | queue); | |
1609 | ||
1610 | if (req) { | |
1611 | if (req->req.length == 0) { | |
1612 | /* Just dequeue request */ | |
1613 | done(ep0, req, 0); | |
1614 | udc->ep0state = WAIT_FOR_SETUP; | |
1615 | return 1; | |
1616 | } | |
1617 | ||
1618 | /* Get data from FIFO */ | |
1619 | bufferspace = req->req.length - req->req.actual; | |
1620 | if (bufferspace > ep0->ep.maxpacket) | |
1621 | bufferspace = ep0->ep.maxpacket; | |
1622 | ||
1623 | /* Copy data to buffer */ | |
1624 | prefetchw(req->req.buf + req->req.actual); | |
1625 | tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual, | |
1626 | bufferspace); | |
1627 | req->req.actual += bufferspace; | |
1628 | ||
1629 | if (tr < ep0->ep.maxpacket) { | |
1630 | /* This is the last packet */ | |
1631 | done(ep0, req, 0); | |
1632 | udc->ep0state = WAIT_FOR_SETUP; | |
1633 | return 1; | |
1634 | } | |
1635 | } | |
1636 | ||
1637 | return 0; | |
1638 | } | |
1639 | ||
1640 | /* Must be called with lock */ | |
1641 | static void stop_activity(struct lpc32xx_udc *udc) | |
1642 | { | |
1643 | struct usb_gadget_driver *driver = udc->driver; | |
1644 | int i; | |
1645 | ||
1646 | if (udc->gadget.speed == USB_SPEED_UNKNOWN) | |
1647 | driver = NULL; | |
1648 | ||
1649 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
1650 | udc->suspended = 0; | |
1651 | ||
1652 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
1653 | struct lpc32xx_ep *ep = &udc->ep[i]; | |
1654 | nuke(ep, -ESHUTDOWN); | |
1655 | } | |
1656 | if (driver) { | |
1657 | spin_unlock(&udc->lock); | |
1658 | driver->disconnect(&udc->gadget); | |
1659 | spin_lock(&udc->lock); | |
1660 | } | |
1661 | ||
1662 | isp1301_pullup_enable(udc, 0, 0); | |
1663 | udc_disable(udc); | |
1664 | udc_reinit(udc); | |
1665 | } | |
1666 | ||
1667 | /* | |
1668 | * Activate or kill host pullup | |
1669 | * Can be called with or without lock | |
1670 | */ | |
1671 | static void pullup(struct lpc32xx_udc *udc, int is_on) | |
1672 | { | |
1673 | if (!udc->clocked) | |
1674 | return; | |
1675 | ||
1676 | if (!udc->enabled || !udc->vbus) | |
1677 | is_on = 0; | |
1678 | ||
1679 | if (is_on != udc->pullup) | |
1680 | isp1301_pullup_enable(udc, is_on, 0); | |
1681 | } | |
1682 | ||
1683 | /* Must be called without lock */ | |
1684 | static int lpc32xx_ep_disable(struct usb_ep *_ep) | |
1685 | { | |
1686 | struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); | |
1687 | struct lpc32xx_udc *udc = ep->udc; | |
1688 | unsigned long flags; | |
1689 | ||
1690 | if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0)) | |
1691 | return -EINVAL; | |
1692 | spin_lock_irqsave(&udc->lock, flags); | |
1693 | ||
1694 | nuke(ep, -ESHUTDOWN); | |
1695 | ||
1696 | /* restore the endpoint's pristine config */ | |
1697 | ep->desc = NULL; | |
1698 | ||
1699 | /* Clear all DMA statuses for this EP */ | |
1700 | udc_ep_dma_disable(udc, ep->hwep_num); | |
1701 | writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); | |
1702 | writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); | |
1703 | writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); | |
1704 | writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); | |
1705 | ||
1706 | /* Remove the DD pointer in the UDCA */ | |
1707 | udc->udca_v_base[ep->hwep_num] = 0; | |
1708 | ||
1709 | /* Disable and reset endpoint and interrupt */ | |
1710 | uda_clear_hwepint(udc, ep->hwep_num); | |
1711 | udc_unrealize_hwep(udc, ep->hwep_num); | |
1712 | ||
1713 | ep->hwep_num = 0; | |
1714 | ||
1715 | spin_unlock_irqrestore(&udc->lock, flags); | |
1716 | ||
1717 | atomic_dec(&udc->enabled_ep_cnt); | |
1718 | wake_up(&udc->ep_disable_wait_queue); | |
1719 | ||
1720 | return 0; | |
1721 | } | |
1722 | ||
1723 | /* Must be called without lock */ | |
1724 | static int lpc32xx_ep_enable(struct usb_ep *_ep, | |
1725 | const struct usb_endpoint_descriptor *desc) | |
1726 | { | |
1727 | struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); | |
1728 | struct lpc32xx_udc *udc = ep->udc; | |
1729 | u16 maxpacket; | |
1730 | u32 tmp; | |
1731 | unsigned long flags; | |
1732 | ||
1733 | /* Verify EP data */ | |
1734 | if ((!_ep) || (!ep) || (!desc) || (ep->desc) || | |
1735 | (desc->bDescriptorType != USB_DT_ENDPOINT)) { | |
1736 | dev_dbg(udc->dev, "bad ep or descriptor\n"); | |
1737 | return -EINVAL; | |
1738 | } | |
1739 | maxpacket = usb_endpoint_maxp(desc); | |
1740 | if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) { | |
1741 | dev_dbg(udc->dev, "bad ep descriptor's packet size\n"); | |
1742 | return -EINVAL; | |
1743 | } | |
1744 | ||
1745 | /* Don't touch EP0 */ | |
1746 | if (ep->hwep_num_base == 0) { | |
1747 | dev_dbg(udc->dev, "Can't re-enable EP0!!!\n"); | |
1748 | return -EINVAL; | |
1749 | } | |
1750 | ||
1751 | /* Is driver ready? */ | |
1752 | if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { | |
1753 | dev_dbg(udc->dev, "bogus device state\n"); | |
1754 | return -ESHUTDOWN; | |
1755 | } | |
1756 | ||
1757 | tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; | |
1758 | switch (tmp) { | |
1759 | case USB_ENDPOINT_XFER_CONTROL: | |
1760 | return -EINVAL; | |
1761 | ||
1762 | case USB_ENDPOINT_XFER_INT: | |
1763 | if (maxpacket > ep->maxpacket) { | |
1764 | dev_dbg(udc->dev, | |
1765 | "Bad INT endpoint maxpacket %d\n", maxpacket); | |
1766 | return -EINVAL; | |
1767 | } | |
1768 | break; | |
1769 | ||
1770 | case USB_ENDPOINT_XFER_BULK: | |
1771 | switch (maxpacket) { | |
1772 | case 8: | |
1773 | case 16: | |
1774 | case 32: | |
1775 | case 64: | |
1776 | break; | |
1777 | ||
1778 | default: | |
1779 | dev_dbg(udc->dev, | |
1780 | "Bad BULK endpoint maxpacket %d\n", maxpacket); | |
1781 | return -EINVAL; | |
1782 | } | |
1783 | break; | |
1784 | ||
1785 | case USB_ENDPOINT_XFER_ISOC: | |
1786 | break; | |
1787 | } | |
1788 | spin_lock_irqsave(&udc->lock, flags); | |
1789 | ||
1790 | /* Initialize endpoint to match the selected descriptor */ | |
1791 | ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0; | |
1792 | ep->desc = desc; | |
1793 | ep->ep.maxpacket = maxpacket; | |
1794 | ||
1795 | /* Map hardware endpoint from base and direction */ | |
1796 | if (ep->is_in) | |
1797 | /* IN endpoints are offset 1 from the OUT endpoint */ | |
1798 | ep->hwep_num = ep->hwep_num_base + EP_IN; | |
1799 | else | |
1800 | ep->hwep_num = ep->hwep_num_base; | |
1801 | ||
1802 | ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name, | |
1803 | ep->hwep_num, maxpacket, (ep->is_in == 1)); | |
1804 | ||
1805 | /* Realize the endpoint, interrupt is enabled later when | |
1806 | * buffers are queued, IN EPs will NAK until buffers are ready */ | |
1807 | udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket); | |
1808 | udc_clr_buffer_hwep(udc, ep->hwep_num); | |
1809 | uda_disable_hwepint(udc, ep->hwep_num); | |
1810 | udc_clrstall_hwep(udc, ep->hwep_num); | |
1811 | ||
1812 | /* Clear all DMA statuses for this EP */ | |
1813 | udc_ep_dma_disable(udc, ep->hwep_num); | |
1814 | writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); | |
1815 | writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); | |
1816 | writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); | |
1817 | writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); | |
1818 | ||
1819 | spin_unlock_irqrestore(&udc->lock, flags); | |
1820 | ||
1821 | atomic_inc(&udc->enabled_ep_cnt); | |
1822 | return 0; | |
1823 | } | |
1824 | ||
1825 | /* | |
1826 | * Allocate a USB request list | |
1827 | * Can be called with or without lock | |
1828 | */ | |
1829 | static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep, | |
1830 | gfp_t gfp_flags) | |
1831 | { | |
1832 | struct lpc32xx_request *req; | |
1833 | ||
1834 | req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags); | |
1835 | if (!req) | |
1836 | return NULL; | |
1837 | ||
1838 | INIT_LIST_HEAD(&req->queue); | |
1839 | return &req->req; | |
1840 | } | |
1841 | ||
1842 | /* | |
1843 | * De-allocate a USB request list | |
1844 | * Can be called with or without lock | |
1845 | */ | |
1846 | static void lpc32xx_ep_free_request(struct usb_ep *_ep, | |
1847 | struct usb_request *_req) | |
1848 | { | |
1849 | struct lpc32xx_request *req; | |
1850 | ||
1851 | req = container_of(_req, struct lpc32xx_request, req); | |
1852 | BUG_ON(!list_empty(&req->queue)); | |
1853 | kfree(req); | |
1854 | } | |
1855 | ||
1856 | /* Must be called without lock */ | |
1857 | static int lpc32xx_ep_queue(struct usb_ep *_ep, | |
1858 | struct usb_request *_req, gfp_t gfp_flags) | |
1859 | { | |
1860 | struct lpc32xx_request *req; | |
1861 | struct lpc32xx_ep *ep; | |
1862 | struct lpc32xx_udc *udc; | |
1863 | unsigned long flags; | |
1864 | int status = 0; | |
1865 | ||
1866 | req = container_of(_req, struct lpc32xx_request, req); | |
1867 | ep = container_of(_ep, struct lpc32xx_ep, ep); | |
1868 | ||
1869 | if (!_req || !_req->complete || !_req->buf || | |
1870 | !list_empty(&req->queue)) | |
1871 | return -EINVAL; | |
1872 | ||
1873 | udc = ep->udc; | |
1874 | ||
1875 | if (!_ep || (!ep->desc && ep->hwep_num_base != 0)) { | |
1876 | dev_dbg(udc->dev, "invalid ep\n"); | |
1877 | return -EINVAL; | |
1878 | } | |
1879 | ||
1880 | ||
1881 | if ((!udc) || (!udc->driver) || | |
1882 | (udc->gadget.speed == USB_SPEED_UNKNOWN)) { | |
1883 | dev_dbg(udc->dev, "invalid device\n"); | |
1884 | return -EINVAL; | |
1885 | } | |
1886 | ||
1887 | if (ep->lep) { | |
1888 | enum dma_data_direction direction; | |
1889 | struct lpc32xx_usbd_dd_gad *dd; | |
1890 | ||
1891 | /* Map DMA pointer */ | |
1892 | if (ep->is_in) | |
1893 | direction = DMA_TO_DEVICE; | |
1894 | else | |
1895 | direction = DMA_FROM_DEVICE; | |
1896 | ||
1897 | if (req->req.dma == 0) { | |
1898 | req->req.dma = dma_map_single( | |
1899 | ep->udc->gadget.dev.parent, | |
1900 | req->req.buf, req->req.length, direction); | |
1901 | req->mapped = 1; | |
1902 | } else { | |
1903 | dma_sync_single_for_device( | |
1904 | ep->udc->gadget.dev.parent, req->req.dma, | |
1905 | req->req.length, direction); | |
1906 | req->mapped = 0; | |
1907 | } | |
1908 | ||
1909 | /* For the request, build a list of DDs */ | |
1910 | dd = udc_dd_alloc(udc); | |
1911 | if (!dd) { | |
1912 | /* Error allocating DD */ | |
1913 | return -ENOMEM; | |
1914 | } | |
1915 | req->dd_desc_ptr = dd; | |
1916 | ||
1917 | /* Setup the DMA descriptor */ | |
1918 | dd->dd_next_phy = dd->dd_next_v = 0; | |
1919 | dd->dd_buffer_addr = req->req.dma; | |
1920 | dd->dd_status = 0; | |
1921 | ||
1922 | /* Special handling for ISO EPs */ | |
1923 | if (ep->eptype == EP_ISO_TYPE) { | |
1924 | dd->dd_setup = DD_SETUP_ISO_EP | | |
1925 | DD_SETUP_PACKETLEN(0) | | |
1926 | DD_SETUP_DMALENBYTES(1); | |
1927 | dd->dd_iso_ps_mem_addr = dd->this_dma + 24; | |
1928 | if (ep->is_in) | |
1929 | dd->iso_status[0] = req->req.length; | |
1930 | else | |
1931 | dd->iso_status[0] = 0; | |
1932 | } else | |
1933 | dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) | | |
1934 | DD_SETUP_DMALENBYTES(req->req.length); | |
1935 | } | |
1936 | ||
1937 | ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name, | |
1938 | _req, _req->length, _req->buf, ep->is_in, _req->zero); | |
1939 | ||
1940 | spin_lock_irqsave(&udc->lock, flags); | |
1941 | ||
1942 | _req->status = -EINPROGRESS; | |
1943 | _req->actual = 0; | |
1944 | req->send_zlp = _req->zero; | |
1945 | ||
1946 | /* Kickstart empty queues */ | |
1947 | if (list_empty(&ep->queue)) { | |
1948 | list_add_tail(&req->queue, &ep->queue); | |
1949 | ||
1950 | if (ep->hwep_num_base == 0) { | |
1951 | /* Handle expected data direction */ | |
1952 | if (ep->is_in) { | |
1953 | /* IN packet to host */ | |
1954 | udc->ep0state = DATA_IN; | |
1955 | status = udc_ep0_in_req(udc); | |
1956 | } else { | |
1957 | /* OUT packet from host */ | |
1958 | udc->ep0state = DATA_OUT; | |
1959 | status = udc_ep0_out_req(udc); | |
1960 | } | |
1961 | } else if (ep->is_in) { | |
1962 | /* IN packet to host and kick off transfer */ | |
1963 | if (!ep->req_pending) | |
1964 | udc_ep_in_req_dma(udc, ep); | |
1965 | } else | |
1966 | /* OUT packet from host and kick off list */ | |
1967 | if (!ep->req_pending) | |
1968 | udc_ep_out_req_dma(udc, ep); | |
1969 | } else | |
1970 | list_add_tail(&req->queue, &ep->queue); | |
1971 | ||
1972 | spin_unlock_irqrestore(&udc->lock, flags); | |
1973 | ||
1974 | return (status < 0) ? status : 0; | |
1975 | } | |
1976 | ||
1977 | /* Must be called without lock */ | |
1978 | static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
1979 | { | |
1980 | struct lpc32xx_ep *ep; | |
1981 | struct lpc32xx_request *req; | |
1982 | unsigned long flags; | |
1983 | ||
1984 | ep = container_of(_ep, struct lpc32xx_ep, ep); | |
1985 | if (!_ep || ep->hwep_num_base == 0) | |
1986 | return -EINVAL; | |
1987 | ||
1988 | spin_lock_irqsave(&ep->udc->lock, flags); | |
1989 | ||
1990 | /* make sure it's actually queued on this endpoint */ | |
1991 | list_for_each_entry(req, &ep->queue, queue) { | |
1992 | if (&req->req == _req) | |
1993 | break; | |
1994 | } | |
1995 | if (&req->req != _req) { | |
1996 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
1997 | return -EINVAL; | |
1998 | } | |
1999 | ||
2000 | done(ep, req, -ECONNRESET); | |
2001 | ||
2002 | spin_unlock_irqrestore(&ep->udc->lock, flags); | |
2003 | ||
2004 | return 0; | |
2005 | } | |
2006 | ||
2007 | /* Must be called without lock */ | |
2008 | static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value) | |
2009 | { | |
2010 | struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); | |
2011 | struct lpc32xx_udc *udc = ep->udc; | |
2012 | unsigned long flags; | |
2013 | ||
2014 | if ((!ep) || (ep->desc == NULL) || (ep->hwep_num <= 1)) | |
2015 | return -EINVAL; | |
2016 | ||
2017 | /* Don't halt an IN EP */ | |
2018 | if (ep->is_in) | |
2019 | return -EAGAIN; | |
2020 | ||
2021 | spin_lock_irqsave(&udc->lock, flags); | |
2022 | ||
2023 | if (value == 1) { | |
2024 | /* stall */ | |
2025 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), | |
2026 | DAT_WR_BYTE(EP_STAT_ST)); | |
2027 | } else { | |
2028 | /* End stall */ | |
2029 | ep->wedge = 0; | |
2030 | udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), | |
2031 | DAT_WR_BYTE(0)); | |
2032 | } | |
2033 | ||
2034 | spin_unlock_irqrestore(&udc->lock, flags); | |
2035 | ||
2036 | return 0; | |
2037 | } | |
2038 | ||
2039 | /* set the halt feature and ignores clear requests */ | |
2040 | static int lpc32xx_ep_set_wedge(struct usb_ep *_ep) | |
2041 | { | |
2042 | struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); | |
2043 | ||
2044 | if (!_ep || !ep->udc) | |
2045 | return -EINVAL; | |
2046 | ||
2047 | ep->wedge = 1; | |
2048 | ||
2049 | return usb_ep_set_halt(_ep); | |
2050 | } | |
2051 | ||
2052 | static const struct usb_ep_ops lpc32xx_ep_ops = { | |
2053 | .enable = lpc32xx_ep_enable, | |
2054 | .disable = lpc32xx_ep_disable, | |
2055 | .alloc_request = lpc32xx_ep_alloc_request, | |
2056 | .free_request = lpc32xx_ep_free_request, | |
2057 | .queue = lpc32xx_ep_queue, | |
2058 | .dequeue = lpc32xx_ep_dequeue, | |
2059 | .set_halt = lpc32xx_ep_set_halt, | |
2060 | .set_wedge = lpc32xx_ep_set_wedge, | |
2061 | }; | |
2062 | ||
2063 | /* Send a ZLP on a non-0 IN EP */ | |
2064 | void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) | |
2065 | { | |
2066 | /* Clear EP status */ | |
2067 | udc_clearep_getsts(udc, ep->hwep_num); | |
2068 | ||
2069 | /* Send ZLP via FIFO mechanism */ | |
2070 | udc_write_hwep(udc, ep->hwep_num, NULL, 0); | |
2071 | } | |
2072 | ||
2073 | /* | |
2074 | * Handle EP completion for ZLP | |
2075 | * This function will only be called when a delayed ZLP needs to be sent out | |
2076 | * after a DMA transfer has filled both buffers. | |
2077 | */ | |
2078 | void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) | |
2079 | { | |
2080 | u32 epstatus; | |
2081 | struct lpc32xx_request *req; | |
2082 | ||
2083 | if (ep->hwep_num <= 0) | |
2084 | return; | |
2085 | ||
2086 | uda_clear_hwepint(udc, ep->hwep_num); | |
2087 | ||
2088 | /* If this interrupt isn't enabled, return now */ | |
2089 | if (!(udc->enabled_hwepints & (1 << ep->hwep_num))) | |
2090 | return; | |
2091 | ||
2092 | /* Get endpoint status */ | |
2093 | epstatus = udc_clearep_getsts(udc, ep->hwep_num); | |
2094 | ||
2095 | /* | |
2096 | * This should never happen, but protect against writing to the | |
2097 | * buffer when full. | |
2098 | */ | |
2099 | if (epstatus & EP_SEL_F) | |
2100 | return; | |
2101 | ||
2102 | if (ep->is_in) { | |
2103 | udc_send_in_zlp(udc, ep); | |
2104 | uda_disable_hwepint(udc, ep->hwep_num); | |
2105 | } else | |
2106 | return; | |
2107 | ||
2108 | /* If there isn't a request waiting, something went wrong */ | |
2109 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); | |
2110 | if (req) { | |
2111 | done(ep, req, 0); | |
2112 | ||
2113 | /* Start another request if ready */ | |
2114 | if (!list_empty(&ep->queue)) { | |
2115 | if (ep->is_in) | |
2116 | udc_ep_in_req_dma(udc, ep); | |
2117 | else | |
2118 | udc_ep_out_req_dma(udc, ep); | |
2119 | } else | |
2120 | ep->req_pending = 0; | |
2121 | } | |
2122 | } | |
2123 | ||
2124 | ||
2125 | /* DMA end of transfer completion */ | |
2126 | static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) | |
2127 | { | |
2128 | u32 status, epstatus; | |
2129 | struct lpc32xx_request *req; | |
2130 | struct lpc32xx_usbd_dd_gad *dd; | |
2131 | ||
2132 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
2133 | ep->totalints++; | |
2134 | #endif | |
2135 | ||
2136 | req = list_entry(ep->queue.next, struct lpc32xx_request, queue); | |
2137 | if (!req) { | |
2138 | ep_err(ep, "DMA interrupt on no req!\n"); | |
2139 | return; | |
2140 | } | |
2141 | dd = req->dd_desc_ptr; | |
2142 | ||
2143 | /* DMA descriptor should always be retired for this call */ | |
2144 | if (!(dd->dd_status & DD_STATUS_DD_RETIRED)) | |
2145 | ep_warn(ep, "DMA descriptor did not retire\n"); | |
2146 | ||
2147 | /* Disable DMA */ | |
2148 | udc_ep_dma_disable(udc, ep->hwep_num); | |
2149 | writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr)); | |
2150 | writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr)); | |
2151 | ||
2152 | /* System error? */ | |
2153 | if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) & | |
2154 | (1 << ep->hwep_num)) { | |
2155 | writel((1 << ep->hwep_num), | |
2156 | USBD_SYSERRTINTCLR(udc->udp_baseaddr)); | |
2157 | ep_err(ep, "AHB critical error!\n"); | |
2158 | ep->req_pending = 0; | |
2159 | ||
2160 | /* The error could have occurred on a packet of a multipacket | |
2161 | * transfer, so recovering the transfer is not possible. Close | |
2162 | * the request with an error */ | |
2163 | done(ep, req, -ECONNABORTED); | |
2164 | return; | |
2165 | } | |
2166 | ||
2167 | /* Handle the current DD's status */ | |
2168 | status = dd->dd_status; | |
2169 | switch (status & DD_STATUS_STS_MASK) { | |
2170 | case DD_STATUS_STS_NS: | |
2171 | /* DD not serviced? This shouldn't happen! */ | |
2172 | ep->req_pending = 0; | |
2173 | ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n", | |
2174 | status); | |
2175 | ||
2176 | done(ep, req, -ECONNABORTED); | |
2177 | return; | |
2178 | ||
2179 | case DD_STATUS_STS_BS: | |
2180 | /* Interrupt only fires on EOT - This shouldn't happen! */ | |
2181 | ep->req_pending = 0; | |
2182 | ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n", | |
2183 | status); | |
2184 | done(ep, req, -ECONNABORTED); | |
2185 | return; | |
2186 | ||
2187 | case DD_STATUS_STS_NC: | |
2188 | case DD_STATUS_STS_DUR: | |
2189 | /* Really just a short packet, not an underrun */ | |
2190 | /* This is a good status and what we expect */ | |
2191 | break; | |
2192 | ||
2193 | default: | |
2194 | /* Data overrun, system error, or unknown */ | |
2195 | ep->req_pending = 0; | |
2196 | ep_err(ep, "DMA critical EP error: System error (0x%x)!\n", | |
2197 | status); | |
2198 | done(ep, req, -ECONNABORTED); | |
2199 | return; | |
2200 | } | |
2201 | ||
2202 | /* ISO endpoints are handled differently */ | |
2203 | if (ep->eptype == EP_ISO_TYPE) { | |
2204 | if (ep->is_in) | |
2205 | req->req.actual = req->req.length; | |
2206 | else | |
2207 | req->req.actual = dd->iso_status[0] & 0xFFFF; | |
2208 | } else | |
2209 | req->req.actual += DD_STATUS_CURDMACNT(status); | |
2210 | ||
2211 | /* Send a ZLP if necessary. This will be done for non-int | |
2212 | * packets which have a size that is a divisor of MAXP */ | |
2213 | if (req->send_zlp) { | |
2214 | /* | |
2215 | * If at least 1 buffer is available, send the ZLP now. | |
2216 | * Otherwise, the ZLP send needs to be deferred until a | |
2217 | * buffer is available. | |
2218 | */ | |
2219 | if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) { | |
2220 | udc_clearep_getsts(udc, ep->hwep_num); | |
2221 | uda_enable_hwepint(udc, ep->hwep_num); | |
2222 | epstatus = udc_clearep_getsts(udc, ep->hwep_num); | |
2223 | ||
2224 | /* Let the EP interrupt handle the ZLP */ | |
2225 | return; | |
2226 | } else | |
2227 | udc_send_in_zlp(udc, ep); | |
2228 | } | |
2229 | ||
2230 | /* Transfer request is complete */ | |
2231 | done(ep, req, 0); | |
2232 | ||
2233 | /* Start another request if ready */ | |
2234 | udc_clearep_getsts(udc, ep->hwep_num); | |
2235 | if (!list_empty((&ep->queue))) { | |
2236 | if (ep->is_in) | |
2237 | udc_ep_in_req_dma(udc, ep); | |
2238 | else | |
2239 | udc_ep_out_req_dma(udc, ep); | |
2240 | } else | |
2241 | ep->req_pending = 0; | |
2242 | ||
2243 | } | |
2244 | ||
2245 | /* | |
2246 | * | |
2247 | * Endpoint 0 functions | |
2248 | * | |
2249 | */ | |
2250 | static void udc_handle_dev(struct lpc32xx_udc *udc) | |
2251 | { | |
2252 | u32 tmp; | |
2253 | ||
2254 | udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT); | |
2255 | tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT); | |
2256 | ||
2257 | if (tmp & DEV_RST) | |
2258 | uda_usb_reset(udc); | |
2259 | else if (tmp & DEV_CON_CH) | |
2260 | uda_power_event(udc, (tmp & DEV_CON)); | |
2261 | else if (tmp & DEV_SUS_CH) { | |
2262 | if (tmp & DEV_SUS) { | |
2263 | if (udc->vbus == 0) | |
2264 | stop_activity(udc); | |
2265 | else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && | |
2266 | udc->driver) { | |
2267 | /* Power down transceiver */ | |
2268 | udc->poweron = 0; | |
2269 | schedule_work(&udc->pullup_job); | |
2270 | uda_resm_susp_event(udc, 1); | |
2271 | } | |
2272 | } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && | |
2273 | udc->driver && udc->vbus) { | |
2274 | uda_resm_susp_event(udc, 0); | |
2275 | /* Power up transceiver */ | |
2276 | udc->poweron = 1; | |
2277 | schedule_work(&udc->pullup_job); | |
2278 | } | |
2279 | } | |
2280 | } | |
2281 | ||
2282 | static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex) | |
2283 | { | |
2284 | struct lpc32xx_ep *ep; | |
2285 | u32 ep0buff = 0, tmp; | |
2286 | ||
2287 | switch (reqtype & USB_RECIP_MASK) { | |
2288 | case USB_RECIP_INTERFACE: | |
2289 | break; /* Not supported */ | |
2290 | ||
2291 | case USB_RECIP_DEVICE: | |
2292 | ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED); | |
2293 | if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP)) | |
2294 | ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP); | |
2295 | break; | |
2296 | ||
2297 | case USB_RECIP_ENDPOINT: | |
2298 | tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; | |
2299 | ep = &udc->ep[tmp]; | |
2300 | if ((tmp == 0) || (tmp >= NUM_ENDPOINTS) || (tmp && !ep->desc)) | |
2301 | return -EOPNOTSUPP; | |
2302 | ||
2303 | if (wIndex & USB_DIR_IN) { | |
2304 | if (!ep->is_in) | |
2305 | return -EOPNOTSUPP; /* Something's wrong */ | |
2306 | } else if (ep->is_in) | |
2307 | return -EOPNOTSUPP; /* Not an IN endpoint */ | |
2308 | ||
2309 | /* Get status of the endpoint */ | |
2310 | udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num)); | |
2311 | tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num)); | |
2312 | ||
2313 | if (tmp & EP_SEL_ST) | |
2314 | ep0buff = (1 << USB_ENDPOINT_HALT); | |
2315 | else | |
2316 | ep0buff = 0; | |
2317 | break; | |
2318 | ||
2319 | default: | |
2320 | break; | |
2321 | } | |
2322 | ||
2323 | /* Return data */ | |
2324 | udc_write_hwep(udc, EP_IN, &ep0buff, 2); | |
2325 | ||
2326 | return 0; | |
2327 | } | |
2328 | ||
2329 | static void udc_handle_ep0_setup(struct lpc32xx_udc *udc) | |
2330 | { | |
2331 | struct lpc32xx_ep *ep, *ep0 = &udc->ep[0]; | |
2332 | struct usb_ctrlrequest ctrlpkt; | |
2333 | int i, bytes; | |
2334 | u16 wIndex, wValue, wLength, reqtype, req, tmp; | |
2335 | ||
2336 | /* Nuke previous transfers */ | |
2337 | nuke(ep0, -EPROTO); | |
2338 | ||
2339 | /* Get setup packet */ | |
2340 | bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8); | |
2341 | if (bytes != 8) { | |
2342 | ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n", | |
2343 | bytes); | |
2344 | return; | |
2345 | } | |
2346 | ||
2347 | /* Native endianness */ | |
2348 | wIndex = le16_to_cpu(ctrlpkt.wIndex); | |
2349 | wValue = le16_to_cpu(ctrlpkt.wValue); | |
2350 | wLength = le16_to_cpu(ctrlpkt.wLength); | |
2351 | reqtype = le16_to_cpu(ctrlpkt.bRequestType); | |
2352 | ||
2353 | /* Set direction of EP0 */ | |
2354 | if (likely(reqtype & USB_DIR_IN)) | |
2355 | ep0->is_in = 1; | |
2356 | else | |
2357 | ep0->is_in = 0; | |
2358 | ||
2359 | /* Handle SETUP packet */ | |
2360 | req = le16_to_cpu(ctrlpkt.bRequest); | |
2361 | switch (req) { | |
2362 | case USB_REQ_CLEAR_FEATURE: | |
2363 | case USB_REQ_SET_FEATURE: | |
2364 | switch (reqtype) { | |
2365 | case (USB_TYPE_STANDARD | USB_RECIP_DEVICE): | |
2366 | if (wValue != USB_DEVICE_REMOTE_WAKEUP) | |
2367 | goto stall; /* Nothing else handled */ | |
2368 | ||
2369 | /* Tell board about event */ | |
2370 | if (req == USB_REQ_CLEAR_FEATURE) | |
2371 | udc->dev_status &= | |
2372 | ~(1 << USB_DEVICE_REMOTE_WAKEUP); | |
2373 | else | |
2374 | udc->dev_status |= | |
2375 | (1 << USB_DEVICE_REMOTE_WAKEUP); | |
2376 | uda_remwkp_cgh(udc); | |
2377 | goto zlp_send; | |
2378 | ||
2379 | case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT): | |
2380 | tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; | |
2381 | if ((wValue != USB_ENDPOINT_HALT) || | |
2382 | (tmp >= NUM_ENDPOINTS)) | |
2383 | break; | |
2384 | ||
2385 | /* Find hardware endpoint from logical endpoint */ | |
2386 | ep = &udc->ep[tmp]; | |
2387 | tmp = ep->hwep_num; | |
2388 | if (tmp == 0) | |
2389 | break; | |
2390 | ||
2391 | if (req == USB_REQ_SET_FEATURE) | |
2392 | udc_stall_hwep(udc, tmp); | |
2393 | else if (!ep->wedge) | |
2394 | udc_clrstall_hwep(udc, tmp); | |
2395 | ||
2396 | goto zlp_send; | |
2397 | ||
2398 | default: | |
2399 | break; | |
2400 | } | |
2401 | ||
2402 | ||
2403 | case USB_REQ_SET_ADDRESS: | |
2404 | if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) { | |
2405 | udc_set_address(udc, wValue); | |
2406 | goto zlp_send; | |
2407 | } | |
2408 | break; | |
2409 | ||
2410 | case USB_REQ_GET_STATUS: | |
2411 | udc_get_status(udc, reqtype, wIndex); | |
2412 | return; | |
2413 | ||
2414 | default: | |
2415 | break; /* Let GadgetFS handle the descriptor instead */ | |
2416 | } | |
2417 | ||
2418 | if (likely(udc->driver)) { | |
2419 | /* device-2-host (IN) or no data setup command, process | |
2420 | * immediately */ | |
2421 | spin_unlock(&udc->lock); | |
2422 | i = udc->driver->setup(&udc->gadget, &ctrlpkt); | |
2423 | ||
2424 | spin_lock(&udc->lock); | |
2425 | if (req == USB_REQ_SET_CONFIGURATION) { | |
2426 | /* Configuration is set after endpoints are realized */ | |
2427 | if (wValue) { | |
2428 | /* Set configuration */ | |
2429 | udc_set_device_configured(udc); | |
2430 | ||
2431 | udc_protocol_cmd_data_w(udc, CMD_SET_MODE, | |
2432 | DAT_WR_BYTE(AP_CLK | | |
2433 | INAK_BI | INAK_II)); | |
2434 | } else { | |
2435 | /* Clear configuration */ | |
2436 | udc_set_device_unconfigured(udc); | |
2437 | ||
2438 | /* Disable NAK interrupts */ | |
2439 | udc_protocol_cmd_data_w(udc, CMD_SET_MODE, | |
2440 | DAT_WR_BYTE(AP_CLK)); | |
2441 | } | |
2442 | } | |
2443 | ||
2444 | if (i < 0) { | |
2445 | /* setup processing failed, force stall */ | |
2446 | dev_err(udc->dev, | |
2447 | "req %02x.%02x protocol STALL; stat %d\n", | |
2448 | reqtype, req, i); | |
2449 | udc->ep0state = WAIT_FOR_SETUP; | |
2450 | goto stall; | |
2451 | } | |
2452 | } | |
2453 | ||
2454 | if (!ep0->is_in) | |
2455 | udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */ | |
2456 | ||
2457 | return; | |
2458 | ||
2459 | stall: | |
2460 | udc_stall_hwep(udc, EP_IN); | |
2461 | return; | |
2462 | ||
2463 | zlp_send: | |
2464 | udc_ep0_send_zlp(udc); | |
2465 | return; | |
2466 | } | |
2467 | ||
2468 | /* IN endpoint 0 transfer */ | |
2469 | static void udc_handle_ep0_in(struct lpc32xx_udc *udc) | |
2470 | { | |
2471 | struct lpc32xx_ep *ep0 = &udc->ep[0]; | |
2472 | u32 epstatus; | |
2473 | ||
2474 | /* Clear EP interrupt */ | |
2475 | epstatus = udc_clearep_getsts(udc, EP_IN); | |
2476 | ||
2477 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
2478 | ep0->totalints++; | |
2479 | #endif | |
2480 | ||
2481 | /* Stalled? Clear stall and reset buffers */ | |
2482 | if (epstatus & EP_SEL_ST) { | |
2483 | udc_clrstall_hwep(udc, EP_IN); | |
2484 | nuke(ep0, -ECONNABORTED); | |
2485 | udc->ep0state = WAIT_FOR_SETUP; | |
2486 | return; | |
2487 | } | |
2488 | ||
2489 | /* Is a buffer available? */ | |
2490 | if (!(epstatus & EP_SEL_F)) { | |
2491 | /* Handle based on current state */ | |
2492 | if (udc->ep0state == DATA_IN) | |
2493 | udc_ep0_in_req(udc); | |
2494 | else { | |
2495 | /* Unknown state for EP0 oe end of DATA IN phase */ | |
2496 | nuke(ep0, -ECONNABORTED); | |
2497 | udc->ep0state = WAIT_FOR_SETUP; | |
2498 | } | |
2499 | } | |
2500 | } | |
2501 | ||
2502 | /* OUT endpoint 0 transfer */ | |
2503 | static void udc_handle_ep0_out(struct lpc32xx_udc *udc) | |
2504 | { | |
2505 | struct lpc32xx_ep *ep0 = &udc->ep[0]; | |
2506 | u32 epstatus; | |
2507 | ||
2508 | /* Clear EP interrupt */ | |
2509 | epstatus = udc_clearep_getsts(udc, EP_OUT); | |
2510 | ||
2511 | ||
2512 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
2513 | ep0->totalints++; | |
2514 | #endif | |
2515 | ||
2516 | /* Stalled? */ | |
2517 | if (epstatus & EP_SEL_ST) { | |
2518 | udc_clrstall_hwep(udc, EP_OUT); | |
2519 | nuke(ep0, -ECONNABORTED); | |
2520 | udc->ep0state = WAIT_FOR_SETUP; | |
2521 | return; | |
2522 | } | |
2523 | ||
2524 | /* A NAK may occur if a packet couldn't be received yet */ | |
2525 | if (epstatus & EP_SEL_EPN) | |
2526 | return; | |
2527 | /* Setup packet incoming? */ | |
2528 | if (epstatus & EP_SEL_STP) { | |
2529 | nuke(ep0, 0); | |
2530 | udc->ep0state = WAIT_FOR_SETUP; | |
2531 | } | |
2532 | ||
2533 | /* Data available? */ | |
2534 | if (epstatus & EP_SEL_F) | |
2535 | /* Handle based on current state */ | |
2536 | switch (udc->ep0state) { | |
2537 | case WAIT_FOR_SETUP: | |
2538 | udc_handle_ep0_setup(udc); | |
2539 | break; | |
2540 | ||
2541 | case DATA_OUT: | |
2542 | udc_ep0_out_req(udc); | |
2543 | break; | |
2544 | ||
2545 | default: | |
2546 | /* Unknown state for EP0 */ | |
2547 | nuke(ep0, -ECONNABORTED); | |
2548 | udc->ep0state = WAIT_FOR_SETUP; | |
2549 | } | |
2550 | } | |
2551 | ||
2552 | /* Must be called without lock */ | |
2553 | static int lpc32xx_get_frame(struct usb_gadget *gadget) | |
2554 | { | |
2555 | int frame; | |
2556 | unsigned long flags; | |
2557 | struct lpc32xx_udc *udc = to_udc(gadget); | |
2558 | ||
2559 | if (!udc->clocked) | |
2560 | return -EINVAL; | |
2561 | ||
2562 | spin_lock_irqsave(&udc->lock, flags); | |
2563 | ||
2564 | frame = (int) udc_get_current_frame(udc); | |
2565 | ||
2566 | spin_unlock_irqrestore(&udc->lock, flags); | |
2567 | ||
2568 | return frame; | |
2569 | } | |
2570 | ||
2571 | static int lpc32xx_wakeup(struct usb_gadget *gadget) | |
2572 | { | |
2573 | return -ENOTSUPP; | |
2574 | } | |
2575 | ||
2576 | static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on) | |
2577 | { | |
2578 | struct lpc32xx_udc *udc = to_udc(gadget); | |
2579 | ||
2580 | /* Always self-powered */ | |
2581 | udc->selfpowered = (is_on != 0); | |
2582 | ||
2583 | return 0; | |
2584 | } | |
2585 | ||
2586 | /* | |
2587 | * vbus is here! turn everything on that's ready | |
2588 | * Must be called without lock | |
2589 | */ | |
2590 | static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active) | |
2591 | { | |
2592 | unsigned long flags; | |
2593 | struct lpc32xx_udc *udc = to_udc(gadget); | |
2594 | ||
2595 | spin_lock_irqsave(&udc->lock, flags); | |
2596 | ||
2597 | /* Doesn't need lock */ | |
2598 | if (udc->driver) { | |
2599 | udc_clk_set(udc, 1); | |
2600 | udc_enable(udc); | |
2601 | pullup(udc, is_active); | |
2602 | } else { | |
2603 | stop_activity(udc); | |
2604 | pullup(udc, 0); | |
2605 | ||
2606 | spin_unlock_irqrestore(&udc->lock, flags); | |
2607 | /* | |
2608 | * Wait for all the endpoints to disable, | |
2609 | * before disabling clocks. Don't wait if | |
2610 | * endpoints are not enabled. | |
2611 | */ | |
2612 | if (atomic_read(&udc->enabled_ep_cnt)) | |
2613 | wait_event_interruptible(udc->ep_disable_wait_queue, | |
2614 | (atomic_read(&udc->enabled_ep_cnt) == 0)); | |
2615 | ||
2616 | spin_lock_irqsave(&udc->lock, flags); | |
2617 | ||
2618 | udc_clk_set(udc, 0); | |
2619 | } | |
2620 | ||
2621 | spin_unlock_irqrestore(&udc->lock, flags); | |
2622 | ||
2623 | return 0; | |
2624 | } | |
2625 | ||
2626 | /* Can be called with or without lock */ | |
2627 | static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on) | |
2628 | { | |
2629 | struct lpc32xx_udc *udc = to_udc(gadget); | |
2630 | ||
2631 | /* Doesn't need lock */ | |
2632 | pullup(udc, is_on); | |
2633 | ||
2634 | return 0; | |
2635 | } | |
2636 | ||
2637 | static int lpc32xx_start(struct usb_gadget_driver *driver, | |
2638 | int (*bind)(struct usb_gadget *)); | |
2639 | static int lpc32xx_stop(struct usb_gadget_driver *driver); | |
2640 | ||
2641 | static const struct usb_gadget_ops lpc32xx_udc_ops = { | |
2642 | .get_frame = lpc32xx_get_frame, | |
2643 | .wakeup = lpc32xx_wakeup, | |
2644 | .set_selfpowered = lpc32xx_set_selfpowered, | |
2645 | .vbus_session = lpc32xx_vbus_session, | |
2646 | .pullup = lpc32xx_pullup, | |
2647 | .start = lpc32xx_start, | |
2648 | .stop = lpc32xx_stop, | |
2649 | }; | |
2650 | ||
2651 | static void nop_release(struct device *dev) | |
2652 | { | |
2653 | /* nothing to free */ | |
2654 | } | |
2655 | ||
2656 | static struct lpc32xx_udc controller = { | |
2657 | .gadget = { | |
2658 | .ops = &lpc32xx_udc_ops, | |
2659 | .ep0 = &controller.ep[0].ep, | |
2660 | .name = driver_name, | |
2661 | .dev = { | |
2662 | .init_name = "gadget", | |
2663 | .release = nop_release, | |
2664 | } | |
2665 | }, | |
2666 | .ep[0] = { | |
2667 | .ep = { | |
2668 | .name = "ep0", | |
2669 | .ops = &lpc32xx_ep_ops, | |
2670 | }, | |
2671 | .udc = &controller, | |
2672 | .maxpacket = 64, | |
2673 | .hwep_num_base = 0, | |
2674 | .hwep_num = 0, /* Can be 0 or 1, has special handling */ | |
2675 | .lep = 0, | |
2676 | .eptype = EP_CTL_TYPE, | |
2677 | }, | |
2678 | .ep[1] = { | |
2679 | .ep = { | |
2680 | .name = "ep1-int", | |
2681 | .ops = &lpc32xx_ep_ops, | |
2682 | }, | |
2683 | .udc = &controller, | |
2684 | .maxpacket = 64, | |
2685 | .hwep_num_base = 2, | |
2686 | .hwep_num = 0, /* 2 or 3, will be set later */ | |
2687 | .lep = 1, | |
2688 | .eptype = EP_INT_TYPE, | |
2689 | }, | |
2690 | .ep[2] = { | |
2691 | .ep = { | |
2692 | .name = "ep2-bulk", | |
2693 | .ops = &lpc32xx_ep_ops, | |
2694 | }, | |
2695 | .udc = &controller, | |
2696 | .maxpacket = 64, | |
2697 | .hwep_num_base = 4, | |
2698 | .hwep_num = 0, /* 4 or 5, will be set later */ | |
2699 | .lep = 2, | |
2700 | .eptype = EP_BLK_TYPE, | |
2701 | }, | |
2702 | .ep[3] = { | |
2703 | .ep = { | |
2704 | .name = "ep3-iso", | |
2705 | .ops = &lpc32xx_ep_ops, | |
2706 | }, | |
2707 | .udc = &controller, | |
2708 | .maxpacket = 1023, | |
2709 | .hwep_num_base = 6, | |
2710 | .hwep_num = 0, /* 6 or 7, will be set later */ | |
2711 | .lep = 3, | |
2712 | .eptype = EP_ISO_TYPE, | |
2713 | }, | |
2714 | .ep[4] = { | |
2715 | .ep = { | |
2716 | .name = "ep4-int", | |
2717 | .ops = &lpc32xx_ep_ops, | |
2718 | }, | |
2719 | .udc = &controller, | |
2720 | .maxpacket = 64, | |
2721 | .hwep_num_base = 8, | |
2722 | .hwep_num = 0, /* 8 or 9, will be set later */ | |
2723 | .lep = 4, | |
2724 | .eptype = EP_INT_TYPE, | |
2725 | }, | |
2726 | .ep[5] = { | |
2727 | .ep = { | |
2728 | .name = "ep5-bulk", | |
2729 | .ops = &lpc32xx_ep_ops, | |
2730 | }, | |
2731 | .udc = &controller, | |
2732 | .maxpacket = 64, | |
2733 | .hwep_num_base = 10, | |
2734 | .hwep_num = 0, /* 10 or 11, will be set later */ | |
2735 | .lep = 5, | |
2736 | .eptype = EP_BLK_TYPE, | |
2737 | }, | |
2738 | .ep[6] = { | |
2739 | .ep = { | |
2740 | .name = "ep6-iso", | |
2741 | .ops = &lpc32xx_ep_ops, | |
2742 | }, | |
2743 | .udc = &controller, | |
2744 | .maxpacket = 1023, | |
2745 | .hwep_num_base = 12, | |
2746 | .hwep_num = 0, /* 12 or 13, will be set later */ | |
2747 | .lep = 6, | |
2748 | .eptype = EP_ISO_TYPE, | |
2749 | }, | |
2750 | .ep[7] = { | |
2751 | .ep = { | |
2752 | .name = "ep7-int", | |
2753 | .ops = &lpc32xx_ep_ops, | |
2754 | }, | |
2755 | .udc = &controller, | |
2756 | .maxpacket = 64, | |
2757 | .hwep_num_base = 14, | |
2758 | .hwep_num = 0, | |
2759 | .lep = 7, | |
2760 | .eptype = EP_INT_TYPE, | |
2761 | }, | |
2762 | .ep[8] = { | |
2763 | .ep = { | |
2764 | .name = "ep8-bulk", | |
2765 | .ops = &lpc32xx_ep_ops, | |
2766 | }, | |
2767 | .udc = &controller, | |
2768 | .maxpacket = 64, | |
2769 | .hwep_num_base = 16, | |
2770 | .hwep_num = 0, | |
2771 | .lep = 8, | |
2772 | .eptype = EP_BLK_TYPE, | |
2773 | }, | |
2774 | .ep[9] = { | |
2775 | .ep = { | |
2776 | .name = "ep9-iso", | |
2777 | .ops = &lpc32xx_ep_ops, | |
2778 | }, | |
2779 | .udc = &controller, | |
2780 | .maxpacket = 1023, | |
2781 | .hwep_num_base = 18, | |
2782 | .hwep_num = 0, | |
2783 | .lep = 9, | |
2784 | .eptype = EP_ISO_TYPE, | |
2785 | }, | |
2786 | .ep[10] = { | |
2787 | .ep = { | |
2788 | .name = "ep10-int", | |
2789 | .ops = &lpc32xx_ep_ops, | |
2790 | }, | |
2791 | .udc = &controller, | |
2792 | .maxpacket = 64, | |
2793 | .hwep_num_base = 20, | |
2794 | .hwep_num = 0, | |
2795 | .lep = 10, | |
2796 | .eptype = EP_INT_TYPE, | |
2797 | }, | |
2798 | .ep[11] = { | |
2799 | .ep = { | |
2800 | .name = "ep11-bulk", | |
2801 | .ops = &lpc32xx_ep_ops, | |
2802 | }, | |
2803 | .udc = &controller, | |
2804 | .maxpacket = 64, | |
2805 | .hwep_num_base = 22, | |
2806 | .hwep_num = 0, | |
2807 | .lep = 11, | |
2808 | .eptype = EP_BLK_TYPE, | |
2809 | }, | |
2810 | .ep[12] = { | |
2811 | .ep = { | |
2812 | .name = "ep12-iso", | |
2813 | .ops = &lpc32xx_ep_ops, | |
2814 | }, | |
2815 | .udc = &controller, | |
2816 | .maxpacket = 1023, | |
2817 | .hwep_num_base = 24, | |
2818 | .hwep_num = 0, | |
2819 | .lep = 12, | |
2820 | .eptype = EP_ISO_TYPE, | |
2821 | }, | |
2822 | .ep[13] = { | |
2823 | .ep = { | |
2824 | .name = "ep13-int", | |
2825 | .ops = &lpc32xx_ep_ops, | |
2826 | }, | |
2827 | .udc = &controller, | |
2828 | .maxpacket = 64, | |
2829 | .hwep_num_base = 26, | |
2830 | .hwep_num = 0, | |
2831 | .lep = 13, | |
2832 | .eptype = EP_INT_TYPE, | |
2833 | }, | |
2834 | .ep[14] = { | |
2835 | .ep = { | |
2836 | .name = "ep14-bulk", | |
2837 | .ops = &lpc32xx_ep_ops, | |
2838 | }, | |
2839 | .udc = &controller, | |
2840 | .maxpacket = 64, | |
2841 | .hwep_num_base = 28, | |
2842 | .hwep_num = 0, | |
2843 | .lep = 14, | |
2844 | .eptype = EP_BLK_TYPE, | |
2845 | }, | |
2846 | .ep[15] = { | |
2847 | .ep = { | |
2848 | .name = "ep15-bulk", | |
2849 | .ops = &lpc32xx_ep_ops, | |
2850 | }, | |
2851 | .udc = &controller, | |
2852 | .maxpacket = 1023, | |
2853 | .hwep_num_base = 30, | |
2854 | .hwep_num = 0, | |
2855 | .lep = 15, | |
2856 | .eptype = EP_BLK_TYPE, | |
2857 | }, | |
2858 | }; | |
2859 | ||
2860 | /* ISO and status interrupts */ | |
2861 | static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc) | |
2862 | { | |
2863 | u32 tmp, devstat; | |
2864 | struct lpc32xx_udc *udc = _udc; | |
2865 | ||
2866 | spin_lock(&udc->lock); | |
2867 | ||
2868 | /* Read the device status register */ | |
2869 | devstat = readl(USBD_DEVINTST(udc->udp_baseaddr)); | |
2870 | ||
2871 | devstat &= ~USBD_EP_FAST; | |
2872 | writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr)); | |
2873 | devstat = devstat & udc->enabled_devints; | |
2874 | ||
2875 | /* Device specific handling needed? */ | |
2876 | if (devstat & USBD_DEV_STAT) | |
2877 | udc_handle_dev(udc); | |
2878 | ||
2879 | /* Start of frame? (devstat & FRAME_INT): | |
2880 | * The frame interrupt isn't really needed for ISO support, | |
2881 | * as the driver will queue the necessary packets */ | |
2882 | ||
2883 | /* Error? */ | |
2884 | if (devstat & ERR_INT) { | |
2885 | /* All types of errors, from cable removal during transfer to | |
2886 | * misc protocol and bit errors. These are mostly for just info, | |
2887 | * as the USB hardware will work around these. If these errors | |
2888 | * happen alot, something is wrong. */ | |
2889 | udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT); | |
2890 | tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT); | |
2891 | dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp); | |
2892 | } | |
2893 | ||
2894 | spin_unlock(&udc->lock); | |
2895 | ||
2896 | return IRQ_HANDLED; | |
2897 | } | |
2898 | ||
2899 | /* EP interrupts */ | |
2900 | static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc) | |
2901 | { | |
2902 | u32 tmp; | |
2903 | struct lpc32xx_udc *udc = _udc; | |
2904 | ||
2905 | spin_lock(&udc->lock); | |
2906 | ||
2907 | /* Read the device status register */ | |
2908 | writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr)); | |
2909 | ||
2910 | /* Endpoints */ | |
2911 | tmp = readl(USBD_EPINTST(udc->udp_baseaddr)); | |
2912 | ||
2913 | /* Special handling for EP0 */ | |
2914 | if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { | |
2915 | /* Handle EP0 IN */ | |
2916 | if (tmp & (EP_MASK_SEL(0, EP_IN))) | |
2917 | udc_handle_ep0_in(udc); | |
2918 | ||
2919 | /* Handle EP0 OUT */ | |
2920 | if (tmp & (EP_MASK_SEL(0, EP_OUT))) | |
2921 | udc_handle_ep0_out(udc); | |
2922 | } | |
2923 | ||
2924 | /* All other EPs */ | |
2925 | if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { | |
2926 | int i; | |
2927 | ||
2928 | /* Handle other EP interrupts */ | |
2929 | for (i = 1; i < NUM_ENDPOINTS; i++) { | |
2930 | if (tmp & (1 << udc->ep[i].hwep_num)) | |
2931 | udc_handle_eps(udc, &udc->ep[i]); | |
2932 | } | |
2933 | } | |
2934 | ||
2935 | spin_unlock(&udc->lock); | |
2936 | ||
2937 | return IRQ_HANDLED; | |
2938 | } | |
2939 | ||
2940 | static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc) | |
2941 | { | |
2942 | struct lpc32xx_udc *udc = _udc; | |
2943 | ||
2944 | int i; | |
2945 | u32 tmp; | |
2946 | ||
2947 | spin_lock(&udc->lock); | |
2948 | ||
2949 | /* Handle EP DMA EOT interrupts */ | |
2950 | tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) | | |
2951 | (readl(USBD_EPDMAST(udc->udp_baseaddr)) & | |
2952 | readl(USBD_NDDRTINTST(udc->udp_baseaddr))) | | |
2953 | readl(USBD_SYSERRTINTST(udc->udp_baseaddr)); | |
2954 | for (i = 1; i < NUM_ENDPOINTS; i++) { | |
2955 | if (tmp & (1 << udc->ep[i].hwep_num)) | |
2956 | udc_handle_dma_ep(udc, &udc->ep[i]); | |
2957 | } | |
2958 | ||
2959 | spin_unlock(&udc->lock); | |
2960 | ||
2961 | return IRQ_HANDLED; | |
2962 | } | |
2963 | ||
2964 | /* | |
2965 | * | |
2966 | * VBUS detection, pullup handler, and Gadget cable state notification | |
2967 | * | |
2968 | */ | |
2969 | static void vbus_work(struct work_struct *work) | |
2970 | { | |
2971 | u8 value; | |
2972 | struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc, | |
2973 | vbus_job); | |
2974 | ||
2975 | if (udc->enabled != 0) { | |
2976 | /* Discharge VBUS real quick */ | |
2977 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
2978 | ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); | |
2979 | ||
2980 | /* Give VBUS some time (100mS) to discharge */ | |
2981 | msleep(100); | |
2982 | ||
2983 | /* Disable VBUS discharge resistor */ | |
2984 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
2985 | ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, | |
2986 | OTG1_VBUS_DISCHRG); | |
2987 | ||
2988 | /* Clear interrupt */ | |
2989 | i2c_smbus_write_byte_data(udc->isp1301_i2c_client, | |
2990 | ISP1301_I2C_INTERRUPT_LATCH | | |
2991 | ISP1301_I2C_REG_CLEAR_ADDR, ~0); | |
2992 | ||
2993 | /* Get the VBUS status from the transceiver */ | |
2994 | value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client, | |
2995 | ISP1301_I2C_OTG_CONTROL_2); | |
2996 | ||
2997 | /* VBUS on or off? */ | |
2998 | if (value & OTG_B_SESS_VLD) | |
2999 | udc->vbus = 1; | |
3000 | else | |
3001 | udc->vbus = 0; | |
3002 | ||
3003 | /* VBUS changed? */ | |
3004 | if (udc->last_vbus != udc->vbus) { | |
3005 | udc->last_vbus = udc->vbus; | |
3006 | lpc32xx_vbus_session(&udc->gadget, udc->vbus); | |
3007 | } | |
3008 | } | |
3009 | ||
3010 | /* Re-enable after completion */ | |
3011 | enable_irq(udc->udp_irq[IRQ_USB_ATX]); | |
3012 | } | |
3013 | ||
3014 | static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc) | |
3015 | { | |
3016 | struct lpc32xx_udc *udc = _udc; | |
3017 | ||
3018 | /* Defer handling of VBUS IRQ to work queue */ | |
3019 | disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]); | |
3020 | schedule_work(&udc->vbus_job); | |
3021 | ||
3022 | return IRQ_HANDLED; | |
3023 | } | |
3024 | ||
3025 | static int lpc32xx_start(struct usb_gadget_driver *driver, | |
3026 | int (*bind)(struct usb_gadget *)) | |
3027 | { | |
3028 | struct lpc32xx_udc *udc = &controller; | |
3029 | int retval, i; | |
3030 | ||
3031 | if (!driver || driver->max_speed < USB_SPEED_FULL || | |
3032 | !bind || !driver->setup) { | |
3033 | dev_err(udc->dev, "bad parameter.\n"); | |
3034 | return -EINVAL; | |
3035 | } | |
3036 | ||
3037 | if (udc->driver) { | |
3038 | dev_err(udc->dev, "UDC already has a gadget driver\n"); | |
3039 | return -EBUSY; | |
3040 | } | |
3041 | ||
3042 | udc->driver = driver; | |
3043 | udc->gadget.dev.driver = &driver->driver; | |
3044 | udc->enabled = 1; | |
3045 | udc->selfpowered = 1; | |
3046 | udc->vbus = 0; | |
3047 | ||
3048 | retval = bind(&udc->gadget); | |
3049 | if (retval) { | |
3050 | dev_err(udc->dev, "bind() returned %d\n", retval); | |
3051 | udc->enabled = 0; | |
3052 | udc->selfpowered = 0; | |
3053 | udc->driver = NULL; | |
3054 | udc->gadget.dev.driver = NULL; | |
3055 | return retval; | |
3056 | } | |
3057 | ||
3058 | dev_dbg(udc->dev, "bound to %s\n", driver->driver.name); | |
3059 | ||
3060 | /* Force VBUS process once to check for cable insertion */ | |
3061 | udc->last_vbus = udc->vbus = 0; | |
3062 | schedule_work(&udc->vbus_job); | |
3063 | ||
3064 | /* Do not re-enable ATX IRQ (3) */ | |
3065 | for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++) | |
3066 | enable_irq(udc->udp_irq[i]); | |
3067 | ||
3068 | return 0; | |
3069 | } | |
3070 | ||
3071 | static int lpc32xx_stop(struct usb_gadget_driver *driver) | |
3072 | { | |
3073 | int i; | |
3074 | struct lpc32xx_udc *udc = &controller; | |
3075 | ||
3076 | if (!driver || driver != udc->driver || !driver->unbind) | |
3077 | return -EINVAL; | |
3078 | ||
3079 | /* Disable USB pullup */ | |
3080 | isp1301_pullup_enable(udc, 0, 1); | |
3081 | ||
3082 | for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++) | |
3083 | disable_irq(udc->udp_irq[i]); | |
3084 | ||
3085 | if (udc->clocked) { | |
3086 | ||
3087 | spin_lock(&udc->lock); | |
3088 | stop_activity(udc); | |
3089 | spin_unlock(&udc->lock); | |
3090 | ||
3091 | /* | |
3092 | * Wait for all the endpoints to disable, | |
3093 | * before disabling clocks. Don't wait if | |
3094 | * endpoints are not enabled. | |
3095 | */ | |
3096 | if (atomic_read(&udc->enabled_ep_cnt)) | |
3097 | wait_event_interruptible(udc->ep_disable_wait_queue, | |
3098 | (atomic_read(&udc->enabled_ep_cnt) == 0)); | |
3099 | ||
3100 | spin_lock(&udc->lock); | |
3101 | udc_clk_set(udc, 0); | |
3102 | spin_unlock(&udc->lock); | |
3103 | } | |
3104 | ||
3105 | udc->enabled = 0; | |
3106 | pullup(udc, 0); | |
3107 | ||
3108 | driver->unbind(&udc->gadget); | |
3109 | udc->gadget.dev.driver = NULL; | |
3110 | udc->driver = NULL; | |
3111 | ||
3112 | dev_dbg(udc->dev, "unbound from %s\n", driver->driver.name); | |
3113 | return 0; | |
3114 | } | |
3115 | ||
3116 | static void lpc32xx_udc_shutdown(struct platform_device *dev) | |
3117 | { | |
3118 | /* Force disconnect on reboot */ | |
3119 | struct lpc32xx_udc *udc = &controller; | |
3120 | ||
3121 | pullup(udc, 0); | |
3122 | } | |
3123 | ||
3124 | /* | |
3125 | * Callbacks to be overridden by options passed via OF (TODO) | |
3126 | */ | |
3127 | ||
3128 | static void lpc32xx_usbd_conn_chg(int conn) | |
3129 | { | |
3130 | /* Do nothing, it might be nice to enable an LED | |
3131 | * based on conn state being !0 */ | |
3132 | } | |
3133 | ||
3134 | static void lpc32xx_usbd_susp_chg(int susp) | |
3135 | { | |
3136 | /* Device suspend if susp != 0 */ | |
3137 | } | |
3138 | ||
3139 | static void lpc32xx_rmwkup_chg(int remote_wakup_enable) | |
3140 | { | |
3141 | /* Enable or disable USB remote wakeup */ | |
3142 | } | |
3143 | ||
3144 | struct lpc32xx_usbd_cfg lpc32xx_usbddata = { | |
3145 | .vbus_drv_pol = 0, | |
3146 | .conn_chgb = &lpc32xx_usbd_conn_chg, | |
3147 | .susp_chgb = &lpc32xx_usbd_susp_chg, | |
3148 | .rmwk_chgb = &lpc32xx_rmwkup_chg, | |
3149 | }; | |
3150 | ||
3151 | ||
3152 | static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F; | |
3153 | ||
3154 | static int __init lpc32xx_udc_probe(struct platform_device *pdev) | |
3155 | { | |
3156 | struct device *dev = &pdev->dev; | |
3157 | struct lpc32xx_udc *udc = &controller; | |
3158 | int retval, i; | |
3159 | struct resource *res; | |
3160 | dma_addr_t dma_handle; | |
3161 | struct device_node *isp1301_node; | |
3162 | ||
3163 | /* init software state */ | |
3164 | udc->gadget.dev.parent = dev; | |
3165 | udc->pdev = pdev; | |
3166 | udc->dev = &pdev->dev; | |
3167 | udc->enabled = 0; | |
3168 | ||
3169 | if (pdev->dev.of_node) { | |
3170 | isp1301_node = of_parse_phandle(pdev->dev.of_node, | |
3171 | "transceiver", 0); | |
3172 | } else { | |
3173 | isp1301_node = NULL; | |
3174 | } | |
3175 | ||
3176 | udc->isp1301_i2c_client = isp1301_get_client(isp1301_node); | |
3177 | if (!udc->isp1301_i2c_client) | |
3178 | return -EPROBE_DEFER; | |
3179 | ||
3180 | dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n", | |
3181 | udc->isp1301_i2c_client->addr); | |
3182 | ||
3183 | pdev->dev.dma_mask = &lpc32xx_usbd_dmamask; | |
3184 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
3185 | ||
3186 | udc->board = &lpc32xx_usbddata; | |
3187 | ||
3188 | /* | |
3189 | * Resources are mapped as follows: | |
3190 | * IORESOURCE_MEM, base address and size of USB space | |
3191 | * IORESOURCE_IRQ, USB device low priority interrupt number | |
3192 | * IORESOURCE_IRQ, USB device high priority interrupt number | |
3193 | * IORESOURCE_IRQ, USB device interrupt number | |
3194 | * IORESOURCE_IRQ, USB transceiver interrupt number | |
3195 | */ | |
3196 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
3197 | if (!res) | |
3198 | return -ENXIO; | |
3199 | ||
3200 | spin_lock_init(&udc->lock); | |
3201 | ||
3202 | /* Get IRQs */ | |
3203 | for (i = 0; i < 4; i++) { | |
3204 | udc->udp_irq[i] = platform_get_irq(pdev, i); | |
3205 | if (udc->udp_irq[i] < 0) { | |
3206 | dev_err(udc->dev, | |
3207 | "irq resource %d not available!\n", i); | |
3208 | return udc->udp_irq[i]; | |
3209 | } | |
3210 | } | |
3211 | ||
3212 | udc->io_p_start = res->start; | |
3213 | udc->io_p_size = resource_size(res); | |
3214 | if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) { | |
3215 | dev_err(udc->dev, "someone's using UDC memory\n"); | |
3216 | return -EBUSY; | |
3217 | } | |
3218 | ||
3219 | udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size); | |
3220 | if (!udc->udp_baseaddr) { | |
3221 | retval = -ENOMEM; | |
3222 | dev_err(udc->dev, "IO map failure\n"); | |
3223 | goto io_map_fail; | |
3224 | } | |
3225 | ||
3226 | /* Enable AHB slave USB clock, needed for further USB clock control */ | |
3227 | writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL); | |
3228 | ||
3229 | /* Get required clocks */ | |
3230 | udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5"); | |
3231 | if (IS_ERR(udc->usb_pll_clk)) { | |
3232 | dev_err(udc->dev, "failed to acquire USB PLL\n"); | |
3233 | retval = PTR_ERR(udc->usb_pll_clk); | |
3234 | goto pll_get_fail; | |
3235 | } | |
3236 | udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd"); | |
3237 | if (IS_ERR(udc->usb_slv_clk)) { | |
3238 | dev_err(udc->dev, "failed to acquire USB device clock\n"); | |
3239 | retval = PTR_ERR(udc->usb_slv_clk); | |
3240 | goto usb_clk_get_fail; | |
3241 | } | |
3242 | ||
3243 | /* Setup PLL clock to 48MHz */ | |
3244 | retval = clk_enable(udc->usb_pll_clk); | |
3245 | if (retval < 0) { | |
3246 | dev_err(udc->dev, "failed to start USB PLL\n"); | |
3247 | goto pll_enable_fail; | |
3248 | } | |
3249 | ||
3250 | retval = clk_set_rate(udc->usb_pll_clk, 48000); | |
3251 | if (retval < 0) { | |
3252 | dev_err(udc->dev, "failed to set USB clock rate\n"); | |
3253 | goto pll_set_fail; | |
3254 | } | |
3255 | ||
3256 | writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL); | |
3257 | ||
3258 | /* Enable USB device clock */ | |
3259 | retval = clk_enable(udc->usb_slv_clk); | |
3260 | if (retval < 0) { | |
3261 | dev_err(udc->dev, "failed to start USB device clock\n"); | |
3262 | goto usb_clk_enable_fail; | |
3263 | } | |
3264 | ||
3265 | /* Set to enable all needed USB OTG clocks */ | |
3266 | writel(USB_CLOCK_MASK, USB_OTG_CLK_CTRL(udc)); | |
3267 | ||
3268 | i = 1000; | |
3269 | while (((readl(USB_OTG_CLK_STAT(udc)) & USB_CLOCK_MASK) != | |
3270 | USB_CLOCK_MASK) && (i > 0)) | |
3271 | i--; | |
3272 | if (!i) | |
3273 | dev_dbg(udc->dev, "USB OTG clocks not correctly enabled\n"); | |
3274 | ||
3275 | /* Setup deferred workqueue data */ | |
3276 | udc->poweron = udc->pullup = 0; | |
3277 | INIT_WORK(&udc->pullup_job, pullup_work); | |
3278 | INIT_WORK(&udc->vbus_job, vbus_work); | |
3279 | #ifdef CONFIG_PM | |
3280 | INIT_WORK(&udc->power_job, power_work); | |
3281 | #endif | |
3282 | ||
3283 | /* All clocks are now on */ | |
3284 | udc->clocked = 1; | |
3285 | ||
3286 | isp1301_udc_configure(udc); | |
3287 | /* Allocate memory for the UDCA */ | |
3288 | udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE, | |
3289 | &dma_handle, | |
3290 | (GFP_KERNEL | GFP_DMA)); | |
3291 | if (!udc->udca_v_base) { | |
3292 | dev_err(udc->dev, "error getting UDCA region\n"); | |
3293 | retval = -ENOMEM; | |
3294 | goto i2c_fail; | |
3295 | } | |
3296 | udc->udca_p_base = dma_handle; | |
3297 | dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n", | |
3298 | UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base); | |
3299 | ||
3300 | /* Setup the DD DMA memory pool */ | |
3301 | udc->dd_cache = dma_pool_create("udc_dd", udc->dev, | |
3302 | sizeof(struct lpc32xx_usbd_dd_gad), | |
3303 | sizeof(u32), 0); | |
3304 | if (!udc->dd_cache) { | |
3305 | dev_err(udc->dev, "error getting DD DMA region\n"); | |
3306 | retval = -ENOMEM; | |
3307 | goto dma_alloc_fail; | |
3308 | } | |
3309 | ||
3310 | /* Clear USB peripheral and initialize gadget endpoints */ | |
3311 | udc_disable(udc); | |
3312 | udc_reinit(udc); | |
3313 | ||
3314 | retval = device_register(&udc->gadget.dev); | |
3315 | if (retval < 0) { | |
3316 | dev_err(udc->dev, "Device registration failure\n"); | |
3317 | goto dev_register_fail; | |
3318 | } | |
3319 | ||
3320 | /* Request IRQs - low and high priority USB device IRQs are routed to | |
3321 | * the same handler, while the DMA interrupt is routed elsewhere */ | |
3322 | retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq, | |
3323 | 0, "udc_lp", udc); | |
3324 | if (retval < 0) { | |
3325 | dev_err(udc->dev, "LP request irq %d failed\n", | |
3326 | udc->udp_irq[IRQ_USB_LP]); | |
3327 | goto irq_lp_fail; | |
3328 | } | |
3329 | retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq, | |
3330 | 0, "udc_hp", udc); | |
3331 | if (retval < 0) { | |
3332 | dev_err(udc->dev, "HP request irq %d failed\n", | |
3333 | udc->udp_irq[IRQ_USB_HP]); | |
3334 | goto irq_hp_fail; | |
3335 | } | |
3336 | ||
3337 | retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA], | |
3338 | lpc32xx_usb_devdma_irq, 0, "udc_dma", udc); | |
3339 | if (retval < 0) { | |
3340 | dev_err(udc->dev, "DEV request irq %d failed\n", | |
3341 | udc->udp_irq[IRQ_USB_DEVDMA]); | |
3342 | goto irq_dev_fail; | |
3343 | } | |
3344 | ||
3345 | /* The transceiver interrupt is used for VBUS detection and will | |
3346 | kick off the VBUS handler function */ | |
3347 | retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq, | |
3348 | 0, "udc_otg", udc); | |
3349 | if (retval < 0) { | |
3350 | dev_err(udc->dev, "VBUS request irq %d failed\n", | |
3351 | udc->udp_irq[IRQ_USB_ATX]); | |
3352 | goto irq_xcvr_fail; | |
3353 | } | |
3354 | ||
3355 | /* Initialize wait queue */ | |
3356 | init_waitqueue_head(&udc->ep_disable_wait_queue); | |
3357 | atomic_set(&udc->enabled_ep_cnt, 0); | |
3358 | ||
3359 | /* Keep all IRQs disabled until GadgetFS starts up */ | |
3360 | for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++) | |
3361 | disable_irq(udc->udp_irq[i]); | |
3362 | ||
3363 | retval = usb_add_gadget_udc(dev, &udc->gadget); | |
3364 | if (retval < 0) | |
3365 | goto add_gadget_fail; | |
3366 | ||
3367 | dev_set_drvdata(dev, udc); | |
3368 | device_init_wakeup(dev, 1); | |
3369 | create_debug_file(udc); | |
3370 | ||
3371 | /* Disable clocks for now */ | |
3372 | udc_clk_set(udc, 0); | |
3373 | ||
3374 | dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION); | |
3375 | return 0; | |
3376 | ||
3377 | add_gadget_fail: | |
3378 | free_irq(udc->udp_irq[IRQ_USB_ATX], udc); | |
3379 | irq_xcvr_fail: | |
3380 | free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc); | |
3381 | irq_dev_fail: | |
3382 | free_irq(udc->udp_irq[IRQ_USB_HP], udc); | |
3383 | irq_hp_fail: | |
3384 | free_irq(udc->udp_irq[IRQ_USB_LP], udc); | |
3385 | irq_lp_fail: | |
3386 | device_unregister(&udc->gadget.dev); | |
3387 | dev_register_fail: | |
3388 | dma_pool_destroy(udc->dd_cache); | |
3389 | dma_alloc_fail: | |
3390 | dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, | |
3391 | udc->udca_v_base, udc->udca_p_base); | |
3392 | i2c_fail: | |
3393 | clk_disable(udc->usb_slv_clk); | |
3394 | usb_clk_enable_fail: | |
3395 | pll_set_fail: | |
3396 | clk_disable(udc->usb_pll_clk); | |
3397 | pll_enable_fail: | |
3398 | clk_put(udc->usb_slv_clk); | |
3399 | usb_clk_get_fail: | |
3400 | clk_put(udc->usb_pll_clk); | |
3401 | pll_get_fail: | |
3402 | iounmap(udc->udp_baseaddr); | |
3403 | io_map_fail: | |
3404 | release_mem_region(udc->io_p_start, udc->io_p_size); | |
3405 | dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval); | |
3406 | ||
3407 | return retval; | |
3408 | } | |
3409 | ||
3410 | static int __devexit lpc32xx_udc_remove(struct platform_device *pdev) | |
3411 | { | |
3412 | struct lpc32xx_udc *udc = platform_get_drvdata(pdev); | |
3413 | ||
3414 | usb_del_gadget_udc(&udc->gadget); | |
3415 | if (udc->driver) | |
3416 | return -EBUSY; | |
3417 | ||
3418 | udc_clk_set(udc, 1); | |
3419 | udc_disable(udc); | |
3420 | pullup(udc, 0); | |
3421 | ||
3422 | free_irq(udc->udp_irq[IRQ_USB_ATX], udc); | |
3423 | ||
3424 | device_init_wakeup(&pdev->dev, 0); | |
3425 | remove_debug_file(udc); | |
3426 | ||
3427 | dma_pool_destroy(udc->dd_cache); | |
3428 | dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, | |
3429 | udc->udca_v_base, udc->udca_p_base); | |
3430 | free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc); | |
3431 | free_irq(udc->udp_irq[IRQ_USB_HP], udc); | |
3432 | free_irq(udc->udp_irq[IRQ_USB_LP], udc); | |
3433 | ||
3434 | device_unregister(&udc->gadget.dev); | |
3435 | ||
3436 | clk_disable(udc->usb_slv_clk); | |
3437 | clk_put(udc->usb_slv_clk); | |
3438 | clk_disable(udc->usb_pll_clk); | |
3439 | clk_put(udc->usb_pll_clk); | |
3440 | iounmap(udc->udp_baseaddr); | |
3441 | release_mem_region(udc->io_p_start, udc->io_p_size); | |
3442 | ||
3443 | return 0; | |
3444 | } | |
3445 | ||
3446 | #ifdef CONFIG_PM | |
3447 | static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg) | |
3448 | { | |
3449 | int to = 1000; | |
3450 | struct lpc32xx_udc *udc = platform_get_drvdata(pdev); | |
3451 | ||
3452 | if (udc->clocked) { | |
3453 | /* Power down ISP */ | |
3454 | udc->poweron = 0; | |
3455 | isp1301_set_powerstate(udc, 0); | |
3456 | ||
3457 | /* Disable clocking */ | |
3458 | udc_clk_set(udc, 0); | |
3459 | ||
3460 | /* Keep clock flag on, so we know to re-enable clocks | |
3461 | on resume */ | |
3462 | udc->clocked = 1; | |
3463 | ||
3464 | /* Kill OTG and I2C clocks */ | |
3465 | writel(0, USB_OTG_CLK_CTRL(udc)); | |
3466 | while (((readl(USB_OTG_CLK_STAT(udc)) & OTGOFF_CLK_MASK) != | |
3467 | OTGOFF_CLK_MASK) && (to > 0)) | |
3468 | to--; | |
3469 | if (!to) | |
3470 | dev_dbg(udc->dev, | |
3471 | "USB OTG clocks not correctly enabled\n"); | |
3472 | ||
3473 | /* Kill global USB clock */ | |
3474 | clk_disable(udc->usb_slv_clk); | |
3475 | } | |
3476 | ||
3477 | return 0; | |
3478 | } | |
3479 | ||
3480 | static int lpc32xx_udc_resume(struct platform_device *pdev) | |
3481 | { | |
3482 | struct lpc32xx_udc *udc = platform_get_drvdata(pdev); | |
3483 | ||
3484 | if (udc->clocked) { | |
3485 | /* Enable global USB clock */ | |
3486 | clk_enable(udc->usb_slv_clk); | |
3487 | ||
3488 | /* Enable clocking */ | |
3489 | udc_clk_set(udc, 1); | |
3490 | ||
3491 | /* ISP back to normal power mode */ | |
3492 | udc->poweron = 1; | |
3493 | isp1301_set_powerstate(udc, 1); | |
3494 | } | |
3495 | ||
3496 | return 0; | |
3497 | } | |
3498 | #else | |
3499 | #define lpc32xx_udc_suspend NULL | |
3500 | #define lpc32xx_udc_resume NULL | |
3501 | #endif | |
3502 | ||
3503 | #ifdef CONFIG_OF | |
3504 | static struct of_device_id lpc32xx_udc_of_match[] = { | |
3505 | { .compatible = "nxp,lpc3220-udc", }, | |
3506 | { }, | |
3507 | }; | |
3508 | MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match); | |
3509 | #endif | |
3510 | ||
3511 | static struct platform_driver lpc32xx_udc_driver = { | |
3512 | .remove = __devexit_p(lpc32xx_udc_remove), | |
3513 | .shutdown = lpc32xx_udc_shutdown, | |
3514 | .suspend = lpc32xx_udc_suspend, | |
3515 | .resume = lpc32xx_udc_resume, | |
3516 | .driver = { | |
3517 | .name = (char *) driver_name, | |
3518 | .owner = THIS_MODULE, | |
3519 | .of_match_table = of_match_ptr(lpc32xx_udc_of_match), | |
3520 | }, | |
3521 | }; | |
3522 | ||
3523 | static int __init udc_init_module(void) | |
3524 | { | |
3525 | return platform_driver_probe(&lpc32xx_udc_driver, lpc32xx_udc_probe); | |
3526 | } | |
3527 | module_init(udc_init_module); | |
3528 | ||
3529 | static void __exit udc_exit_module(void) | |
3530 | { | |
3531 | platform_driver_unregister(&lpc32xx_udc_driver); | |
3532 | } | |
3533 | module_exit(udc_exit_module); | |
3534 | ||
3535 | MODULE_DESCRIPTION("LPC32XX udc driver"); | |
3536 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); | |
3537 | MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); | |
3538 | MODULE_LICENSE("GPL"); | |
3539 | MODULE_ALIAS("platform:lpc32xx_udc"); |