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usb: gadget: lpc32xx_udc: Propagate devicetree to gadget drivers
[deliverable/linux.git] / drivers / usb / gadget / lpc32xx_udc.c
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24a28e42
RS		 1/*
2 * USB Gadget driver for LPC32xx
3 *
4 * Authors:
5 * Kevin Wells <kevin.wells@nxp.com>
6 * Mike James
7 * Roland Stigge <stigge@antcom.de>
8 *
9 * Copyright (C) 2006 Philips Semiconductors
10 * Copyright (C) 2009 NXP Semiconductors
11 * Copyright (C) 2012 Roland Stigge
12 *
13 * Note: This driver is based on original work done by Mike James for
14 * the LPC3180.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/delay.h>
35#include <linux/ioport.h>
36#include <linux/slab.h>
37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/list.h>
40#include <linux/interrupt.h>
41#include <linux/proc_fs.h>
42#include <linux/clk.h>
43#include <linux/usb/ch9.h>
44#include <linux/usb/gadget.h>
45#include <linux/i2c.h>
46#include <linux/kthread.h>
47#include <linux/freezer.h>
48#include <linux/dma-mapping.h>
49#include <linux/dmapool.h>
50#include <linux/workqueue.h>
51#include <linux/of.h>
52#include <linux/usb/isp1301.h>
53
54#include <asm/byteorder.h>
55#include <mach/hardware.h>
56#include <linux/io.h>
57#include <asm/irq.h>
58#include <asm/system.h>
59
60#include <mach/platform.h>
61#include <mach/irqs.h>
62#include <mach/board.h>
63#ifdef CONFIG_USB_GADGET_DEBUG_FILES
64#include <linux/seq_file.h>
65#endif
66
67/*
68 * USB device configuration structure
69 */
70typedef void (*usc_chg_event)(int);
71struct lpc32xx_usbd_cfg {
72 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
73 usc_chg_event conn_chgb; /* Connection change event (optional) */
74 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
75 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
76};
77
78/*
79 * controller driver data structures
80 */
81
82/* 16 endpoints (not to be confused with 32 hardware endpoints) */
83#define NUM_ENDPOINTS 16
84
85/*
86 * IRQ indices make reading the code a little easier
87 */
88#define IRQ_USB_LP 0
89#define IRQ_USB_HP 1
90#define IRQ_USB_DEVDMA 2
91#define IRQ_USB_ATX 3
92
93#define EP_OUT 0 /* RX (from host) */
94#define EP_IN 1 /* TX (to host) */
95
96/* Returns the interrupt mask for the selected hardware endpoint */
97#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
98
99#define EP_INT_TYPE 0
100#define EP_ISO_TYPE 1
101#define EP_BLK_TYPE 2
102#define EP_CTL_TYPE 3
103
104/* EP0 states */
105#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
106#define DATA_IN 1 /* Expect dev->host transfer */
107#define DATA_OUT 2 /* Expect host->dev transfer */
108
109/* DD (DMA Descriptor) structure, requires word alignment, this is already
110 * defined in the LPC32XX USB device header file, but this version is slightly
111 * modified to tag some work data with each DMA descriptor. */
112struct lpc32xx_usbd_dd_gad {
113 u32 dd_next_phy;
114 u32 dd_setup;
115 u32 dd_buffer_addr;
116 u32 dd_status;
117 u32 dd_iso_ps_mem_addr;
118 u32 this_dma;
119 u32 iso_status[6]; /* 5 spare */
120 u32 dd_next_v;
121};
122
123/*
124 * Logical endpoint structure
125 */
126struct lpc32xx_ep {
127 struct usb_ep ep;
128 struct list_head queue;
129 struct lpc32xx_udc *udc;
130
131 u32 hwep_num_base; /* Physical hardware EP */
132 u32 hwep_num; /* Maps to hardware endpoint */
133 u32 maxpacket;
134 u32 lep;
135
136 bool is_in;
137 bool req_pending;
138 u32 eptype;
139
140 u32 totalints;
141
142 bool wedge;
143
144 const struct usb_endpoint_descriptor *desc;
145};
146
147/*
148 * Common UDC structure
149 */
150struct lpc32xx_udc {
151 struct usb_gadget gadget;
152 struct usb_gadget_driver *driver;
153 struct platform_device *pdev;
154 struct device *dev;
155 struct dentry *pde;
156 spinlock_t lock;
157 struct i2c_client *isp1301_i2c_client;
158
159 /* Board and device specific */
160 struct lpc32xx_usbd_cfg *board;
161 u32 io_p_start;
162 u32 io_p_size;
163 void __iomem *udp_baseaddr;
164 int udp_irq[4];
165 struct clk *usb_pll_clk;
166 struct clk *usb_slv_clk;
50856699 167 struct clk *usb_otg_clk;
24a28e42
RS		 168
169 /* DMA support */
170 u32 *udca_v_base;
171 u32 udca_p_base;
172 struct dma_pool *dd_cache;
173
174 /* Common EP and control data */
175 u32 enabled_devints;
176 u32 enabled_hwepints;
177 u32 dev_status;
178 u32 realized_eps;
179
180 /* VBUS detection, pullup, and power flags */
181 u8 vbus;
182 u8 last_vbus;
183 int pullup;
184 int poweron;
185
186 /* Work queues related to I2C support */
187 struct work_struct pullup_job;
188 struct work_struct vbus_job;
189 struct work_struct power_job;
190
191 /* USB device peripheral - various */
192 struct lpc32xx_ep ep[NUM_ENDPOINTS];
193 bool enabled;
194 bool clocked;
195 bool suspended;
196 bool selfpowered;
197 int ep0state;
198 atomic_t enabled_ep_cnt;
199 wait_queue_head_t ep_disable_wait_queue;
200};
201
202/*
203 * Endpoint request
204 */
205struct lpc32xx_request {
206 struct usb_request req;
207 struct list_head queue;
208 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
209 bool mapped;
210 bool send_zlp;
211};
212
213static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
214{
215 return container_of(g, struct lpc32xx_udc, gadget);
216}
217
218#define ep_dbg(epp, fmt, arg...) \
219 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
220#define ep_err(epp, fmt, arg...) \
221 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
222#define ep_info(epp, fmt, arg...) \
223 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
224#define ep_warn(epp, fmt, arg...) \
225 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
226
227#define UDCA_BUFF_SIZE (128)
228
229/* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
50856699 230 * be replaced with an inremap()ed pointer
24a28e42
RS		 231 * */
232#define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
24a28e42
RS		 233
234/* USB_CTRL bit defines */
235#define USB_SLAVE_HCLK_EN (1 << 24)
236#define USB_HOST_NEED_CLK_EN (1 << 21)
237#define USB_DEV_NEED_CLK_EN (1 << 22)
238
24a28e42
RS		 239/**********************************************************************
240 * USB device controller register offsets
241 **********************************************************************/
242
243#define USBD_DEVINTST(x) ((x) + 0x200)
244#define USBD_DEVINTEN(x) ((x) + 0x204)
245#define USBD_DEVINTCLR(x) ((x) + 0x208)
246#define USBD_DEVINTSET(x) ((x) + 0x20C)
247#define USBD_CMDCODE(x) ((x) + 0x210)
248#define USBD_CMDDATA(x) ((x) + 0x214)
249#define USBD_RXDATA(x) ((x) + 0x218)
250#define USBD_TXDATA(x) ((x) + 0x21C)
251#define USBD_RXPLEN(x) ((x) + 0x220)
252#define USBD_TXPLEN(x) ((x) + 0x224)
253#define USBD_CTRL(x) ((x) + 0x228)
254#define USBD_DEVINTPRI(x) ((x) + 0x22C)
255#define USBD_EPINTST(x) ((x) + 0x230)
256#define USBD_EPINTEN(x) ((x) + 0x234)
257#define USBD_EPINTCLR(x) ((x) + 0x238)
258#define USBD_EPINTSET(x) ((x) + 0x23C)
259#define USBD_EPINTPRI(x) ((x) + 0x240)
260#define USBD_REEP(x) ((x) + 0x244)
261#define USBD_EPIND(x) ((x) + 0x248)
262#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
263/* DMA support registers only below */
264/* Set, clear, or get enabled state of the DMA request status. If
265 * enabled, an IN or OUT token will start a DMA transfer for the EP */
266#define USBD_DMARST(x) ((x) + 0x250)
267#define USBD_DMARCLR(x) ((x) + 0x254)
268#define USBD_DMARSET(x) ((x) + 0x258)
269/* DMA UDCA head pointer */
270#define USBD_UDCAH(x) ((x) + 0x280)
271/* EP DMA status, enable, and disable. This is used to specifically
272 * enabled or disable DMA for a specific EP */
273#define USBD_EPDMAST(x) ((x) + 0x284)
274#define USBD_EPDMAEN(x) ((x) + 0x288)
275#define USBD_EPDMADIS(x) ((x) + 0x28C)
276/* DMA master interrupts enable and pending interrupts */
277#define USBD_DMAINTST(x) ((x) + 0x290)
278#define USBD_DMAINTEN(x) ((x) + 0x294)
279/* DMA end of transfer interrupt enable, disable, status */
280#define USBD_EOTINTST(x) ((x) + 0x2A0)
281#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
282#define USBD_EOTINTSET(x) ((x) + 0x2A8)
283/* New DD request interrupt enable, disable, status */
284#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
285#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
286#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
287/* DMA error interrupt enable, disable, status */
288#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
289#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
290#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
291
292/**********************************************************************
293 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
294 * USBD_DEVINTPRI register definitions
295 **********************************************************************/
296#define USBD_ERR_INT (1 << 9)
297#define USBD_EP_RLZED (1 << 8)
298#define USBD_TXENDPKT (1 << 7)
299#define USBD_RXENDPKT (1 << 6)
300#define USBD_CDFULL (1 << 5)
301#define USBD_CCEMPTY (1 << 4)
302#define USBD_DEV_STAT (1 << 3)
303#define USBD_EP_SLOW (1 << 2)
304#define USBD_EP_FAST (1 << 1)
305#define USBD_FRAME (1 << 0)
306
307/**********************************************************************
308 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
309 * USBD_EPINTPRI register definitions
310 **********************************************************************/
311/* End point selection macro (RX) */
312#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
313
314/* End point selection macro (TX) */
315#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
316
317/**********************************************************************
318 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
319 * USBD_EPDMAEN/USBD_EPDMADIS/
320 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
321 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
322 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
323 * register definitions
324 **********************************************************************/
325/* Endpoint selection macro */
326#define USBD_EP_SEL(e) (1 << (e))
327
328/**********************************************************************
329 * SBD_DMAINTST/USBD_DMAINTEN
330 **********************************************************************/
331#define USBD_SYS_ERR_INT (1 << 2)
332#define USBD_NEW_DD_INT (1 << 1)
333#define USBD_EOT_INT (1 << 0)
334
335/**********************************************************************
336 * USBD_RXPLEN register definitions
337 **********************************************************************/
338#define USBD_PKT_RDY (1 << 11)
339#define USBD_DV (1 << 10)
340#define USBD_PK_LEN_MASK 0x3FF
341
342/**********************************************************************
343 * USBD_CTRL register definitions
344 **********************************************************************/
345#define USBD_LOG_ENDPOINT(e) ((e) << 2)
346#define USBD_WR_EN (1 << 1)
347#define USBD_RD_EN (1 << 0)
348
349/**********************************************************************
350 * USBD_CMDCODE register definitions
351 **********************************************************************/
352#define USBD_CMD_CODE(c) ((c) << 16)
353#define USBD_CMD_PHASE(p) ((p) << 8)
354
355/**********************************************************************
356 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
357 **********************************************************************/
358#define USBD_DMAEP(e) (1 << (e))
359
360/* DD (DMA Descriptor) structure, requires word alignment */
361struct lpc32xx_usbd_dd {
362 u32 *dd_next;
363 u32 dd_setup;
364 u32 dd_buffer_addr;
365 u32 dd_status;
366 u32 dd_iso_ps_mem_addr;
367};
368
369/* dd_setup bit defines */
370#define DD_SETUP_ATLE_DMA_MODE 0x01
371#define DD_SETUP_NEXT_DD_VALID 0x04
372#define DD_SETUP_ISO_EP 0x10
373#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
374#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
375
376/* dd_status bit defines */
377#define DD_STATUS_DD_RETIRED 0x01
378#define DD_STATUS_STS_MASK 0x1E
379#define DD_STATUS_STS_NS 0x00 /* Not serviced */
380#define DD_STATUS_STS_BS 0x02 /* Being serviced */
381#define DD_STATUS_STS_NC 0x04 /* Normal completion */
382#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
383#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
384#define DD_STATUS_STS_SE 0x12 /* System error */
385#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
386#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
387#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
388#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
389#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
390
391/*
392 *
393 * Protocol engine bits below
394 *
395 */
396/* Device Interrupt Bit Definitions */
397#define FRAME_INT 0x00000001
398#define EP_FAST_INT 0x00000002
399#define EP_SLOW_INT 0x00000004
400#define DEV_STAT_INT 0x00000008
401#define CCEMTY_INT 0x00000010
402#define CDFULL_INT 0x00000020
403#define RxENDPKT_INT 0x00000040
404#define TxENDPKT_INT 0x00000080
405#define EP_RLZED_INT 0x00000100
406#define ERR_INT 0x00000200
407
408/* Rx & Tx Packet Length Definitions */
409#define PKT_LNGTH_MASK 0x000003FF
410#define PKT_DV 0x00000400
411#define PKT_RDY 0x00000800
412
413/* USB Control Definitions */
414#define CTRL_RD_EN 0x00000001
415#define CTRL_WR_EN 0x00000002
416
417/* Command Codes */
418#define CMD_SET_ADDR 0x00D00500
419#define CMD_CFG_DEV 0x00D80500
420#define CMD_SET_MODE 0x00F30500
421#define CMD_RD_FRAME 0x00F50500
422#define DAT_RD_FRAME 0x00F50200
423#define CMD_RD_TEST 0x00FD0500
424#define DAT_RD_TEST 0x00FD0200
425#define CMD_SET_DEV_STAT 0x00FE0500
426#define CMD_GET_DEV_STAT 0x00FE0500
427#define DAT_GET_DEV_STAT 0x00FE0200
428#define CMD_GET_ERR_CODE 0x00FF0500
429#define DAT_GET_ERR_CODE 0x00FF0200
430#define CMD_RD_ERR_STAT 0x00FB0500
431#define DAT_RD_ERR_STAT 0x00FB0200
432#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
433#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
434#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
435#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
436#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
437#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
438#define CMD_CLR_BUF 0x00F20500
439#define DAT_CLR_BUF 0x00F20200
440#define CMD_VALID_BUF 0x00FA0500
441
442/* Device Address Register Definitions */
443#define DEV_ADDR_MASK 0x7F
444#define DEV_EN 0x80
445
446/* Device Configure Register Definitions */
447#define CONF_DVICE 0x01
448
449/* Device Mode Register Definitions */
450#define AP_CLK 0x01
451#define INAK_CI 0x02
452#define INAK_CO 0x04
453#define INAK_II 0x08
454#define INAK_IO 0x10
455#define INAK_BI 0x20
456#define INAK_BO 0x40
457
458/* Device Status Register Definitions */
459#define DEV_CON 0x01
460#define DEV_CON_CH 0x02
461#define DEV_SUS 0x04
462#define DEV_SUS_CH 0x08
463#define DEV_RST 0x10
464
465/* Error Code Register Definitions */
466#define ERR_EC_MASK 0x0F
467#define ERR_EA 0x10
468
469/* Error Status Register Definitions */
470#define ERR_PID 0x01
471#define ERR_UEPKT 0x02
472#define ERR_DCRC 0x04
473#define ERR_TIMOUT 0x08
474#define ERR_EOP 0x10
475#define ERR_B_OVRN 0x20
476#define ERR_BTSTF 0x40
477#define ERR_TGL 0x80
478
479/* Endpoint Select Register Definitions */
480#define EP_SEL_F 0x01
481#define EP_SEL_ST 0x02
482#define EP_SEL_STP 0x04
483#define EP_SEL_PO 0x08
484#define EP_SEL_EPN 0x10
485#define EP_SEL_B_1_FULL 0x20
486#define EP_SEL_B_2_FULL 0x40
487
488/* Endpoint Status Register Definitions */
489#define EP_STAT_ST 0x01
490#define EP_STAT_DA 0x20
491#define EP_STAT_RF_MO 0x40
492#define EP_STAT_CND_ST 0x80
493
494/* Clear Buffer Register Definitions */
495#define CLR_BUF_PO 0x01
496
497/* DMA Interrupt Bit Definitions */
498#define EOT_INT 0x01
499#define NDD_REQ_INT 0x02
500#define SYS_ERR_INT 0x04
501
502#define DRIVER_VERSION "1.03"
503static const char driver_name[] = "lpc32xx_udc";
504
505/*
506 *
507 * proc interface support
508 *
509 */
510#ifdef CONFIG_USB_GADGET_DEBUG_FILES
511static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
512static const char debug_filename[] = "driver/udc";
513
514static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
515{
516 struct lpc32xx_request *req;
517
518 seq_printf(s, "\n");
519 seq_printf(s, "%12s, maxpacket %4d %3s",
520 ep->ep.name, ep->ep.maxpacket,
521 ep->is_in ? "in" : "out");
522 seq_printf(s, " type %4s", epnames[ep->eptype]);
523 seq_printf(s, " ints: %12d", ep->totalints);
524
525 if (list_empty(&ep->queue))
526 seq_printf(s, "\t(queue empty)\n");
527 else {
528 list_for_each_entry(req, &ep->queue, queue) {
529 u32 length = req->req.actual;
530
531 seq_printf(s, "\treq %p len %d/%d buf %p\n",
532 &req->req, length,
533 req->req.length, req->req.buf);
534 }
535 }
536}
537
538static int proc_udc_show(struct seq_file *s, void *unused)
539{
540 struct lpc32xx_udc *udc = s->private;
541 struct lpc32xx_ep *ep;
542 unsigned long flags;
543
544 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
545
546 spin_lock_irqsave(&udc->lock, flags);
547
548 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
549 udc->vbus ? "present" : "off",
550 udc->enabled ? (udc->vbus ? "active" : "enabled") :
551 "disabled",
552 udc->selfpowered ? "self" : "VBUS",
553 udc->suspended ? ", suspended" : "",
554 udc->driver ? udc->driver->driver.name : "(none)");
555
556 if (udc->enabled && udc->vbus) {
557 proc_ep_show(s, &udc->ep[0]);
558 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
559 if (ep->desc)
560 proc_ep_show(s, ep);
561 }
562 }
563
564 spin_unlock_irqrestore(&udc->lock, flags);
565
566 return 0;
567}
568
569static int proc_udc_open(struct inode *inode, struct file *file)
570{
571 return single_open(file, proc_udc_show, PDE(inode)->data);
572}
573
574static const struct file_operations proc_ops = {
575 .owner = THIS_MODULE,
576 .open = proc_udc_open,
577 .read = seq_read,
578 .llseek = seq_lseek,
579 .release = single_release,
580};
581
582static void create_debug_file(struct lpc32xx_udc *udc)
583{
584 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
585}
586
587static void remove_debug_file(struct lpc32xx_udc *udc)
588{
589 if (udc->pde)
590 debugfs_remove(udc->pde);
591}
592
593#else
594static inline void create_debug_file(struct lpc32xx_udc *udc) {}
595static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
596#endif
597
598/* Primary initialization sequence for the ISP1301 transceiver */
599static void isp1301_udc_configure(struct lpc32xx_udc *udc)
600{
601 /* LPC32XX only supports DAT_SE0 USB mode */
602 /* This sequence is important */
603
604 /* Disable transparent UART mode first */
605 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
606 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
607 MC1_UART_EN);
608
609 /* Set full speed and SE0 mode */
610 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
611 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
612 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
613 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
614
615 /*
616 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
617 */
618 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
619 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
620 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
621 ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
622
623 /* Driver VBUS_DRV high or low depending on board setup */
624 if (udc->board->vbus_drv_pol != 0)
625 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
626 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
627 else
628 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
629 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
630 OTG1_VBUS_DRV);
631
632 /* Bi-directional mode with suspend control
633 * Enable both pulldowns for now - the pullup will be enable when VBUS
634 * is detected */
635 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
636 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
637 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
638 ISP1301_I2C_OTG_CONTROL_1,
639 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
640
641 /* Discharge VBUS (just in case) */
642 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
643 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
644 msleep(1);
645 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
646 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
647 OTG1_VBUS_DISCHRG);
648
649 /* Clear and enable VBUS high edge interrupt */
650 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
651 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
652 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
653 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
654 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
655 ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
656 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
657 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
658 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
659 ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
660
661 /* Enable usb_need_clk clock after transceiver is initialized */
50856699 662 writel((readl(USB_CTRL) | USB_DEV_NEED_CLK_EN), USB_CTRL);
24a28e42
RS		 663
664 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
665 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
666 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
667 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
668 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
669 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
670}
671
672/* Enables or disables the USB device pullup via the ISP1301 transceiver */
673static void isp1301_pullup_set(struct lpc32xx_udc *udc)
674{
675 if (udc->pullup)
676 /* Enable pullup for bus signalling */
677 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
678 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
679 else
680 /* Enable pullup for bus signalling */
681 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
682 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
683 OTG1_DP_PULLUP);
684}
685
686static void pullup_work(struct work_struct *work)
687{
688 struct lpc32xx_udc *udc =
689 container_of(work, struct lpc32xx_udc, pullup_job);
690
691 isp1301_pullup_set(udc);
692}
693
694static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
695 int block)
696{
697 if (en_pullup == udc->pullup)
698 return;
699
700 udc->pullup = en_pullup;
701 if (block)
702 isp1301_pullup_set(udc);
703 else
704 /* defer slow i2c pull up setting */
705 schedule_work(&udc->pullup_job);
706}
707
708#ifdef CONFIG_PM
709/* Powers up or down the ISP1301 transceiver */
710static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
711{
712 if (enable != 0)
713 /* Power up ISP1301 - this ISP1301 will automatically wakeup
714 when VBUS is detected */
715 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
716 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
717 MC2_GLOBAL_PWR_DN);
718 else
719 /* Power down ISP1301 */
720 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
721 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
722}
723
724static void power_work(struct work_struct *work)
725{
726 struct lpc32xx_udc *udc =
727 container_of(work, struct lpc32xx_udc, power_job);
728
729 isp1301_set_powerstate(udc, udc->poweron);
730}
731#endif
732
733/*
734 *
735 * USB protocol engine command/data read/write helper functions
736 *
737 */
738/* Issues a single command to the USB device state machine */
739static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
740{
741 u32 pass = 0;
742 int to;
743
744 /* EP may lock on CLRI if this read isn't done */
745 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
746 (void) tmp;
747
748 while (pass == 0) {
749 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
750
751 /* Write command code */
752 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
753 to = 10000;
754 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
755 USBD_CCEMPTY) == 0) && (to > 0)) {
756 to--;
757 }
758
759 if (to > 0)
760 pass = 1;
761
762 cpu_relax();
763 }
764}
765
766/* Issues 2 commands (or command and data) to the USB device state machine */
767static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
768 u32 data)
769{
770 udc_protocol_cmd_w(udc, cmd);
771 udc_protocol_cmd_w(udc, data);
772}
773
774/* Issues a single command to the USB device state machine and reads
775 * response data */
776static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
777{
778 u32 tmp;
779 int to = 1000;
780
781 /* Write a command and read data from the protocol engine */
782 writel((USBD_CDFULL | USBD_CCEMPTY),
783 USBD_DEVINTCLR(udc->udp_baseaddr));
784
785 /* Write command code */
786 udc_protocol_cmd_w(udc, cmd);
787
788 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
789 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
790 && (to > 0))
791 to--;
792 if (!to)
793 dev_dbg(udc->dev,
794 "Protocol engine didn't receive response (CDFULL)\n");
795
796 return readl(USBD_CMDDATA(udc->udp_baseaddr));
797}
798
799/*
800 *
801 * USB device interrupt mask support functions
802 *
803 */
804/* Enable one or more USB device interrupts */
805static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
806{
807 udc->enabled_devints |= devmask;
808 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
809}
810
811/* Disable one or more USB device interrupts */
812static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
813{
814 udc->enabled_devints &= ~mask;
815 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
816}
817
818/* Clear one or more USB device interrupts */
819static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
820{
821 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
822}
823
824/*
825 *
826 * Endpoint interrupt disable/enable functions
827 *
828 */
829/* Enable one or more USB endpoint interrupts */
830static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
831{
832 udc->enabled_hwepints |= (1 << hwep);
833 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
834}
835
836/* Disable one or more USB endpoint interrupts */
837static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
838{
839 udc->enabled_hwepints &= ~(1 << hwep);
840 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
841}
842
843/* Clear one or more USB endpoint interrupts */
844static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
845{
846 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
847}
848
849/* Enable DMA for the HW channel */
850static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
851{
852 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
853}
854
855/* Disable DMA for the HW channel */
856static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
857{
858 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
859}
860
861/*
862 *
863 * Endpoint realize/unrealize functions
864 *
865 */
866/* Before an endpoint can be used, it needs to be realized
867 * in the USB protocol engine - this realizes the endpoint.
868 * The interrupt (FIFO or DMA) is not enabled with this function */
869static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
870 u32 maxpacket)
871{
872 int to = 1000;
873
874 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
875 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
876 udc->realized_eps |= (1 << hwep);
877 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
878 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
879
880 /* Wait until endpoint is realized in hardware */
881 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
882 USBD_EP_RLZED)) && (to > 0))
883 to--;
884 if (!to)
885 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
886
887 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
888}
889
890/* Unrealize an EP */
891static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
892{
893 udc->realized_eps &= ~(1 << hwep);
894 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
895}
896
897/*
898 *
899 * Endpoint support functions
900 *
901 */
902/* Select and clear endpoint interrupt */
903static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
904{
905 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
906 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
907}
908
909/* Disables the endpoint in the USB protocol engine */
910static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
911{
912 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
913 DAT_WR_BYTE(EP_STAT_DA));
914}
915
916/* Stalls the endpoint - endpoint will return STALL */
917static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
918{
919 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
920 DAT_WR_BYTE(EP_STAT_ST));
921}
922
923/* Clear stall or reset endpoint */
924static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
925{
926 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
927 DAT_WR_BYTE(0));
928}
929
930/* Select an endpoint for endpoint status, clear, validate */
931static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
932{
933 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
934}
935
936/*
937 *
938 * Endpoint buffer management functions
939 *
940 */
941/* Clear the current endpoint's buffer */
942static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
943{
944 udc_select_hwep(udc, hwep);
945 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
946}
947
948/* Validate the current endpoint's buffer */
949static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
950{
951 udc_select_hwep(udc, hwep);
952 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
953}
954
955static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
956{
957 /* Clear EP interrupt */
958 uda_clear_hwepint(udc, hwep);
959 return udc_selep_clrint(udc, hwep);
960}
961
962/*
963 *
964 * USB EP DMA support
965 *
966 */
967/* Allocate a DMA Descriptor */
968static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
969{
970 dma_addr_t dma;
971 struct lpc32xx_usbd_dd_gad *dd;
972
973 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
974 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
975 if (dd)
976 dd->this_dma = dma;
977
978 return dd;
979}
980
981/* Free a DMA Descriptor */
982static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
983{
984 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
985}
986
987/*
988 *
989 * USB setup and shutdown functions
990 *
991 */
992/* Enables or disables most of the USB system clocks when low power mode is
993 * needed. Clocks are typically started on a connection event, and disabled
994 * when a cable is disconnected */
24a28e42
RS		 995static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
996{
24a28e42
RS		 997 if (enable != 0) {
998 if (udc->clocked)
999 return;
1000
1001 udc->clocked = 1;
1002
1003 /* 48MHz PLL up */
1004 clk_enable(udc->usb_pll_clk);
1005
1006 /* Enable the USB device clock */
1007 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
1008 USB_CTRL);
1009
50856699 1010 clk_enable(udc->usb_otg_clk);
24a28e42
RS		 1011 } else {
1012 if (!udc->clocked)
1013 return;
1014
1015 udc->clocked = 0;
1016
1017 /* Never disable the USB_HCLK during normal operation */
1018
1019 /* 48MHz PLL dpwn */
1020 clk_disable(udc->usb_pll_clk);
1021
50856699 1022 /* Disable the USB device clock */
24a28e42
RS		 1023 writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
1024 USB_CTRL);
1025
50856699 1026 clk_disable(udc->usb_otg_clk);
24a28e42
RS		 1027 }
1028}
1029
1030/* Set/reset USB device address */
1031static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
1032{
1033 /* Address will be latched at the end of the status phase, or
1034 latched immediately if function is called twice */
1035 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
1036 DAT_WR_BYTE(DEV_EN | addr));
1037}
1038
1039/* Setup up a IN request for DMA transfer - this consists of determining the
1040 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1041 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1042static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1043{
1044 struct lpc32xx_request *req;
1045 u32 hwep = ep->hwep_num;
1046
1047 ep->req_pending = 1;
1048
1049 /* There will always be a request waiting here */
1050 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1051
1052 /* Place the DD Descriptor into the UDCA */
1053 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1054
1055 /* Enable DMA and interrupt for the HW EP */
1056 udc_ep_dma_enable(udc, hwep);
1057
1058 /* Clear ZLP if last packet is not of MAXP size */
1059 if (req->req.length % ep->ep.maxpacket)
1060 req->send_zlp = 0;
1061
1062 return 0;
1063}
1064
1065/* Setup up a OUT request for DMA transfer - this consists of determining the
1066 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1067 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1068static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1069{
1070 struct lpc32xx_request *req;
1071 u32 hwep = ep->hwep_num;
1072
1073 ep->req_pending = 1;
1074
1075 /* There will always be a request waiting here */
1076 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1077
1078 /* Place the DD Descriptor into the UDCA */
1079 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1080
1081 /* Enable DMA and interrupt for the HW EP */
1082 udc_ep_dma_enable(udc, hwep);
1083 return 0;
1084}
1085
1086static void udc_disable(struct lpc32xx_udc *udc)
1087{
1088 u32 i;
1089
1090 /* Disable device */
1091 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1092 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1093
1094 /* Disable all device interrupts (including EP0) */
1095 uda_disable_devint(udc, 0x3FF);
1096
1097 /* Disable and reset all endpoint interrupts */
1098 for (i = 0; i < 32; i++) {
1099 uda_disable_hwepint(udc, i);
1100 uda_clear_hwepint(udc, i);
1101 udc_disable_hwep(udc, i);
1102 udc_unrealize_hwep(udc, i);
1103 udc->udca_v_base[i] = 0;
1104
1105 /* Disable and clear all interrupts and DMA */
1106 udc_ep_dma_disable(udc, i);
1107 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1108 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1109 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1110 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1111 }
1112
1113 /* Disable DMA interrupts */
1114 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1115
1116 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1117}
1118
1119static void udc_enable(struct lpc32xx_udc *udc)
1120{
1121 u32 i;
1122 struct lpc32xx_ep *ep = &udc->ep[0];
1123
1124 /* Start with known state */
1125 udc_disable(udc);
1126
1127 /* Enable device */
1128 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1129
1130 /* EP interrupts on high priority, FRAME interrupt on low priority */
1131 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1132 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1133
1134 /* Clear any pending device interrupts */
1135 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1136
1137 /* Setup UDCA - not yet used (DMA) */
1138 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1139
1140 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1141 for (i = 0; i <= 1; i++) {
1142 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1143 uda_enable_hwepint(udc, i);
1144 udc_select_hwep(udc, i);
1145 udc_clrstall_hwep(udc, i);
1146 udc_clr_buffer_hwep(udc, i);
1147 }
1148
1149 /* Device interrupt setup */
1150 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1151 USBD_EP_FAST));
1152 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1153 USBD_EP_FAST));
1154
1155 /* Set device address to 0 - called twice to force a latch in the USB
1156 engine without the need of a setup packet status closure */
1157 udc_set_address(udc, 0);
1158 udc_set_address(udc, 0);
1159
1160 /* Enable master DMA interrupts */
1161 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1162 USBD_DMAINTEN(udc->udp_baseaddr));
1163
1164 udc->dev_status = 0;
1165}
1166
1167/*
1168 *
1169 * USB device board specific events handled via callbacks
1170 *
1171 */
1172/* Connection change event - notify board function of change */
1173static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1174{
1175 /* Just notify of a connection change event (optional) */
1176 if (udc->board->conn_chgb != NULL)
1177 udc->board->conn_chgb(conn);
1178}
1179
1180/* Suspend/resume event - notify board function of change */
1181static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1182{
1183 /* Just notify of a Suspend/resume change event (optional) */
1184 if (udc->board->susp_chgb != NULL)
1185 udc->board->susp_chgb(conn);
1186
1187 if (conn)
1188 udc->suspended = 0;
1189 else
1190 udc->suspended = 1;
1191}
1192
1193/* Remote wakeup enable/disable - notify board function of change */
1194static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1195{
1196 if (udc->board->rmwk_chgb != NULL)
1197 udc->board->rmwk_chgb(udc->dev_status &
1198 (1 << USB_DEVICE_REMOTE_WAKEUP));
1199}
1200
1201/* Reads data from FIFO, adjusts for alignment and data size */
1202static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1203{
1204 int n, i, bl;
1205 u16 *p16;
1206 u32 *p32, tmp, cbytes;
1207
1208 /* Use optimal data transfer method based on source address and size */
1209 switch (((u32) data) & 0x3) {
1210 case 0: /* 32-bit aligned */
1211 p32 = (u32 *) data;
1212 cbytes = (bytes & ~0x3);
1213
1214 /* Copy 32-bit aligned data first */
1215 for (n = 0; n < cbytes; n += 4)
1216 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1217
1218 /* Handle any remaining bytes */
1219 bl = bytes - cbytes;
1220 if (bl) {
1221 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1222 for (n = 0; n < bl; n++)
1223 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1224
1225 }
1226 break;
1227
1228 case 1: /* 8-bit aligned */
1229 case 3:
1230 /* Each byte has to be handled independently */
1231 for (n = 0; n < bytes; n += 4) {
1232 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1233
1234 bl = bytes - n;
1235 if (bl > 3)
1236 bl = 3;
1237
1238 for (i = 0; i < bl; i++)
1239 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
1240 }
1241 break;
1242
1243 case 2: /* 16-bit aligned */
1244 p16 = (u16 *) data;
1245 cbytes = (bytes & ~0x3);
1246
1247 /* Copy 32-bit sized objects first with 16-bit alignment */
1248 for (n = 0; n < cbytes; n += 4) {
1249 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1250 *p16++ = (u16)(tmp & 0xFFFF);
1251 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1252 }
1253
1254 /* Handle any remaining bytes */
1255 bl = bytes - cbytes;
1256 if (bl) {
1257 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1258 for (n = 0; n < bl; n++)
1259 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1260 }
1261 break;
1262 }
1263}
1264
1265/* Read data from the FIFO for an endpoint. This function is for endpoints (such
1266 * as EP0) that don't use DMA. This function should only be called if a packet
1267 * is known to be ready to read for the endpoint. Note that the endpoint must
1268 * be selected in the protocol engine prior to this call. */
1269static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1270 u32 bytes)
1271{
1272 u32 tmpv;
1273 int to = 1000;
1274 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1275
1276 /* Setup read of endpoint */
1277 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1278
1279 /* Wait until packet is ready */
1280 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1281 PKT_RDY) == 0) && (to > 0))
1282 to--;
1283 if (!to)
1284 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1285
1286 /* Mask out count */
1287 tmp = tmpv & PKT_LNGTH_MASK;
1288 if (bytes < tmp)
1289 tmp = bytes;
1290
1291 if ((tmp > 0) && (data != NULL))
1292 udc_pop_fifo(udc, (u8 *) data, tmp);
1293
1294 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1295
1296 /* Clear the buffer */
1297 udc_clr_buffer_hwep(udc, hwep);
1298
1299 return tmp;
1300}
1301
1302/* Stuffs data into the FIFO, adjusts for alignment and data size */
1303static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1304{
1305 int n, i, bl;
1306 u16 *p16;
1307 u32 *p32, tmp, cbytes;
1308
1309 /* Use optimal data transfer method based on source address and size */
1310 switch (((u32) data) & 0x3) {
1311 case 0: /* 32-bit aligned */
1312 p32 = (u32 *) data;
1313 cbytes = (bytes & ~0x3);
1314
1315 /* Copy 32-bit aligned data first */
1316 for (n = 0; n < cbytes; n += 4)
1317 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1318
1319 /* Handle any remaining bytes */
1320 bl = bytes - cbytes;
1321 if (bl) {
1322 tmp = 0;
1323 for (n = 0; n < bl; n++)
1324 tmp |= data[cbytes + n] << (n * 8);
1325
1326 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1327 }
1328 break;
1329
1330 case 1: /* 8-bit aligned */
1331 case 3:
1332 /* Each byte has to be handled independently */
1333 for (n = 0; n < bytes; n += 4) {
1334 bl = bytes - n;
1335 if (bl > 4)
1336 bl = 4;
1337
1338 tmp = 0;
1339 for (i = 0; i < bl; i++)
1340 tmp |= data[n + i] << (i * 8);
1341
1342 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1343 }
1344 break;
1345
1346 case 2: /* 16-bit aligned */
1347 p16 = (u16 *) data;
1348 cbytes = (bytes & ~0x3);
1349
1350 /* Copy 32-bit aligned data first */
1351 for (n = 0; n < cbytes; n += 4) {
1352 tmp = *p16++ & 0xFFFF;
1353 tmp |= (*p16++ & 0xFFFF) << 16;
1354 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1355 }
1356
1357 /* Handle any remaining bytes */
1358 bl = bytes - cbytes;
1359 if (bl) {
1360 tmp = 0;
1361 for (n = 0; n < bl; n++)
1362 tmp |= data[cbytes + n] << (n * 8);
1363
1364 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1365 }
1366 break;
1367 }
1368}
1369
1370/* Write data to the FIFO for an endpoint. This function is for endpoints (such
1371 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1372 * protocol engine prior to this call. */
1373static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1374 u32 bytes)
1375{
1376 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1377
1378 if ((bytes > 0) && (data == NULL))
1379 return;
1380
1381 /* Setup write of endpoint */
1382 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1383
1384 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1385
1386 /* Need at least 1 byte to trigger TX */
1387 if (bytes == 0)
1388 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1389 else
1390 udc_stuff_fifo(udc, (u8 *) data, bytes);
1391
1392 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1393
1394 udc_val_buffer_hwep(udc, hwep);
1395}
1396
1397/* USB device reset - resets USB to a default state with just EP0
1398 enabled */
1399static void uda_usb_reset(struct lpc32xx_udc *udc)
1400{
1401 u32 i = 0;
1402 /* Re-init device controller and EP0 */
1403 udc_enable(udc);
1404 udc->gadget.speed = USB_SPEED_FULL;
1405
1406 for (i = 1; i < NUM_ENDPOINTS; i++) {
1407 struct lpc32xx_ep *ep = &udc->ep[i];
1408 ep->req_pending = 0;
1409 }
1410}
1411
1412/* Send a ZLP on EP0 */
1413static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1414{
1415 udc_write_hwep(udc, EP_IN, NULL, 0);
1416}
1417
1418/* Get current frame number */
1419static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1420{
1421 u16 flo, fhi;
1422
1423 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1424 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1425 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1426
1427 return (fhi << 8) | flo;
1428}
1429
1430/* Set the device as configured - enables all endpoints */
1431static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1432{
1433 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1434}
1435
1436/* Set the device as unconfigured - disables all endpoints */
1437static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1438{
1439 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1440}
1441
1442/* reinit == restore initial software state */
1443static void udc_reinit(struct lpc32xx_udc *udc)
1444{
1445 u32 i;
1446
1447 INIT_LIST_HEAD(&udc->gadget.ep_list);
1448 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1449
1450 for (i = 0; i < NUM_ENDPOINTS; i++) {
1451 struct lpc32xx_ep *ep = &udc->ep[i];
1452
1453 if (i != 0)
1454 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1455 ep->desc = NULL;
1456 ep->ep.maxpacket = ep->maxpacket;
1457 INIT_LIST_HEAD(&ep->queue);
1458 ep->req_pending = 0;
1459 }
1460
1461 udc->ep0state = WAIT_FOR_SETUP;
1462}
1463
1464/* Must be called with lock */
1465static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1466{
1467 struct lpc32xx_udc *udc = ep->udc;
1468
1469 list_del_init(&req->queue);
1470 if (req->req.status == -EINPROGRESS)
1471 req->req.status = status;
1472 else
1473 status = req->req.status;
1474
1475 if (ep->lep) {
1476 enum dma_data_direction direction;
1477
1478 if (ep->is_in)
1479 direction = DMA_TO_DEVICE;
1480 else
1481 direction = DMA_FROM_DEVICE;
1482
1483 if (req->mapped) {
1484 dma_unmap_single(ep->udc->gadget.dev.parent,
1485 req->req.dma, req->req.length,
1486 direction);
1487 req->req.dma = 0;
1488 req->mapped = 0;
1489 } else
1490 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
1491 req->req.dma, req->req.length,
1492 direction);
1493
1494 /* Free DDs */
1495 udc_dd_free(udc, req->dd_desc_ptr);
1496 }
1497
1498 if (status && status != -ESHUTDOWN)
1499 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1500
1501 ep->req_pending = 0;
1502 spin_unlock(&udc->lock);
1503 req->req.complete(&ep->ep, &req->req);
1504 spin_lock(&udc->lock);
1505}
1506
1507/* Must be called with lock */
1508static void nuke(struct lpc32xx_ep *ep, int status)
1509{
1510 struct lpc32xx_request *req;
1511
1512 while (!list_empty(&ep->queue)) {
1513 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1514 done(ep, req, status);
1515 }
1516
1517 if (ep->desc && status == -ESHUTDOWN) {
1518 uda_disable_hwepint(ep->udc, ep->hwep_num);
1519 udc_disable_hwep(ep->udc, ep->hwep_num);
1520 }
1521}
1522
1523/* IN endpoint 0 transfer */
1524static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1525{
1526 struct lpc32xx_request *req;
1527 struct lpc32xx_ep *ep0 = &udc->ep[0];
1528 u32 tsend, ts = 0;
1529
1530 if (list_empty(&ep0->queue))
1531 /* Nothing to send */
1532 return 0;
1533 else
1534 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1535 queue);
1536
1537 tsend = ts = req->req.length - req->req.actual;
1538 if (ts == 0) {
1539 /* Send a ZLP */
1540 udc_ep0_send_zlp(udc);
1541 done(ep0, req, 0);
1542 return 1;
1543 } else if (ts > ep0->ep.maxpacket)
1544 ts = ep0->ep.maxpacket; /* Just send what we can */
1545
1546 /* Write data to the EP0 FIFO and start transfer */
1547 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1548
1549 /* Increment data pointer */
1550 req->req.actual += ts;
1551
1552 if (tsend >= ep0->ep.maxpacket)
1553 return 0; /* Stay in data transfer state */
1554
1555 /* Transfer request is complete */
1556 udc->ep0state = WAIT_FOR_SETUP;
1557 done(ep0, req, 0);
1558 return 1;
1559}
1560
1561/* OUT endpoint 0 transfer */
1562static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1563{
1564 struct lpc32xx_request *req;
1565 struct lpc32xx_ep *ep0 = &udc->ep[0];
1566 u32 tr, bufferspace;
1567
1568 if (list_empty(&ep0->queue))
1569 return 0;
1570 else
1571 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1572 queue);
1573
1574 if (req) {
1575 if (req->req.length == 0) {
1576 /* Just dequeue request */
1577 done(ep0, req, 0);
1578 udc->ep0state = WAIT_FOR_SETUP;
1579 return 1;
1580 }
1581
1582 /* Get data from FIFO */
1583 bufferspace = req->req.length - req->req.actual;
1584 if (bufferspace > ep0->ep.maxpacket)
1585 bufferspace = ep0->ep.maxpacket;
1586
1587 /* Copy data to buffer */
1588 prefetchw(req->req.buf + req->req.actual);
1589 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1590 bufferspace);
1591 req->req.actual += bufferspace;
1592
1593 if (tr < ep0->ep.maxpacket) {
1594 /* This is the last packet */
1595 done(ep0, req, 0);
1596 udc->ep0state = WAIT_FOR_SETUP;
1597 return 1;
1598 }
1599 }
1600
1601 return 0;
1602}
1603
1604/* Must be called with lock */
1605static void stop_activity(struct lpc32xx_udc *udc)
1606{
1607 struct usb_gadget_driver *driver = udc->driver;
1608 int i;
1609
1610 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1611 driver = NULL;
1612
1613 udc->gadget.speed = USB_SPEED_UNKNOWN;
1614 udc->suspended = 0;
1615
1616 for (i = 0; i < NUM_ENDPOINTS; i++) {
1617 struct lpc32xx_ep *ep = &udc->ep[i];
1618 nuke(ep, -ESHUTDOWN);
1619 }
1620 if (driver) {
1621 spin_unlock(&udc->lock);
1622 driver->disconnect(&udc->gadget);
1623 spin_lock(&udc->lock);
1624 }
1625
1626 isp1301_pullup_enable(udc, 0, 0);
1627 udc_disable(udc);
1628 udc_reinit(udc);
1629}
1630
1631/*
1632 * Activate or kill host pullup
1633 * Can be called with or without lock
1634 */
1635static void pullup(struct lpc32xx_udc *udc, int is_on)
1636{
1637 if (!udc->clocked)
1638 return;
1639
1640 if (!udc->enabled || !udc->vbus)
1641 is_on = 0;
1642
1643 if (is_on != udc->pullup)
1644 isp1301_pullup_enable(udc, is_on, 0);
1645}
1646
1647/* Must be called without lock */
1648static int lpc32xx_ep_disable(struct usb_ep *_ep)
1649{
1650 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1651 struct lpc32xx_udc *udc = ep->udc;
1652 unsigned long flags;
1653
1654 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1655 return -EINVAL;
1656 spin_lock_irqsave(&udc->lock, flags);
1657
1658 nuke(ep, -ESHUTDOWN);
1659
1660 /* restore the endpoint's pristine config */
1661 ep->desc = NULL;
1662
1663 /* Clear all DMA statuses for this EP */
1664 udc_ep_dma_disable(udc, ep->hwep_num);
1665 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1666 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1667 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1668 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1669
1670 /* Remove the DD pointer in the UDCA */
1671 udc->udca_v_base[ep->hwep_num] = 0;
1672
1673 /* Disable and reset endpoint and interrupt */
1674 uda_clear_hwepint(udc, ep->hwep_num);
1675 udc_unrealize_hwep(udc, ep->hwep_num);
1676
1677 ep->hwep_num = 0;
1678
1679 spin_unlock_irqrestore(&udc->lock, flags);
1680
1681 atomic_dec(&udc->enabled_ep_cnt);
1682 wake_up(&udc->ep_disable_wait_queue);
1683
1684 return 0;
1685}
1686
1687/* Must be called without lock */
1688static int lpc32xx_ep_enable(struct usb_ep *_ep,
1689 const struct usb_endpoint_descriptor *desc)
1690{
1691 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1692 struct lpc32xx_udc *udc = ep->udc;
1693 u16 maxpacket;
1694 u32 tmp;
1695 unsigned long flags;
1696
1697 /* Verify EP data */
1698 if ((!_ep) || (!ep) || (!desc) || (ep->desc) ||
1699 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1700 dev_dbg(udc->dev, "bad ep or descriptor\n");
1701 return -EINVAL;
1702 }
1703 maxpacket = usb_endpoint_maxp(desc);
1704 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1705 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1706 return -EINVAL;
1707 }
1708
1709 /* Don't touch EP0 */
1710 if (ep->hwep_num_base == 0) {
1711 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1712 return -EINVAL;
1713 }
1714
1715 /* Is driver ready? */
1716 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1717 dev_dbg(udc->dev, "bogus device state\n");
1718 return -ESHUTDOWN;
1719 }
1720
1721 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1722 switch (tmp) {
1723 case USB_ENDPOINT_XFER_CONTROL:
1724 return -EINVAL;
1725
1726 case USB_ENDPOINT_XFER_INT:
1727 if (maxpacket > ep->maxpacket) {
1728 dev_dbg(udc->dev,
1729 "Bad INT endpoint maxpacket %d\n", maxpacket);
1730 return -EINVAL;
1731 }
1732 break;
1733
1734 case USB_ENDPOINT_XFER_BULK:
1735 switch (maxpacket) {
1736 case 8:
1737 case 16:
1738 case 32:
1739 case 64:
1740 break;
1741
1742 default:
1743 dev_dbg(udc->dev,
1744 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1745 return -EINVAL;
1746 }
1747 break;
1748
1749 case USB_ENDPOINT_XFER_ISOC:
1750 break;
1751 }
1752 spin_lock_irqsave(&udc->lock, flags);
1753
1754 /* Initialize endpoint to match the selected descriptor */
1755 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1756 ep->desc = desc;
1757 ep->ep.maxpacket = maxpacket;
1758
1759 /* Map hardware endpoint from base and direction */
1760 if (ep->is_in)
1761 /* IN endpoints are offset 1 from the OUT endpoint */
1762 ep->hwep_num = ep->hwep_num_base + EP_IN;
1763 else
1764 ep->hwep_num = ep->hwep_num_base;
1765
1766 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1767 ep->hwep_num, maxpacket, (ep->is_in == 1));
1768
1769 /* Realize the endpoint, interrupt is enabled later when
1770 * buffers are queued, IN EPs will NAK until buffers are ready */
1771 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1772 udc_clr_buffer_hwep(udc, ep->hwep_num);
1773 uda_disable_hwepint(udc, ep->hwep_num);
1774 udc_clrstall_hwep(udc, ep->hwep_num);
1775
1776 /* Clear all DMA statuses for this EP */
1777 udc_ep_dma_disable(udc, ep->hwep_num);
1778 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1779 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1780 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1781 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1782
1783 spin_unlock_irqrestore(&udc->lock, flags);
1784
1785 atomic_inc(&udc->enabled_ep_cnt);
1786 return 0;
1787}
1788
1789/*
1790 * Allocate a USB request list
1791 * Can be called with or without lock
1792 */
1793static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1794 gfp_t gfp_flags)
1795{
1796 struct lpc32xx_request *req;
1797
1798 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1799 if (!req)
1800 return NULL;
1801
1802 INIT_LIST_HEAD(&req->queue);
1803 return &req->req;
1804}
1805
1806/*
1807 * De-allocate a USB request list
1808 * Can be called with or without lock
1809 */
1810static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1811 struct usb_request *_req)
1812{
1813 struct lpc32xx_request *req;
1814
1815 req = container_of(_req, struct lpc32xx_request, req);
1816 BUG_ON(!list_empty(&req->queue));
1817 kfree(req);
1818}
1819
1820/* Must be called without lock */
1821static int lpc32xx_ep_queue(struct usb_ep *_ep,
1822 struct usb_request *_req, gfp_t gfp_flags)
1823{
1824 struct lpc32xx_request *req;
1825 struct lpc32xx_ep *ep;
1826 struct lpc32xx_udc *udc;
1827 unsigned long flags;
1828 int status = 0;
1829
1830 req = container_of(_req, struct lpc32xx_request, req);
1831 ep = container_of(_ep, struct lpc32xx_ep, ep);
1832
1833 if (!_req || !_req->complete || !_req->buf ||
1834 !list_empty(&req->queue))
1835 return -EINVAL;
1836
1837 udc = ep->udc;
1838
1839 if (!_ep || (!ep->desc && ep->hwep_num_base != 0)) {
1840 dev_dbg(udc->dev, "invalid ep\n");
1841 return -EINVAL;
1842 }
1843
1844
1845 if ((!udc) || (!udc->driver) ||
1846 (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1847 dev_dbg(udc->dev, "invalid device\n");
1848 return -EINVAL;
1849 }
1850
1851 if (ep->lep) {
1852 enum dma_data_direction direction;
1853 struct lpc32xx_usbd_dd_gad *dd;
1854
1855 /* Map DMA pointer */
1856 if (ep->is_in)
1857 direction = DMA_TO_DEVICE;
1858 else
1859 direction = DMA_FROM_DEVICE;
1860
1861 if (req->req.dma == 0) {
1862 req->req.dma = dma_map_single(
1863 ep->udc->gadget.dev.parent,
1864 req->req.buf, req->req.length, direction);
1865 req->mapped = 1;
1866 } else {
1867 dma_sync_single_for_device(
1868 ep->udc->gadget.dev.parent, req->req.dma,
1869 req->req.length, direction);
1870 req->mapped = 0;
1871 }
1872
1873 /* For the request, build a list of DDs */
1874 dd = udc_dd_alloc(udc);
1875 if (!dd) {
1876 /* Error allocating DD */
1877 return -ENOMEM;
1878 }
1879 req->dd_desc_ptr = dd;
1880
1881 /* Setup the DMA descriptor */
1882 dd->dd_next_phy = dd->dd_next_v = 0;
1883 dd->dd_buffer_addr = req->req.dma;
1884 dd->dd_status = 0;
1885
1886 /* Special handling for ISO EPs */
1887 if (ep->eptype == EP_ISO_TYPE) {
1888 dd->dd_setup = DD_SETUP_ISO_EP |
1889 DD_SETUP_PACKETLEN(0) |
1890 DD_SETUP_DMALENBYTES(1);
1891 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1892 if (ep->is_in)
1893 dd->iso_status[0] = req->req.length;
1894 else
1895 dd->iso_status[0] = 0;
1896 } else
1897 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1898 DD_SETUP_DMALENBYTES(req->req.length);
1899 }
1900
1901 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1902 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1903
1904 spin_lock_irqsave(&udc->lock, flags);
1905
1906 _req->status = -EINPROGRESS;
1907 _req->actual = 0;
1908 req->send_zlp = _req->zero;
1909
1910 /* Kickstart empty queues */
1911 if (list_empty(&ep->queue)) {
1912 list_add_tail(&req->queue, &ep->queue);
1913
1914 if (ep->hwep_num_base == 0) {
1915 /* Handle expected data direction */
1916 if (ep->is_in) {
1917 /* IN packet to host */
1918 udc->ep0state = DATA_IN;
1919 status = udc_ep0_in_req(udc);
1920 } else {
1921 /* OUT packet from host */
1922 udc->ep0state = DATA_OUT;
1923 status = udc_ep0_out_req(udc);
1924 }
1925 } else if (ep->is_in) {
1926 /* IN packet to host and kick off transfer */
1927 if (!ep->req_pending)
1928 udc_ep_in_req_dma(udc, ep);
1929 } else
1930 /* OUT packet from host and kick off list */
1931 if (!ep->req_pending)
1932 udc_ep_out_req_dma(udc, ep);
1933 } else
1934 list_add_tail(&req->queue, &ep->queue);
1935
1936 spin_unlock_irqrestore(&udc->lock, flags);
1937
1938 return (status < 0) ? status : 0;
1939}
1940
1941/* Must be called without lock */
1942static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1943{
1944 struct lpc32xx_ep *ep;
1945 struct lpc32xx_request *req;
1946 unsigned long flags;
1947
1948 ep = container_of(_ep, struct lpc32xx_ep, ep);
1949 if (!_ep || ep->hwep_num_base == 0)
1950 return -EINVAL;
1951
1952 spin_lock_irqsave(&ep->udc->lock, flags);
1953
1954 /* make sure it's actually queued on this endpoint */
1955 list_for_each_entry(req, &ep->queue, queue) {
1956 if (&req->req == _req)
1957 break;
1958 }
1959 if (&req->req != _req) {
1960 spin_unlock_irqrestore(&ep->udc->lock, flags);
1961 return -EINVAL;
1962 }
1963
1964 done(ep, req, -ECONNRESET);
1965
1966 spin_unlock_irqrestore(&ep->udc->lock, flags);
1967
1968 return 0;
1969}
1970
1971/* Must be called without lock */
1972static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1973{
1974 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1975 struct lpc32xx_udc *udc = ep->udc;
1976 unsigned long flags;
1977
1978 if ((!ep) || (ep->desc == NULL) || (ep->hwep_num <= 1))
1979 return -EINVAL;
1980
1981 /* Don't halt an IN EP */
1982 if (ep->is_in)
1983 return -EAGAIN;
1984
1985 spin_lock_irqsave(&udc->lock, flags);
1986
1987 if (value == 1) {
1988 /* stall */
1989 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1990 DAT_WR_BYTE(EP_STAT_ST));
1991 } else {
1992 /* End stall */
1993 ep->wedge = 0;
1994 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1995 DAT_WR_BYTE(0));
1996 }
1997
1998 spin_unlock_irqrestore(&udc->lock, flags);
1999
2000 return 0;
2001}
2002
2003/* set the halt feature and ignores clear requests */
2004static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
2005{
2006 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
2007
2008 if (!_ep || !ep->udc)
2009 return -EINVAL;
2010
2011 ep->wedge = 1;
2012
2013 return usb_ep_set_halt(_ep);
2014}
2015
2016static const struct usb_ep_ops lpc32xx_ep_ops = {
2017 .enable = lpc32xx_ep_enable,
2018 .disable = lpc32xx_ep_disable,
2019 .alloc_request = lpc32xx_ep_alloc_request,
2020 .free_request = lpc32xx_ep_free_request,
2021 .queue = lpc32xx_ep_queue,
2022 .dequeue = lpc32xx_ep_dequeue,
2023 .set_halt = lpc32xx_ep_set_halt,
2024 .set_wedge = lpc32xx_ep_set_wedge,
2025};
2026
2027/* Send a ZLP on a non-0 IN EP */
2028void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2029{
2030 /* Clear EP status */
2031 udc_clearep_getsts(udc, ep->hwep_num);
2032
2033 /* Send ZLP via FIFO mechanism */
2034 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
2035}
2036
2037/*
2038 * Handle EP completion for ZLP
2039 * This function will only be called when a delayed ZLP needs to be sent out
2040 * after a DMA transfer has filled both buffers.
2041 */
2042void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2043{
2044 u32 epstatus;
2045 struct lpc32xx_request *req;
2046
2047 if (ep->hwep_num <= 0)
2048 return;
2049
2050 uda_clear_hwepint(udc, ep->hwep_num);
2051
2052 /* If this interrupt isn't enabled, return now */
2053 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
2054 return;
2055
2056 /* Get endpoint status */
2057 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2058
2059 /*
2060 * This should never happen, but protect against writing to the
2061 * buffer when full.
2062 */
2063 if (epstatus & EP_SEL_F)
2064 return;
2065
2066 if (ep->is_in) {
2067 udc_send_in_zlp(udc, ep);
2068 uda_disable_hwepint(udc, ep->hwep_num);
2069 } else
2070 return;
2071
2072 /* If there isn't a request waiting, something went wrong */
2073 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2074 if (req) {
2075 done(ep, req, 0);
2076
2077 /* Start another request if ready */
2078 if (!list_empty(&ep->queue)) {
2079 if (ep->is_in)
2080 udc_ep_in_req_dma(udc, ep);
2081 else
2082 udc_ep_out_req_dma(udc, ep);
2083 } else
2084 ep->req_pending = 0;
2085 }
2086}
2087
2088
2089/* DMA end of transfer completion */
2090static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2091{
2092 u32 status, epstatus;
2093 struct lpc32xx_request *req;
2094 struct lpc32xx_usbd_dd_gad *dd;
2095
2096#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2097 ep->totalints++;
2098#endif
2099
2100 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2101 if (!req) {
2102 ep_err(ep, "DMA interrupt on no req!\n");
2103 return;
2104 }
2105 dd = req->dd_desc_ptr;
2106
2107 /* DMA descriptor should always be retired for this call */
2108 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2109 ep_warn(ep, "DMA descriptor did not retire\n");
2110
2111 /* Disable DMA */
2112 udc_ep_dma_disable(udc, ep->hwep_num);
2113 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2114 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2115
2116 /* System error? */
2117 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2118 (1 << ep->hwep_num)) {
2119 writel((1 << ep->hwep_num),
2120 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2121 ep_err(ep, "AHB critical error!\n");
2122 ep->req_pending = 0;
2123
2124 /* The error could have occurred on a packet of a multipacket
2125 * transfer, so recovering the transfer is not possible. Close
2126 * the request with an error */
2127 done(ep, req, -ECONNABORTED);
2128 return;
2129 }
2130
2131 /* Handle the current DD's status */
2132 status = dd->dd_status;
2133 switch (status & DD_STATUS_STS_MASK) {
2134 case DD_STATUS_STS_NS:
2135 /* DD not serviced? This shouldn't happen! */
2136 ep->req_pending = 0;
2137 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2138 status);
2139
2140 done(ep, req, -ECONNABORTED);
2141 return;
2142
2143 case DD_STATUS_STS_BS:
2144 /* Interrupt only fires on EOT - This shouldn't happen! */
2145 ep->req_pending = 0;
2146 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2147 status);
2148 done(ep, req, -ECONNABORTED);
2149 return;
2150
2151 case DD_STATUS_STS_NC:
2152 case DD_STATUS_STS_DUR:
2153 /* Really just a short packet, not an underrun */
2154 /* This is a good status and what we expect */
2155 break;
2156
2157 default:
2158 /* Data overrun, system error, or unknown */
2159 ep->req_pending = 0;
2160 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2161 status);
2162 done(ep, req, -ECONNABORTED);
2163 return;
2164 }
2165
2166 /* ISO endpoints are handled differently */
2167 if (ep->eptype == EP_ISO_TYPE) {
2168 if (ep->is_in)
2169 req->req.actual = req->req.length;
2170 else
2171 req->req.actual = dd->iso_status[0] & 0xFFFF;
2172 } else
2173 req->req.actual += DD_STATUS_CURDMACNT(status);
2174
2175 /* Send a ZLP if necessary. This will be done for non-int
2176 * packets which have a size that is a divisor of MAXP */
2177 if (req->send_zlp) {
2178 /*
2179 * If at least 1 buffer is available, send the ZLP now.
2180 * Otherwise, the ZLP send needs to be deferred until a
2181 * buffer is available.
2182 */
2183 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2184 udc_clearep_getsts(udc, ep->hwep_num);
2185 uda_enable_hwepint(udc, ep->hwep_num);
2186 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2187
2188 /* Let the EP interrupt handle the ZLP */
2189 return;
2190 } else
2191 udc_send_in_zlp(udc, ep);
2192 }
2193
2194 /* Transfer request is complete */
2195 done(ep, req, 0);
2196
2197 /* Start another request if ready */
2198 udc_clearep_getsts(udc, ep->hwep_num);
2199 if (!list_empty((&ep->queue))) {
2200 if (ep->is_in)
2201 udc_ep_in_req_dma(udc, ep);
2202 else
2203 udc_ep_out_req_dma(udc, ep);
2204 } else
2205 ep->req_pending = 0;
2206
2207}
2208
2209/*
2210 *
2211 * Endpoint 0 functions
2212 *
2213 */
2214static void udc_handle_dev(struct lpc32xx_udc *udc)
2215{
2216 u32 tmp;
2217
2218 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2219 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2220
2221 if (tmp & DEV_RST)
2222 uda_usb_reset(udc);
2223 else if (tmp & DEV_CON_CH)
2224 uda_power_event(udc, (tmp & DEV_CON));
2225 else if (tmp & DEV_SUS_CH) {
2226 if (tmp & DEV_SUS) {
2227 if (udc->vbus == 0)
2228 stop_activity(udc);
2229 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2230 udc->driver) {
2231 /* Power down transceiver */
2232 udc->poweron = 0;
2233 schedule_work(&udc->pullup_job);
2234 uda_resm_susp_event(udc, 1);
2235 }
2236 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2237 udc->driver && udc->vbus) {
2238 uda_resm_susp_event(udc, 0);
2239 /* Power up transceiver */
2240 udc->poweron = 1;
2241 schedule_work(&udc->pullup_job);
2242 }
2243 }
2244}
2245
2246static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2247{
2248 struct lpc32xx_ep *ep;
2249 u32 ep0buff = 0, tmp;
2250
2251 switch (reqtype & USB_RECIP_MASK) {
2252 case USB_RECIP_INTERFACE:
2253 break; /* Not supported */
2254
2255 case USB_RECIP_DEVICE:
2256 ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
2257 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2258 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2259 break;
2260
2261 case USB_RECIP_ENDPOINT:
2262 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2263 ep = &udc->ep[tmp];
2264 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS) || (tmp && !ep->desc))
2265 return -EOPNOTSUPP;
2266
2267 if (wIndex & USB_DIR_IN) {
2268 if (!ep->is_in)
2269 return -EOPNOTSUPP; /* Something's wrong */
2270 } else if (ep->is_in)
2271 return -EOPNOTSUPP; /* Not an IN endpoint */
2272
2273 /* Get status of the endpoint */
2274 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2275 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2276
2277 if (tmp & EP_SEL_ST)
2278 ep0buff = (1 << USB_ENDPOINT_HALT);
2279 else
2280 ep0buff = 0;
2281 break;
2282
2283 default:
2284 break;
2285 }
2286
2287 /* Return data */
2288 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2289
2290 return 0;
2291}
2292
2293static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2294{
2295 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2296 struct usb_ctrlrequest ctrlpkt;
2297 int i, bytes;
2298 u16 wIndex, wValue, wLength, reqtype, req, tmp;
2299
2300 /* Nuke previous transfers */
2301 nuke(ep0, -EPROTO);
2302
2303 /* Get setup packet */
2304 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2305 if (bytes != 8) {
2306 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2307 bytes);
2308 return;
2309 }
2310
2311 /* Native endianness */
2312 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2313 wValue = le16_to_cpu(ctrlpkt.wValue);
2314 wLength = le16_to_cpu(ctrlpkt.wLength);
2315 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2316
2317 /* Set direction of EP0 */
2318 if (likely(reqtype & USB_DIR_IN))
2319 ep0->is_in = 1;
2320 else
2321 ep0->is_in = 0;
2322
2323 /* Handle SETUP packet */
2324 req = le16_to_cpu(ctrlpkt.bRequest);
2325 switch (req) {
2326 case USB_REQ_CLEAR_FEATURE:
2327 case USB_REQ_SET_FEATURE:
2328 switch (reqtype) {
2329 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2330 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2331 goto stall; /* Nothing else handled */
2332
2333 /* Tell board about event */
2334 if (req == USB_REQ_CLEAR_FEATURE)
2335 udc->dev_status &=
2336 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2337 else
2338 udc->dev_status |=
2339 (1 << USB_DEVICE_REMOTE_WAKEUP);
2340 uda_remwkp_cgh(udc);
2341 goto zlp_send;
2342
2343 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2344 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2345 if ((wValue != USB_ENDPOINT_HALT) ||
2346 (tmp >= NUM_ENDPOINTS))
2347 break;
2348
2349 /* Find hardware endpoint from logical endpoint */
2350 ep = &udc->ep[tmp];
2351 tmp = ep->hwep_num;
2352 if (tmp == 0)
2353 break;
2354
2355 if (req == USB_REQ_SET_FEATURE)
2356 udc_stall_hwep(udc, tmp);
2357 else if (!ep->wedge)
2358 udc_clrstall_hwep(udc, tmp);
2359
2360 goto zlp_send;
2361
2362 default:
2363 break;
2364 }
2365
2366
2367 case USB_REQ_SET_ADDRESS:
2368 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2369 udc_set_address(udc, wValue);
2370 goto zlp_send;
2371 }
2372 break;
2373
2374 case USB_REQ_GET_STATUS:
2375 udc_get_status(udc, reqtype, wIndex);
2376 return;
2377
2378 default:
2379 break; /* Let GadgetFS handle the descriptor instead */
2380 }
2381
2382 if (likely(udc->driver)) {
2383 /* device-2-host (IN) or no data setup command, process
2384 * immediately */
2385 spin_unlock(&udc->lock);
2386 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2387
2388 spin_lock(&udc->lock);
2389 if (req == USB_REQ_SET_CONFIGURATION) {
2390 /* Configuration is set after endpoints are realized */
2391 if (wValue) {
2392 /* Set configuration */
2393 udc_set_device_configured(udc);
2394
2395 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2396 DAT_WR_BYTE(AP_CLK |
2397 INAK_BI | INAK_II));
2398 } else {
2399 /* Clear configuration */
2400 udc_set_device_unconfigured(udc);
2401
2402 /* Disable NAK interrupts */
2403 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2404 DAT_WR_BYTE(AP_CLK));
2405 }
2406 }
2407
2408 if (i < 0) {
2409 /* setup processing failed, force stall */
2410 dev_err(udc->dev,
2411 "req %02x.%02x protocol STALL; stat %d\n",
2412 reqtype, req, i);
2413 udc->ep0state = WAIT_FOR_SETUP;
2414 goto stall;
2415 }
2416 }
2417
2418 if (!ep0->is_in)
2419 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2420
2421 return;
2422
2423stall:
2424 udc_stall_hwep(udc, EP_IN);
2425 return;
2426
2427zlp_send:
2428 udc_ep0_send_zlp(udc);
2429 return;
2430}
2431
2432/* IN endpoint 0 transfer */
2433static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2434{
2435 struct lpc32xx_ep *ep0 = &udc->ep[0];
2436 u32 epstatus;
2437
2438 /* Clear EP interrupt */
2439 epstatus = udc_clearep_getsts(udc, EP_IN);
2440
2441#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2442 ep0->totalints++;
2443#endif
2444
2445 /* Stalled? Clear stall and reset buffers */
2446 if (epstatus & EP_SEL_ST) {
2447 udc_clrstall_hwep(udc, EP_IN);
2448 nuke(ep0, -ECONNABORTED);
2449 udc->ep0state = WAIT_FOR_SETUP;
2450 return;
2451 }
2452
2453 /* Is a buffer available? */
2454 if (!(epstatus & EP_SEL_F)) {
2455 /* Handle based on current state */
2456 if (udc->ep0state == DATA_IN)
2457 udc_ep0_in_req(udc);
2458 else {
2459 /* Unknown state for EP0 oe end of DATA IN phase */
2460 nuke(ep0, -ECONNABORTED);
2461 udc->ep0state = WAIT_FOR_SETUP;
2462 }
2463 }
2464}
2465
2466/* OUT endpoint 0 transfer */
2467static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2468{
2469 struct lpc32xx_ep *ep0 = &udc->ep[0];
2470 u32 epstatus;
2471
2472 /* Clear EP interrupt */
2473 epstatus = udc_clearep_getsts(udc, EP_OUT);
2474
2475
2476#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2477 ep0->totalints++;
2478#endif
2479
2480 /* Stalled? */
2481 if (epstatus & EP_SEL_ST) {
2482 udc_clrstall_hwep(udc, EP_OUT);
2483 nuke(ep0, -ECONNABORTED);
2484 udc->ep0state = WAIT_FOR_SETUP;
2485 return;
2486 }
2487
2488 /* A NAK may occur if a packet couldn't be received yet */
2489 if (epstatus & EP_SEL_EPN)
2490 return;
2491 /* Setup packet incoming? */
2492 if (epstatus & EP_SEL_STP) {
2493 nuke(ep0, 0);
2494 udc->ep0state = WAIT_FOR_SETUP;
2495 }
2496
2497 /* Data available? */
2498 if (epstatus & EP_SEL_F)
2499 /* Handle based on current state */
2500 switch (udc->ep0state) {
2501 case WAIT_FOR_SETUP:
2502 udc_handle_ep0_setup(udc);
2503 break;
2504
2505 case DATA_OUT:
2506 udc_ep0_out_req(udc);
2507 break;
2508
2509 default:
2510 /* Unknown state for EP0 */
2511 nuke(ep0, -ECONNABORTED);
2512 udc->ep0state = WAIT_FOR_SETUP;
2513 }
2514}
2515
2516/* Must be called without lock */
2517static int lpc32xx_get_frame(struct usb_gadget *gadget)
2518{
2519 int frame;
2520 unsigned long flags;
2521 struct lpc32xx_udc *udc = to_udc(gadget);
2522
2523 if (!udc->clocked)
2524 return -EINVAL;
2525
2526 spin_lock_irqsave(&udc->lock, flags);
2527
2528 frame = (int) udc_get_current_frame(udc);
2529
2530 spin_unlock_irqrestore(&udc->lock, flags);
2531
2532 return frame;
2533}
2534
2535static int lpc32xx_wakeup(struct usb_gadget *gadget)
2536{
2537 return -ENOTSUPP;
2538}
2539
2540static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2541{
2542 struct lpc32xx_udc *udc = to_udc(gadget);
2543
2544 /* Always self-powered */
2545 udc->selfpowered = (is_on != 0);
2546
2547 return 0;
2548}
2549
2550/*
2551 * vbus is here! turn everything on that's ready
2552 * Must be called without lock
2553 */
2554static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2555{
2556 unsigned long flags;
2557 struct lpc32xx_udc *udc = to_udc(gadget);
2558
2559 spin_lock_irqsave(&udc->lock, flags);
2560
2561 /* Doesn't need lock */
2562 if (udc->driver) {
2563 udc_clk_set(udc, 1);
2564 udc_enable(udc);
2565 pullup(udc, is_active);
2566 } else {
2567 stop_activity(udc);
2568 pullup(udc, 0);
2569
2570 spin_unlock_irqrestore(&udc->lock, flags);
2571 /*
2572 * Wait for all the endpoints to disable,
2573 * before disabling clocks. Don't wait if
2574 * endpoints are not enabled.
2575 */
2576 if (atomic_read(&udc->enabled_ep_cnt))
2577 wait_event_interruptible(udc->ep_disable_wait_queue,
2578 (atomic_read(&udc->enabled_ep_cnt) == 0));
2579
2580 spin_lock_irqsave(&udc->lock, flags);
2581
2582 udc_clk_set(udc, 0);
2583 }
2584
2585 spin_unlock_irqrestore(&udc->lock, flags);
2586
2587 return 0;
2588}
2589
2590/* Can be called with or without lock */
2591static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2592{
2593 struct lpc32xx_udc *udc = to_udc(gadget);
2594
2595 /* Doesn't need lock */
2596 pullup(udc, is_on);
2597
2598 return 0;
2599}
2600
2601static int lpc32xx_start(struct usb_gadget_driver *driver,
2602 int (*bind)(struct usb_gadget *));
2603static int lpc32xx_stop(struct usb_gadget_driver *driver);
2604
2605static const struct usb_gadget_ops lpc32xx_udc_ops = {
2606 .get_frame = lpc32xx_get_frame,
2607 .wakeup = lpc32xx_wakeup,
2608 .set_selfpowered = lpc32xx_set_selfpowered,
2609 .vbus_session = lpc32xx_vbus_session,
2610 .pullup = lpc32xx_pullup,
2611 .start = lpc32xx_start,
2612 .stop = lpc32xx_stop,
2613};
2614
2615static void nop_release(struct device *dev)
2616{
2617 /* nothing to free */
2618}
2619
2620static struct lpc32xx_udc controller = {
2621 .gadget = {
2622 .ops = &lpc32xx_udc_ops,
2623 .ep0 = &controller.ep[0].ep,
2624 .name = driver_name,
2625 .dev = {
2626 .init_name = "gadget",
2627 .release = nop_release,
2628 }
2629 },
2630 .ep[0] = {
2631 .ep = {
2632 .name = "ep0",
2633 .ops = &lpc32xx_ep_ops,
2634 },
2635 .udc = &controller,
2636 .maxpacket = 64,
2637 .hwep_num_base = 0,
2638 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2639 .lep = 0,
2640 .eptype = EP_CTL_TYPE,
2641 },
2642 .ep[1] = {
2643 .ep = {
2644 .name = "ep1-int",
2645 .ops = &lpc32xx_ep_ops,
2646 },
2647 .udc = &controller,
2648 .maxpacket = 64,
2649 .hwep_num_base = 2,
2650 .hwep_num = 0, /* 2 or 3, will be set later */
2651 .lep = 1,
2652 .eptype = EP_INT_TYPE,
2653 },
2654 .ep[2] = {
2655 .ep = {
2656 .name = "ep2-bulk",
2657 .ops = &lpc32xx_ep_ops,
2658 },
2659 .udc = &controller,
2660 .maxpacket = 64,
2661 .hwep_num_base = 4,
2662 .hwep_num = 0, /* 4 or 5, will be set later */
2663 .lep = 2,
2664 .eptype = EP_BLK_TYPE,
2665 },
2666 .ep[3] = {
2667 .ep = {
2668 .name = "ep3-iso",
2669 .ops = &lpc32xx_ep_ops,
2670 },
2671 .udc = &controller,
2672 .maxpacket = 1023,
2673 .hwep_num_base = 6,
2674 .hwep_num = 0, /* 6 or 7, will be set later */
2675 .lep = 3,
2676 .eptype = EP_ISO_TYPE,
2677 },
2678 .ep[4] = {
2679 .ep = {
2680 .name = "ep4-int",
2681 .ops = &lpc32xx_ep_ops,
2682 },
2683 .udc = &controller,
2684 .maxpacket = 64,
2685 .hwep_num_base = 8,
2686 .hwep_num = 0, /* 8 or 9, will be set later */
2687 .lep = 4,
2688 .eptype = EP_INT_TYPE,
2689 },
2690 .ep[5] = {
2691 .ep = {
2692 .name = "ep5-bulk",
2693 .ops = &lpc32xx_ep_ops,
2694 },
2695 .udc = &controller,
2696 .maxpacket = 64,
2697 .hwep_num_base = 10,
2698 .hwep_num = 0, /* 10 or 11, will be set later */
2699 .lep = 5,
2700 .eptype = EP_BLK_TYPE,
2701 },
2702 .ep[6] = {
2703 .ep = {
2704 .name = "ep6-iso",
2705 .ops = &lpc32xx_ep_ops,
2706 },
2707 .udc = &controller,
2708 .maxpacket = 1023,
2709 .hwep_num_base = 12,
2710 .hwep_num = 0, /* 12 or 13, will be set later */
2711 .lep = 6,
2712 .eptype = EP_ISO_TYPE,
2713 },
2714 .ep[7] = {
2715 .ep = {
2716 .name = "ep7-int",
2717 .ops = &lpc32xx_ep_ops,
2718 },
2719 .udc = &controller,
2720 .maxpacket = 64,
2721 .hwep_num_base = 14,
2722 .hwep_num = 0,
2723 .lep = 7,
2724 .eptype = EP_INT_TYPE,
2725 },
2726 .ep[8] = {
2727 .ep = {
2728 .name = "ep8-bulk",
2729 .ops = &lpc32xx_ep_ops,
2730 },
2731 .udc = &controller,
2732 .maxpacket = 64,
2733 .hwep_num_base = 16,
2734 .hwep_num = 0,
2735 .lep = 8,
2736 .eptype = EP_BLK_TYPE,
2737 },
2738 .ep[9] = {
2739 .ep = {
2740 .name = "ep9-iso",
2741 .ops = &lpc32xx_ep_ops,
2742 },
2743 .udc = &controller,
2744 .maxpacket = 1023,
2745 .hwep_num_base = 18,
2746 .hwep_num = 0,
2747 .lep = 9,
2748 .eptype = EP_ISO_TYPE,
2749 },
2750 .ep[10] = {
2751 .ep = {
2752 .name = "ep10-int",
2753 .ops = &lpc32xx_ep_ops,
2754 },
2755 .udc = &controller,
2756 .maxpacket = 64,
2757 .hwep_num_base = 20,
2758 .hwep_num = 0,
2759 .lep = 10,
2760 .eptype = EP_INT_TYPE,
2761 },
2762 .ep[11] = {
2763 .ep = {
2764 .name = "ep11-bulk",
2765 .ops = &lpc32xx_ep_ops,
2766 },
2767 .udc = &controller,
2768 .maxpacket = 64,
2769 .hwep_num_base = 22,
2770 .hwep_num = 0,
2771 .lep = 11,
2772 .eptype = EP_BLK_TYPE,
2773 },
2774 .ep[12] = {
2775 .ep = {
2776 .name = "ep12-iso",
2777 .ops = &lpc32xx_ep_ops,
2778 },
2779 .udc = &controller,
2780 .maxpacket = 1023,
2781 .hwep_num_base = 24,
2782 .hwep_num = 0,
2783 .lep = 12,
2784 .eptype = EP_ISO_TYPE,
2785 },
2786 .ep[13] = {
2787 .ep = {
2788 .name = "ep13-int",
2789 .ops = &lpc32xx_ep_ops,
2790 },
2791 .udc = &controller,
2792 .maxpacket = 64,
2793 .hwep_num_base = 26,
2794 .hwep_num = 0,
2795 .lep = 13,
2796 .eptype = EP_INT_TYPE,
2797 },
2798 .ep[14] = {
2799 .ep = {
2800 .name = "ep14-bulk",
2801 .ops = &lpc32xx_ep_ops,
2802 },
2803 .udc = &controller,
2804 .maxpacket = 64,
2805 .hwep_num_base = 28,
2806 .hwep_num = 0,
2807 .lep = 14,
2808 .eptype = EP_BLK_TYPE,
2809 },
2810 .ep[15] = {
2811 .ep = {
2812 .name = "ep15-bulk",
2813 .ops = &lpc32xx_ep_ops,
2814 },
2815 .udc = &controller,
2816 .maxpacket = 1023,
2817 .hwep_num_base = 30,
2818 .hwep_num = 0,
2819 .lep = 15,
2820 .eptype = EP_BLK_TYPE,
2821 },
2822};
2823
2824/* ISO and status interrupts */
2825static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2826{
2827 u32 tmp, devstat;
2828 struct lpc32xx_udc *udc = _udc;
2829
2830 spin_lock(&udc->lock);
2831
2832 /* Read the device status register */
2833 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2834
2835 devstat &= ~USBD_EP_FAST;
2836 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2837 devstat = devstat & udc->enabled_devints;
2838
2839 /* Device specific handling needed? */
2840 if (devstat & USBD_DEV_STAT)
2841 udc_handle_dev(udc);
2842
2843 /* Start of frame? (devstat & FRAME_INT):
2844 * The frame interrupt isn't really needed for ISO support,
2845 * as the driver will queue the necessary packets */
2846
2847 /* Error? */
2848 if (devstat & ERR_INT) {
2849 /* All types of errors, from cable removal during transfer to
2850 * misc protocol and bit errors. These are mostly for just info,
2851 * as the USB hardware will work around these. If these errors
2852 * happen alot, something is wrong. */
2853 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2854 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2855 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2856 }
2857
2858 spin_unlock(&udc->lock);
2859
2860 return IRQ_HANDLED;
2861}
2862
2863/* EP interrupts */
2864static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2865{
2866 u32 tmp;
2867 struct lpc32xx_udc *udc = _udc;
2868
2869 spin_lock(&udc->lock);
2870
2871 /* Read the device status register */
2872 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2873
2874 /* Endpoints */
2875 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2876
2877 /* Special handling for EP0 */
2878 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2879 /* Handle EP0 IN */
2880 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2881 udc_handle_ep0_in(udc);
2882
2883 /* Handle EP0 OUT */
2884 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2885 udc_handle_ep0_out(udc);
2886 }
2887
2888 /* All other EPs */
2889 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2890 int i;
2891
2892 /* Handle other EP interrupts */
2893 for (i = 1; i < NUM_ENDPOINTS; i++) {
2894 if (tmp & (1 << udc->ep[i].hwep_num))
2895 udc_handle_eps(udc, &udc->ep[i]);
2896 }
2897 }
2898
2899 spin_unlock(&udc->lock);
2900
2901 return IRQ_HANDLED;
2902}
2903
2904static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2905{
2906 struct lpc32xx_udc *udc = _udc;
2907
2908 int i;
2909 u32 tmp;
2910
2911 spin_lock(&udc->lock);
2912
2913 /* Handle EP DMA EOT interrupts */
2914 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2915 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2916 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2917 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2918 for (i = 1; i < NUM_ENDPOINTS; i++) {
2919 if (tmp & (1 << udc->ep[i].hwep_num))
2920 udc_handle_dma_ep(udc, &udc->ep[i]);
2921 }
2922
2923 spin_unlock(&udc->lock);
2924
2925 return IRQ_HANDLED;
2926}
2927
2928/*
2929 *
2930 * VBUS detection, pullup handler, and Gadget cable state notification
2931 *
2932 */
2933static void vbus_work(struct work_struct *work)
2934{
2935 u8 value;
2936 struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
2937 vbus_job);
2938
2939 if (udc->enabled != 0) {
2940 /* Discharge VBUS real quick */
2941 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2942 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2943
2944 /* Give VBUS some time (100mS) to discharge */
2945 msleep(100);
2946
2947 /* Disable VBUS discharge resistor */
2948 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2949 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2950 OTG1_VBUS_DISCHRG);
2951
2952 /* Clear interrupt */
2953 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2954 ISP1301_I2C_INTERRUPT_LATCH |
2955 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2956
2957 /* Get the VBUS status from the transceiver */
2958 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2959 ISP1301_I2C_OTG_CONTROL_2);
2960
2961 /* VBUS on or off? */
2962 if (value & OTG_B_SESS_VLD)
2963 udc->vbus = 1;
2964 else
2965 udc->vbus = 0;
2966
2967 /* VBUS changed? */
2968 if (udc->last_vbus != udc->vbus) {
2969 udc->last_vbus = udc->vbus;
2970 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2971 }
2972 }
2973
2974 /* Re-enable after completion */
2975 enable_irq(udc->udp_irq[IRQ_USB_ATX]);
2976}
2977
2978static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2979{
2980 struct lpc32xx_udc *udc = _udc;
2981
2982 /* Defer handling of VBUS IRQ to work queue */
2983 disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
2984 schedule_work(&udc->vbus_job);
2985
2986 return IRQ_HANDLED;
2987}
2988
2989static int lpc32xx_start(struct usb_gadget_driver *driver,
2990 int (*bind)(struct usb_gadget *))
2991{
2992 struct lpc32xx_udc *udc = &controller;
2993 int retval, i;
2994
2995 if (!driver || driver->max_speed < USB_SPEED_FULL ||
2996 !bind || !driver->setup) {
2997 dev_err(udc->dev, "bad parameter.\n");
2998 return -EINVAL;
2999 }
3000
3001 if (udc->driver) {
3002 dev_err(udc->dev, "UDC already has a gadget driver\n");
3003 return -EBUSY;
3004 }
3005
3006 udc->driver = driver;
3007 udc->gadget.dev.driver = &driver->driver;
eebc0d36 3008 udc->gadget.dev.of_node = udc->dev->of_node;
24a28e42
RS		 3009 udc->enabled = 1;
3010 udc->selfpowered = 1;
3011 udc->vbus = 0;
3012
3013 retval = bind(&udc->gadget);
3014 if (retval) {
3015 dev_err(udc->dev, "bind() returned %d\n", retval);
3016 udc->enabled = 0;
3017 udc->selfpowered = 0;
3018 udc->driver = NULL;
3019 udc->gadget.dev.driver = NULL;
3020 return retval;
3021 }
3022
3023 dev_dbg(udc->dev, "bound to %s\n", driver->driver.name);
3024
3025 /* Force VBUS process once to check for cable insertion */
3026 udc->last_vbus = udc->vbus = 0;
3027 schedule_work(&udc->vbus_job);
3028
3029 /* Do not re-enable ATX IRQ (3) */
3030 for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
3031 enable_irq(udc->udp_irq[i]);
3032
3033 return 0;
3034}
3035
3036static int lpc32xx_stop(struct usb_gadget_driver *driver)
3037{
3038 int i;
3039 struct lpc32xx_udc *udc = &controller;
3040
3041 if (!driver || driver != udc->driver || !driver->unbind)
3042 return -EINVAL;
3043
3044 /* Disable USB pullup */
3045 isp1301_pullup_enable(udc, 0, 1);
3046
3047 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3048 disable_irq(udc->udp_irq[i]);
3049
3050 if (udc->clocked) {
3051
3052 spin_lock(&udc->lock);
3053 stop_activity(udc);
3054 spin_unlock(&udc->lock);
3055
3056 /*
3057 * Wait for all the endpoints to disable,
3058 * before disabling clocks. Don't wait if
3059 * endpoints are not enabled.
3060 */
3061 if (atomic_read(&udc->enabled_ep_cnt))
3062 wait_event_interruptible(udc->ep_disable_wait_queue,
3063 (atomic_read(&udc->enabled_ep_cnt) == 0));
3064
3065 spin_lock(&udc->lock);
3066 udc_clk_set(udc, 0);
3067 spin_unlock(&udc->lock);
3068 }
3069
3070 udc->enabled = 0;
3071 pullup(udc, 0);
3072
3073 driver->unbind(&udc->gadget);
3074 udc->gadget.dev.driver = NULL;
3075 udc->driver = NULL;
3076
3077 dev_dbg(udc->dev, "unbound from %s\n", driver->driver.name);
3078 return 0;
3079}
3080
3081static void lpc32xx_udc_shutdown(struct platform_device *dev)
3082{
3083 /* Force disconnect on reboot */
3084 struct lpc32xx_udc *udc = &controller;
3085
3086 pullup(udc, 0);
3087}
3088
3089/*
3090 * Callbacks to be overridden by options passed via OF (TODO)
3091 */
3092
3093static void lpc32xx_usbd_conn_chg(int conn)
3094{
3095 /* Do nothing, it might be nice to enable an LED
3096 * based on conn state being !0 */
3097}
3098
3099static void lpc32xx_usbd_susp_chg(int susp)
3100{
3101 /* Device suspend if susp != 0 */
3102}
3103
3104static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
3105{
3106 /* Enable or disable USB remote wakeup */
3107}
3108
3109struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
3110 .vbus_drv_pol = 0,
3111 .conn_chgb = &lpc32xx_usbd_conn_chg,
3112 .susp_chgb = &lpc32xx_usbd_susp_chg,
3113 .rmwk_chgb = &lpc32xx_rmwkup_chg,
3114};
3115
3116
3117static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
3118
3119static int __init lpc32xx_udc_probe(struct platform_device *pdev)
3120{
3121 struct device *dev = &pdev->dev;
3122 struct lpc32xx_udc *udc = &controller;
3123 int retval, i;
3124 struct resource *res;
3125 dma_addr_t dma_handle;
3126 struct device_node *isp1301_node;
3127
3128 /* init software state */
3129 udc->gadget.dev.parent = dev;
3130 udc->pdev = pdev;
3131 udc->dev = &pdev->dev;
3132 udc->enabled = 0;
3133
3134 if (pdev->dev.of_node) {
3135 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3136 "transceiver", 0);
3137 } else {
3138 isp1301_node = NULL;
3139 }
3140
3141 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3142 if (!udc->isp1301_i2c_client)
3143 return -EPROBE_DEFER;
3144
3145 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3146 udc->isp1301_i2c_client->addr);
3147
3148 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3149 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3150
3151 udc->board = &lpc32xx_usbddata;
3152
3153 /*
3154 * Resources are mapped as follows:
3155 * IORESOURCE_MEM, base address and size of USB space
3156 * IORESOURCE_IRQ, USB device low priority interrupt number
3157 * IORESOURCE_IRQ, USB device high priority interrupt number
3158 * IORESOURCE_IRQ, USB device interrupt number
3159 * IORESOURCE_IRQ, USB transceiver interrupt number
3160 */
3161 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3162 if (!res)
3163 return -ENXIO;
3164
3165 spin_lock_init(&udc->lock);
3166
3167 /* Get IRQs */
3168 for (i = 0; i < 4; i++) {
3169 udc->udp_irq[i] = platform_get_irq(pdev, i);
3170 if (udc->udp_irq[i] < 0) {
3171 dev_err(udc->dev,
3172 "irq resource %d not available!\n", i);
3173 return udc->udp_irq[i];
3174 }
3175 }
3176
3177 udc->io_p_start = res->start;
3178 udc->io_p_size = resource_size(res);
3179 if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
3180 dev_err(udc->dev, "someone's using UDC memory\n");
3181 return -EBUSY;
3182 }
3183
3184 udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
3185 if (!udc->udp_baseaddr) {
3186 retval = -ENOMEM;
3187 dev_err(udc->dev, "IO map failure\n");
3188 goto io_map_fail;
3189 }
3190
3191 /* Enable AHB slave USB clock, needed for further USB clock control */
3192 writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
3193
3194 /* Get required clocks */
3195 udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
3196 if (IS_ERR(udc->usb_pll_clk)) {
3197 dev_err(udc->dev, "failed to acquire USB PLL\n");
3198 retval = PTR_ERR(udc->usb_pll_clk);
3199 goto pll_get_fail;
3200 }
3201 udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd");
3202 if (IS_ERR(udc->usb_slv_clk)) {
3203 dev_err(udc->dev, "failed to acquire USB device clock\n");
3204 retval = PTR_ERR(udc->usb_slv_clk);
3205 goto usb_clk_get_fail;
3206 }
50856699
APS		 3207 udc->usb_otg_clk = clk_get(&pdev->dev, "ck_usb_otg");
3208 if (IS_ERR(udc->usb_otg_clk)) {
3209 dev_err(udc->dev, "failed to acquire USB otg clock\n");
3210 retval = PTR_ERR(udc->usb_slv_clk);
3211 goto usb_otg_clk_get_fail;
3212 }
24a28e42
RS		 3213
3214 /* Setup PLL clock to 48MHz */
3215 retval = clk_enable(udc->usb_pll_clk);
3216 if (retval < 0) {
3217 dev_err(udc->dev, "failed to start USB PLL\n");
3218 goto pll_enable_fail;
3219 }
3220
3221 retval = clk_set_rate(udc->usb_pll_clk, 48000);
3222 if (retval < 0) {
3223 dev_err(udc->dev, "failed to set USB clock rate\n");
3224 goto pll_set_fail;
3225 }
3226
3227 writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
3228
3229 /* Enable USB device clock */
3230 retval = clk_enable(udc->usb_slv_clk);
3231 if (retval < 0) {
3232 dev_err(udc->dev, "failed to start USB device clock\n");
3233 goto usb_clk_enable_fail;
3234 }
3235
50856699
APS		 3236 /* Enable USB OTG clock */
3237 retval = clk_enable(udc->usb_otg_clk);
3238 if (retval < 0) {
3239 dev_err(udc->dev, "failed to start USB otg clock\n");
3240 goto usb_otg_clk_enable_fail;
3241 }
24a28e42
RS		 3242
3243 /* Setup deferred workqueue data */
3244 udc->poweron = udc->pullup = 0;
3245 INIT_WORK(&udc->pullup_job, pullup_work);
3246 INIT_WORK(&udc->vbus_job, vbus_work);
3247#ifdef CONFIG_PM
3248 INIT_WORK(&udc->power_job, power_work);
3249#endif
3250
3251 /* All clocks are now on */
3252 udc->clocked = 1;
3253
3254 isp1301_udc_configure(udc);
3255 /* Allocate memory for the UDCA */
3256 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3257 &dma_handle,
3258 (GFP_KERNEL | GFP_DMA));
3259 if (!udc->udca_v_base) {
3260 dev_err(udc->dev, "error getting UDCA region\n");
3261 retval = -ENOMEM;
3262 goto i2c_fail;
3263 }
3264 udc->udca_p_base = dma_handle;
3265 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3266 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3267
3268 /* Setup the DD DMA memory pool */
3269 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3270 sizeof(struct lpc32xx_usbd_dd_gad),
3271 sizeof(u32), 0);
3272 if (!udc->dd_cache) {
3273 dev_err(udc->dev, "error getting DD DMA region\n");
3274 retval = -ENOMEM;
3275 goto dma_alloc_fail;
3276 }
3277
3278 /* Clear USB peripheral and initialize gadget endpoints */
3279 udc_disable(udc);
3280 udc_reinit(udc);
3281
3282 retval = device_register(&udc->gadget.dev);
3283 if (retval < 0) {
3284 dev_err(udc->dev, "Device registration failure\n");
3285 goto dev_register_fail;
3286 }
3287
3288 /* Request IRQs - low and high priority USB device IRQs are routed to
3289 * the same handler, while the DMA interrupt is routed elsewhere */
3290 retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
3291 0, "udc_lp", udc);
3292 if (retval < 0) {
3293 dev_err(udc->dev, "LP request irq %d failed\n",
3294 udc->udp_irq[IRQ_USB_LP]);
3295 goto irq_lp_fail;
3296 }
3297 retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
3298 0, "udc_hp", udc);
3299 if (retval < 0) {
3300 dev_err(udc->dev, "HP request irq %d failed\n",
3301 udc->udp_irq[IRQ_USB_HP]);
3302 goto irq_hp_fail;
3303 }
3304
3305 retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
3306 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3307 if (retval < 0) {
3308 dev_err(udc->dev, "DEV request irq %d failed\n",
3309 udc->udp_irq[IRQ_USB_DEVDMA]);
3310 goto irq_dev_fail;
3311 }
3312
3313 /* The transceiver interrupt is used for VBUS detection and will
3314 kick off the VBUS handler function */
3315 retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
3316 0, "udc_otg", udc);
3317 if (retval < 0) {
3318 dev_err(udc->dev, "VBUS request irq %d failed\n",
3319 udc->udp_irq[IRQ_USB_ATX]);
3320 goto irq_xcvr_fail;
3321 }
3322
3323 /* Initialize wait queue */
3324 init_waitqueue_head(&udc->ep_disable_wait_queue);
3325 atomic_set(&udc->enabled_ep_cnt, 0);
3326
3327 /* Keep all IRQs disabled until GadgetFS starts up */
3328 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3329 disable_irq(udc->udp_irq[i]);
3330
3331 retval = usb_add_gadget_udc(dev, &udc->gadget);
3332 if (retval < 0)
3333 goto add_gadget_fail;
3334
3335 dev_set_drvdata(dev, udc);
3336 device_init_wakeup(dev, 1);
3337 create_debug_file(udc);
3338
3339 /* Disable clocks for now */
3340 udc_clk_set(udc, 0);
3341
3342 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3343 return 0;
3344
3345add_gadget_fail:
3346 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3347irq_xcvr_fail:
3348 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3349irq_dev_fail:
3350 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3351irq_hp_fail:
3352 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3353irq_lp_fail:
3354 device_unregister(&udc->gadget.dev);
3355dev_register_fail:
3356 dma_pool_destroy(udc->dd_cache);
3357dma_alloc_fail:
3358 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3359 udc->udca_v_base, udc->udca_p_base);
3360i2c_fail:
50856699
APS		 3361 clk_disable(udc->usb_otg_clk);
3362usb_otg_clk_enable_fail:
24a28e42
RS		 3363 clk_disable(udc->usb_slv_clk);
3364usb_clk_enable_fail:
3365pll_set_fail:
3366 clk_disable(udc->usb_pll_clk);
3367pll_enable_fail:
3368 clk_put(udc->usb_slv_clk);
50856699
APS		 3369usb_otg_clk_get_fail:
3370 clk_put(udc->usb_otg_clk);
24a28e42
RS		 3371usb_clk_get_fail:
3372 clk_put(udc->usb_pll_clk);
3373pll_get_fail:
3374 iounmap(udc->udp_baseaddr);
3375io_map_fail:
3376 release_mem_region(udc->io_p_start, udc->io_p_size);
3377 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3378
3379 return retval;
3380}
3381
3382static int __devexit lpc32xx_udc_remove(struct platform_device *pdev)
3383{
3384 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3385
3386 usb_del_gadget_udc(&udc->gadget);
3387 if (udc->driver)
3388 return -EBUSY;
3389
3390 udc_clk_set(udc, 1);
3391 udc_disable(udc);
3392 pullup(udc, 0);
3393
3394 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3395
3396 device_init_wakeup(&pdev->dev, 0);
3397 remove_debug_file(udc);
3398
3399 dma_pool_destroy(udc->dd_cache);
3400 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3401 udc->udca_v_base, udc->udca_p_base);
3402 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3403 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3404 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3405
3406 device_unregister(&udc->gadget.dev);
3407
50856699
APS		 3408 clk_disable(udc->usb_otg_clk);
3409 clk_put(udc->usb_otg_clk);
24a28e42
RS		 3410 clk_disable(udc->usb_slv_clk);
3411 clk_put(udc->usb_slv_clk);
3412 clk_disable(udc->usb_pll_clk);
3413 clk_put(udc->usb_pll_clk);
3414 iounmap(udc->udp_baseaddr);
3415 release_mem_region(udc->io_p_start, udc->io_p_size);
3416
3417 return 0;
3418}
3419
3420#ifdef CONFIG_PM
3421static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3422{
24a28e42
RS		 3423 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3424
3425 if (udc->clocked) {
3426 /* Power down ISP */
3427 udc->poweron = 0;
3428 isp1301_set_powerstate(udc, 0);
3429
3430 /* Disable clocking */
3431 udc_clk_set(udc, 0);
3432
3433 /* Keep clock flag on, so we know to re-enable clocks
3434 on resume */
3435 udc->clocked = 1;
3436
24a28e42
RS		 3437 /* Kill global USB clock */
3438 clk_disable(udc->usb_slv_clk);
3439 }
3440
3441 return 0;
3442}
3443
3444static int lpc32xx_udc_resume(struct platform_device *pdev)
3445{
3446 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3447
3448 if (udc->clocked) {
3449 /* Enable global USB clock */
3450 clk_enable(udc->usb_slv_clk);
3451
3452 /* Enable clocking */
3453 udc_clk_set(udc, 1);
3454
3455 /* ISP back to normal power mode */
3456 udc->poweron = 1;
3457 isp1301_set_powerstate(udc, 1);
3458 }
3459
3460 return 0;
3461}
3462#else
3463#define lpc32xx_udc_suspend NULL
3464#define lpc32xx_udc_resume NULL
3465#endif
3466
3467#ifdef CONFIG_OF
3468static struct of_device_id lpc32xx_udc_of_match[] = {
3469 { .compatible = "nxp,lpc3220-udc", },
3470 { },
3471};
3472MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3473#endif
3474
3475static struct platform_driver lpc32xx_udc_driver = {
3476 .remove = __devexit_p(lpc32xx_udc_remove),
3477 .shutdown = lpc32xx_udc_shutdown,
3478 .suspend = lpc32xx_udc_suspend,
3479 .resume = lpc32xx_udc_resume,
3480 .driver = {
3481 .name = (char *) driver_name,
3482 .owner = THIS_MODULE,
3483 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3484 },
3485};
3486
3487static int __init udc_init_module(void)
3488{
3489 return platform_driver_probe(&lpc32xx_udc_driver, lpc32xx_udc_probe);
3490}
3491module_init(udc_init_module);
3492
3493static void __exit udc_exit_module(void)
3494{
3495 platform_driver_unregister(&lpc32xx_udc_driver);
3496}
3497module_exit(udc_exit_module);
3498
3499MODULE_DESCRIPTION("LPC32XX udc driver");
3500MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3501MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3502MODULE_LICENSE("GPL");
3503MODULE_ALIAS("platform:lpc32xx_udc");
Linux kernel - Deliverables
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