projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4cf2503c YS |
1 | /* |
| 2 | * M66592 UDC (USB gadget) | |
| 3 | * | |
| 4 | * Copyright (C) 2006-2007 Renesas Solutions Corp. | |
| 5 | * | |
| 6 | * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License as published by | |
| 10 | * the Free Software Foundation; version 2 of the License. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
| 20 | * | |
| 21 | */ | |
| 22 | ||
| 23 | #ifndef __M66592_UDC_H__ | |
| 24 | #define __M66592_UDC_H__ | |
| 25 | ||
| 26 | #define M66592_SYSCFG 0x00 | |
| 598f22e1 YS |
27 | #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ |
| 28 | #define M66592_XTAL48 0x8000 /* 48MHz */ | |
| 29 | #define M66592_XTAL24 0x4000 /* 24MHz */ | |
| 30 | #define M66592_XTAL12 0x0000 /* 12MHz */ | |
| 31 | #define M66592_XCKE 0x2000 /* b13: External clock enable */ | |
| 32 | #define M66592_RCKE 0x1000 /* b12: Register clock enable */ | |
| 33 | #define M66592_PLLC 0x0800 /* b11: PLL control */ | |
| 34 | #define M66592_SCKE 0x0400 /* b10: USB clock enable */ | |
| 35 | #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */ | |
| 36 | #define M66592_HSE 0x0080 /* b7: Hi-speed enable */ | |
| 37 | #define M66592_DCFM 0x0040 /* b6: Controller function select */ | |
| 38 | #define M66592_DMRPD 0x0020 /* b5: D- pull down control */ | |
| 39 | #define M66592_DPRPU 0x0010 /* b4: D+ pull up control */ | |
| 40 | #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */ | |
| 41 | #define M66592_PCUT 0x0002 /* b1: Low power sleep enable */ | |
| 42 | #define M66592_USBE 0x0001 /* b0: USB module operation enable */ | |
| 4cf2503c YS |
43 | |
| 44 | #define M66592_SYSSTS 0x02 | |
| 598f22e1 YS |
45 | #define M66592_LNST 0x0003 /* b1-0: D+, D- line status */ |
| 46 | #define M66592_SE1 0x0003 /* SE1 */ | |
| 47 | #define M66592_KSTS 0x0002 /* K State */ | |
| 48 | #define M66592_JSTS 0x0001 /* J State */ | |
| 49 | #define M66592_SE0 0x0000 /* SE0 */ | |
| 4cf2503c YS |
50 | |
| 51 | #define M66592_DVSTCTR 0x04 | |
| 598f22e1 YS |
52 | #define M66592_WKUP 0x0100 /* b8: Remote wakeup */ |
| 53 | #define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */ | |
| 54 | #define M66592_USBRST 0x0040 /* b6: USB reset enable */ | |
| 55 | #define M66592_RESUME 0x0020 /* b5: Resume enable */ | |
| 56 | #define M66592_UACT 0x0010 /* b4: USB bus enable */ | |
| 57 | #define M66592_RHST 0x0003 /* b1-0: Reset handshake status */ | |
| 58 | #define M66592_HSMODE 0x0003 /* Hi-Speed mode */ | |
| 59 | #define M66592_FSMODE 0x0002 /* Full-Speed mode */ | |
| 60 | #define M66592_HSPROC 0x0001 /* HS handshake is processing */ | |
| 4cf2503c YS |
61 | |
| 62 | #define M66592_TESTMODE 0x06 | |
| 598f22e1 YS |
63 | #define M66592_UTST 0x000F /* b4-0: Test select */ |
| 64 | #define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */ | |
| 65 | #define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ | |
| 66 | #define M66592_H_TST_K 0x000A /* HOST TEST K */ | |
| 67 | #define M66592_H_TST_J 0x0009 /* HOST TEST J */ | |
| 68 | #define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */ | |
| 69 | #define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */ | |
| 70 | #define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ | |
| 71 | #define M66592_P_TST_K 0x0002 /* PERI TEST K */ | |
| 72 | #define M66592_P_TST_J 0x0001 /* PERI TEST J */ | |
| 73 | #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ | |
| 4cf2503c | 74 | |
| 8c73aff6 YS |
75 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) |
| 76 | #define M66592_CFBCFG 0x0A | |
| 77 | #define M66592_D0FBCFG 0x0C | |
| 78 | #define M66592_LITTLE 0x0100 /* b8: Little endian mode */ | |
| 79 | #else | |
| 4cf2503c | 80 | #define M66592_PINCFG 0x0A |
| 598f22e1 YS |
81 | #define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ |
| 82 | #define M66592_BIGEND 0x0100 /* b8: Big endian mode */ | |
| 4cf2503c YS |
83 | |
| 84 | #define M66592_DMA0CFG 0x0C | |
| 85 | #define M66592_DMA1CFG 0x0E | |
| 598f22e1 YS |
86 | #define M66592_DREQA 0x4000 /* b14: Dreq active select */ |
| 87 | #define M66592_BURST 0x2000 /* b13: Burst mode */ | |
| 88 | #define M66592_DACKA 0x0400 /* b10: Dack active select */ | |
| 89 | #define M66592_DFORM 0x0380 /* b9-7: DMA mode select */ | |
| 90 | #define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ | |
| 91 | #define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ | |
| 92 | #define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ | |
| 93 | #define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ | |
| 94 | #define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */ | |
| 95 | #define M66592_DENDA 0x0040 /* b6: Dend active select */ | |
| 96 | #define M66592_PKTM 0x0020 /* b5: Packet mode */ | |
| 97 | #define M66592_DENDE 0x0010 /* b4: Dend enable */ | |
| 98 | #define M66592_OBUS 0x0004 /* b2: OUTbus mode */ | |
| 8c73aff6 | 99 | #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */ |
| 4cf2503c YS |
100 | |
| 101 | #define M66592_CFIFO 0x10 | |
| 102 | #define M66592_D0FIFO 0x14 | |
| 103 | #define M66592_D1FIFO 0x18 | |
| 104 | ||
| 105 | #define M66592_CFIFOSEL 0x1E | |
| 106 | #define M66592_D0FIFOSEL 0x24 | |
| 107 | #define M66592_D1FIFOSEL 0x2A | |
| 598f22e1 YS |
108 | #define M66592_RCNT 0x8000 /* b15: Read count mode */ |
| 109 | #define M66592_REW 0x4000 /* b14: Buffer rewind */ | |
| 110 | #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ | |
| 111 | #define M66592_DREQE 0x1000 /* b12: DREQ output enable */ | |
| 8c73aff6 YS |
112 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) |
| 113 | #define M66592_MBW 0x0800 /* b11: Maximum bit width for FIFO */ | |
| 114 | #else | |
| 598f22e1 YS |
115 | #define M66592_MBW 0x0400 /* b10: Maximum bit width for FIFO */ |
| 116 | #define M66592_MBW_8 0x0000 /* 8bit */ | |
| 117 | #define M66592_MBW_16 0x0400 /* 16bit */ | |
| 8c73aff6 | 118 | #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */ |
| 598f22e1 YS |
119 | #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ |
| 120 | #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ | |
| 121 | #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */ | |
| 122 | #define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */ | |
| 123 | #define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */ | |
| 4cf2503c YS |
124 | |
| 125 | #define M66592_CFIFOCTR 0x20 | |
| 126 | #define M66592_D0FIFOCTR 0x26 | |
| 127 | #define M66592_D1FIFOCTR 0x2c | |
| 598f22e1 YS |
128 | #define M66592_BVAL 0x8000 /* b15: Buffer valid flag */ |
| 129 | #define M66592_BCLR 0x4000 /* b14: Buffer clear */ | |
| 130 | #define M66592_FRDY 0x2000 /* b13: FIFO ready */ | |
| 131 | #define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */ | |
| 4cf2503c YS |
132 | |
| 133 | #define M66592_CFIFOSIE 0x22 | |
| 598f22e1 YS |
134 | #define M66592_TGL 0x8000 /* b15: Buffer toggle */ |
| 135 | #define M66592_SCLR 0x4000 /* b14: Buffer clear */ | |
| 136 | #define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */ | |
| 4cf2503c YS |
137 | |
| 138 | #define M66592_D0FIFOTRN 0x28 | |
| 139 | #define M66592_D1FIFOTRN 0x2E | |
| 598f22e1 | 140 | #define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */ |
| 4cf2503c YS |
141 | |
| 142 | #define M66592_INTENB0 0x30 | |
| 598f22e1 YS |
143 | #define M66592_VBSE 0x8000 /* b15: VBUS interrupt */ |
| 144 | #define M66592_RSME 0x4000 /* b14: Resume interrupt */ | |
| 145 | #define M66592_SOFE 0x2000 /* b13: Frame update interrupt */ | |
| 146 | #define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */ | |
| 147 | #define M66592_CTRE 0x0800 /* b11: Control transfer stage transition irq */ | |
| 148 | #define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */ | |
| 149 | #define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */ | |
| 150 | #define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */ | |
| 151 | #define M66592_URST 0x0080 /* b7: USB reset detected interrupt */ | |
| 152 | #define M66592_SADR 0x0040 /* b6: Set address executed interrupt */ | |
| 153 | #define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */ | |
| 154 | #define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */ | |
| 155 | #define M66592_WDST 0x0008 /* b3: Control write data stage completed irq */ | |
| 156 | #define M66592_RDST 0x0004 /* b2: Control read data stage completed irq */ | |
| 157 | #define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */ | |
| 158 | #define M66592_SERR 0x0001 /* b0: Sequence error interrupt */ | |
| 4cf2503c YS |
159 | |
| 160 | #define M66592_INTENB1 0x32 | |
| 598f22e1 YS |
161 | #define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */ |
| 162 | #define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */ | |
| 163 | #define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ | |
| 164 | #define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */ | |
| 165 | #define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */ | |
| 166 | #define M66592_INTL 0x0002 /* b1: Interrupt sense select */ | |
| 167 | #define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */ | |
| 4cf2503c YS |
168 | |
| 169 | #define M66592_BRDYENB 0x36 | |
| 170 | #define M66592_BRDYSTS 0x46 | |
| 598f22e1 YS |
171 | #define M66592_BRDY7 0x0080 /* b7: PIPE7 */ |
| 172 | #define M66592_BRDY6 0x0040 /* b6: PIPE6 */ | |
| 173 | #define M66592_BRDY5 0x0020 /* b5: PIPE5 */ | |
| 174 | #define M66592_BRDY4 0x0010 /* b4: PIPE4 */ | |
| 175 | #define M66592_BRDY3 0x0008 /* b3: PIPE3 */ | |
| 176 | #define M66592_BRDY2 0x0004 /* b2: PIPE2 */ | |
| 177 | #define M66592_BRDY1 0x0002 /* b1: PIPE1 */ | |
| 178 | #define M66592_BRDY0 0x0001 /* b1: PIPE0 */ | |
| 4cf2503c YS |
179 | |
| 180 | #define M66592_NRDYENB 0x38 | |
| 181 | #define M66592_NRDYSTS 0x48 | |
| 598f22e1 YS |
182 | #define M66592_NRDY7 0x0080 /* b7: PIPE7 */ |
| 183 | #define M66592_NRDY6 0x0040 /* b6: PIPE6 */ | |
| 184 | #define M66592_NRDY5 0x0020 /* b5: PIPE5 */ | |
| 185 | #define M66592_NRDY4 0x0010 /* b4: PIPE4 */ | |
| 186 | #define M66592_NRDY3 0x0008 /* b3: PIPE3 */ | |
| 187 | #define M66592_NRDY2 0x0004 /* b2: PIPE2 */ | |
| 188 | #define M66592_NRDY1 0x0002 /* b1: PIPE1 */ | |
| 189 | #define M66592_NRDY0 0x0001 /* b1: PIPE0 */ | |
| 4cf2503c YS |
190 | |
| 191 | #define M66592_BEMPENB 0x3A | |
| 192 | #define M66592_BEMPSTS 0x4A | |
| 598f22e1 YS |
193 | #define M66592_BEMP7 0x0080 /* b7: PIPE7 */ |
| 194 | #define M66592_BEMP6 0x0040 /* b6: PIPE6 */ | |
| 195 | #define M66592_BEMP5 0x0020 /* b5: PIPE5 */ | |
| 196 | #define M66592_BEMP4 0x0010 /* b4: PIPE4 */ | |
| 197 | #define M66592_BEMP3 0x0008 /* b3: PIPE3 */ | |
| 198 | #define M66592_BEMP2 0x0004 /* b2: PIPE2 */ | |
| 199 | #define M66592_BEMP1 0x0002 /* b1: PIPE1 */ | |
| 200 | #define M66592_BEMP0 0x0001 /* b0: PIPE0 */ | |
| 4cf2503c YS |
201 | |
| 202 | #define M66592_SOFCFG 0x3C | |
| 598f22e1 YS |
203 | #define M66592_SOFM 0x000C /* b3-2: SOF palse mode */ |
| 204 | #define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */ | |
| 205 | #define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ | |
| 206 | #define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */ | |
| 4cf2503c YS |
207 | |
| 208 | #define M66592_INTSTS0 0x40 | |
| 598f22e1 YS |
209 | #define M66592_VBINT 0x8000 /* b15: VBUS interrupt */ |
| 210 | #define M66592_RESM 0x4000 /* b14: Resume interrupt */ | |
| 211 | #define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */ | |
| 212 | #define M66592_DVST 0x1000 /* b12: Device state transition */ | |
| 213 | #define M66592_CTRT 0x0800 /* b11: Control stage transition */ | |
| 214 | #define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */ | |
| 215 | #define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */ | |
| 216 | #define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */ | |
| 217 | #define M66592_VBSTS 0x0080 /* b7: VBUS input port */ | |
| 218 | #define M66592_DVSQ 0x0070 /* b6-4: Device state */ | |
| 219 | #define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */ | |
| 220 | #define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */ | |
| 221 | #define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */ | |
| 222 | #define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */ | |
| 223 | #define M66592_DS_SUSP 0x0040 /* Suspend */ | |
| 224 | #define M66592_DS_CNFG 0x0030 /* Configured */ | |
| 225 | #define M66592_DS_ADDS 0x0020 /* Address */ | |
| 226 | #define M66592_DS_DFLT 0x0010 /* Default */ | |
| 227 | #define M66592_DS_POWR 0x0000 /* Powered */ | |
| 228 | #define M66592_DVSQS 0x0030 /* b5-4: Device state */ | |
| 229 | #define M66592_VALID 0x0008 /* b3: Setup packet detected flag */ | |
| 230 | #define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */ | |
| 231 | #define M66592_CS_SQER 0x0006 /* Sequence error */ | |
| 232 | #define M66592_CS_WRND 0x0005 /* Control write nodata status */ | |
| 233 | #define M66592_CS_WRSS 0x0004 /* Control write status stage */ | |
| 234 | #define M66592_CS_WRDS 0x0003 /* Control write data stage */ | |
| 235 | #define M66592_CS_RDSS 0x0002 /* Control read status stage */ | |
| 236 | #define M66592_CS_RDDS 0x0001 /* Control read data stage */ | |
| 237 | #define M66592_CS_IDST 0x0000 /* Idle or setup stage */ | |
| 4cf2503c YS |
238 | |
| 239 | #define M66592_INTSTS1 0x42 | |
| 598f22e1 YS |
240 | #define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */ |
| 241 | #define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */ | |
| 242 | #define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */ | |
| 243 | #define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */ | |
| 4cf2503c YS |
244 | |
| 245 | #define M66592_FRMNUM 0x4C | |
| 598f22e1 YS |
246 | #define M66592_OVRN 0x8000 /* b15: Overrun error */ |
| 247 | #define M66592_CRCE 0x4000 /* b14: Received data error */ | |
| 248 | #define M66592_SOFRM 0x0800 /* b11: SOF output mode */ | |
| 249 | #define M66592_FRNM 0x07FF /* b10-0: Frame number */ | |
| 4cf2503c YS |
250 | |
| 251 | #define M66592_UFRMNUM 0x4E | |
| 598f22e1 | 252 | #define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */ |
| 4cf2503c YS |
253 | |
| 254 | #define M66592_RECOVER 0x50 | |
| 598f22e1 YS |
255 | #define M66592_STSRECOV 0x0700 /* Status recovery */ |
| 256 | #define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */ | |
| 257 | #define M66592_STSR_DEFAULT 0x0100 /* Default state */ | |
| 258 | #define M66592_STSR_ADDRESS 0x0200 /* Address state */ | |
| 259 | #define M66592_STSR_CONFIG 0x0300 /* Configured state */ | |
| 260 | #define M66592_USBADDR 0x007F /* b6-0: USB address */ | |
| 4cf2503c YS |
261 | |
| 262 | #define M66592_USBREQ 0x54 | |
| 598f22e1 YS |
263 | #define M66592_bRequest 0xFF00 /* b15-8: bRequest */ |
| 264 | #define M66592_GET_STATUS 0x0000 | |
| 265 | #define M66592_CLEAR_FEATURE 0x0100 | |
| 266 | #define M66592_ReqRESERVED 0x0200 | |
| 267 | #define M66592_SET_FEATURE 0x0300 | |
| 268 | #define M66592_ReqRESERVED1 0x0400 | |
| 269 | #define M66592_SET_ADDRESS 0x0500 | |
| 270 | #define M66592_GET_DESCRIPTOR 0x0600 | |
| 271 | #define M66592_SET_DESCRIPTOR 0x0700 | |
| 272 | #define M66592_GET_CONFIGURATION 0x0800 | |
| 273 | #define M66592_SET_CONFIGURATION 0x0900 | |
| 274 | #define M66592_GET_INTERFACE 0x0A00 | |
| 275 | #define M66592_SET_INTERFACE 0x0B00 | |
| 276 | #define M66592_SYNCH_FRAME 0x0C00 | |
| 277 | #define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */ | |
| 278 | #define M66592_bmRequestTypeDir 0x0080 /* b7 : Data direction */ | |
| 279 | #define M66592_HOST_TO_DEVICE 0x0000 | |
| 280 | #define M66592_DEVICE_TO_HOST 0x0080 | |
| 281 | #define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */ | |
| 282 | #define M66592_STANDARD 0x0000 | |
| 283 | #define M66592_CLASS 0x0020 | |
| 284 | #define M66592_VENDOR 0x0040 | |
| 285 | #define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */ | |
| 286 | #define M66592_DEVICE 0x0000 | |
| 287 | #define M66592_INTERFACE 0x0001 | |
| 288 | #define M66592_ENDPOINT 0x0002 | |
| 4cf2503c YS |
289 | |
| 290 | #define M66592_USBVAL 0x56 | |
| 598f22e1 | 291 | #define M66592_wValue 0xFFFF /* b15-0: wValue */ |
| 4cf2503c | 292 | /* Standard Feature Selector */ |
| 598f22e1 YS |
293 | #define M66592_ENDPOINT_HALT 0x0000 |
| 294 | #define M66592_DEVICE_REMOTE_WAKEUP 0x0001 | |
| 295 | #define M66592_TEST_MODE 0x0002 | |
| 4cf2503c | 296 | /* Descriptor Types */ |
| 598f22e1 YS |
297 | #define M66592_DT_TYPE 0xFF00 |
| 298 | #define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8) | |
| 299 | #define M66592_DT_DEVICE 0x01 | |
| 300 | #define M66592_DT_CONFIGURATION 0x02 | |
| 301 | #define M66592_DT_STRING 0x03 | |
| 302 | #define M66592_DT_INTERFACE 0x04 | |
| 303 | #define M66592_DT_ENDPOINT 0x05 | |
| 304 | #define M66592_DT_DEVICE_QUALIFIER 0x06 | |
| 305 | #define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07 | |
| 306 | #define M66592_DT_INTERFACE_POWER 0x08 | |
| 307 | #define M66592_DT_INDEX 0x00FF | |
| 308 | #define M66592_CONF_NUM 0x00FF | |
| 309 | #define M66592_ALT_SET 0x00FF | |
| 4cf2503c YS |
310 | |
| 311 | #define M66592_USBINDEX 0x58 | |
| 598f22e1 YS |
312 | #define M66592_wIndex 0xFFFF /* b15-0: wIndex */ |
| 313 | #define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */ | |
| 314 | #define M66592_TEST_J 0x0100 /* Test_J */ | |
| 315 | #define M66592_TEST_K 0x0200 /* Test_K */ | |
| 316 | #define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */ | |
| 317 | #define M66592_TEST_PACKET 0x0400 /* Test_Packet */ | |
| 318 | #define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */ | |
| 319 | #define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */ | |
| 320 | #define M66592_TEST_Reserved 0x4000 /* Reserved */ | |
| 321 | #define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */ | |
| 322 | #define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */ | |
| 323 | #define M66592_EP_DIR_IN 0x0080 | |
| 324 | #define M66592_EP_DIR_OUT 0x0000 | |
| 4cf2503c YS |
325 | |
| 326 | #define M66592_USBLENG 0x5A | |
| 598f22e1 | 327 | #define M66592_wLength 0xFFFF /* b15-0: wLength */ |
| 4cf2503c YS |
328 | |
| 329 | #define M66592_DCPCFG 0x5C | |
| 598f22e1 YS |
330 | #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */ |
| 331 | #define M66592_DIR 0x0010 /* b4: Control transfer DIR select */ | |
| 4cf2503c YS |
332 | |
| 333 | #define M66592_DCPMAXP 0x5E | |
| 598f22e1 YS |
334 | #define M66592_DEVSEL 0xC000 /* b15-14: Device address select */ |
| 335 | #define M66592_DEVICE_0 0x0000 /* Device address 0 */ | |
| 336 | #define M66592_DEVICE_1 0x4000 /* Device address 1 */ | |
| 337 | #define M66592_DEVICE_2 0x8000 /* Device address 2 */ | |
| 338 | #define M66592_DEVICE_3 0xC000 /* Device address 3 */ | |
| 339 | #define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */ | |
| 4cf2503c YS |
340 | |
| 341 | #define M66592_DCPCTR 0x60 | |
| 598f22e1 YS |
342 | #define M66592_BSTS 0x8000 /* b15: Buffer status */ |
| 343 | #define M66592_SUREQ 0x4000 /* b14: Send USB request */ | |
| 344 | #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ | |
| 345 | #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ | |
| 346 | #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ | |
| 347 | #define M66592_CCPL 0x0004 /* b2: control transfer complete */ | |
| 348 | #define M66592_PID 0x0003 /* b1-0: Response PID */ | |
| 349 | #define M66592_PID_STALL 0x0002 /* STALL */ | |
| 350 | #define M66592_PID_BUF 0x0001 /* BUF */ | |
| 351 | #define M66592_PID_NAK 0x0000 /* NAK */ | |
| 4cf2503c YS |
352 | |
| 353 | #define M66592_PIPESEL 0x64 | |
| 598f22e1 YS |
354 | #define M66592_PIPENM 0x0007 /* b2-0: Pipe select */ |
| 355 | #define M66592_PIPE0 0x0000 /* PIPE 0 */ | |
| 356 | #define M66592_PIPE1 0x0001 /* PIPE 1 */ | |
| 357 | #define M66592_PIPE2 0x0002 /* PIPE 2 */ | |
| 358 | #define M66592_PIPE3 0x0003 /* PIPE 3 */ | |
| 359 | #define M66592_PIPE4 0x0004 /* PIPE 4 */ | |
| 360 | #define M66592_PIPE5 0x0005 /* PIPE 5 */ | |
| 361 | #define M66592_PIPE6 0x0006 /* PIPE 6 */ | |
| 362 | #define M66592_PIPE7 0x0007 /* PIPE 7 */ | |
| 4cf2503c YS |
363 | |
| 364 | #define M66592_PIPECFG 0x66 | |
| 598f22e1 YS |
365 | #define M66592_TYP 0xC000 /* b15-14: Transfer type */ |
| 366 | #define M66592_ISO 0xC000 /* Isochronous */ | |
| 367 | #define M66592_INT 0x8000 /* Interrupt */ | |
| 368 | #define M66592_BULK 0x4000 /* Bulk */ | |
| 369 | #define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode */ | |
| 370 | #define M66592_DBLB 0x0200 /* b9: Double buffer mode select */ | |
| 371 | #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */ | |
| 372 | #define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */ | |
| 373 | #define M66592_DIR 0x0010 /* b4: Transfer direction select */ | |
| 374 | #define M66592_DIR_H_OUT 0x0010 /* HOST OUT */ | |
| 375 | #define M66592_DIR_P_IN 0x0010 /* PERI IN */ | |
| 376 | #define M66592_DIR_H_IN 0x0000 /* HOST IN */ | |
| 377 | #define M66592_DIR_P_OUT 0x0000 /* PERI OUT */ | |
| 378 | #define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */ | |
| 379 | #define M66592_EP1 0x0001 | |
| 380 | #define M66592_EP2 0x0002 | |
| 381 | #define M66592_EP3 0x0003 | |
| 382 | #define M66592_EP4 0x0004 | |
| 383 | #define M66592_EP5 0x0005 | |
| 384 | #define M66592_EP6 0x0006 | |
| 385 | #define M66592_EP7 0x0007 | |
| 386 | #define M66592_EP8 0x0008 | |
| 387 | #define M66592_EP9 0x0009 | |
| 388 | #define M66592_EP10 0x000A | |
| 389 | #define M66592_EP11 0x000B | |
| 390 | #define M66592_EP12 0x000C | |
| 391 | #define M66592_EP13 0x000D | |
| 392 | #define M66592_EP14 0x000E | |
| 393 | #define M66592_EP15 0x000F | |
| 4cf2503c YS |
394 | |
| 395 | #define M66592_PIPEBUF 0x68 | |
| 598f22e1 YS |
396 | #define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ |
| 397 | #define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10) | |
| 398 | #define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */ | |
| 4cf2503c YS |
399 | |
| 400 | #define M66592_PIPEMAXP 0x6A | |
| 598f22e1 | 401 | #define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */ |
| 4cf2503c YS |
402 | |
| 403 | #define M66592_PIPEPERI 0x6C | |
| 598f22e1 YS |
404 | #define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */ |
| 405 | #define M66592_IITV 0x0007 /* b2-0: ISO interval */ | |
| 4cf2503c YS |
406 | |
| 407 | #define M66592_PIPE1CTR 0x70 | |
| 408 | #define M66592_PIPE2CTR 0x72 | |
| 409 | #define M66592_PIPE3CTR 0x74 | |
| 410 | #define M66592_PIPE4CTR 0x76 | |
| 411 | #define M66592_PIPE5CTR 0x78 | |
| 412 | #define M66592_PIPE6CTR 0x7A | |
| 413 | #define M66592_PIPE7CTR 0x7C | |
| 598f22e1 YS |
414 | #define M66592_BSTS 0x8000 /* b15: Buffer status */ |
| 415 | #define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */ | |
| 416 | #define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */ | |
| 417 | #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ | |
| 418 | #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ | |
| 419 | #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ | |
| 420 | #define M66592_PID 0x0003 /* b1-0: Response PID */ | |
| 4cf2503c YS |
421 | |
| 422 | #define M66592_INVALID_REG 0x7E | |
| 423 | ||
| 424 | ||
| 4cf2503c YS |
425 | #define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2) |
| 426 | ||
| 427 | #define M66592_MAX_SAMPLING 10 | |
| 428 | ||
| 429 | #define M66592_MAX_NUM_PIPE 8 | |
| 430 | #define M66592_MAX_NUM_BULK 3 | |
| 431 | #define M66592_MAX_NUM_ISOC 2 | |
| 432 | #define M66592_MAX_NUM_INT 2 | |
| 433 | ||
| 434 | #define M66592_BASE_PIPENUM_BULK 3 | |
| 435 | #define M66592_BASE_PIPENUM_ISOC 1 | |
| 436 | #define M66592_BASE_PIPENUM_INT 6 | |
| 437 | ||
| 438 | #define M66592_BASE_BUFNUM 6 | |
| 439 | #define M66592_MAX_BUFNUM 0x4F | |
| 440 | ||
| 441 | struct m66592_pipe_info { | |
| 442 | u16 pipe; | |
| 443 | u16 epnum; | |
| 444 | u16 maxpacket; | |
| 445 | u16 type; | |
| 446 | u16 interval; | |
| 447 | u16 dir_in; | |
| 448 | }; | |
| 449 | ||
| 450 | struct m66592_request { | |
| 451 | struct usb_request req; | |
| 452 | struct list_head queue; | |
| 453 | }; | |
| 454 | ||
| 455 | struct m66592_ep { | |
| 456 | struct usb_ep ep; | |
| 457 | struct m66592 *m66592; | |
| 458 | ||
| 459 | struct list_head queue; | |
| 598f22e1 | 460 | unsigned busy:1; |
| 4cf2503c YS |
461 | unsigned internal_ccpl:1; /* use only control */ |
| 462 | ||
| 463 | /* this member can able to after m66592_enable */ | |
| 464 | unsigned use_dma:1; | |
| 465 | u16 pipenum; | |
| 466 | u16 type; | |
| 467 | const struct usb_endpoint_descriptor *desc; | |
| 468 | /* register address */ | |
| 469 | unsigned long fifoaddr; | |
| 470 | unsigned long fifosel; | |
| 471 | unsigned long fifoctr; | |
| 472 | unsigned long fifotrn; | |
| 473 | unsigned long pipectr; | |
| 474 | }; | |
| 475 | ||
| 476 | struct m66592 { | |
| 477 | spinlock_t lock; | |
| 478 | void __iomem *reg; | |
| 479 | ||
| 480 | struct usb_gadget gadget; | |
| 481 | struct usb_gadget_driver *driver; | |
| 482 | ||
| 483 | struct m66592_ep ep[M66592_MAX_NUM_PIPE]; | |
| 484 | struct m66592_ep *pipenum2ep[M66592_MAX_NUM_PIPE]; | |
| 485 | struct m66592_ep *epaddr2ep[16]; | |
| 486 | ||
| 487 | struct usb_request *ep0_req; /* for internal request */ | |
| 598f22e1 | 488 | u16 ep0_data; /* for internal request */ |
| 96f9bc37 | 489 | u16 old_vbus; |
| 4cf2503c YS |
490 | |
| 491 | struct timer_list timer; | |
| 492 | ||
| 4cf2503c YS |
493 | int scount; |
| 494 | ||
| 495 | int old_dvsq; | |
| 496 | ||
| 497 | /* pipe config */ | |
| 498 | int bulk; | |
| 499 | int interrupt; | |
| 500 | int isochronous; | |
| 501 | int num_dma; | |
| 502 | int bi_bufnum; /* bulk and isochronous's bufnum */ | |
| 503 | }; | |
| 504 | ||
| 505 | #define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget) | |
| 506 | #define m66592_to_gadget(m66592) (&m66592->gadget) | |
| 507 | ||
| 508 | #define is_bulk_pipe(pipenum) \ | |
| 509 | ((pipenum >= M66592_BASE_PIPENUM_BULK) && \ | |
| 510 | (pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK))) | |
| 511 | #define is_interrupt_pipe(pipenum) \ | |
| 512 | ((pipenum >= M66592_BASE_PIPENUM_INT) && \ | |
| 513 | (pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT))) | |
| 514 | #define is_isoc_pipe(pipenum) \ | |
| 515 | ((pipenum >= M66592_BASE_PIPENUM_ISOC) && \ | |
| 516 | (pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC))) | |
| 517 | ||
| 518 | #define enable_irq_ready(m66592, pipenum) \ | |
| 519 | enable_pipe_irq(m66592, pipenum, M66592_BRDYENB) | |
| 520 | #define disable_irq_ready(m66592, pipenum) \ | |
| 521 | disable_pipe_irq(m66592, pipenum, M66592_BRDYENB) | |
| 522 | #define enable_irq_empty(m66592, pipenum) \ | |
| 523 | enable_pipe_irq(m66592, pipenum, M66592_BEMPENB) | |
| 524 | #define disable_irq_empty(m66592, pipenum) \ | |
| 525 | disable_pipe_irq(m66592, pipenum, M66592_BEMPENB) | |
| 526 | #define enable_irq_nrdy(m66592, pipenum) \ | |
| 527 | enable_pipe_irq(m66592, pipenum, M66592_NRDYENB) | |
| 528 | #define disable_irq_nrdy(m66592, pipenum) \ | |
| 529 | disable_pipe_irq(m66592, pipenum, M66592_NRDYENB) | |
| 530 | ||
| 531 | /*-------------------------------------------------------------------------*/ | |
| 532 | static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset) | |
| 533 | { | |
| 534 | return inw((unsigned long)m66592->reg + offset); | |
| 535 | } | |
| 536 | ||
| 537 | static inline void m66592_read_fifo(struct m66592 *m66592, | |
| 598f22e1 YS |
538 | unsigned long offset, |
| 539 | void *buf, unsigned long len) | |
| 4cf2503c YS |
540 | { |
| 541 | unsigned long fifoaddr = (unsigned long)m66592->reg + offset; | |
| 542 | ||
| 8c73aff6 YS |
543 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) |
| 544 | len = (len + 3) / 4; | |
| 545 | insl(fifoaddr, buf, len); | |
| 546 | #else | |
| 4cf2503c YS |
547 | len = (len + 1) / 2; |
| 548 | insw(fifoaddr, buf, len); | |
| 8c73aff6 | 549 | #endif |
| 4cf2503c YS |
550 | } |
| 551 | ||
| 552 | static inline void m66592_write(struct m66592 *m66592, u16 val, | |
| 553 | unsigned long offset) | |
| 554 | { | |
| 555 | outw(val, (unsigned long)m66592->reg + offset); | |
| 556 | } | |
| 557 | ||
| 558 | static inline void m66592_write_fifo(struct m66592 *m66592, | |
| 598f22e1 YS |
559 | unsigned long offset, |
| 560 | void *buf, unsigned long len) | |
| 4cf2503c YS |
561 | { |
| 562 | unsigned long fifoaddr = (unsigned long)m66592->reg + offset; | |
| 8c73aff6 YS |
563 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) |
| 564 | unsigned long count; | |
| 565 | unsigned char *pb; | |
| 566 | int i; | |
| 567 | ||
| 568 | count = len / 4; | |
| 569 | outsl(fifoaddr, buf, count); | |
| 570 | ||
| 571 | if (len & 0x00000003) { | |
| 572 | pb = buf + count * 4; | |
| 573 | for (i = 0; i < (len & 0x00000003); i++) { | |
| 574 | if (m66592_read(m66592, M66592_CFBCFG)) /* little */ | |
| 575 | outb(pb[i], fifoaddr + (3 - i)); | |
| 576 | else | |
| 577 | outb(pb[i], fifoaddr + i); | |
| 578 | } | |
| 579 | } | |
| 580 | #else | |
| 4cf2503c YS |
581 | unsigned long odd = len & 0x0001; |
| 582 | ||
| 583 | len = len / 2; | |
| 584 | outsw(fifoaddr, buf, len); | |
| 585 | if (odd) { | |
| 586 | unsigned char *p = buf + len*2; | |
| 587 | outb(*p, fifoaddr); | |
| 588 | } | |
| 8c73aff6 | 589 | #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */ |
| 4cf2503c YS |
590 | } |
| 591 | ||
| 592 | static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, | |
| 598f22e1 | 593 | unsigned long offset) |
| 4cf2503c YS |
594 | { |
| 595 | u16 tmp; | |
| 596 | tmp = m66592_read(m66592, offset); | |
| 597 | tmp = tmp & (~pat); | |
| 598 | tmp = tmp | val; | |
| 599 | m66592_write(m66592, tmp, offset); | |
| 600 | } | |
| 601 | ||
| 602 | #define m66592_bclr(m66592, val, offset) \ | |
| 603 | m66592_mdfy(m66592, 0, val, offset) | |
| 604 | #define m66592_bset(m66592, val, offset) \ | |
| 605 | m66592_mdfy(m66592, val, 0, offset) | |
| 606 | ||
| 8c73aff6 YS |
607 | #if defined(CONFIG_SUPERH_BUILT_IN_M66592) |
| 608 | #include <asm/io.h> | |
| 609 | #define MSTPCR2 0xA4150038 /* for SH7722 */ | |
| 610 | #define MSTPCR2_USB 0x00000800 | |
| 611 | ||
| 612 | static inline void usbf_start_clock(void) | |
| 613 | { | |
| 614 | ctrl_outl(ctrl_inl(MSTPCR2) & ~MSTPCR2_USB, MSTPCR2); | |
| 615 | } | |
| 616 | ||
| 617 | static inline void usbf_stop_clock(void) | |
| 618 | { | |
| 619 | ctrl_outl(ctrl_inl(MSTPCR2) | MSTPCR2_USB, MSTPCR2); | |
| 620 | } | |
| 621 | ||
| 622 | #else | |
| 623 | #define usbf_start_clock(x) | |
| 624 | #define usbf_stop_clock(x) | |
| 625 | #endif /* if defined(CONFIG_SUPERH_BUILT_IN_M66592) */ | |
| 626 | ||
| 4cf2503c YS |
627 | #endif /* ifndef __M66592_UDC_H__ */ |
| 628 | ||
| 629 |