Commit | Line | Data |
---|---|---|
3d4eb9df YX |
1 | /* |
2 | * Copyright (C) 2011 Marvell International Ltd. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/dmapool.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/timer.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/notifier.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/usb/ch9.h> | |
26 | #include <linux/usb/gadget.h> | |
27 | #include <linux/pm.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/platform_data/mv_usb.h> | |
32 | #include <linux/clk.h> | |
3d4eb9df YX |
33 | |
34 | #include "mv_u3d.h" | |
35 | ||
36 | #define DRIVER_DESC "Marvell PXA USB3.0 Device Controller driver" | |
37 | ||
38 | static const char driver_name[] = "mv_u3d"; | |
39 | static const char driver_desc[] = DRIVER_DESC; | |
40 | ||
41 | static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status); | |
42 | static void mv_u3d_stop_activity(struct mv_u3d *u3d, | |
43 | struct usb_gadget_driver *driver); | |
44 | ||
45 | /* for endpoint 0 operations */ | |
46 | static const struct usb_endpoint_descriptor mv_u3d_ep0_desc = { | |
47 | .bLength = USB_DT_ENDPOINT_SIZE, | |
48 | .bDescriptorType = USB_DT_ENDPOINT, | |
49 | .bEndpointAddress = 0, | |
50 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
51 | .wMaxPacketSize = MV_U3D_EP0_MAX_PKT_SIZE, | |
52 | }; | |
53 | ||
54 | static void mv_u3d_ep0_reset(struct mv_u3d *u3d) | |
55 | { | |
56 | struct mv_u3d_ep *ep; | |
57 | u32 epxcr; | |
58 | int i; | |
59 | ||
60 | for (i = 0; i < 2; i++) { | |
61 | ep = &u3d->eps[i]; | |
62 | ep->u3d = u3d; | |
63 | ||
64 | /* ep0 ep context, ep0 in and out share the same ep context */ | |
65 | ep->ep_context = &u3d->ep_context[1]; | |
66 | } | |
67 | ||
68 | /* reset ep state machine */ | |
69 | /* reset ep0 out */ | |
70 | epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0); | |
71 | epxcr |= MV_U3D_EPXCR_EP_INIT; | |
72 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
73 | udelay(5); | |
74 | epxcr &= ~MV_U3D_EPXCR_EP_INIT; | |
75 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
76 | ||
77 | epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE | |
78 | << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT) | |
79 | | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT) | |
80 | | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
81 | | MV_U3D_EPXCR_EP_TYPE_CONTROL); | |
82 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr1); | |
83 | ||
84 | /* reset ep0 in */ | |
85 | epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxincr0); | |
86 | epxcr |= MV_U3D_EPXCR_EP_INIT; | |
87 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0); | |
88 | udelay(5); | |
89 | epxcr &= ~MV_U3D_EPXCR_EP_INIT; | |
90 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0); | |
91 | ||
92 | epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE | |
93 | << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT) | |
94 | | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT) | |
95 | | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
96 | | MV_U3D_EPXCR_EP_TYPE_CONTROL); | |
97 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr1); | |
98 | } | |
99 | ||
100 | static void mv_u3d_ep0_stall(struct mv_u3d *u3d) | |
101 | { | |
102 | u32 tmp; | |
103 | dev_dbg(u3d->dev, "%s\n", __func__); | |
104 | ||
105 | /* set TX and RX to stall */ | |
106 | tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0); | |
107 | tmp |= MV_U3D_EPXCR_EP_HALT; | |
108 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
109 | ||
110 | tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0); | |
111 | tmp |= MV_U3D_EPXCR_EP_HALT; | |
112 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0); | |
113 | ||
114 | /* update ep0 state */ | |
115 | u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; | |
116 | u3d->ep0_dir = MV_U3D_EP_DIR_OUT; | |
117 | } | |
118 | ||
119 | static int mv_u3d_process_ep_req(struct mv_u3d *u3d, int index, | |
120 | struct mv_u3d_req *curr_req) | |
121 | { | |
122 | struct mv_u3d_trb *curr_trb; | |
123 | dma_addr_t cur_deq_lo; | |
124 | struct mv_u3d_ep_context *curr_ep_context; | |
e6667ef7 | 125 | int trb_complete, actual, remaining_length = 0; |
3d4eb9df YX |
126 | int direction, ep_num; |
127 | int retval = 0; | |
128 | u32 tmp, status, length; | |
129 | ||
130 | curr_ep_context = &u3d->ep_context[index]; | |
131 | direction = index % 2; | |
132 | ep_num = index / 2; | |
133 | ||
134 | trb_complete = 0; | |
135 | actual = curr_req->req.length; | |
136 | ||
137 | while (!list_empty(&curr_req->trb_list)) { | |
138 | curr_trb = list_entry(curr_req->trb_list.next, | |
139 | struct mv_u3d_trb, trb_list); | |
140 | if (!curr_trb->trb_hw->ctrl.own) { | |
141 | dev_err(u3d->dev, "%s, TRB own error!\n", | |
142 | u3d->eps[index].name); | |
143 | return 1; | |
144 | } | |
145 | ||
146 | curr_trb->trb_hw->ctrl.own = 0; | |
147 | if (direction == MV_U3D_EP_DIR_OUT) { | |
148 | tmp = ioread32(&u3d->vuc_regs->rxst[ep_num].statuslo); | |
149 | cur_deq_lo = | |
150 | ioread32(&u3d->vuc_regs->rxst[ep_num].curdeqlo); | |
151 | } else { | |
152 | tmp = ioread32(&u3d->vuc_regs->txst[ep_num].statuslo); | |
153 | cur_deq_lo = | |
154 | ioread32(&u3d->vuc_regs->txst[ep_num].curdeqlo); | |
155 | } | |
156 | ||
157 | status = tmp >> MV_U3D_XFERSTATUS_COMPLETE_SHIFT; | |
158 | length = tmp & MV_U3D_XFERSTATUS_TRB_LENGTH_MASK; | |
159 | ||
160 | if (status == MV_U3D_COMPLETE_SUCCESS || | |
161 | (status == MV_U3D_COMPLETE_SHORT_PACKET && | |
162 | direction == MV_U3D_EP_DIR_OUT)) { | |
163 | remaining_length += length; | |
164 | actual -= remaining_length; | |
165 | } else { | |
166 | dev_err(u3d->dev, | |
167 | "complete_tr error: ep=%d %s: error = 0x%x\n", | |
168 | index >> 1, direction ? "SEND" : "RECV", | |
169 | status); | |
170 | retval = -EPROTO; | |
171 | } | |
172 | ||
173 | list_del_init(&curr_trb->trb_list); | |
174 | } | |
175 | if (retval) | |
176 | return retval; | |
177 | ||
178 | curr_req->req.actual = actual; | |
179 | return 0; | |
180 | } | |
181 | ||
182 | /* | |
183 | * mv_u3d_done() - retire a request; caller blocked irqs | |
184 | * @status : request status to be set, only works when | |
185 | * request is still in progress. | |
186 | */ | |
187 | static | |
188 | void mv_u3d_done(struct mv_u3d_ep *ep, struct mv_u3d_req *req, int status) | |
6fbb2f7d FB |
189 | __releases(&ep->udc->lock) |
190 | __acquires(&ep->udc->lock) | |
3d4eb9df YX |
191 | { |
192 | struct mv_u3d *u3d = (struct mv_u3d *)ep->u3d; | |
193 | ||
194 | dev_dbg(u3d->dev, "mv_u3d_done: remove req->queue\n"); | |
195 | /* Removed the req from ep queue */ | |
196 | list_del_init(&req->queue); | |
197 | ||
198 | /* req.status should be set as -EINPROGRESS in ep_queue() */ | |
199 | if (req->req.status == -EINPROGRESS) | |
200 | req->req.status = status; | |
201 | else | |
202 | status = req->req.status; | |
203 | ||
204 | /* Free trb for the request */ | |
205 | if (!req->chain) | |
206 | dma_pool_free(u3d->trb_pool, | |
207 | req->trb_head->trb_hw, req->trb_head->trb_dma); | |
208 | else { | |
209 | dma_unmap_single(ep->u3d->gadget.dev.parent, | |
210 | (dma_addr_t)req->trb_head->trb_dma, | |
211 | req->trb_count * sizeof(struct mv_u3d_trb_hw), | |
212 | DMA_BIDIRECTIONAL); | |
213 | kfree(req->trb_head->trb_hw); | |
214 | } | |
215 | kfree(req->trb_head); | |
216 | ||
217 | usb_gadget_unmap_request(&u3d->gadget, &req->req, mv_u3d_ep_dir(ep)); | |
218 | ||
219 | if (status && (status != -ESHUTDOWN)) { | |
220 | dev_dbg(u3d->dev, "complete %s req %p stat %d len %u/%u", | |
221 | ep->ep.name, &req->req, status, | |
222 | req->req.actual, req->req.length); | |
223 | } | |
224 | ||
225 | spin_unlock(&ep->u3d->lock); | |
226 | /* | |
227 | * complete() is from gadget layer, | |
228 | * eg fsg->bulk_in_complete() | |
229 | */ | |
230 | if (req->req.complete) | |
231 | req->req.complete(&ep->ep, &req->req); | |
232 | ||
233 | spin_lock(&ep->u3d->lock); | |
234 | } | |
235 | ||
236 | static int mv_u3d_queue_trb(struct mv_u3d_ep *ep, struct mv_u3d_req *req) | |
237 | { | |
238 | u32 tmp, direction; | |
239 | struct mv_u3d *u3d; | |
240 | struct mv_u3d_ep_context *ep_context; | |
241 | int retval = 0; | |
242 | ||
243 | u3d = ep->u3d; | |
244 | direction = mv_u3d_ep_dir(ep); | |
245 | ||
246 | /* ep0 in and out share the same ep context slot 1*/ | |
247 | if (ep->ep_num == 0) | |
248 | ep_context = &(u3d->ep_context[1]); | |
249 | else | |
250 | ep_context = &(u3d->ep_context[ep->ep_num * 2 + direction]); | |
251 | ||
252 | /* check if the pipe is empty or not */ | |
253 | if (!list_empty(&ep->queue)) { | |
254 | dev_err(u3d->dev, "add trb to non-empty queue!\n"); | |
255 | retval = -ENOMEM; | |
256 | WARN_ON(1); | |
257 | } else { | |
258 | ep_context->rsvd0 = cpu_to_le32(1); | |
259 | ep_context->rsvd1 = 0; | |
260 | ||
261 | /* Configure the trb address and set the DCS bit. | |
262 | * Both DCS bit and own bit in trb should be set. | |
263 | */ | |
264 | ep_context->trb_addr_lo = | |
265 | cpu_to_le32(req->trb_head->trb_dma | DCS_ENABLE); | |
266 | ep_context->trb_addr_hi = 0; | |
267 | ||
268 | /* Ensure that updates to the EP Context will | |
269 | * occure before Ring Bell. | |
270 | */ | |
271 | wmb(); | |
272 | ||
273 | /* ring bell the ep */ | |
274 | if (ep->ep_num == 0) | |
275 | tmp = 0x1; | |
276 | else | |
277 | tmp = ep->ep_num * 2 | |
278 | + ((direction == MV_U3D_EP_DIR_OUT) ? 0 : 1); | |
279 | ||
280 | iowrite32(tmp, &u3d->op_regs->doorbell); | |
281 | } | |
282 | return retval; | |
283 | } | |
284 | ||
285 | static struct mv_u3d_trb *mv_u3d_build_trb_one(struct mv_u3d_req *req, | |
286 | unsigned *length, dma_addr_t *dma) | |
287 | { | |
288 | u32 temp; | |
289 | unsigned int direction; | |
290 | struct mv_u3d_trb *trb; | |
291 | struct mv_u3d_trb_hw *trb_hw; | |
292 | struct mv_u3d *u3d; | |
293 | ||
294 | /* how big will this transfer be? */ | |
295 | *length = req->req.length - req->req.actual; | |
296 | BUG_ON(*length > (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER); | |
297 | ||
298 | u3d = req->ep->u3d; | |
299 | ||
300 | trb = kzalloc(sizeof(*trb), GFP_ATOMIC); | |
301 | if (!trb) { | |
302 | dev_err(u3d->dev, "%s, trb alloc fail\n", __func__); | |
303 | return NULL; | |
304 | } | |
305 | ||
306 | /* | |
307 | * Be careful that no _GFP_HIGHMEM is set, | |
308 | * or we can not use dma_to_virt | |
309 | * cannot use GFP_KERNEL in spin lock | |
310 | */ | |
311 | trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma); | |
312 | if (!trb_hw) { | |
313 | dev_err(u3d->dev, | |
314 | "%s, dma_pool_alloc fail\n", __func__); | |
315 | return NULL; | |
316 | } | |
317 | trb->trb_dma = *dma; | |
318 | trb->trb_hw = trb_hw; | |
319 | ||
320 | /* initialize buffer page pointers */ | |
321 | temp = (u32)(req->req.dma + req->req.actual); | |
322 | ||
323 | trb_hw->buf_addr_lo = cpu_to_le32(temp); | |
324 | trb_hw->buf_addr_hi = 0; | |
325 | trb_hw->trb_len = cpu_to_le32(*length); | |
326 | trb_hw->ctrl.own = 1; | |
327 | ||
328 | if (req->ep->ep_num == 0) | |
329 | trb_hw->ctrl.type = TYPE_DATA; | |
330 | else | |
331 | trb_hw->ctrl.type = TYPE_NORMAL; | |
332 | ||
333 | req->req.actual += *length; | |
334 | ||
335 | direction = mv_u3d_ep_dir(req->ep); | |
336 | if (direction == MV_U3D_EP_DIR_IN) | |
337 | trb_hw->ctrl.dir = 1; | |
338 | else | |
339 | trb_hw->ctrl.dir = 0; | |
340 | ||
341 | /* Enable interrupt for the last trb of a request */ | |
342 | if (!req->req.no_interrupt) | |
343 | trb_hw->ctrl.ioc = 1; | |
344 | ||
345 | trb_hw->ctrl.chain = 0; | |
346 | ||
347 | wmb(); | |
348 | return trb; | |
349 | } | |
350 | ||
351 | static int mv_u3d_build_trb_chain(struct mv_u3d_req *req, unsigned *length, | |
352 | struct mv_u3d_trb *trb, int *is_last) | |
353 | { | |
354 | u32 temp; | |
355 | unsigned int direction; | |
356 | struct mv_u3d *u3d; | |
357 | ||
358 | /* how big will this transfer be? */ | |
359 | *length = min(req->req.length - req->req.actual, | |
360 | (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER); | |
361 | ||
362 | u3d = req->ep->u3d; | |
363 | ||
364 | trb->trb_dma = 0; | |
365 | ||
366 | /* initialize buffer page pointers */ | |
367 | temp = (u32)(req->req.dma + req->req.actual); | |
368 | ||
369 | trb->trb_hw->buf_addr_lo = cpu_to_le32(temp); | |
370 | trb->trb_hw->buf_addr_hi = 0; | |
371 | trb->trb_hw->trb_len = cpu_to_le32(*length); | |
372 | trb->trb_hw->ctrl.own = 1; | |
373 | ||
374 | if (req->ep->ep_num == 0) | |
375 | trb->trb_hw->ctrl.type = TYPE_DATA; | |
376 | else | |
377 | trb->trb_hw->ctrl.type = TYPE_NORMAL; | |
378 | ||
379 | req->req.actual += *length; | |
380 | ||
381 | direction = mv_u3d_ep_dir(req->ep); | |
382 | if (direction == MV_U3D_EP_DIR_IN) | |
383 | trb->trb_hw->ctrl.dir = 1; | |
384 | else | |
385 | trb->trb_hw->ctrl.dir = 0; | |
386 | ||
387 | /* zlp is needed if req->req.zero is set */ | |
388 | if (req->req.zero) { | |
389 | if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) | |
390 | *is_last = 1; | |
391 | else | |
392 | *is_last = 0; | |
393 | } else if (req->req.length == req->req.actual) | |
394 | *is_last = 1; | |
395 | else | |
396 | *is_last = 0; | |
397 | ||
398 | /* Enable interrupt for the last trb of a request */ | |
399 | if (*is_last && !req->req.no_interrupt) | |
400 | trb->trb_hw->ctrl.ioc = 1; | |
401 | ||
402 | if (*is_last) | |
403 | trb->trb_hw->ctrl.chain = 0; | |
404 | else { | |
405 | trb->trb_hw->ctrl.chain = 1; | |
406 | dev_dbg(u3d->dev, "chain trb\n"); | |
407 | } | |
408 | ||
409 | wmb(); | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | /* generate TRB linked list for a request | |
415 | * usb controller only supports continous trb chain, | |
416 | * that trb structure physical address should be continous. | |
417 | */ | |
418 | static int mv_u3d_req_to_trb(struct mv_u3d_req *req) | |
419 | { | |
420 | unsigned count; | |
421 | int is_last; | |
422 | struct mv_u3d_trb *trb; | |
423 | struct mv_u3d_trb_hw *trb_hw; | |
424 | struct mv_u3d *u3d; | |
425 | dma_addr_t dma; | |
426 | unsigned length; | |
427 | unsigned trb_num; | |
428 | ||
429 | u3d = req->ep->u3d; | |
430 | ||
431 | INIT_LIST_HEAD(&req->trb_list); | |
432 | ||
433 | length = req->req.length - req->req.actual; | |
434 | /* normally the request transfer length is less than 16KB. | |
435 | * we use buil_trb_one() to optimize it. | |
436 | */ | |
437 | if (length <= (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER) { | |
438 | trb = mv_u3d_build_trb_one(req, &count, &dma); | |
439 | list_add_tail(&trb->trb_list, &req->trb_list); | |
440 | req->trb_head = trb; | |
441 | req->trb_count = 1; | |
442 | req->chain = 0; | |
443 | } else { | |
444 | trb_num = length / MV_U3D_EP_MAX_LENGTH_TRANSFER; | |
445 | if (length % MV_U3D_EP_MAX_LENGTH_TRANSFER) | |
446 | trb_num++; | |
447 | ||
448 | trb = kcalloc(trb_num, sizeof(*trb), GFP_ATOMIC); | |
449 | if (!trb) { | |
450 | dev_err(u3d->dev, | |
451 | "%s, trb alloc fail\n", __func__); | |
452 | return -ENOMEM; | |
453 | } | |
454 | ||
455 | trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC); | |
456 | if (!trb_hw) { | |
457 | dev_err(u3d->dev, | |
458 | "%s, trb_hw alloc fail\n", __func__); | |
459 | return -ENOMEM; | |
460 | } | |
461 | ||
462 | do { | |
463 | trb->trb_hw = trb_hw; | |
464 | if (mv_u3d_build_trb_chain(req, &count, | |
465 | trb, &is_last)) { | |
466 | dev_err(u3d->dev, | |
467 | "%s, mv_u3d_build_trb_chain fail\n", | |
468 | __func__); | |
469 | return -EIO; | |
470 | } | |
471 | ||
472 | list_add_tail(&trb->trb_list, &req->trb_list); | |
473 | req->trb_count++; | |
474 | trb++; | |
475 | trb_hw++; | |
476 | } while (!is_last); | |
477 | ||
478 | req->trb_head = list_entry(req->trb_list.next, | |
479 | struct mv_u3d_trb, trb_list); | |
480 | req->trb_head->trb_dma = dma_map_single(u3d->gadget.dev.parent, | |
481 | req->trb_head->trb_hw, | |
482 | trb_num * sizeof(*trb_hw), | |
483 | DMA_BIDIRECTIONAL); | |
484 | ||
485 | req->chain = 1; | |
486 | } | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
491 | static int | |
492 | mv_u3d_start_queue(struct mv_u3d_ep *ep) | |
493 | { | |
494 | struct mv_u3d *u3d = ep->u3d; | |
495 | struct mv_u3d_req *req; | |
496 | int ret; | |
497 | ||
498 | if (!list_empty(&ep->req_list) && !ep->processing) | |
499 | req = list_entry(ep->req_list.next, struct mv_u3d_req, list); | |
500 | else | |
501 | return 0; | |
502 | ||
503 | ep->processing = 1; | |
504 | ||
505 | /* set up dma mapping */ | |
506 | ret = usb_gadget_map_request(&u3d->gadget, &req->req, | |
507 | mv_u3d_ep_dir(ep)); | |
508 | if (ret) | |
509 | return ret; | |
510 | ||
511 | req->req.status = -EINPROGRESS; | |
512 | req->req.actual = 0; | |
513 | req->trb_count = 0; | |
514 | ||
515 | /* build trbs and push them to device queue */ | |
516 | if (!mv_u3d_req_to_trb(req)) { | |
517 | ret = mv_u3d_queue_trb(ep, req); | |
518 | if (ret) { | |
519 | ep->processing = 0; | |
520 | return ret; | |
521 | } | |
522 | } else { | |
523 | ep->processing = 0; | |
524 | dev_err(u3d->dev, "%s, mv_u3d_req_to_trb fail\n", __func__); | |
525 | return -ENOMEM; | |
526 | } | |
527 | ||
528 | /* irq handler advances the queue */ | |
529 | if (req) | |
530 | list_add_tail(&req->queue, &ep->queue); | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static int mv_u3d_ep_enable(struct usb_ep *_ep, | |
536 | const struct usb_endpoint_descriptor *desc) | |
537 | { | |
538 | struct mv_u3d *u3d; | |
539 | struct mv_u3d_ep *ep; | |
540 | struct mv_u3d_ep_context *ep_context; | |
541 | u16 max = 0; | |
542 | unsigned maxburst = 0; | |
543 | u32 epxcr, direction; | |
544 | ||
545 | if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) | |
546 | return -EINVAL; | |
547 | ||
548 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
549 | u3d = ep->u3d; | |
550 | ||
551 | if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) | |
552 | return -ESHUTDOWN; | |
553 | ||
554 | direction = mv_u3d_ep_dir(ep); | |
555 | max = le16_to_cpu(desc->wMaxPacketSize); | |
556 | ||
557 | if (!_ep->maxburst) | |
558 | _ep->maxburst = 1; | |
559 | maxburst = _ep->maxburst; | |
560 | ||
561 | /* Get the endpoint context address */ | |
562 | ep_context = (struct mv_u3d_ep_context *)ep->ep_context; | |
563 | ||
564 | /* Set the max burst size */ | |
565 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { | |
566 | case USB_ENDPOINT_XFER_BULK: | |
567 | if (maxburst > 16) { | |
568 | dev_dbg(u3d->dev, | |
569 | "max burst should not be greater " | |
570 | "than 16 on bulk ep\n"); | |
571 | maxburst = 1; | |
572 | _ep->maxburst = maxburst; | |
573 | } | |
574 | dev_dbg(u3d->dev, | |
575 | "maxburst: %d on bulk %s\n", maxburst, ep->name); | |
576 | break; | |
577 | case USB_ENDPOINT_XFER_CONTROL: | |
578 | /* control transfer only supports maxburst as one */ | |
579 | maxburst = 1; | |
580 | _ep->maxburst = maxburst; | |
581 | break; | |
582 | case USB_ENDPOINT_XFER_INT: | |
583 | if (maxburst != 1) { | |
584 | dev_dbg(u3d->dev, | |
585 | "max burst should be 1 on int ep " | |
586 | "if transfer size is not 1024\n"); | |
587 | maxburst = 1; | |
588 | _ep->maxburst = maxburst; | |
589 | } | |
590 | break; | |
591 | case USB_ENDPOINT_XFER_ISOC: | |
592 | if (maxburst != 1) { | |
593 | dev_dbg(u3d->dev, | |
594 | "max burst should be 1 on isoc ep " | |
595 | "if transfer size is not 1024\n"); | |
596 | maxburst = 1; | |
597 | _ep->maxburst = maxburst; | |
598 | } | |
599 | break; | |
600 | default: | |
601 | goto en_done; | |
602 | } | |
603 | ||
604 | ep->ep.maxpacket = max; | |
605 | ep->ep.desc = desc; | |
606 | ep->enabled = 1; | |
607 | ||
608 | /* Enable the endpoint for Rx or Tx and set the endpoint type */ | |
609 | if (direction == MV_U3D_EP_DIR_OUT) { | |
610 | epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
611 | epxcr |= MV_U3D_EPXCR_EP_INIT; | |
612 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
613 | udelay(5); | |
614 | epxcr &= ~MV_U3D_EPXCR_EP_INIT; | |
615 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
616 | ||
617 | epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT) | |
618 | | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT) | |
619 | | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
620 | | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)); | |
621 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1); | |
622 | } else { | |
623 | epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
624 | epxcr |= MV_U3D_EPXCR_EP_INIT; | |
625 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
626 | udelay(5); | |
627 | epxcr &= ~MV_U3D_EPXCR_EP_INIT; | |
628 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
629 | ||
630 | epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT) | |
631 | | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT) | |
632 | | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
633 | | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)); | |
634 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1); | |
635 | } | |
636 | ||
637 | return 0; | |
638 | en_done: | |
639 | return -EINVAL; | |
640 | } | |
641 | ||
642 | static int mv_u3d_ep_disable(struct usb_ep *_ep) | |
643 | { | |
644 | struct mv_u3d *u3d; | |
645 | struct mv_u3d_ep *ep; | |
646 | struct mv_u3d_ep_context *ep_context; | |
647 | u32 epxcr, direction; | |
2389df45 | 648 | unsigned long flags; |
3d4eb9df YX |
649 | |
650 | if (!_ep) | |
651 | return -EINVAL; | |
652 | ||
653 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
654 | if (!ep->ep.desc) | |
655 | return -EINVAL; | |
656 | ||
657 | u3d = ep->u3d; | |
658 | ||
659 | /* Get the endpoint context address */ | |
660 | ep_context = ep->ep_context; | |
661 | ||
662 | direction = mv_u3d_ep_dir(ep); | |
663 | ||
664 | /* nuke all pending requests (does flush) */ | |
2389df45 | 665 | spin_lock_irqsave(&u3d->lock, flags); |
3d4eb9df | 666 | mv_u3d_nuke(ep, -ESHUTDOWN); |
2389df45 | 667 | spin_unlock_irqrestore(&u3d->lock, flags); |
3d4eb9df YX |
668 | |
669 | /* Disable the endpoint for Rx or Tx and reset the endpoint type */ | |
670 | if (direction == MV_U3D_EP_DIR_OUT) { | |
671 | epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1); | |
672 | epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
673 | | USB_ENDPOINT_XFERTYPE_MASK); | |
674 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1); | |
675 | } else { | |
676 | epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr1); | |
677 | epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
678 | | USB_ENDPOINT_XFERTYPE_MASK); | |
679 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1); | |
680 | } | |
681 | ||
682 | ep->enabled = 0; | |
683 | ||
684 | ep->ep.desc = NULL; | |
685 | return 0; | |
686 | } | |
687 | ||
688 | static struct usb_request * | |
689 | mv_u3d_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) | |
690 | { | |
691 | struct mv_u3d_req *req = NULL; | |
692 | ||
693 | req = kzalloc(sizeof *req, gfp_flags); | |
694 | if (!req) | |
695 | return NULL; | |
696 | ||
697 | INIT_LIST_HEAD(&req->queue); | |
698 | ||
699 | return &req->req; | |
700 | } | |
701 | ||
702 | static void mv_u3d_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
703 | { | |
704 | struct mv_u3d_req *req = container_of(_req, struct mv_u3d_req, req); | |
705 | ||
706 | kfree(req); | |
707 | } | |
708 | ||
709 | static void mv_u3d_ep_fifo_flush(struct usb_ep *_ep) | |
710 | { | |
711 | struct mv_u3d *u3d; | |
712 | u32 direction; | |
713 | struct mv_u3d_ep *ep = container_of(_ep, struct mv_u3d_ep, ep); | |
714 | unsigned int loops; | |
715 | u32 tmp; | |
716 | ||
717 | /* if endpoint is not enabled, cannot flush endpoint */ | |
718 | if (!ep->enabled) | |
719 | return; | |
720 | ||
721 | u3d = ep->u3d; | |
722 | direction = mv_u3d_ep_dir(ep); | |
723 | ||
724 | /* ep0 need clear bit after flushing fifo. */ | |
725 | if (!ep->ep_num) { | |
726 | if (direction == MV_U3D_EP_DIR_OUT) { | |
727 | tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0); | |
728 | tmp |= MV_U3D_EPXCR_EP_FLUSH; | |
729 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
730 | udelay(10); | |
731 | tmp &= ~MV_U3D_EPXCR_EP_FLUSH; | |
732 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
733 | } else { | |
734 | tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0); | |
735 | tmp |= MV_U3D_EPXCR_EP_FLUSH; | |
736 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0); | |
737 | udelay(10); | |
738 | tmp &= ~MV_U3D_EPXCR_EP_FLUSH; | |
739 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0); | |
740 | } | |
741 | return; | |
742 | } | |
743 | ||
744 | if (direction == MV_U3D_EP_DIR_OUT) { | |
745 | tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
746 | tmp |= MV_U3D_EPXCR_EP_FLUSH; | |
747 | iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
748 | ||
749 | /* Wait until flushing completed */ | |
750 | loops = LOOPS(MV_U3D_FLUSH_TIMEOUT); | |
751 | while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0) & | |
752 | MV_U3D_EPXCR_EP_FLUSH) { | |
753 | /* | |
754 | * EP_FLUSH bit should be cleared to indicate this | |
755 | * operation is complete | |
756 | */ | |
757 | if (loops == 0) { | |
758 | dev_dbg(u3d->dev, | |
759 | "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num, | |
760 | direction ? "in" : "out"); | |
761 | return; | |
762 | } | |
763 | loops--; | |
764 | udelay(LOOPS_USEC); | |
765 | } | |
766 | } else { /* EP_DIR_IN */ | |
767 | tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
768 | tmp |= MV_U3D_EPXCR_EP_FLUSH; | |
769 | iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
770 | ||
771 | /* Wait until flushing completed */ | |
772 | loops = LOOPS(MV_U3D_FLUSH_TIMEOUT); | |
773 | while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0) & | |
774 | MV_U3D_EPXCR_EP_FLUSH) { | |
775 | /* | |
776 | * EP_FLUSH bit should be cleared to indicate this | |
777 | * operation is complete | |
778 | */ | |
779 | if (loops == 0) { | |
780 | dev_dbg(u3d->dev, | |
781 | "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num, | |
782 | direction ? "in" : "out"); | |
783 | return; | |
784 | } | |
785 | loops--; | |
786 | udelay(LOOPS_USEC); | |
787 | } | |
788 | } | |
789 | } | |
790 | ||
791 | /* queues (submits) an I/O request to an endpoint */ | |
792 | static int | |
793 | mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |
794 | { | |
795 | struct mv_u3d_ep *ep; | |
796 | struct mv_u3d_req *req; | |
797 | struct mv_u3d *u3d; | |
798 | unsigned long flags; | |
799 | int is_first_req = 0; | |
800 | ||
801 | if (unlikely(!_ep || !_req)) | |
802 | return -EINVAL; | |
803 | ||
804 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
805 | u3d = ep->u3d; | |
806 | ||
807 | req = container_of(_req, struct mv_u3d_req, req); | |
808 | ||
809 | if (!ep->ep_num | |
810 | && u3d->ep0_state == MV_U3D_STATUS_STAGE | |
811 | && !_req->length) { | |
812 | dev_dbg(u3d->dev, "ep0 status stage\n"); | |
813 | u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; | |
814 | return 0; | |
815 | } | |
816 | ||
e6667ef7 FB |
817 | dev_dbg(u3d->dev, "%s: %s, req: 0x%p\n", |
818 | __func__, _ep->name, req); | |
3d4eb9df YX |
819 | |
820 | /* catch various bogus parameters */ | |
821 | if (!req->req.complete || !req->req.buf | |
822 | || !list_empty(&req->queue)) { | |
823 | dev_err(u3d->dev, | |
e6667ef7 FB |
824 | "%s, bad params, _req: 0x%p," |
825 | "req->req.complete: 0x%p, req->req.buf: 0x%p," | |
3d4eb9df | 826 | "list_empty: 0x%x\n", |
e6667ef7 FB |
827 | __func__, _req, |
828 | req->req.complete, req->req.buf, | |
829 | list_empty(&req->queue)); | |
3d4eb9df YX |
830 | return -EINVAL; |
831 | } | |
832 | if (unlikely(!ep->ep.desc)) { | |
833 | dev_err(u3d->dev, "%s, bad ep\n", __func__); | |
834 | return -EINVAL; | |
835 | } | |
836 | if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
837 | if (req->req.length > ep->ep.maxpacket) | |
838 | return -EMSGSIZE; | |
839 | } | |
840 | ||
841 | if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) { | |
842 | dev_err(u3d->dev, | |
843 | "bad params of driver/speed\n"); | |
844 | return -ESHUTDOWN; | |
845 | } | |
846 | ||
847 | req->ep = ep; | |
848 | ||
849 | /* Software list handles usb request. */ | |
850 | spin_lock_irqsave(&ep->req_lock, flags); | |
851 | is_first_req = list_empty(&ep->req_list); | |
852 | list_add_tail(&req->list, &ep->req_list); | |
853 | spin_unlock_irqrestore(&ep->req_lock, flags); | |
854 | if (!is_first_req) { | |
855 | dev_dbg(u3d->dev, "list is not empty\n"); | |
856 | return 0; | |
857 | } | |
858 | ||
859 | dev_dbg(u3d->dev, "call mv_u3d_start_queue from usb_ep_queue\n"); | |
860 | spin_lock_irqsave(&u3d->lock, flags); | |
861 | mv_u3d_start_queue(ep); | |
862 | spin_unlock_irqrestore(&u3d->lock, flags); | |
863 | return 0; | |
864 | } | |
865 | ||
866 | /* dequeues (cancels, unlinks) an I/O request from an endpoint */ | |
867 | static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
868 | { | |
869 | struct mv_u3d_ep *ep; | |
870 | struct mv_u3d_req *req; | |
871 | struct mv_u3d *u3d; | |
872 | struct mv_u3d_ep_context *ep_context; | |
873 | struct mv_u3d_req *next_req; | |
874 | ||
875 | unsigned long flags; | |
876 | int ret = 0; | |
877 | ||
878 | if (!_ep || !_req) | |
879 | return -EINVAL; | |
880 | ||
881 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
882 | u3d = ep->u3d; | |
883 | ||
884 | spin_lock_irqsave(&ep->u3d->lock, flags); | |
885 | ||
886 | /* make sure it's actually queued on this endpoint */ | |
887 | list_for_each_entry(req, &ep->queue, queue) { | |
888 | if (&req->req == _req) | |
889 | break; | |
890 | } | |
891 | if (&req->req != _req) { | |
892 | ret = -EINVAL; | |
893 | goto out; | |
894 | } | |
895 | ||
896 | /* The request is in progress, or completed but not dequeued */ | |
897 | if (ep->queue.next == &req->queue) { | |
898 | _req->status = -ECONNRESET; | |
899 | mv_u3d_ep_fifo_flush(_ep); | |
900 | ||
901 | /* The request isn't the last request in this ep queue */ | |
902 | if (req->queue.next != &ep->queue) { | |
903 | dev_dbg(u3d->dev, | |
904 | "it is the last request in this ep queue\n"); | |
905 | ep_context = ep->ep_context; | |
906 | next_req = list_entry(req->queue.next, | |
907 | struct mv_u3d_req, queue); | |
908 | ||
909 | /* Point first TRB of next request to the EP context. */ | |
e6667ef7 | 910 | iowrite32((unsigned long) next_req->trb_head, |
3d4eb9df YX |
911 | &ep_context->trb_addr_lo); |
912 | } else { | |
913 | struct mv_u3d_ep_context *ep_context; | |
914 | ep_context = ep->ep_context; | |
915 | ep_context->trb_addr_lo = 0; | |
916 | ep_context->trb_addr_hi = 0; | |
917 | } | |
918 | ||
919 | } else | |
920 | WARN_ON(1); | |
921 | ||
922 | mv_u3d_done(ep, req, -ECONNRESET); | |
923 | ||
924 | /* remove the req from the ep req list */ | |
925 | if (!list_empty(&ep->req_list)) { | |
926 | struct mv_u3d_req *curr_req; | |
927 | curr_req = list_entry(ep->req_list.next, | |
928 | struct mv_u3d_req, list); | |
929 | if (curr_req == req) { | |
930 | list_del_init(&req->list); | |
931 | ep->processing = 0; | |
932 | } | |
933 | } | |
934 | ||
935 | out: | |
936 | spin_unlock_irqrestore(&ep->u3d->lock, flags); | |
937 | return ret; | |
938 | } | |
939 | ||
940 | static void | |
941 | mv_u3d_ep_set_stall(struct mv_u3d *u3d, u8 ep_num, u8 direction, int stall) | |
942 | { | |
943 | u32 tmp; | |
944 | struct mv_u3d_ep *ep = u3d->eps; | |
945 | ||
946 | dev_dbg(u3d->dev, "%s\n", __func__); | |
947 | if (direction == MV_U3D_EP_DIR_OUT) { | |
948 | tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
949 | if (stall) | |
950 | tmp |= MV_U3D_EPXCR_EP_HALT; | |
951 | else | |
952 | tmp &= ~MV_U3D_EPXCR_EP_HALT; | |
953 | iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
954 | } else { | |
955 | tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
956 | if (stall) | |
957 | tmp |= MV_U3D_EPXCR_EP_HALT; | |
958 | else | |
959 | tmp &= ~MV_U3D_EPXCR_EP_HALT; | |
960 | iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
961 | } | |
962 | } | |
963 | ||
964 | static int mv_u3d_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge) | |
965 | { | |
966 | struct mv_u3d_ep *ep; | |
967 | unsigned long flags = 0; | |
968 | int status = 0; | |
969 | struct mv_u3d *u3d; | |
970 | ||
971 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
972 | u3d = ep->u3d; | |
973 | if (!ep->ep.desc) { | |
974 | status = -EINVAL; | |
975 | goto out; | |
976 | } | |
977 | ||
978 | if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
979 | status = -EOPNOTSUPP; | |
980 | goto out; | |
981 | } | |
982 | ||
983 | /* | |
984 | * Attempt to halt IN ep will fail if any transfer requests | |
985 | * are still queue | |
986 | */ | |
987 | if (halt && (mv_u3d_ep_dir(ep) == MV_U3D_EP_DIR_IN) | |
988 | && !list_empty(&ep->queue)) { | |
989 | status = -EAGAIN; | |
990 | goto out; | |
991 | } | |
992 | ||
993 | spin_lock_irqsave(&ep->u3d->lock, flags); | |
994 | mv_u3d_ep_set_stall(u3d, ep->ep_num, mv_u3d_ep_dir(ep), halt); | |
995 | if (halt && wedge) | |
996 | ep->wedge = 1; | |
997 | else if (!halt) | |
998 | ep->wedge = 0; | |
999 | spin_unlock_irqrestore(&ep->u3d->lock, flags); | |
1000 | ||
1001 | if (ep->ep_num == 0) | |
1002 | u3d->ep0_dir = MV_U3D_EP_DIR_OUT; | |
1003 | out: | |
1004 | return status; | |
1005 | } | |
1006 | ||
1007 | static int mv_u3d_ep_set_halt(struct usb_ep *_ep, int halt) | |
1008 | { | |
1009 | return mv_u3d_ep_set_halt_wedge(_ep, halt, 0); | |
1010 | } | |
1011 | ||
1012 | static int mv_u3d_ep_set_wedge(struct usb_ep *_ep) | |
1013 | { | |
1014 | return mv_u3d_ep_set_halt_wedge(_ep, 1, 1); | |
1015 | } | |
1016 | ||
1017 | static struct usb_ep_ops mv_u3d_ep_ops = { | |
1018 | .enable = mv_u3d_ep_enable, | |
1019 | .disable = mv_u3d_ep_disable, | |
1020 | ||
1021 | .alloc_request = mv_u3d_alloc_request, | |
1022 | .free_request = mv_u3d_free_request, | |
1023 | ||
1024 | .queue = mv_u3d_ep_queue, | |
1025 | .dequeue = mv_u3d_ep_dequeue, | |
1026 | ||
1027 | .set_wedge = mv_u3d_ep_set_wedge, | |
1028 | .set_halt = mv_u3d_ep_set_halt, | |
1029 | .fifo_flush = mv_u3d_ep_fifo_flush, | |
1030 | }; | |
1031 | ||
1032 | static void mv_u3d_controller_stop(struct mv_u3d *u3d) | |
1033 | { | |
1034 | u32 tmp; | |
1035 | ||
1036 | if (!u3d->clock_gating && u3d->vbus_valid_detect) | |
1037 | iowrite32(MV_U3D_INTR_ENABLE_VBUS_VALID, | |
1038 | &u3d->vuc_regs->intrenable); | |
1039 | else | |
1040 | iowrite32(0, &u3d->vuc_regs->intrenable); | |
1041 | iowrite32(~0x0, &u3d->vuc_regs->endcomplete); | |
1042 | iowrite32(~0x0, &u3d->vuc_regs->trbunderrun); | |
1043 | iowrite32(~0x0, &u3d->vuc_regs->trbcomplete); | |
1044 | iowrite32(~0x0, &u3d->vuc_regs->linkchange); | |
1045 | iowrite32(0x1, &u3d->vuc_regs->setuplock); | |
1046 | ||
1047 | /* Reset the RUN bit in the command register to stop USB */ | |
1048 | tmp = ioread32(&u3d->op_regs->usbcmd); | |
1049 | tmp &= ~MV_U3D_CMD_RUN_STOP; | |
1050 | iowrite32(tmp, &u3d->op_regs->usbcmd); | |
1051 | dev_dbg(u3d->dev, "after u3d_stop, USBCMD 0x%x\n", | |
1052 | ioread32(&u3d->op_regs->usbcmd)); | |
1053 | } | |
1054 | ||
1055 | static void mv_u3d_controller_start(struct mv_u3d *u3d) | |
1056 | { | |
1057 | u32 usbintr; | |
1058 | u32 temp; | |
1059 | ||
1060 | /* enable link LTSSM state machine */ | |
1061 | temp = ioread32(&u3d->vuc_regs->ltssm); | |
1062 | temp |= MV_U3D_LTSSM_PHY_INIT_DONE; | |
1063 | iowrite32(temp, &u3d->vuc_regs->ltssm); | |
1064 | ||
1065 | /* Enable interrupts */ | |
1066 | usbintr = MV_U3D_INTR_ENABLE_LINK_CHG | MV_U3D_INTR_ENABLE_TXDESC_ERR | | |
1067 | MV_U3D_INTR_ENABLE_RXDESC_ERR | MV_U3D_INTR_ENABLE_TX_COMPLETE | | |
1068 | MV_U3D_INTR_ENABLE_RX_COMPLETE | MV_U3D_INTR_ENABLE_SETUP | | |
1069 | (u3d->vbus_valid_detect ? MV_U3D_INTR_ENABLE_VBUS_VALID : 0); | |
1070 | iowrite32(usbintr, &u3d->vuc_regs->intrenable); | |
1071 | ||
1072 | /* Enable ctrl ep */ | |
1073 | iowrite32(0x1, &u3d->vuc_regs->ctrlepenable); | |
1074 | ||
1075 | /* Set the Run bit in the command register */ | |
1076 | iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd); | |
1077 | dev_dbg(u3d->dev, "after u3d_start, USBCMD 0x%x\n", | |
1078 | ioread32(&u3d->op_regs->usbcmd)); | |
1079 | } | |
1080 | ||
1081 | static int mv_u3d_controller_reset(struct mv_u3d *u3d) | |
1082 | { | |
1083 | unsigned int loops; | |
1084 | u32 tmp; | |
1085 | ||
1086 | /* Stop the controller */ | |
1087 | tmp = ioread32(&u3d->op_regs->usbcmd); | |
1088 | tmp &= ~MV_U3D_CMD_RUN_STOP; | |
1089 | iowrite32(tmp, &u3d->op_regs->usbcmd); | |
1090 | ||
1091 | /* Reset the controller to get default values */ | |
1092 | iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd); | |
1093 | ||
1094 | /* wait for reset to complete */ | |
1095 | loops = LOOPS(MV_U3D_RESET_TIMEOUT); | |
1096 | while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) { | |
1097 | if (loops == 0) { | |
1098 | dev_err(u3d->dev, | |
1099 | "Wait for RESET completed TIMEOUT\n"); | |
1100 | return -ETIMEDOUT; | |
1101 | } | |
1102 | loops--; | |
1103 | udelay(LOOPS_USEC); | |
1104 | } | |
1105 | ||
1106 | /* Configure the Endpoint Context Address */ | |
1107 | iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl); | |
1108 | iowrite32(0, &u3d->op_regs->dcbaaph); | |
1109 | ||
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | static int mv_u3d_enable(struct mv_u3d *u3d) | |
1114 | { | |
e01ee9f5 | 1115 | struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev); |
3d4eb9df YX |
1116 | int retval; |
1117 | ||
1118 | if (u3d->active) | |
1119 | return 0; | |
1120 | ||
1121 | if (!u3d->clock_gating) { | |
1122 | u3d->active = 1; | |
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | dev_dbg(u3d->dev, "enable u3d\n"); | |
1127 | clk_enable(u3d->clk); | |
1128 | if (pdata->phy_init) { | |
1129 | retval = pdata->phy_init(u3d->phy_regs); | |
1130 | if (retval) { | |
1131 | dev_err(u3d->dev, | |
1132 | "init phy error %d\n", retval); | |
1133 | clk_disable(u3d->clk); | |
1134 | return retval; | |
1135 | } | |
1136 | } | |
1137 | u3d->active = 1; | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | static void mv_u3d_disable(struct mv_u3d *u3d) | |
1143 | { | |
e01ee9f5 | 1144 | struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev); |
3d4eb9df YX |
1145 | if (u3d->clock_gating && u3d->active) { |
1146 | dev_dbg(u3d->dev, "disable u3d\n"); | |
1147 | if (pdata->phy_deinit) | |
1148 | pdata->phy_deinit(u3d->phy_regs); | |
1149 | clk_disable(u3d->clk); | |
1150 | u3d->active = 0; | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | static int mv_u3d_vbus_session(struct usb_gadget *gadget, int is_active) | |
1155 | { | |
1156 | struct mv_u3d *u3d; | |
1157 | unsigned long flags; | |
1158 | int retval = 0; | |
1159 | ||
1160 | u3d = container_of(gadget, struct mv_u3d, gadget); | |
1161 | ||
1162 | spin_lock_irqsave(&u3d->lock, flags); | |
1163 | ||
1164 | u3d->vbus_active = (is_active != 0); | |
1165 | dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n", | |
1166 | __func__, u3d->softconnect, u3d->vbus_active); | |
1167 | /* | |
1168 | * 1. external VBUS detect: we can disable/enable clock on demand. | |
1169 | * 2. UDC VBUS detect: we have to enable clock all the time. | |
1170 | * 3. No VBUS detect: we have to enable clock all the time. | |
1171 | */ | |
1172 | if (u3d->driver && u3d->softconnect && u3d->vbus_active) { | |
1173 | retval = mv_u3d_enable(u3d); | |
1174 | if (retval == 0) { | |
1175 | /* | |
1176 | * after clock is disabled, we lost all the register | |
1177 | * context. We have to re-init registers | |
1178 | */ | |
1179 | mv_u3d_controller_reset(u3d); | |
1180 | mv_u3d_ep0_reset(u3d); | |
1181 | mv_u3d_controller_start(u3d); | |
1182 | } | |
1183 | } else if (u3d->driver && u3d->softconnect) { | |
1184 | if (!u3d->active) | |
1185 | goto out; | |
1186 | ||
1187 | /* stop all the transfer in queue*/ | |
1188 | mv_u3d_stop_activity(u3d, u3d->driver); | |
1189 | mv_u3d_controller_stop(u3d); | |
1190 | mv_u3d_disable(u3d); | |
1191 | } | |
1192 | ||
1193 | out: | |
1194 | spin_unlock_irqrestore(&u3d->lock, flags); | |
1195 | return retval; | |
1196 | } | |
1197 | ||
1198 | /* constrain controller's VBUS power usage | |
1199 | * This call is used by gadget drivers during SET_CONFIGURATION calls, | |
1200 | * reporting how much power the device may consume. For example, this | |
1201 | * could affect how quickly batteries are recharged. | |
1202 | * | |
1203 | * Returns zero on success, else negative errno. | |
1204 | */ | |
1205 | static int mv_u3d_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1206 | { | |
1207 | struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget); | |
1208 | ||
1209 | u3d->power = mA; | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | static int mv_u3d_pullup(struct usb_gadget *gadget, int is_on) | |
1215 | { | |
1216 | struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget); | |
1217 | unsigned long flags; | |
1218 | int retval = 0; | |
1219 | ||
1220 | spin_lock_irqsave(&u3d->lock, flags); | |
1221 | ||
1222 | dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n", | |
1223 | __func__, u3d->softconnect, u3d->vbus_active); | |
1224 | u3d->softconnect = (is_on != 0); | |
1225 | if (u3d->driver && u3d->softconnect && u3d->vbus_active) { | |
1226 | retval = mv_u3d_enable(u3d); | |
1227 | if (retval == 0) { | |
1228 | /* | |
1229 | * after clock is disabled, we lost all the register | |
1230 | * context. We have to re-init registers | |
1231 | */ | |
1232 | mv_u3d_controller_reset(u3d); | |
1233 | mv_u3d_ep0_reset(u3d); | |
1234 | mv_u3d_controller_start(u3d); | |
1235 | } | |
1236 | } else if (u3d->driver && u3d->vbus_active) { | |
1237 | /* stop all the transfer in queue*/ | |
1238 | mv_u3d_stop_activity(u3d, u3d->driver); | |
1239 | mv_u3d_controller_stop(u3d); | |
1240 | mv_u3d_disable(u3d); | |
1241 | } | |
1242 | ||
1243 | spin_unlock_irqrestore(&u3d->lock, flags); | |
1244 | ||
1245 | return retval; | |
1246 | } | |
1247 | ||
1248 | static int mv_u3d_start(struct usb_gadget *g, | |
1249 | struct usb_gadget_driver *driver) | |
1250 | { | |
1251 | struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget); | |
e01ee9f5 | 1252 | struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev); |
3d4eb9df YX |
1253 | unsigned long flags; |
1254 | ||
1255 | if (u3d->driver) | |
1256 | return -EBUSY; | |
1257 | ||
1258 | spin_lock_irqsave(&u3d->lock, flags); | |
1259 | ||
1260 | if (!u3d->clock_gating) { | |
1261 | clk_enable(u3d->clk); | |
1262 | if (pdata->phy_init) | |
1263 | pdata->phy_init(u3d->phy_regs); | |
1264 | } | |
1265 | ||
1266 | /* hook up the driver ... */ | |
1267 | driver->driver.bus = NULL; | |
1268 | u3d->driver = driver; | |
3d4eb9df YX |
1269 | |
1270 | u3d->ep0_dir = USB_DIR_OUT; | |
1271 | ||
1272 | spin_unlock_irqrestore(&u3d->lock, flags); | |
1273 | ||
1274 | u3d->vbus_valid_detect = 1; | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | static int mv_u3d_stop(struct usb_gadget *g, | |
1280 | struct usb_gadget_driver *driver) | |
1281 | { | |
1282 | struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget); | |
e01ee9f5 | 1283 | struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev); |
3d4eb9df YX |
1284 | unsigned long flags; |
1285 | ||
1286 | u3d->vbus_valid_detect = 0; | |
1287 | spin_lock_irqsave(&u3d->lock, flags); | |
1288 | ||
1289 | /* enable clock to access controller register */ | |
1290 | clk_enable(u3d->clk); | |
1291 | if (pdata->phy_init) | |
1292 | pdata->phy_init(u3d->phy_regs); | |
1293 | ||
1294 | mv_u3d_controller_stop(u3d); | |
1295 | /* stop all usb activities */ | |
1296 | u3d->gadget.speed = USB_SPEED_UNKNOWN; | |
1297 | mv_u3d_stop_activity(u3d, driver); | |
1298 | mv_u3d_disable(u3d); | |
1299 | ||
1300 | if (pdata->phy_deinit) | |
1301 | pdata->phy_deinit(u3d->phy_regs); | |
1302 | clk_disable(u3d->clk); | |
1303 | ||
1304 | spin_unlock_irqrestore(&u3d->lock, flags); | |
1305 | ||
3d4eb9df YX |
1306 | u3d->driver = NULL; |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
1311 | /* device controller usb_gadget_ops structure */ | |
1312 | static const struct usb_gadget_ops mv_u3d_ops = { | |
1313 | /* notify controller that VBUS is powered or not */ | |
1314 | .vbus_session = mv_u3d_vbus_session, | |
1315 | ||
1316 | /* constrain controller's VBUS power usage */ | |
1317 | .vbus_draw = mv_u3d_vbus_draw, | |
1318 | ||
1319 | .pullup = mv_u3d_pullup, | |
1320 | .udc_start = mv_u3d_start, | |
1321 | .udc_stop = mv_u3d_stop, | |
1322 | }; | |
1323 | ||
1324 | static int mv_u3d_eps_init(struct mv_u3d *u3d) | |
1325 | { | |
1326 | struct mv_u3d_ep *ep; | |
1327 | char name[14]; | |
1328 | int i; | |
1329 | ||
1330 | /* initialize ep0, ep0 in/out use eps[1] */ | |
1331 | ep = &u3d->eps[1]; | |
1332 | ep->u3d = u3d; | |
1333 | strncpy(ep->name, "ep0", sizeof(ep->name)); | |
1334 | ep->ep.name = ep->name; | |
1335 | ep->ep.ops = &mv_u3d_ep_ops; | |
1336 | ep->wedge = 0; | |
1337 | ep->ep.maxpacket = MV_U3D_EP0_MAX_PKT_SIZE; | |
1338 | ep->ep_num = 0; | |
1339 | ep->ep.desc = &mv_u3d_ep0_desc; | |
1340 | INIT_LIST_HEAD(&ep->queue); | |
1341 | INIT_LIST_HEAD(&ep->req_list); | |
1342 | ep->ep_type = USB_ENDPOINT_XFER_CONTROL; | |
1343 | ||
1344 | /* add ep0 ep_context */ | |
1345 | ep->ep_context = &u3d->ep_context[1]; | |
1346 | ||
1347 | /* initialize other endpoints */ | |
1348 | for (i = 2; i < u3d->max_eps * 2; i++) { | |
1349 | ep = &u3d->eps[i]; | |
1350 | if (i & 1) { | |
1351 | snprintf(name, sizeof(name), "ep%din", i >> 1); | |
1352 | ep->direction = MV_U3D_EP_DIR_IN; | |
1353 | } else { | |
1354 | snprintf(name, sizeof(name), "ep%dout", i >> 1); | |
1355 | ep->direction = MV_U3D_EP_DIR_OUT; | |
1356 | } | |
1357 | ep->u3d = u3d; | |
1358 | strncpy(ep->name, name, sizeof(ep->name)); | |
1359 | ep->ep.name = ep->name; | |
1360 | ||
1361 | ep->ep.ops = &mv_u3d_ep_ops; | |
1362 | ep->ep.maxpacket = (unsigned short) ~0; | |
1363 | ep->ep_num = i / 2; | |
1364 | ||
1365 | INIT_LIST_HEAD(&ep->queue); | |
1366 | list_add_tail(&ep->ep.ep_list, &u3d->gadget.ep_list); | |
1367 | ||
1368 | INIT_LIST_HEAD(&ep->req_list); | |
1369 | spin_lock_init(&ep->req_lock); | |
1370 | ep->ep_context = &u3d->ep_context[i]; | |
1371 | } | |
1372 | ||
1373 | return 0; | |
1374 | } | |
1375 | ||
1376 | /* delete all endpoint requests, called with spinlock held */ | |
1377 | static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status) | |
1378 | { | |
1379 | /* endpoint fifo flush */ | |
1380 | mv_u3d_ep_fifo_flush(&ep->ep); | |
1381 | ||
1382 | while (!list_empty(&ep->queue)) { | |
1383 | struct mv_u3d_req *req = NULL; | |
1384 | req = list_entry(ep->queue.next, struct mv_u3d_req, queue); | |
1385 | mv_u3d_done(ep, req, status); | |
1386 | } | |
1387 | } | |
1388 | ||
1389 | /* stop all USB activities */ | |
1390 | static | |
1391 | void mv_u3d_stop_activity(struct mv_u3d *u3d, struct usb_gadget_driver *driver) | |
1392 | { | |
1393 | struct mv_u3d_ep *ep; | |
1394 | ||
1395 | mv_u3d_nuke(&u3d->eps[1], -ESHUTDOWN); | |
1396 | ||
1397 | list_for_each_entry(ep, &u3d->gadget.ep_list, ep.ep_list) { | |
1398 | mv_u3d_nuke(ep, -ESHUTDOWN); | |
1399 | } | |
1400 | ||
1401 | /* report disconnect; the driver is already quiesced */ | |
1402 | if (driver) { | |
1403 | spin_unlock(&u3d->lock); | |
1404 | driver->disconnect(&u3d->gadget); | |
1405 | spin_lock(&u3d->lock); | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | static void mv_u3d_irq_process_error(struct mv_u3d *u3d) | |
1410 | { | |
1411 | /* Increment the error count */ | |
1412 | u3d->errors++; | |
1413 | dev_err(u3d->dev, "%s\n", __func__); | |
1414 | } | |
1415 | ||
1416 | static void mv_u3d_irq_process_link_change(struct mv_u3d *u3d) | |
1417 | { | |
1418 | u32 linkchange; | |
1419 | ||
1420 | linkchange = ioread32(&u3d->vuc_regs->linkchange); | |
1421 | iowrite32(linkchange, &u3d->vuc_regs->linkchange); | |
1422 | ||
1423 | dev_dbg(u3d->dev, "linkchange: 0x%x\n", linkchange); | |
1424 | ||
1425 | if (linkchange & MV_U3D_LINK_CHANGE_LINK_UP) { | |
1426 | dev_dbg(u3d->dev, "link up: ltssm state: 0x%x\n", | |
1427 | ioread32(&u3d->vuc_regs->ltssmstate)); | |
1428 | ||
1429 | u3d->usb_state = USB_STATE_DEFAULT; | |
1430 | u3d->ep0_dir = MV_U3D_EP_DIR_OUT; | |
1431 | u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; | |
1432 | ||
1433 | /* set speed */ | |
1434 | u3d->gadget.speed = USB_SPEED_SUPER; | |
1435 | } | |
1436 | ||
1437 | if (linkchange & MV_U3D_LINK_CHANGE_SUSPEND) { | |
1438 | dev_dbg(u3d->dev, "link suspend\n"); | |
1439 | u3d->resume_state = u3d->usb_state; | |
1440 | u3d->usb_state = USB_STATE_SUSPENDED; | |
1441 | } | |
1442 | ||
1443 | if (linkchange & MV_U3D_LINK_CHANGE_RESUME) { | |
1444 | dev_dbg(u3d->dev, "link resume\n"); | |
1445 | u3d->usb_state = u3d->resume_state; | |
1446 | u3d->resume_state = 0; | |
1447 | } | |
1448 | ||
1449 | if (linkchange & MV_U3D_LINK_CHANGE_WRESET) { | |
1450 | dev_dbg(u3d->dev, "warm reset\n"); | |
1451 | u3d->usb_state = USB_STATE_POWERED; | |
1452 | } | |
1453 | ||
1454 | if (linkchange & MV_U3D_LINK_CHANGE_HRESET) { | |
1455 | dev_dbg(u3d->dev, "hot reset\n"); | |
1456 | u3d->usb_state = USB_STATE_DEFAULT; | |
1457 | } | |
1458 | ||
1459 | if (linkchange & MV_U3D_LINK_CHANGE_INACT) | |
1460 | dev_dbg(u3d->dev, "inactive\n"); | |
1461 | ||
1462 | if (linkchange & MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0) | |
1463 | dev_dbg(u3d->dev, "ss.disabled\n"); | |
1464 | ||
1465 | if (linkchange & MV_U3D_LINK_CHANGE_VBUS_INVALID) { | |
1466 | dev_dbg(u3d->dev, "vbus invalid\n"); | |
1467 | u3d->usb_state = USB_STATE_ATTACHED; | |
1468 | u3d->vbus_valid_detect = 1; | |
1469 | /* if external vbus detect is not supported, | |
1470 | * we handle it here. | |
1471 | */ | |
1472 | if (!u3d->vbus) { | |
1473 | spin_unlock(&u3d->lock); | |
1474 | mv_u3d_vbus_session(&u3d->gadget, 0); | |
1475 | spin_lock(&u3d->lock); | |
1476 | } | |
1477 | } | |
1478 | } | |
1479 | ||
1480 | static void mv_u3d_ch9setaddress(struct mv_u3d *u3d, | |
1481 | struct usb_ctrlrequest *setup) | |
1482 | { | |
1483 | u32 tmp; | |
1484 | ||
1485 | if (u3d->usb_state != USB_STATE_DEFAULT) { | |
1486 | dev_err(u3d->dev, | |
1487 | "%s, cannot setaddr in this state (%d)\n", | |
1488 | __func__, u3d->usb_state); | |
1489 | goto err; | |
1490 | } | |
1491 | ||
1492 | u3d->dev_addr = (u8)setup->wValue; | |
1493 | ||
1494 | dev_dbg(u3d->dev, "%s: 0x%x\n", __func__, u3d->dev_addr); | |
1495 | ||
1496 | if (u3d->dev_addr > 127) { | |
1497 | dev_err(u3d->dev, | |
1498 | "%s, u3d address is wrong (out of range)\n", __func__); | |
1499 | u3d->dev_addr = 0; | |
1500 | goto err; | |
1501 | } | |
1502 | ||
1503 | /* update usb state */ | |
1504 | u3d->usb_state = USB_STATE_ADDRESS; | |
1505 | ||
1506 | /* set the new address */ | |
1507 | tmp = ioread32(&u3d->vuc_regs->devaddrtiebrkr); | |
1508 | tmp &= ~0x7F; | |
1509 | tmp |= (u32)u3d->dev_addr; | |
1510 | iowrite32(tmp, &u3d->vuc_regs->devaddrtiebrkr); | |
1511 | ||
1512 | return; | |
1513 | err: | |
1514 | mv_u3d_ep0_stall(u3d); | |
1515 | } | |
1516 | ||
1517 | static int mv_u3d_is_set_configuration(struct usb_ctrlrequest *setup) | |
1518 | { | |
1519 | if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
1520 | if (setup->bRequest == USB_REQ_SET_CONFIGURATION) | |
1521 | return 1; | |
1522 | ||
1523 | return 0; | |
1524 | } | |
1525 | ||
1526 | static void mv_u3d_handle_setup_packet(struct mv_u3d *u3d, u8 ep_num, | |
1527 | struct usb_ctrlrequest *setup) | |
6fbb2f7d FB |
1528 | __releases(&u3c->lock) |
1529 | __acquires(&u3c->lock) | |
3d4eb9df YX |
1530 | { |
1531 | bool delegate = false; | |
1532 | ||
1533 | mv_u3d_nuke(&u3d->eps[ep_num * 2 + MV_U3D_EP_DIR_IN], -ESHUTDOWN); | |
1534 | ||
1535 | dev_dbg(u3d->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1536 | setup->bRequestType, setup->bRequest, | |
1537 | setup->wValue, setup->wIndex, setup->wLength); | |
1538 | ||
1539 | /* We process some stardard setup requests here */ | |
1540 | if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1541 | switch (setup->bRequest) { | |
1542 | case USB_REQ_GET_STATUS: | |
1543 | delegate = true; | |
1544 | break; | |
1545 | ||
1546 | case USB_REQ_SET_ADDRESS: | |
1547 | mv_u3d_ch9setaddress(u3d, setup); | |
1548 | break; | |
1549 | ||
1550 | case USB_REQ_CLEAR_FEATURE: | |
1551 | delegate = true; | |
1552 | break; | |
1553 | ||
1554 | case USB_REQ_SET_FEATURE: | |
1555 | delegate = true; | |
1556 | break; | |
1557 | ||
1558 | default: | |
1559 | delegate = true; | |
1560 | } | |
1561 | } else | |
1562 | delegate = true; | |
1563 | ||
1564 | /* delegate USB standard requests to the gadget driver */ | |
1565 | if (delegate == true) { | |
1566 | /* USB requests handled by gadget */ | |
1567 | if (setup->wLength) { | |
1568 | /* DATA phase from gadget, STATUS phase from u3d */ | |
1569 | u3d->ep0_dir = (setup->bRequestType & USB_DIR_IN) | |
1570 | ? MV_U3D_EP_DIR_IN : MV_U3D_EP_DIR_OUT; | |
1571 | spin_unlock(&u3d->lock); | |
1572 | if (u3d->driver->setup(&u3d->gadget, | |
1573 | &u3d->local_setup_buff) < 0) { | |
1574 | dev_err(u3d->dev, "setup error!\n"); | |
1575 | mv_u3d_ep0_stall(u3d); | |
1576 | } | |
1577 | spin_lock(&u3d->lock); | |
1578 | } else { | |
1579 | /* no DATA phase, STATUS phase from gadget */ | |
1580 | u3d->ep0_dir = MV_U3D_EP_DIR_IN; | |
1581 | u3d->ep0_state = MV_U3D_STATUS_STAGE; | |
1582 | spin_unlock(&u3d->lock); | |
1583 | if (u3d->driver->setup(&u3d->gadget, | |
1584 | &u3d->local_setup_buff) < 0) | |
1585 | mv_u3d_ep0_stall(u3d); | |
1586 | spin_lock(&u3d->lock); | |
1587 | } | |
1588 | ||
1589 | if (mv_u3d_is_set_configuration(setup)) { | |
1590 | dev_dbg(u3d->dev, "u3d configured\n"); | |
1591 | u3d->usb_state = USB_STATE_CONFIGURED; | |
1592 | } | |
1593 | } | |
1594 | } | |
1595 | ||
1596 | static void mv_u3d_get_setup_data(struct mv_u3d *u3d, u8 ep_num, u8 *buffer_ptr) | |
1597 | { | |
1598 | struct mv_u3d_ep_context *epcontext; | |
1599 | ||
1600 | epcontext = &u3d->ep_context[ep_num * 2 + MV_U3D_EP_DIR_IN]; | |
1601 | ||
1602 | /* Copy the setup packet to local buffer */ | |
1603 | memcpy(buffer_ptr, (u8 *) &epcontext->setup_buffer, 8); | |
1604 | } | |
1605 | ||
1606 | static void mv_u3d_irq_process_setup(struct mv_u3d *u3d) | |
1607 | { | |
1608 | u32 tmp, i; | |
1609 | /* Process all Setup packet received interrupts */ | |
1610 | tmp = ioread32(&u3d->vuc_regs->setuplock); | |
1611 | if (tmp) { | |
1612 | for (i = 0; i < u3d->max_eps; i++) { | |
1613 | if (tmp & (1 << i)) { | |
1614 | mv_u3d_get_setup_data(u3d, i, | |
1615 | (u8 *)(&u3d->local_setup_buff)); | |
1616 | mv_u3d_handle_setup_packet(u3d, i, | |
1617 | &u3d->local_setup_buff); | |
1618 | } | |
1619 | } | |
1620 | } | |
1621 | ||
1622 | iowrite32(tmp, &u3d->vuc_regs->setuplock); | |
1623 | } | |
1624 | ||
1625 | static void mv_u3d_irq_process_tr_complete(struct mv_u3d *u3d) | |
1626 | { | |
1627 | u32 tmp, bit_pos; | |
1628 | int i, ep_num = 0, direction = 0; | |
1629 | struct mv_u3d_ep *curr_ep; | |
1630 | struct mv_u3d_req *curr_req, *temp_req; | |
1631 | int status; | |
1632 | ||
1633 | tmp = ioread32(&u3d->vuc_regs->endcomplete); | |
1634 | ||
1635 | dev_dbg(u3d->dev, "tr_complete: ep: 0x%x\n", tmp); | |
1636 | if (!tmp) | |
1637 | return; | |
1638 | iowrite32(tmp, &u3d->vuc_regs->endcomplete); | |
1639 | ||
1640 | for (i = 0; i < u3d->max_eps * 2; i++) { | |
1641 | ep_num = i >> 1; | |
1642 | direction = i % 2; | |
1643 | ||
1644 | bit_pos = 1 << (ep_num + 16 * direction); | |
1645 | ||
1646 | if (!(bit_pos & tmp)) | |
1647 | continue; | |
1648 | ||
1649 | if (i == 0) | |
1650 | curr_ep = &u3d->eps[1]; | |
1651 | else | |
1652 | curr_ep = &u3d->eps[i]; | |
1653 | ||
1654 | /* remove req out of ep request list after completion */ | |
1655 | dev_dbg(u3d->dev, "tr comp: check req_list\n"); | |
1656 | spin_lock(&curr_ep->req_lock); | |
1657 | if (!list_empty(&curr_ep->req_list)) { | |
1658 | struct mv_u3d_req *req; | |
1659 | req = list_entry(curr_ep->req_list.next, | |
1660 | struct mv_u3d_req, list); | |
1661 | list_del_init(&req->list); | |
1662 | curr_ep->processing = 0; | |
1663 | } | |
1664 | spin_unlock(&curr_ep->req_lock); | |
1665 | ||
1666 | /* process the req queue until an uncomplete request */ | |
1667 | list_for_each_entry_safe(curr_req, temp_req, | |
1668 | &curr_ep->queue, queue) { | |
1669 | status = mv_u3d_process_ep_req(u3d, i, curr_req); | |
1670 | if (status) | |
1671 | break; | |
1672 | /* write back status to req */ | |
1673 | curr_req->req.status = status; | |
1674 | ||
1675 | /* ep0 request completion */ | |
1676 | if (ep_num == 0) { | |
1677 | mv_u3d_done(curr_ep, curr_req, 0); | |
1678 | break; | |
1679 | } else { | |
1680 | mv_u3d_done(curr_ep, curr_req, status); | |
1681 | } | |
1682 | } | |
1683 | ||
1684 | dev_dbg(u3d->dev, "call mv_u3d_start_queue from ep complete\n"); | |
1685 | mv_u3d_start_queue(curr_ep); | |
1686 | } | |
1687 | } | |
1688 | ||
1689 | static irqreturn_t mv_u3d_irq(int irq, void *dev) | |
1690 | { | |
1691 | struct mv_u3d *u3d = (struct mv_u3d *)dev; | |
1692 | u32 status, intr; | |
1693 | u32 bridgesetting; | |
1694 | u32 trbunderrun; | |
1695 | ||
1696 | spin_lock(&u3d->lock); | |
1697 | ||
1698 | status = ioread32(&u3d->vuc_regs->intrcause); | |
1699 | intr = ioread32(&u3d->vuc_regs->intrenable); | |
1700 | status &= intr; | |
1701 | ||
1702 | if (status == 0) { | |
1703 | spin_unlock(&u3d->lock); | |
1704 | dev_err(u3d->dev, "irq error!\n"); | |
1705 | return IRQ_NONE; | |
1706 | } | |
1707 | ||
1708 | if (status & MV_U3D_USBINT_VBUS_VALID) { | |
1709 | bridgesetting = ioread32(&u3d->vuc_regs->bridgesetting); | |
1710 | if (bridgesetting & MV_U3D_BRIDGE_SETTING_VBUS_VALID) { | |
1711 | /* write vbus valid bit of bridge setting to clear */ | |
1712 | bridgesetting = MV_U3D_BRIDGE_SETTING_VBUS_VALID; | |
1713 | iowrite32(bridgesetting, &u3d->vuc_regs->bridgesetting); | |
1714 | dev_dbg(u3d->dev, "vbus valid\n"); | |
1715 | ||
1716 | u3d->usb_state = USB_STATE_POWERED; | |
1717 | u3d->vbus_valid_detect = 0; | |
1718 | /* if external vbus detect is not supported, | |
1719 | * we handle it here. | |
1720 | */ | |
1721 | if (!u3d->vbus) { | |
1722 | spin_unlock(&u3d->lock); | |
1723 | mv_u3d_vbus_session(&u3d->gadget, 1); | |
1724 | spin_lock(&u3d->lock); | |
1725 | } | |
1726 | } else | |
1727 | dev_err(u3d->dev, "vbus bit is not set\n"); | |
1728 | } | |
1729 | ||
1730 | /* RX data is already in the 16KB FIFO.*/ | |
1731 | if (status & MV_U3D_USBINT_UNDER_RUN) { | |
1732 | trbunderrun = ioread32(&u3d->vuc_regs->trbunderrun); | |
1733 | dev_err(u3d->dev, "under run, ep%d\n", trbunderrun); | |
1734 | iowrite32(trbunderrun, &u3d->vuc_regs->trbunderrun); | |
1735 | mv_u3d_irq_process_error(u3d); | |
1736 | } | |
1737 | ||
1738 | if (status & (MV_U3D_USBINT_RXDESC_ERR | MV_U3D_USBINT_TXDESC_ERR)) { | |
1739 | /* write one to clear */ | |
1740 | iowrite32(status & (MV_U3D_USBINT_RXDESC_ERR | |
1741 | | MV_U3D_USBINT_TXDESC_ERR), | |
1742 | &u3d->vuc_regs->intrcause); | |
1743 | dev_err(u3d->dev, "desc err 0x%x\n", status); | |
1744 | mv_u3d_irq_process_error(u3d); | |
1745 | } | |
1746 | ||
1747 | if (status & MV_U3D_USBINT_LINK_CHG) | |
1748 | mv_u3d_irq_process_link_change(u3d); | |
1749 | ||
1750 | if (status & MV_U3D_USBINT_TX_COMPLETE) | |
1751 | mv_u3d_irq_process_tr_complete(u3d); | |
1752 | ||
1753 | if (status & MV_U3D_USBINT_RX_COMPLETE) | |
1754 | mv_u3d_irq_process_tr_complete(u3d); | |
1755 | ||
1756 | if (status & MV_U3D_USBINT_SETUP) | |
1757 | mv_u3d_irq_process_setup(u3d); | |
1758 | ||
1759 | spin_unlock(&u3d->lock); | |
1760 | return IRQ_HANDLED; | |
1761 | } | |
1762 | ||
fb4e98ab | 1763 | static int mv_u3d_remove(struct platform_device *dev) |
3d4eb9df YX |
1764 | { |
1765 | struct mv_u3d *u3d = platform_get_drvdata(dev); | |
1766 | ||
1767 | BUG_ON(u3d == NULL); | |
1768 | ||
1769 | usb_del_gadget_udc(&u3d->gadget); | |
1770 | ||
1771 | /* free memory allocated in probe */ | |
1772 | if (u3d->trb_pool) | |
1773 | dma_pool_destroy(u3d->trb_pool); | |
1774 | ||
1775 | if (u3d->ep_context) | |
1776 | dma_free_coherent(&dev->dev, u3d->ep_context_size, | |
1777 | u3d->ep_context, u3d->ep_context_dma); | |
1778 | ||
1779 | kfree(u3d->eps); | |
1780 | ||
1781 | if (u3d->irq) | |
5257a633 | 1782 | free_irq(u3d->irq, u3d); |
3d4eb9df YX |
1783 | |
1784 | if (u3d->cap_regs) | |
1785 | iounmap(u3d->cap_regs); | |
1786 | u3d->cap_regs = NULL; | |
1787 | ||
1788 | kfree(u3d->status_req); | |
1789 | ||
1790 | clk_put(u3d->clk); | |
1791 | ||
3d4eb9df YX |
1792 | kfree(u3d); |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | ||
1797 | static int mv_u3d_probe(struct platform_device *dev) | |
1798 | { | |
1799 | struct mv_u3d *u3d = NULL; | |
e01ee9f5 | 1800 | struct mv_usb_platform_data *pdata = dev_get_platdata(&dev->dev); |
3d4eb9df YX |
1801 | int retval = 0; |
1802 | struct resource *r; | |
1803 | size_t size; | |
1804 | ||
e01ee9f5 | 1805 | if (!dev_get_platdata(&dev->dev)) { |
3d4eb9df YX |
1806 | dev_err(&dev->dev, "missing platform_data\n"); |
1807 | retval = -ENODEV; | |
1808 | goto err_pdata; | |
1809 | } | |
1810 | ||
1811 | u3d = kzalloc(sizeof(*u3d), GFP_KERNEL); | |
1812 | if (!u3d) { | |
1813 | dev_err(&dev->dev, "failed to allocate memory for u3d\n"); | |
1814 | retval = -ENOMEM; | |
1815 | goto err_alloc_private; | |
1816 | } | |
1817 | ||
1818 | spin_lock_init(&u3d->lock); | |
1819 | ||
1820 | platform_set_drvdata(dev, u3d); | |
1821 | ||
1822 | u3d->dev = &dev->dev; | |
1823 | u3d->vbus = pdata->vbus; | |
1824 | ||
65cd3f2b | 1825 | u3d->clk = clk_get(&dev->dev, NULL); |
3d4eb9df YX |
1826 | if (IS_ERR(u3d->clk)) { |
1827 | retval = PTR_ERR(u3d->clk); | |
1828 | goto err_get_clk; | |
1829 | } | |
1830 | ||
1831 | r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs"); | |
1832 | if (!r) { | |
1833 | dev_err(&dev->dev, "no I/O memory resource defined\n"); | |
1834 | retval = -ENODEV; | |
1835 | goto err_get_cap_regs; | |
1836 | } | |
1837 | ||
1838 | u3d->cap_regs = (struct mv_u3d_cap_regs __iomem *) | |
1839 | ioremap(r->start, resource_size(r)); | |
1840 | if (!u3d->cap_regs) { | |
1841 | dev_err(&dev->dev, "failed to map I/O memory\n"); | |
1842 | retval = -EBUSY; | |
1843 | goto err_map_cap_regs; | |
1844 | } else { | |
e6667ef7 FB |
1845 | dev_dbg(&dev->dev, "cap_regs address: 0x%lx/0x%lx\n", |
1846 | (unsigned long) r->start, | |
1847 | (unsigned long) u3d->cap_regs); | |
3d4eb9df YX |
1848 | } |
1849 | ||
1850 | /* we will access controller register, so enable the u3d controller */ | |
1851 | clk_enable(u3d->clk); | |
1852 | ||
1853 | if (pdata->phy_init) { | |
1854 | retval = pdata->phy_init(u3d->phy_regs); | |
1855 | if (retval) { | |
1856 | dev_err(&dev->dev, "init phy error %d\n", retval); | |
1857 | goto err_u3d_enable; | |
1858 | } | |
1859 | } | |
1860 | ||
e6667ef7 | 1861 | u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs |
3d4eb9df YX |
1862 | + MV_U3D_USB3_OP_REGS_OFFSET); |
1863 | ||
e6667ef7 | 1864 | u3d->vuc_regs = (struct mv_u3d_vuc_regs __iomem *)(u3d->cap_regs |
3d4eb9df YX |
1865 | + ioread32(&u3d->cap_regs->vuoff)); |
1866 | ||
1867 | u3d->max_eps = 16; | |
1868 | ||
1869 | /* | |
1870 | * some platform will use usb to download image, it may not disconnect | |
1871 | * usb gadget before loading kernel. So first stop u3d here. | |
1872 | */ | |
1873 | mv_u3d_controller_stop(u3d); | |
1874 | iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause); | |
1875 | ||
1876 | if (pdata->phy_deinit) | |
1877 | pdata->phy_deinit(u3d->phy_regs); | |
1878 | clk_disable(u3d->clk); | |
1879 | ||
1880 | size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2; | |
1881 | size = (size + MV_U3D_EP_CONTEXT_ALIGNMENT - 1) | |
1882 | & ~(MV_U3D_EP_CONTEXT_ALIGNMENT - 1); | |
1883 | u3d->ep_context = dma_alloc_coherent(&dev->dev, size, | |
1884 | &u3d->ep_context_dma, GFP_KERNEL); | |
1885 | if (!u3d->ep_context) { | |
1886 | dev_err(&dev->dev, "allocate ep context memory failed\n"); | |
1887 | retval = -ENOMEM; | |
1888 | goto err_alloc_ep_context; | |
1889 | } | |
1890 | u3d->ep_context_size = size; | |
1891 | ||
1892 | /* create TRB dma_pool resource */ | |
1893 | u3d->trb_pool = dma_pool_create("u3d_trb", | |
1894 | &dev->dev, | |
1895 | sizeof(struct mv_u3d_trb_hw), | |
1896 | MV_U3D_TRB_ALIGNMENT, | |
1897 | MV_U3D_DMA_BOUNDARY); | |
1898 | ||
1899 | if (!u3d->trb_pool) { | |
1900 | retval = -ENOMEM; | |
1901 | goto err_alloc_trb_pool; | |
1902 | } | |
1903 | ||
1904 | size = u3d->max_eps * sizeof(struct mv_u3d_ep) * 2; | |
1905 | u3d->eps = kzalloc(size, GFP_KERNEL); | |
1906 | if (!u3d->eps) { | |
1907 | dev_err(&dev->dev, "allocate ep memory failed\n"); | |
1908 | retval = -ENOMEM; | |
1909 | goto err_alloc_eps; | |
1910 | } | |
1911 | ||
1912 | /* initialize ep0 status request structure */ | |
1913 | u3d->status_req = kzalloc(sizeof(struct mv_u3d_req) + 8, GFP_KERNEL); | |
1914 | if (!u3d->status_req) { | |
1915 | dev_err(&dev->dev, "allocate status_req memory failed\n"); | |
1916 | retval = -ENOMEM; | |
1917 | goto err_alloc_status_req; | |
1918 | } | |
1919 | INIT_LIST_HEAD(&u3d->status_req->queue); | |
1920 | ||
1921 | /* allocate a small amount of memory to get valid address */ | |
1922 | u3d->status_req->req.buf = (char *)u3d->status_req | |
1923 | + sizeof(struct mv_u3d_req); | |
1924 | u3d->status_req->req.dma = virt_to_phys(u3d->status_req->req.buf); | |
1925 | ||
1926 | u3d->resume_state = USB_STATE_NOTATTACHED; | |
1927 | u3d->usb_state = USB_STATE_ATTACHED; | |
1928 | u3d->ep0_dir = MV_U3D_EP_DIR_OUT; | |
1929 | u3d->remote_wakeup = 0; | |
1930 | ||
1931 | r = platform_get_resource(dev, IORESOURCE_IRQ, 0); | |
1932 | if (!r) { | |
1933 | dev_err(&dev->dev, "no IRQ resource defined\n"); | |
1934 | retval = -ENODEV; | |
1935 | goto err_get_irq; | |
1936 | } | |
1937 | u3d->irq = r->start; | |
1938 | if (request_irq(u3d->irq, mv_u3d_irq, | |
1939 | IRQF_DISABLED | IRQF_SHARED, driver_name, u3d)) { | |
1940 | u3d->irq = 0; | |
1941 | dev_err(&dev->dev, "Request irq %d for u3d failed\n", | |
1942 | u3d->irq); | |
1943 | retval = -ENODEV; | |
1944 | goto err_request_irq; | |
1945 | } | |
1946 | ||
1947 | /* initialize gadget structure */ | |
1948 | u3d->gadget.ops = &mv_u3d_ops; /* usb_gadget_ops */ | |
1949 | u3d->gadget.ep0 = &u3d->eps[1].ep; /* gadget ep0 */ | |
1950 | INIT_LIST_HEAD(&u3d->gadget.ep_list); /* ep_list */ | |
1951 | u3d->gadget.speed = USB_SPEED_UNKNOWN; /* speed */ | |
1952 | ||
1953 | /* the "gadget" abstracts/virtualizes the controller */ | |
3d4eb9df | 1954 | u3d->gadget.name = driver_name; /* gadget name */ |
3d4eb9df YX |
1955 | |
1956 | mv_u3d_eps_init(u3d); | |
1957 | ||
1958 | /* external vbus detection */ | |
1959 | if (u3d->vbus) { | |
1960 | u3d->clock_gating = 1; | |
1961 | dev_err(&dev->dev, "external vbus detection\n"); | |
1962 | } | |
1963 | ||
1964 | if (!u3d->clock_gating) | |
1965 | u3d->vbus_active = 1; | |
1966 | ||
1967 | /* enable usb3 controller vbus detection */ | |
1968 | u3d->vbus_valid_detect = 1; | |
1969 | ||
1970 | retval = usb_add_gadget_udc(&dev->dev, &u3d->gadget); | |
1971 | if (retval) | |
1972 | goto err_unregister; | |
1973 | ||
1974 | dev_dbg(&dev->dev, "successful probe usb3 device %s clock gating.\n", | |
1975 | u3d->clock_gating ? "with" : "without"); | |
1976 | ||
1977 | return 0; | |
1978 | ||
1979 | err_unregister: | |
5257a633 | 1980 | free_irq(u3d->irq, u3d); |
3d4eb9df YX |
1981 | err_request_irq: |
1982 | err_get_irq: | |
1983 | kfree(u3d->status_req); | |
1984 | err_alloc_status_req: | |
1985 | kfree(u3d->eps); | |
1986 | err_alloc_eps: | |
1987 | dma_pool_destroy(u3d->trb_pool); | |
1988 | err_alloc_trb_pool: | |
1989 | dma_free_coherent(&dev->dev, u3d->ep_context_size, | |
1990 | u3d->ep_context, u3d->ep_context_dma); | |
1991 | err_alloc_ep_context: | |
1992 | if (pdata->phy_deinit) | |
1993 | pdata->phy_deinit(u3d->phy_regs); | |
1994 | clk_disable(u3d->clk); | |
1995 | err_u3d_enable: | |
1996 | iounmap(u3d->cap_regs); | |
1997 | err_map_cap_regs: | |
1998 | err_get_cap_regs: | |
1999 | err_get_clk: | |
2000 | clk_put(u3d->clk); | |
3d4eb9df YX |
2001 | kfree(u3d); |
2002 | err_alloc_private: | |
2003 | err_pdata: | |
2004 | return retval; | |
2005 | } | |
2006 | ||
4895a2ee | 2007 | #ifdef CONFIG_PM_SLEEP |
3d4eb9df YX |
2008 | static int mv_u3d_suspend(struct device *dev) |
2009 | { | |
2010 | struct mv_u3d *u3d = dev_get_drvdata(dev); | |
2011 | ||
2012 | /* | |
2013 | * only cable is unplugged, usb can suspend. | |
2014 | * So do not care about clock_gating == 1, it is handled by | |
2015 | * vbus session. | |
2016 | */ | |
2017 | if (!u3d->clock_gating) { | |
2018 | mv_u3d_controller_stop(u3d); | |
2019 | ||
2020 | spin_lock_irq(&u3d->lock); | |
2021 | /* stop all usb activities */ | |
2022 | mv_u3d_stop_activity(u3d, u3d->driver); | |
2023 | spin_unlock_irq(&u3d->lock); | |
2024 | ||
2025 | mv_u3d_disable(u3d); | |
2026 | } | |
2027 | ||
2028 | return 0; | |
2029 | } | |
2030 | ||
2031 | static int mv_u3d_resume(struct device *dev) | |
2032 | { | |
2033 | struct mv_u3d *u3d = dev_get_drvdata(dev); | |
2034 | int retval; | |
2035 | ||
2036 | if (!u3d->clock_gating) { | |
2037 | retval = mv_u3d_enable(u3d); | |
2038 | if (retval) | |
2039 | return retval; | |
2040 | ||
2041 | if (u3d->driver && u3d->softconnect) { | |
2042 | mv_u3d_controller_reset(u3d); | |
2043 | mv_u3d_ep0_reset(u3d); | |
2044 | mv_u3d_controller_start(u3d); | |
2045 | } | |
2046 | } | |
2047 | ||
2048 | return 0; | |
2049 | } | |
3d4eb9df YX |
2050 | #endif |
2051 | ||
4895a2ee JH |
2052 | static SIMPLE_DEV_PM_OPS(mv_u3d_pm_ops, mv_u3d_suspend, mv_u3d_resume); |
2053 | ||
3d4eb9df YX |
2054 | static void mv_u3d_shutdown(struct platform_device *dev) |
2055 | { | |
dae8eadf | 2056 | struct mv_u3d *u3d = platform_get_drvdata(dev); |
3d4eb9df YX |
2057 | u32 tmp; |
2058 | ||
2059 | tmp = ioread32(&u3d->op_regs->usbcmd); | |
2060 | tmp &= ~MV_U3D_CMD_RUN_STOP; | |
2061 | iowrite32(tmp, &u3d->op_regs->usbcmd); | |
2062 | } | |
2063 | ||
2064 | static struct platform_driver mv_u3d_driver = { | |
2065 | .probe = mv_u3d_probe, | |
2cd807e7 | 2066 | .remove = mv_u3d_remove, |
3d4eb9df YX |
2067 | .shutdown = mv_u3d_shutdown, |
2068 | .driver = { | |
2069 | .owner = THIS_MODULE, | |
2070 | .name = "mv-u3d", | |
3d4eb9df | 2071 | .pm = &mv_u3d_pm_ops, |
3d4eb9df YX |
2072 | }, |
2073 | }; | |
2074 | ||
2075 | module_platform_driver(mv_u3d_driver); | |
2076 | MODULE_ALIAS("platform:mv-u3d"); | |
2077 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2078 | MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>"); | |
2079 | MODULE_LICENSE("GPL"); |