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usb: gadget: mv_udc: refine the clock relative code
[deliverable/linux.git] / drivers / usb / gadget / mv_udc_core.c
CommitLineData
dde34cc5
NZ		 1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 * Author: Chao Xie <chao.xie@marvell.com>
4 * Neil Zhang <zhangwm@marvell.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
e7cddda4 12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/dmapool.h>
16#include <linux/kernel.h>
17#include <linux/delay.h>
18#include <linux/ioport.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/errno.h>
22#include <linux/init.h>
23#include <linux/timer.h>
24#include <linux/list.h>
25#include <linux/interrupt.h>
26#include <linux/moduleparam.h>
27#include <linux/device.h>
28#include <linux/usb/ch9.h>
29#include <linux/usb/gadget.h>
30#include <linux/usb/otg.h>
31#include <linux/pm.h>
32#include <linux/io.h>
33#include <linux/irq.h>
34#include <linux/platform_device.h>
35#include <linux/clk.h>
dde34cc5 36#include <linux/platform_data/mv_usb.h>
e7cddda4 37#include <asm/system.h>
38#include <asm/unaligned.h>
39
40#include "mv_udc.h"
41
42#define DRIVER_DESC "Marvell PXA USB Device Controller driver"
43#define DRIVER_VERSION "8 Nov 2010"
44
45#define ep_dir(ep) (((ep)->ep_num == 0) ? \
46 ((ep)->udc->ep0_dir) : ((ep)->direction))
47
48/* timeout value -- usec */
49#define RESET_TIMEOUT 10000
50#define FLUSH_TIMEOUT 10000
51#define EPSTATUS_TIMEOUT 10000
52#define PRIME_TIMEOUT 10000
53#define READSAFE_TIMEOUT 1000
54#define DTD_TIMEOUT 1000
55
56#define LOOPS_USEC_SHIFT 4
57#define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
58#define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
59
dde34cc5
NZ		 60static DECLARE_COMPLETION(release_done);
61
e7cddda4 62static const char driver_name[] = "mv_udc";
63static const char driver_desc[] = DRIVER_DESC;
64
65/* controller device global variable */
66static struct mv_udc *the_controller;
67int mv_usb_otgsc;
68
69static void nuke(struct mv_ep *ep, int status);
1aec033b 70static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
e7cddda4 71
72/* for endpoint 0 operations */
73static const struct usb_endpoint_descriptor mv_ep0_desc = {
74 .bLength = USB_DT_ENDPOINT_SIZE,
75 .bDescriptorType = USB_DT_ENDPOINT,
76 .bEndpointAddress = 0,
77 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
78 .wMaxPacketSize = EP0_MAX_PKT_SIZE,
79};
80
81static void ep0_reset(struct mv_udc *udc)
82{
83 struct mv_ep *ep;
84 u32 epctrlx;
85 int i = 0;
86
87 /* ep0 in and out */
88 for (i = 0; i < 2; i++) {
89 ep = &udc->eps[i];
90 ep->udc = udc;
91
92 /* ep0 dQH */
93 ep->dqh = &udc->ep_dqh[i];
94
95 /* configure ep0 endpoint capabilities in dQH */
96 ep->dqh->max_packet_length =
97 (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
98 | EP_QUEUE_HEAD_IOS;
99
fbebe1f0
NZ		 100 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
101
e7cddda4 102 epctrlx = readl(&udc->op_regs->epctrlx[0]);
103 if (i) { /* TX */
43ad9f3f 104 epctrlx |= EPCTRL_TX_ENABLE
e7cddda4 105 | (USB_ENDPOINT_XFER_CONTROL
106 << EPCTRL_TX_EP_TYPE_SHIFT);
107
108 } else { /* RX */
43ad9f3f 109 epctrlx |= EPCTRL_RX_ENABLE
e7cddda4 110 | (USB_ENDPOINT_XFER_CONTROL
111 << EPCTRL_RX_EP_TYPE_SHIFT);
112 }
113
114 writel(epctrlx, &udc->op_regs->epctrlx[0]);
115 }
116}
117
118/* protocol ep0 stall, will automatically be cleared on new transaction */
119static void ep0_stall(struct mv_udc *udc)
120{
121 u32 epctrlx;
122
123 /* set TX and RX to stall */
124 epctrlx = readl(&udc->op_regs->epctrlx[0]);
125 epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
126 writel(epctrlx, &udc->op_regs->epctrlx[0]);
127
128 /* update ep0 state */
129 udc->ep0_state = WAIT_FOR_SETUP;
130 udc->ep0_dir = EP_DIR_OUT;
131}
132
133static int process_ep_req(struct mv_udc *udc, int index,
134 struct mv_req *curr_req)
135{
136 struct mv_dtd *curr_dtd;
137 struct mv_dqh *curr_dqh;
138 int td_complete, actual, remaining_length;
139 int i, direction;
140 int retval = 0;
141 u32 errors;
daec765d 142 u32 bit_pos;
e7cddda4 143
144 curr_dqh = &udc->ep_dqh[index];
145 direction = index % 2;
146
147 curr_dtd = curr_req->head;
148 td_complete = 0;
149 actual = curr_req->req.length;
150
151 for (i = 0; i < curr_req->dtd_count; i++) {
152 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
153 dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
154 udc->eps[index].name);
155 return 1;
156 }
157
158 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
159 if (!errors) {
daec765d 160 remaining_length =
e7cddda4 161 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
162 >> DTD_LENGTH_BIT_POS;
163 actual -= remaining_length;
daec765d
NZ		 164
165 if (remaining_length) {
166 if (direction) {
167 dev_dbg(&udc->dev->dev,
168 "TX dTD remains data\n");
169 retval = -EPROTO;
170 break;
171 } else
172 break;
173 }
e7cddda4 174 } else {
175 dev_info(&udc->dev->dev,
176 "complete_tr error: ep=%d %s: error = 0x%x\n",
177 index >> 1, direction ? "SEND" : "RECV",
178 errors);
179 if (errors & DTD_STATUS_HALTED) {
180 /* Clear the errors and Halt condition */
181 curr_dqh->size_ioc_int_sts &= ~errors;
182 retval = -EPIPE;
183 } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
184 retval = -EPROTO;
185 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
186 retval = -EILSEQ;
187 }
188 }
189 if (i != curr_req->dtd_count - 1)
190 curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
191 }
192 if (retval)
193 return retval;
194
daec765d
NZ		 195 if (direction == EP_DIR_OUT)
196 bit_pos = 1 << curr_req->ep->ep_num;
197 else
198 bit_pos = 1 << (16 + curr_req->ep->ep_num);
199
200 while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
201 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
202 while (readl(&udc->op_regs->epstatus) & bit_pos)
203 udelay(1);
204 break;
205 }
206 udelay(1);
207 }
208
e7cddda4 209 curr_req->req.actual = actual;
210
211 return 0;
212}
213
214/*
215 * done() - retire a request; caller blocked irqs
216 * @status : request status to be set, only works when
217 * request is still in progress.
218 */
219static void done(struct mv_ep *ep, struct mv_req *req, int status)
220{
221 struct mv_udc *udc = NULL;
222 unsigned char stopped = ep->stopped;
223 struct mv_dtd *curr_td, *next_td;
224 int j;
225
226 udc = (struct mv_udc *)ep->udc;
227 /* Removed the req from fsl_ep->queue */
228 list_del_init(&req->queue);
229
230 /* req.status should be set as -EINPROGRESS in ep_queue() */
231 if (req->req.status == -EINPROGRESS)
232 req->req.status = status;
233 else
234 status = req->req.status;
235
236 /* Free dtd for the request */
237 next_td = req->head;
238 for (j = 0; j < req->dtd_count; j++) {
239 curr_td = next_td;
240 if (j != req->dtd_count - 1)
241 next_td = curr_td->next_dtd_virt;
242 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
243 }
244
245 if (req->mapped) {
246 dma_unmap_single(ep->udc->gadget.dev.parent,
247 req->req.dma, req->req.length,
248 ((ep_dir(ep) == EP_DIR_IN) ?
249 DMA_TO_DEVICE : DMA_FROM_DEVICE));
250 req->req.dma = DMA_ADDR_INVALID;
251 req->mapped = 0;
252 } else
253 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
254 req->req.dma, req->req.length,
255 ((ep_dir(ep) == EP_DIR_IN) ?
256 DMA_TO_DEVICE : DMA_FROM_DEVICE));
257
258 if (status && (status != -ESHUTDOWN))
259 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
260 ep->ep.name, &req->req, status,
261 req->req.actual, req->req.length);
262
263 ep->stopped = 1;
264
265 spin_unlock(&ep->udc->lock);
266 /*
267 * complete() is from gadget layer,
268 * eg fsg->bulk_in_complete()
269 */
270 if (req->req.complete)
271 req->req.complete(&ep->ep, &req->req);
272
273 spin_lock(&ep->udc->lock);
274 ep->stopped = stopped;
275}
276
277static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
278{
279 u32 tmp, epstatus, bit_pos, direction;
280 struct mv_udc *udc;
281 struct mv_dqh *dqh;
282 unsigned int loops;
283 int readsafe, retval = 0;
284
285 udc = ep->udc;
286 direction = ep_dir(ep);
287 dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
288 bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
289
290 /* check if the pipe is empty */
291 if (!(list_empty(&ep->queue))) {
292 struct mv_req *lastreq;
293 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
294 lastreq->tail->dtd_next =
295 req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
296 if (readl(&udc->op_regs->epprime) & bit_pos) {
297 loops = LOOPS(PRIME_TIMEOUT);
298 while (readl(&udc->op_regs->epprime) & bit_pos) {
299 if (loops == 0) {
300 retval = -ETIME;
301 goto done;
302 }
303 udelay(LOOPS_USEC);
304 loops--;
305 }
306 if (readl(&udc->op_regs->epstatus) & bit_pos)
307 goto done;
308 }
309 readsafe = 0;
310 loops = LOOPS(READSAFE_TIMEOUT);
311 while (readsafe == 0) {
312 if (loops == 0) {
313 retval = -ETIME;
314 goto done;
315 }
316 /* start with setting the semaphores */
317 tmp = readl(&udc->op_regs->usbcmd);
318 tmp |= USBCMD_ATDTW_TRIPWIRE_SET;
319 writel(tmp, &udc->op_regs->usbcmd);
320
321 /* read the endpoint status */
322 epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
323
324 /*
325 * Reread the ATDTW semaphore bit to check if it is
326 * cleared. When hardware see a hazard, it will clear
327 * the bit or else we remain set to 1 and we can
328 * proceed with priming of endpoint if not already
329 * primed.
330 */
331 if (readl(&udc->op_regs->usbcmd)
332 & USBCMD_ATDTW_TRIPWIRE_SET) {
333 readsafe = 1;
334 }
335 loops--;
336 udelay(LOOPS_USEC);
337 }
338
339 /* Clear the semaphore */
340 tmp = readl(&udc->op_regs->usbcmd);
341 tmp &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
342 writel(tmp, &udc->op_regs->usbcmd);
343
344 /* If endpoint is not active, we activate it now. */
345 if (!epstatus) {
346 if (direction == EP_DIR_IN) {
347 struct mv_dtd *curr_dtd = dma_to_virt(
348 &udc->dev->dev, dqh->curr_dtd_ptr);
349
350 loops = LOOPS(DTD_TIMEOUT);
351 while (curr_dtd->size_ioc_sts
352 & DTD_STATUS_ACTIVE) {
353 if (loops == 0) {
354 retval = -ETIME;
355 goto done;
356 }
357 loops--;
358 udelay(LOOPS_USEC);
359 }
360 }
361 /* No other transfers on the queue */
362
363 /* Write dQH next pointer and terminate bit to 0 */
364 dqh->next_dtd_ptr = req->head->td_dma
365 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
366 dqh->size_ioc_int_sts = 0;
367
368 /*
369 * Ensure that updates to the QH will
25985edc 370 * occur before priming.
e7cddda4 371 */
372 wmb();
373
374 /* Prime the Endpoint */
375 writel(bit_pos, &udc->op_regs->epprime);
376 }
377 } else {
378 /* Write dQH next pointer and terminate bit to 0 */
379 dqh->next_dtd_ptr = req->head->td_dma
69932487 380 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
e7cddda4 381 dqh->size_ioc_int_sts = 0;
382
25985edc 383 /* Ensure that updates to the QH will occur before priming. */
e7cddda4 384 wmb();
385
386 /* Prime the Endpoint */
387 writel(bit_pos, &udc->op_regs->epprime);
388
389 if (direction == EP_DIR_IN) {
390 /* FIXME add status check after prime the IN ep */
391 int prime_again;
392 u32 curr_dtd_ptr = dqh->curr_dtd_ptr;
393
394 loops = LOOPS(DTD_TIMEOUT);
395 prime_again = 0;
396 while ((curr_dtd_ptr != req->head->td_dma)) {
397 curr_dtd_ptr = dqh->curr_dtd_ptr;
398 if (loops == 0) {
399 dev_err(&udc->dev->dev,
400 "failed to prime %s\n",
401 ep->name);
402 retval = -ETIME;
403 goto done;
404 }
405 loops--;
406 udelay(LOOPS_USEC);
407
408 if (loops == (LOOPS(DTD_TIMEOUT) >> 2)) {
409 if (prime_again)
410 goto done;
411 dev_info(&udc->dev->dev,
412 "prime again\n");
413 writel(bit_pos,
414 &udc->op_regs->epprime);
415 prime_again = 1;
416 }
417 }
418 }
419 }
420done:
69932487 421 return retval;
e7cddda4 422}
423
424static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
425 dma_addr_t *dma, int *is_last)
426{
427 u32 temp;
428 struct mv_dtd *dtd;
429 struct mv_udc *udc;
430
431 /* how big will this transfer be? */
432 *length = min(req->req.length - req->req.actual,
433 (unsigned)EP_MAX_LENGTH_TRANSFER);
434
435 udc = req->ep->udc;
436
437 /*
438 * Be careful that no _GFP_HIGHMEM is set,
439 * or we can not use dma_to_virt
440 */
441 dtd = dma_pool_alloc(udc->dtd_pool, GFP_KERNEL, dma);
442 if (dtd == NULL)
443 return dtd;
444
445 dtd->td_dma = *dma;
446 /* initialize buffer page pointers */
447 temp = (u32)(req->req.dma + req->req.actual);
448 dtd->buff_ptr0 = cpu_to_le32(temp);
449 temp &= ~0xFFF;
450 dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
451 dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
452 dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
453 dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
454
455 req->req.actual += *length;
456
457 /* zlp is needed if req->req.zero is set */
458 if (req->req.zero) {
459 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
460 *is_last = 1;
461 else
462 *is_last = 0;
463 } else if (req->req.length == req->req.actual)
464 *is_last = 1;
465 else
466 *is_last = 0;
467
468 /* Fill in the transfer size; set active bit */
469 temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
470
471 /* Enable interrupt for the last dtd of a request */
472 if (*is_last && !req->req.no_interrupt)
473 temp |= DTD_IOC;
474
475 dtd->size_ioc_sts = temp;
476
477 mb();
478
479 return dtd;
480}
481
482/* generate dTD linked list for a request */
483static int req_to_dtd(struct mv_req *req)
484{
485 unsigned count;
486 int is_last, is_first = 1;
487 struct mv_dtd *dtd, *last_dtd = NULL;
488 struct mv_udc *udc;
489 dma_addr_t dma;
490
491 udc = req->ep->udc;
492
493 do {
494 dtd = build_dtd(req, &count, &dma, &is_last);
495 if (dtd == NULL)
496 return -ENOMEM;
497
498 if (is_first) {
499 is_first = 0;
500 req->head = dtd;
501 } else {
502 last_dtd->dtd_next = dma;
503 last_dtd->next_dtd_virt = dtd;
504 }
505 last_dtd = dtd;
506 req->dtd_count++;
507 } while (!is_last);
508
509 /* set terminate bit to 1 for the last dTD */
510 dtd->dtd_next = DTD_NEXT_TERMINATE;
511
512 req->tail = dtd;
513
514 return 0;
515}
516
517static int mv_ep_enable(struct usb_ep *_ep,
518 const struct usb_endpoint_descriptor *desc)
519{
520 struct mv_udc *udc;
521 struct mv_ep *ep;
522 struct mv_dqh *dqh;
523 u16 max = 0;
524 u32 bit_pos, epctrlx, direction;
525 unsigned char zlt = 0, ios = 0, mult = 0;
27cec2b2 526 unsigned long flags;
e7cddda4 527
528 ep = container_of(_ep, struct mv_ep, ep);
529 udc = ep->udc;
530
531 if (!_ep || !desc || ep->desc
532 || desc->bDescriptorType != USB_DT_ENDPOINT)
533 return -EINVAL;
534
535 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
536 return -ESHUTDOWN;
537
538 direction = ep_dir(ep);
29cc8897 539 max = usb_endpoint_maxp(desc);
e7cddda4 540
541 /*
542 * disable HW zero length termination select
543 * driver handles zero length packet through req->req.zero
544 */
545 zlt = 1;
546
e7cddda4 547 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
548
549 /* Check if the Endpoint is Primed */
550 if ((readl(&udc->op_regs->epprime) & bit_pos)
551 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
552 dev_info(&udc->dev->dev,
553 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
554 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
555 (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
556 (unsigned)readl(&udc->op_regs->epprime),
557 (unsigned)readl(&udc->op_regs->epstatus),
558 (unsigned)bit_pos);
559 goto en_done;
560 }
561 /* Set the max packet length, interrupt on Setup and Mult fields */
562 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
563 case USB_ENDPOINT_XFER_BULK:
564 zlt = 1;
565 mult = 0;
566 break;
567 case USB_ENDPOINT_XFER_CONTROL:
568 ios = 1;
569 case USB_ENDPOINT_XFER_INT:
570 mult = 0;
571 break;
572 case USB_ENDPOINT_XFER_ISOC:
573 /* Calculate transactions needed for high bandwidth iso */
574 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
bedcff97 575 max = max & 0x7ff; /* bit 0~10 */
e7cddda4 576 /* 3 transactions at most */
577 if (mult > 3)
578 goto en_done;
579 break;
580 default:
581 goto en_done;
582 }
27cec2b2
NZ		 583
584 spin_lock_irqsave(&udc->lock, flags);
585 /* Get the endpoint queue head address */
586 dqh = ep->dqh;
e7cddda4 587 dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
588 | (mult << EP_QUEUE_HEAD_MULT_POS)
589 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
590 | (ios ? EP_QUEUE_HEAD_IOS : 0);
591 dqh->next_dtd_ptr = 1;
592 dqh->size_ioc_int_sts = 0;
593
594 ep->ep.maxpacket = max;
595 ep->desc = desc;
596 ep->stopped = 0;
597
598 /* Enable the endpoint for Rx or Tx and set the endpoint type */
599 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
600 if (direction == EP_DIR_IN) {
601 epctrlx &= ~EPCTRL_TX_ALL_MASK;
602 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
603 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
604 << EPCTRL_TX_EP_TYPE_SHIFT);
605 } else {
606 epctrlx &= ~EPCTRL_RX_ALL_MASK;
607 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
608 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
609 << EPCTRL_RX_EP_TYPE_SHIFT);
610 }
611 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
612
613 /*
614 * Implement Guideline (GL# USB-7) The unused endpoint type must
615 * be programmed to bulk.
616 */
617 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
618 if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
615268b0 619 epctrlx |= (USB_ENDPOINT_XFER_BULK
e7cddda4 620 << EPCTRL_RX_EP_TYPE_SHIFT);
621 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
622 }
623
624 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
625 if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
615268b0 626 epctrlx |= (USB_ENDPOINT_XFER_BULK
e7cddda4 627 << EPCTRL_TX_EP_TYPE_SHIFT);
628 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
629 }
630
27cec2b2
NZ		 631 spin_unlock_irqrestore(&udc->lock, flags);
632
e7cddda4 633 return 0;
634en_done:
635 return -EINVAL;
636}
637
638static int mv_ep_disable(struct usb_ep *_ep)
639{
640 struct mv_udc *udc;
641 struct mv_ep *ep;
642 struct mv_dqh *dqh;
643 u32 bit_pos, epctrlx, direction;
27cec2b2 644 unsigned long flags;
e7cddda4 645
646 ep = container_of(_ep, struct mv_ep, ep);
647 if ((_ep == NULL) || !ep->desc)
648 return -EINVAL;
649
650 udc = ep->udc;
651
652 /* Get the endpoint queue head address */
653 dqh = ep->dqh;
654
27cec2b2
NZ		 655 spin_lock_irqsave(&udc->lock, flags);
656
e7cddda4 657 direction = ep_dir(ep);
658 bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
659
660 /* Reset the max packet length and the interrupt on Setup */
661 dqh->max_packet_length = 0;
662
663 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
664 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
665 epctrlx &= ~((direction == EP_DIR_IN)
666 ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
667 : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
668 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
669
670 /* nuke all pending requests (does flush) */
671 nuke(ep, -ESHUTDOWN);
672
673 ep->desc = NULL;
674 ep->stopped = 1;
27cec2b2
NZ		 675
676 spin_unlock_irqrestore(&udc->lock, flags);
677
e7cddda4 678 return 0;
679}
680
681static struct usb_request *
682mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
683{
684 struct mv_req *req = NULL;
685
686 req = kzalloc(sizeof *req, gfp_flags);
687 if (!req)
688 return NULL;
689
690 req->req.dma = DMA_ADDR_INVALID;
691 INIT_LIST_HEAD(&req->queue);
692
693 return &req->req;
694}
695
696static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
697{
698 struct mv_req *req = NULL;
699
700 req = container_of(_req, struct mv_req, req);
701
702 if (_req)
703 kfree(req);
704}
705
706static void mv_ep_fifo_flush(struct usb_ep *_ep)
707{
708 struct mv_udc *udc;
709 u32 bit_pos, direction;
0c70840b 710 struct mv_ep *ep;
e7cddda4 711 unsigned int loops;
712
0c70840b
NZ		 713 if (!_ep)
714 return;
715
716 ep = container_of(_ep, struct mv_ep, ep);
717 if (!ep->desc)
718 return;
719
e7cddda4 720 udc = ep->udc;
721 direction = ep_dir(ep);
e7cddda4 722
0c70840b
NZ		 723 if (ep->ep_num == 0)
724 bit_pos = (1 << 16) | 1;
725 else if (direction == EP_DIR_OUT)
726 bit_pos = 1 << ep->ep_num;
727 else
728 bit_pos = 1 << (16 + ep->ep_num);
729
e7cddda4 730 loops = LOOPS(EPSTATUS_TIMEOUT);
0c70840b 731 do {
e7cddda4 732 unsigned int inter_loops;
733
734 if (loops == 0) {
735 dev_err(&udc->dev->dev,
736 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
737 (unsigned)readl(&udc->op_regs->epstatus),
738 (unsigned)bit_pos);
739 return;
740 }
741 /* Write 1 to the Flush register */
742 writel(bit_pos, &udc->op_regs->epflush);
743
744 /* Wait until flushing completed */
745 inter_loops = LOOPS(FLUSH_TIMEOUT);
0c70840b 746 while (readl(&udc->op_regs->epflush)) {
e7cddda4 747 /*
748 * ENDPTFLUSH bit should be cleared to indicate this
749 * operation is complete
750 */
751 if (inter_loops == 0) {
752 dev_err(&udc->dev->dev,
753 "TIMEOUT for ENDPTFLUSH=0x%x,"
754 "bit_pos=0x%x\n",
755 (unsigned)readl(&udc->op_regs->epflush),
756 (unsigned)bit_pos);
757 return;
758 }
759 inter_loops--;
760 udelay(LOOPS_USEC);
761 }
762 loops--;
0c70840b 763 } while (readl(&udc->op_regs->epstatus) & bit_pos);
e7cddda4 764}
765
766/* queues (submits) an I/O request to an endpoint */
767static int
768mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
769{
770 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
771 struct mv_req *req = container_of(_req, struct mv_req, req);
772 struct mv_udc *udc = ep->udc;
773 unsigned long flags;
774
775 /* catch various bogus parameters */
776 if (!_req || !req->req.complete || !req->req.buf
777 || !list_empty(&req->queue)) {
778 dev_err(&udc->dev->dev, "%s, bad params", __func__);
779 return -EINVAL;
780 }
781 if (unlikely(!_ep || !ep->desc)) {
782 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
783 return -EINVAL;
784 }
785 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
786 if (req->req.length > ep->ep.maxpacket)
787 return -EMSGSIZE;
788 }
789
790 udc = ep->udc;
791 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
792 return -ESHUTDOWN;
793
794 req->ep = ep;
795
796 /* map virtual address to hardware */
797 if (req->req.dma == DMA_ADDR_INVALID) {
798 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
799 req->req.buf,
800 req->req.length, ep_dir(ep)
801 ? DMA_TO_DEVICE
802 : DMA_FROM_DEVICE);
803 req->mapped = 1;
804 } else {
805 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
806 req->req.dma, req->req.length,
807 ep_dir(ep)
808 ? DMA_TO_DEVICE
809 : DMA_FROM_DEVICE);
810 req->mapped = 0;
811 }
812
813 req->req.status = -EINPROGRESS;
814 req->req.actual = 0;
815 req->dtd_count = 0;
816
817 spin_lock_irqsave(&udc->lock, flags);
818
819 /* build dtds and push them to device queue */
820 if (!req_to_dtd(req)) {
821 int retval;
822 retval = queue_dtd(ep, req);
823 if (retval) {
824 spin_unlock_irqrestore(&udc->lock, flags);
825 return retval;
826 }
827 } else {
828 spin_unlock_irqrestore(&udc->lock, flags);
829 return -ENOMEM;
830 }
831
832 /* Update ep0 state */
833 if (ep->ep_num == 0)
834 udc->ep0_state = DATA_STATE_XMIT;
835
836 /* irq handler advances the queue */
837 if (req != NULL)
838 list_add_tail(&req->queue, &ep->queue);
839 spin_unlock_irqrestore(&udc->lock, flags);
840
841 return 0;
842}
843
844/* dequeues (cancels, unlinks) an I/O request from an endpoint */
845static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
846{
847 struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
848 struct mv_req *req;
849 struct mv_udc *udc = ep->udc;
850 unsigned long flags;
851 int stopped, ret = 0;
852 u32 epctrlx;
853
854 if (!_ep || !_req)
855 return -EINVAL;
856
857 spin_lock_irqsave(&ep->udc->lock, flags);
858 stopped = ep->stopped;
859
860 /* Stop the ep before we deal with the queue */
861 ep->stopped = 1;
862 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
863 if (ep_dir(ep) == EP_DIR_IN)
864 epctrlx &= ~EPCTRL_TX_ENABLE;
865 else
866 epctrlx &= ~EPCTRL_RX_ENABLE;
867 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
868
869 /* make sure it's actually queued on this endpoint */
870 list_for_each_entry(req, &ep->queue, queue) {
871 if (&req->req == _req)
872 break;
873 }
874 if (&req->req != _req) {
875 ret = -EINVAL;
876 goto out;
877 }
878
879 /* The request is in progress, or completed but not dequeued */
880 if (ep->queue.next == &req->queue) {
881 _req->status = -ECONNRESET;
882 mv_ep_fifo_flush(_ep); /* flush current transfer */
883
884 /* The request isn't the last request in this ep queue */
885 if (req->queue.next != &ep->queue) {
886 struct mv_dqh *qh;
887 struct mv_req *next_req;
888
889 qh = ep->dqh;
890 next_req = list_entry(req->queue.next, struct mv_req,
891 queue);
892
893 /* Point the QH to the first TD of next request */
894 writel((u32) next_req->head, &qh->curr_dtd_ptr);
895 } else {
896 struct mv_dqh *qh;
897
898 qh = ep->dqh;
899 qh->next_dtd_ptr = 1;
900 qh->size_ioc_int_sts = 0;
901 }
902
903 /* The request hasn't been processed, patch up the TD chain */
904 } else {
905 struct mv_req *prev_req;
906
907 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
908 writel(readl(&req->tail->dtd_next),
909 &prev_req->tail->dtd_next);
910
911 }
912
913 done(ep, req, -ECONNRESET);
914
915 /* Enable EP */
916out:
917 epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
918 if (ep_dir(ep) == EP_DIR_IN)
919 epctrlx |= EPCTRL_TX_ENABLE;
920 else
921 epctrlx |= EPCTRL_RX_ENABLE;
922 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
923 ep->stopped = stopped;
924
925 spin_unlock_irqrestore(&ep->udc->lock, flags);
926 return ret;
927}
928
929static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
930{
931 u32 epctrlx;
932
933 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
934
935 if (stall) {
936 if (direction == EP_DIR_IN)
937 epctrlx |= EPCTRL_TX_EP_STALL;
938 else
939 epctrlx |= EPCTRL_RX_EP_STALL;
940 } else {
941 if (direction == EP_DIR_IN) {
942 epctrlx &= ~EPCTRL_TX_EP_STALL;
943 epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
944 } else {
945 epctrlx &= ~EPCTRL_RX_EP_STALL;
946 epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
947 }
948 }
949 writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
950}
951
952static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
953{
954 u32 epctrlx;
955
956 epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
957
958 if (direction == EP_DIR_OUT)
959 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
960 else
961 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
962}
963
964static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
965{
966 struct mv_ep *ep;
967 unsigned long flags = 0;
968 int status = 0;
969 struct mv_udc *udc;
970
971 ep = container_of(_ep, struct mv_ep, ep);
972 udc = ep->udc;
973 if (!_ep || !ep->desc) {
974 status = -EINVAL;
975 goto out;
976 }
977
978 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
979 status = -EOPNOTSUPP;
980 goto out;
981 }
982
983 /*
984 * Attempt to halt IN ep will fail if any transfer requests
985 * are still queue
986 */
987 if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
988 status = -EAGAIN;
989 goto out;
990 }
991
992 spin_lock_irqsave(&ep->udc->lock, flags);
993 ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
994 if (halt && wedge)
995 ep->wedge = 1;
996 else if (!halt)
997 ep->wedge = 0;
998 spin_unlock_irqrestore(&ep->udc->lock, flags);
999
1000 if (ep->ep_num == 0) {
1001 udc->ep0_state = WAIT_FOR_SETUP;
1002 udc->ep0_dir = EP_DIR_OUT;
1003 }
1004out:
1005 return status;
1006}
1007
1008static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
1009{
1010 return mv_ep_set_halt_wedge(_ep, halt, 0);
1011}
1012
1013static int mv_ep_set_wedge(struct usb_ep *_ep)
1014{
1015 return mv_ep_set_halt_wedge(_ep, 1, 1);
1016}
1017
1018static struct usb_ep_ops mv_ep_ops = {
1019 .enable = mv_ep_enable,
1020 .disable = mv_ep_disable,
1021
1022 .alloc_request = mv_alloc_request,
1023 .free_request = mv_free_request,
1024
1025 .queue = mv_ep_queue,
1026 .dequeue = mv_ep_dequeue,
1027
1028 .set_wedge = mv_ep_set_wedge,
1029 .set_halt = mv_ep_set_halt,
1030 .fifo_flush = mv_ep_fifo_flush, /* flush fifo */
1031};
1032
dde34cc5
NZ		 1033static void udc_clock_enable(struct mv_udc *udc)
1034{
1035 unsigned int i;
1036
1037 for (i = 0; i < udc->clknum; i++)
1038 clk_enable(udc->clk[i]);
1039}
1040
1041static void udc_clock_disable(struct mv_udc *udc)
1042{
1043 unsigned int i;
1044
1045 for (i = 0; i < udc->clknum; i++)
1046 clk_disable(udc->clk[i]);
1047}
1048
e7cddda4 1049static void udc_stop(struct mv_udc *udc)
1050{
1051 u32 tmp;
1052
1053 /* Disable interrupts */
1054 tmp = readl(&udc->op_regs->usbintr);
1055 tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
1056 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
1057 writel(tmp, &udc->op_regs->usbintr);
1058
309d6d2b
NZ		 1059 udc->stopped = 1;
1060
e7cddda4 1061 /* Reset the Run the bit in the command register to stop VUSB */
1062 tmp = readl(&udc->op_regs->usbcmd);
1063 tmp &= ~USBCMD_RUN_STOP;
1064 writel(tmp, &udc->op_regs->usbcmd);
1065}
1066
1067static void udc_start(struct mv_udc *udc)
1068{
1069 u32 usbintr;
1070
1071 usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1072 | USBINTR_PORT_CHANGE_DETECT_EN
1073 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1074 /* Enable interrupts */
1075 writel(usbintr, &udc->op_regs->usbintr);
1076
309d6d2b
NZ		 1077 udc->stopped = 0;
1078
e7cddda4 1079 /* Set the Run bit in the command register */
1080 writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1081}
1082
1083static int udc_reset(struct mv_udc *udc)
1084{
1085 unsigned int loops;
1086 u32 tmp, portsc;
1087
1088 /* Stop the controller */
1089 tmp = readl(&udc->op_regs->usbcmd);
1090 tmp &= ~USBCMD_RUN_STOP;
1091 writel(tmp, &udc->op_regs->usbcmd);
1092
1093 /* Reset the controller to get default values */
1094 writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1095
1096 /* wait for reset to complete */
1097 loops = LOOPS(RESET_TIMEOUT);
1098 while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1099 if (loops == 0) {
1100 dev_err(&udc->dev->dev,
1101 "Wait for RESET completed TIMEOUT\n");
1102 return -ETIMEDOUT;
1103 }
1104 loops--;
1105 udelay(LOOPS_USEC);
1106 }
1107
1108 /* set controller to device mode */
1109 tmp = readl(&udc->op_regs->usbmode);
1110 tmp |= USBMODE_CTRL_MODE_DEVICE;
1111
1112 /* turn setup lockout off, require setup tripwire in usbcmd */
1113 tmp |= USBMODE_SETUP_LOCK_OFF | USBMODE_STREAM_DISABLE;
1114
1115 writel(tmp, &udc->op_regs->usbmode);
1116
1117 writel(0x0, &udc->op_regs->epsetupstat);
1118
1119 /* Configure the Endpoint List Address */
1120 writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1121 &udc->op_regs->eplistaddr);
1122
1123 portsc = readl(&udc->op_regs->portsc[0]);
1124 if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1125 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1126
1127 if (udc->force_fs)
1128 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1129 else
1130 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1131
1132 writel(portsc, &udc->op_regs->portsc[0]);
1133
1134 tmp = readl(&udc->op_regs->epctrlx[0]);
1135 tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1136 writel(tmp, &udc->op_regs->epctrlx[0]);
1137
1138 return 0;
1139}
1140
85ff7bfb 1141static int mv_udc_enable_internal(struct mv_udc *udc)
1aec033b
NZ		 1142{
1143 int retval;
1144
85ff7bfb 1145 if (udc->active)
1aec033b
NZ		 1146 return 0;
1147
1148 dev_dbg(&udc->dev->dev, "enable udc\n");
1149 udc_clock_enable(udc);
1150 if (udc->pdata->phy_init) {
1151 retval = udc->pdata->phy_init(udc->phy_regs);
1152 if (retval) {
1153 dev_err(&udc->dev->dev,
1154 "init phy error %d\n", retval);
1155 udc_clock_disable(udc);
1156 return retval;
1157 }
1158 }
1159 udc->active = 1;
1160
1161 return 0;
1162}
1163
85ff7bfb 1164static int mv_udc_enable(struct mv_udc *udc)
1aec033b 1165{
85ff7bfb
NZ		 1166 if (udc->clock_gating)
1167 return mv_udc_enable_internal(udc);
1168
1169 return 0;
1170}
1171
1172static void mv_udc_disable_internal(struct mv_udc *udc)
1173{
1174 if (udc->active) {
1aec033b
NZ		 1175 dev_dbg(&udc->dev->dev, "disable udc\n");
1176 if (udc->pdata->phy_deinit)
1177 udc->pdata->phy_deinit(udc->phy_regs);
1178 udc_clock_disable(udc);
1179 udc->active = 0;
1180 }
1181}
1182
85ff7bfb
NZ		 1183static void mv_udc_disable(struct mv_udc *udc)
1184{
1185 if (udc->clock_gating)
1186 mv_udc_disable_internal(udc);
1187}
1188
e7cddda4 1189static int mv_udc_get_frame(struct usb_gadget *gadget)
1190{
1191 struct mv_udc *udc;
1192 u16 retval;
1193
1194 if (!gadget)
1195 return -ENODEV;
1196
1197 udc = container_of(gadget, struct mv_udc, gadget);
1198
1199 retval = readl(udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1200
1201 return retval;
1202}
1203
1204/* Tries to wake up the host connected to this gadget */
1205static int mv_udc_wakeup(struct usb_gadget *gadget)
1206{
1207 struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1208 u32 portsc;
1209
1210 /* Remote wakeup feature not enabled by host */
1211 if (!udc->remote_wakeup)
1212 return -ENOTSUPP;
1213
1214 portsc = readl(&udc->op_regs->portsc);
1215 /* not suspended? */
1216 if (!(portsc & PORTSCX_PORT_SUSPEND))
1217 return 0;
1218 /* trigger force resume */
1219 portsc |= PORTSCX_PORT_FORCE_RESUME;
1220 writel(portsc, &udc->op_regs->portsc[0]);
1221 return 0;
1222}
1223
1aec033b
NZ		 1224static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1225{
1226 struct mv_udc *udc;
1227 unsigned long flags;
1228 int retval = 0;
1229
1230 udc = container_of(gadget, struct mv_udc, gadget);
1231 spin_lock_irqsave(&udc->lock, flags);
1232
1233 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1234 __func__, udc->softconnect, udc->vbus_active);
1235
1236 udc->vbus_active = (is_active != 0);
1237 if (udc->driver && udc->softconnect && udc->vbus_active) {
1238 retval = mv_udc_enable(udc);
1239 if (retval == 0) {
1240 /* Clock is disabled, need re-init registers */
1241 udc_reset(udc);
1242 ep0_reset(udc);
1243 udc_start(udc);
1244 }
1245 } else if (udc->driver && udc->softconnect) {
1246 /* stop all the transfer in queue*/
1247 stop_activity(udc, udc->driver);
1248 udc_stop(udc);
1249 mv_udc_disable(udc);
1250 }
1251
1252 spin_unlock_irqrestore(&udc->lock, flags);
1253 return retval;
1254}
1255
e7cddda4 1256static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1257{
1258 struct mv_udc *udc;
1259 unsigned long flags;
1aec033b 1260 int retval = 0;
e7cddda4 1261
1262 udc = container_of(gadget, struct mv_udc, gadget);
1263 spin_lock_irqsave(&udc->lock, flags);
1264
1aec033b
NZ		 1265 dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1266 __func__, udc->softconnect, udc->vbus_active);
1267
e7cddda4 1268 udc->softconnect = (is_on != 0);
1aec033b
NZ		 1269 if (udc->driver && udc->softconnect && udc->vbus_active) {
1270 retval = mv_udc_enable(udc);
1271 if (retval == 0) {
1272 /* Clock is disabled, need re-init registers */
1273 udc_reset(udc);
1274 ep0_reset(udc);
1275 udc_start(udc);
1276 }
1277 } else if (udc->driver && udc->vbus_active) {
1278 /* stop all the transfer in queue*/
1279 stop_activity(udc, udc->driver);
e7cddda4 1280 udc_stop(udc);
1aec033b
NZ		 1281 mv_udc_disable(udc);
1282 }
e7cddda4 1283
1284 spin_unlock_irqrestore(&udc->lock, flags);
1aec033b 1285 return retval;
e7cddda4 1286}
1287
0f91349b
SAS		 1288static int mv_udc_start(struct usb_gadget_driver *driver,
1289 int (*bind)(struct usb_gadget *));
1290static int mv_udc_stop(struct usb_gadget_driver *driver);
e7cddda4 1291/* device controller usb_gadget_ops structure */
1292static const struct usb_gadget_ops mv_ops = {
1293
1294 /* returns the current frame number */
1295 .get_frame = mv_udc_get_frame,
1296
1297 /* tries to wake up the host connected to this gadget */
1298 .wakeup = mv_udc_wakeup,
1299
1aec033b
NZ		 1300 /* notify controller that VBUS is powered or not */
1301 .vbus_session = mv_udc_vbus_session,
1302
e7cddda4 1303 /* D+ pullup, software-controlled connect/disconnect to USB host */
1304 .pullup = mv_udc_pullup,
0f91349b
SAS		 1305 .start = mv_udc_start,
1306 .stop = mv_udc_stop,
e7cddda4 1307};
1308
e7cddda4 1309static int eps_init(struct mv_udc *udc)
1310{
1311 struct mv_ep *ep;
1312 char name[14];
1313 int i;
1314
1315 /* initialize ep0 */
1316 ep = &udc->eps[0];
1317 ep->udc = udc;
1318 strncpy(ep->name, "ep0", sizeof(ep->name));
1319 ep->ep.name = ep->name;
1320 ep->ep.ops = &mv_ep_ops;
1321 ep->wedge = 0;
1322 ep->stopped = 0;
1323 ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1324 ep->ep_num = 0;
1325 ep->desc = &mv_ep0_desc;
1326 INIT_LIST_HEAD(&ep->queue);
1327
1328 ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1329
1330 /* initialize other endpoints */
1331 for (i = 2; i < udc->max_eps * 2; i++) {
1332 ep = &udc->eps[i];
1333 if (i % 2) {
1334 snprintf(name, sizeof(name), "ep%din", i / 2);
1335 ep->direction = EP_DIR_IN;
1336 } else {
1337 snprintf(name, sizeof(name), "ep%dout", i / 2);
1338 ep->direction = EP_DIR_OUT;
1339 }
1340 ep->udc = udc;
1341 strncpy(ep->name, name, sizeof(ep->name));
1342 ep->ep.name = ep->name;
1343
1344 ep->ep.ops = &mv_ep_ops;
1345 ep->stopped = 0;
1346 ep->ep.maxpacket = (unsigned short) ~0;
1347 ep->ep_num = i / 2;
1348
1349 INIT_LIST_HEAD(&ep->queue);
1350 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1351
1352 ep->dqh = &udc->ep_dqh[i];
1353 }
1354
1355 return 0;
1356}
1357
1358/* delete all endpoint requests, called with spinlock held */
1359static void nuke(struct mv_ep *ep, int status)
1360{
1361 /* called with spinlock held */
1362 ep->stopped = 1;
1363
1364 /* endpoint fifo flush */
1365 mv_ep_fifo_flush(&ep->ep);
1366
1367 while (!list_empty(&ep->queue)) {
1368 struct mv_req *req = NULL;
1369 req = list_entry(ep->queue.next, struct mv_req, queue);
1370 done(ep, req, status);
1371 }
1372}
1373
1374/* stop all USB activities */
1375static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1376{
1377 struct mv_ep *ep;
1378
1379 nuke(&udc->eps[0], -ESHUTDOWN);
1380
1381 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1382 nuke(ep, -ESHUTDOWN);
1383 }
1384
1385 /* report disconnect; the driver is already quiesced */
1386 if (driver) {
1387 spin_unlock(&udc->lock);
1388 driver->disconnect(&udc->gadget);
1389 spin_lock(&udc->lock);
1390 }
1391}
1392
0f91349b 1393static int mv_udc_start(struct usb_gadget_driver *driver,
e7cddda4 1394 int (*bind)(struct usb_gadget *))
1395{
1396 struct mv_udc *udc = the_controller;
1397 int retval = 0;
1398 unsigned long flags;
1399
1400 if (!udc)
1401 return -ENODEV;
1402
1403 if (udc->driver)
1404 return -EBUSY;
1405
1406 spin_lock_irqsave(&udc->lock, flags);
1407
1408 /* hook up the driver ... */
1409 driver->driver.bus = NULL;
1410 udc->driver = driver;
1411 udc->gadget.dev.driver = &driver->driver;
1412
1413 udc->usb_state = USB_STATE_ATTACHED;
1414 udc->ep0_state = WAIT_FOR_SETUP;
1aec033b 1415 udc->ep0_dir = EP_DIR_OUT;
e7cddda4 1416
1417 spin_unlock_irqrestore(&udc->lock, flags);
1418
1419 retval = bind(&udc->gadget);
1420 if (retval) {
1421 dev_err(&udc->dev->dev, "bind to driver %s --> %d\n",
1422 driver->driver.name, retval);
1423 udc->driver = NULL;
1424 udc->gadget.dev.driver = NULL;
1425 return retval;
1426 }
1aec033b 1427
487d54d1
NZ		 1428 if (udc->transceiver) {
1429 retval = otg_set_peripheral(udc->transceiver, &udc->gadget);
1430 if (retval) {
1431 dev_err(&udc->dev->dev,
1432 "unable to register peripheral to otg\n");
1433 if (driver->unbind) {
1434 driver->unbind(&udc->gadget);
1435 udc->gadget.dev.driver = NULL;
1436 udc->driver = NULL;
1437 }
1438 return retval;
1439 }
1440 }
1441
1aec033b
NZ		 1442 /* pullup is always on */
1443 mv_udc_pullup(&udc->gadget, 1);
1444
1445 /* When boot with cable attached, there will be no vbus irq occurred */
1446 if (udc->qwork)
1447 queue_work(udc->qwork, &udc->vbus_work);
e7cddda4 1448
1449 return 0;
1450}
e7cddda4 1451
0f91349b 1452static int mv_udc_stop(struct usb_gadget_driver *driver)
e7cddda4 1453{
1454 struct mv_udc *udc = the_controller;
1455 unsigned long flags;
1456
1457 if (!udc)
1458 return -ENODEV;
1459
e7cddda4 1460 spin_lock_irqsave(&udc->lock, flags);
1461
1aec033b
NZ		 1462 mv_udc_enable(udc);
1463 udc_stop(udc);
1464
e7cddda4 1465 /* stop all usb activities */
1466 udc->gadget.speed = USB_SPEED_UNKNOWN;
1467 stop_activity(udc, driver);
1aec033b
NZ		 1468 mv_udc_disable(udc);
1469
e7cddda4 1470 spin_unlock_irqrestore(&udc->lock, flags);
1471
1472 /* unbind gadget driver */
1473 driver->unbind(&udc->gadget);
1474 udc->gadget.dev.driver = NULL;
1475 udc->driver = NULL;
1476
1477 return 0;
1478}
e7cddda4 1479
fb22cbac
NZ		 1480static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1481{
1482 u32 portsc;
1483
1484 portsc = readl(&udc->op_regs->portsc[0]);
1485 portsc |= mode << 16;
1486 writel(portsc, &udc->op_regs->portsc[0]);
1487}
1488
1489static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1490{
1491 struct mv_udc *udc = the_controller;
1492 struct mv_req *req = container_of(_req, struct mv_req, req);
1493 unsigned long flags;
1494
1495 dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1496
1497 spin_lock_irqsave(&udc->lock, flags);
1498 if (req->test_mode) {
1499 mv_set_ptc(udc, req->test_mode);
1500 req->test_mode = 0;
1501 }
1502 spin_unlock_irqrestore(&udc->lock, flags);
1503}
1504
e7cddda4 1505static int
1506udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1507{
1508 int retval = 0;
1509 struct mv_req *req;
1510 struct mv_ep *ep;
1511
1512 ep = &udc->eps[0];
1513 udc->ep0_dir = direction;
36616224 1514 udc->ep0_state = WAIT_FOR_OUT_STATUS;
e7cddda4 1515
1516 req = udc->status_req;
1517
1518 /* fill in the reqest structure */
1519 if (empty == false) {
1520 *((u16 *) req->req.buf) = cpu_to_le16(status);
1521 req->req.length = 2;
1522 } else
1523 req->req.length = 0;
1524
1525 req->ep = ep;
1526 req->req.status = -EINPROGRESS;
1527 req->req.actual = 0;
fb22cbac
NZ		 1528 if (udc->test_mode) {
1529 req->req.complete = prime_status_complete;
1530 req->test_mode = udc->test_mode;
1531 udc->test_mode = 0;
1532 } else
1533 req->req.complete = NULL;
e7cddda4 1534 req->dtd_count = 0;
1535
46e172df
NZ		 1536 if (req->req.dma == DMA_ADDR_INVALID) {
1537 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1538 req->req.buf, req->req.length,
1539 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1540 req->mapped = 1;
1541 }
1542
e7cddda4 1543 /* prime the data phase */
1544 if (!req_to_dtd(req))
1545 retval = queue_dtd(ep, req);
1546 else{ /* no mem */
1547 retval = -ENOMEM;
1548 goto out;
1549 }
1550
1551 if (retval) {
1552 dev_err(&udc->dev->dev, "response error on GET_STATUS request\n");
1553 goto out;
1554 }
1555
1556 list_add_tail(&req->queue, &ep->queue);
1557
1558 return 0;
1559out:
1560 return retval;
1561}
1562
fb22cbac
NZ		 1563static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1564{
1565 if (index <= TEST_FORCE_EN) {
1566 udc->test_mode = index;
1567 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1568 ep0_stall(udc);
1569 } else
1570 dev_err(&udc->dev->dev,
1571 "This test mode(%d) is not supported\n", index);
1572}
1573
e7cddda4 1574static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1575{
1576 udc->dev_addr = (u8)setup->wValue;
1577
1578 /* update usb state */
1579 udc->usb_state = USB_STATE_ADDRESS;
1580
1581 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1582 ep0_stall(udc);
1583}
1584
1585static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1586 struct usb_ctrlrequest *setup)
1587{
431879a7 1588 u16 status = 0;
e7cddda4 1589 int retval;
1590
1591 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1592 != (USB_DIR_IN | USB_TYPE_STANDARD))
1593 return;
1594
1595 if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1596 status = 1 << USB_DEVICE_SELF_POWERED;
1597 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1598 } else if ((setup->bRequestType & USB_RECIP_MASK)
1599 == USB_RECIP_INTERFACE) {
1600 /* get interface status */
1601 status = 0;
1602 } else if ((setup->bRequestType & USB_RECIP_MASK)
1603 == USB_RECIP_ENDPOINT) {
1604 u8 ep_num, direction;
1605
1606 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1607 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1608 ? EP_DIR_IN : EP_DIR_OUT;
1609 status = ep_is_stall(udc, ep_num, direction)
1610 << USB_ENDPOINT_HALT;
1611 }
1612
1613 retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1614 if (retval)
1615 ep0_stall(udc);
36616224
NZ		 1616 else
1617 udc->ep0_state = DATA_STATE_XMIT;
e7cddda4 1618}
1619
1620static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1621{
1622 u8 ep_num;
1623 u8 direction;
1624 struct mv_ep *ep;
1625
1626 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1627 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1628 switch (setup->wValue) {
1629 case USB_DEVICE_REMOTE_WAKEUP:
1630 udc->remote_wakeup = 0;
1631 break;
e7cddda4 1632 default:
1633 goto out;
1634 }
1635 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1636 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1637 switch (setup->wValue) {
1638 case USB_ENDPOINT_HALT:
1639 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1640 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1641 ? EP_DIR_IN : EP_DIR_OUT;
1642 if (setup->wValue != 0 || setup->wLength != 0
1643 || ep_num > udc->max_eps)
1644 goto out;
1645 ep = &udc->eps[ep_num * 2 + direction];
1646 if (ep->wedge == 1)
1647 break;
1648 spin_unlock(&udc->lock);
1649 ep_set_stall(udc, ep_num, direction, 0);
1650 spin_lock(&udc->lock);
1651 break;
1652 default:
1653 goto out;
1654 }
1655 } else
1656 goto out;
1657
1658 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1659 ep0_stall(udc);
e7cddda4 1660out:
1661 return;
1662}
1663
1664static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1665{
1666 u8 ep_num;
1667 u8 direction;
1668
1669 if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1670 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1671 switch (setup->wValue) {
1672 case USB_DEVICE_REMOTE_WAKEUP:
1673 udc->remote_wakeup = 1;
1674 break;
1675 case USB_DEVICE_TEST_MODE:
1676 if (setup->wIndex & 0xFF
fb22cbac
NZ		 1677 || udc->gadget.speed != USB_SPEED_HIGH)
1678 ep0_stall(udc);
1679
1680 if (udc->usb_state != USB_STATE_CONFIGURED
1681 && udc->usb_state != USB_STATE_ADDRESS
1682 && udc->usb_state != USB_STATE_DEFAULT)
1683 ep0_stall(udc);
1684
1685 mv_udc_testmode(udc, (setup->wIndex >> 8));
1686 goto out;
e7cddda4 1687 default:
1688 goto out;
1689 }
1690 } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1691 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1692 switch (setup->wValue) {
1693 case USB_ENDPOINT_HALT:
1694 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1695 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1696 ? EP_DIR_IN : EP_DIR_OUT;
1697 if (setup->wValue != 0 || setup->wLength != 0
1698 || ep_num > udc->max_eps)
1699 goto out;
1700 spin_unlock(&udc->lock);
1701 ep_set_stall(udc, ep_num, direction, 1);
1702 spin_lock(&udc->lock);
1703 break;
1704 default:
1705 goto out;
1706 }
1707 } else
1708 goto out;
1709
1710 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1711 ep0_stall(udc);
1712out:
1713 return;
1714}
1715
1716static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1717 struct usb_ctrlrequest *setup)
1718{
1719 bool delegate = false;
1720
1721 nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1722
1723 dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1724 setup->bRequestType, setup->bRequest,
1725 setup->wValue, setup->wIndex, setup->wLength);
1726 /* We process some stardard setup requests here */
1727 if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1728 switch (setup->bRequest) {
1729 case USB_REQ_GET_STATUS:
1730 ch9getstatus(udc, ep_num, setup);
1731 break;
1732
1733 case USB_REQ_SET_ADDRESS:
1734 ch9setaddress(udc, setup);
1735 break;
1736
1737 case USB_REQ_CLEAR_FEATURE:
1738 ch9clearfeature(udc, setup);
1739 break;
1740
1741 case USB_REQ_SET_FEATURE:
1742 ch9setfeature(udc, setup);
1743 break;
1744
1745 default:
1746 delegate = true;
1747 }
1748 } else
1749 delegate = true;
1750
1751 /* delegate USB standard requests to the gadget driver */
1752 if (delegate == true) {
1753 /* USB requests handled by gadget */
1754 if (setup->wLength) {
1755 /* DATA phase from gadget, STATUS phase from udc */
1756 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1757 ? EP_DIR_IN : EP_DIR_OUT;
1758 spin_unlock(&udc->lock);
1759 if (udc->driver->setup(&udc->gadget,
1760 &udc->local_setup_buff) < 0)
1761 ep0_stall(udc);
1762 spin_lock(&udc->lock);
1763 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1764 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1765 } else {
1766 /* no DATA phase, IN STATUS phase from gadget */
1767 udc->ep0_dir = EP_DIR_IN;
1768 spin_unlock(&udc->lock);
1769 if (udc->driver->setup(&udc->gadget,
1770 &udc->local_setup_buff) < 0)
1771 ep0_stall(udc);
1772 spin_lock(&udc->lock);
1773 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1774 }
1775 }
1776}
1777
1778/* complete DATA or STATUS phase of ep0 prime status phase if needed */
1779static void ep0_req_complete(struct mv_udc *udc,
1780 struct mv_ep *ep0, struct mv_req *req)
1781{
1782 u32 new_addr;
1783
1784 if (udc->usb_state == USB_STATE_ADDRESS) {
1785 /* set the new address */
1786 new_addr = (u32)udc->dev_addr;
1787 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1788 &udc->op_regs->deviceaddr);
1789 }
1790
1791 done(ep0, req, 0);
1792
1793 switch (udc->ep0_state) {
1794 case DATA_STATE_XMIT:
1795 /* receive status phase */
1796 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1797 ep0_stall(udc);
1798 break;
1799 case DATA_STATE_RECV:
1800 /* send status phase */
1801 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1802 ep0_stall(udc);
1803 break;
1804 case WAIT_FOR_OUT_STATUS:
1805 udc->ep0_state = WAIT_FOR_SETUP;
1806 break;
1807 case WAIT_FOR_SETUP:
1808 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1809 break;
1810 default:
1811 ep0_stall(udc);
1812 break;
1813 }
1814}
1815
1816static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1817{
1818 u32 temp;
1819 struct mv_dqh *dqh;
1820
1821 dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1822
1823 /* Clear bit in ENDPTSETUPSTAT */
96c2bbb0 1824 writel((1 << ep_num), &udc->op_regs->epsetupstat);
e7cddda4 1825
1826 /* while a hazard exists when setup package arrives */
1827 do {
1828 /* Set Setup Tripwire */
1829 temp = readl(&udc->op_regs->usbcmd);
1830 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1831
1832 /* Copy the setup packet to local buffer */
1833 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1834 } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1835
1836 /* Clear Setup Tripwire */
1837 temp = readl(&udc->op_regs->usbcmd);
1838 writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1839}
1840
1841static void irq_process_tr_complete(struct mv_udc *udc)
1842{
1843 u32 tmp, bit_pos;
1844 int i, ep_num = 0, direction = 0;
1845 struct mv_ep *curr_ep;
1846 struct mv_req *curr_req, *temp_req;
1847 int status;
1848
1849 /*
1850 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1851 * because the setup packets are to be read ASAP
1852 */
1853
1854 /* Process all Setup packet received interrupts */
1855 tmp = readl(&udc->op_regs->epsetupstat);
1856
1857 if (tmp) {
1858 for (i = 0; i < udc->max_eps; i++) {
1859 if (tmp & (1 << i)) {
1860 get_setup_data(udc, i,
1861 (u8 *)(&udc->local_setup_buff));
1862 handle_setup_packet(udc, i,
1863 &udc->local_setup_buff);
1864 }
1865 }
1866 }
1867
1868 /* Don't clear the endpoint setup status register here.
1869 * It is cleared as a setup packet is read out of the buffer
1870 */
1871
1872 /* Process non-setup transaction complete interrupts */
1873 tmp = readl(&udc->op_regs->epcomplete);
1874
1875 if (!tmp)
1876 return;
1877
1878 writel(tmp, &udc->op_regs->epcomplete);
1879
1880 for (i = 0; i < udc->max_eps * 2; i++) {
1881 ep_num = i >> 1;
1882 direction = i % 2;
1883
1884 bit_pos = 1 << (ep_num + 16 * direction);
1885
1886 if (!(bit_pos & tmp))
1887 continue;
1888
1889 if (i == 1)
1890 curr_ep = &udc->eps[0];
1891 else
1892 curr_ep = &udc->eps[i];
1893 /* process the req queue until an uncomplete request */
1894 list_for_each_entry_safe(curr_req, temp_req,
1895 &curr_ep->queue, queue) {
1896 status = process_ep_req(udc, i, curr_req);
1897 if (status)
1898 break;
1899
1900 /* write back status to req */
1901 curr_req->req.status = status;
1902
1903 /* ep0 request completion */
1904 if (ep_num == 0) {
1905 ep0_req_complete(udc, curr_ep, curr_req);
1906 break;
1907 } else {
1908 done(curr_ep, curr_req, status);
1909 }
1910 }
1911 }
1912}
1913
1914void irq_process_reset(struct mv_udc *udc)
1915{
1916 u32 tmp;
1917 unsigned int loops;
1918
1919 udc->ep0_dir = EP_DIR_OUT;
1920 udc->ep0_state = WAIT_FOR_SETUP;
1921 udc->remote_wakeup = 0; /* default to 0 on reset */
1922
1923 /* The address bits are past bit 25-31. Set the address */
1924 tmp = readl(&udc->op_regs->deviceaddr);
1925 tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1926 writel(tmp, &udc->op_regs->deviceaddr);
1927
1928 /* Clear all the setup token semaphores */
1929 tmp = readl(&udc->op_regs->epsetupstat);
1930 writel(tmp, &udc->op_regs->epsetupstat);
1931
1932 /* Clear all the endpoint complete status bits */
1933 tmp = readl(&udc->op_regs->epcomplete);
1934 writel(tmp, &udc->op_regs->epcomplete);
1935
1936 /* wait until all endptprime bits cleared */
1937 loops = LOOPS(PRIME_TIMEOUT);
1938 while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1939 if (loops == 0) {
1940 dev_err(&udc->dev->dev,
1941 "Timeout for ENDPTPRIME = 0x%x\n",
1942 readl(&udc->op_regs->epprime));
1943 break;
1944 }
1945 loops--;
1946 udelay(LOOPS_USEC);
1947 }
1948
1949 /* Write 1s to the Flush register */
1950 writel((u32)~0, &udc->op_regs->epflush);
1951
1952 if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1953 dev_info(&udc->dev->dev, "usb bus reset\n");
1954 udc->usb_state = USB_STATE_DEFAULT;
1955 /* reset all the queues, stop all USB activities */
1956 stop_activity(udc, udc->driver);
1957 } else {
1958 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1959 readl(&udc->op_regs->portsc));
1960
1961 /*
1962 * re-initialize
1963 * controller reset
1964 */
1965 udc_reset(udc);
1966
1967 /* reset all the queues, stop all USB activities */
1968 stop_activity(udc, udc->driver);
1969
1970 /* reset ep0 dQH and endptctrl */
1971 ep0_reset(udc);
1972
1973 /* enable interrupt and set controller to run state */
1974 udc_start(udc);
1975
1976 udc->usb_state = USB_STATE_ATTACHED;
1977 }
1978}
1979
1980static void handle_bus_resume(struct mv_udc *udc)
1981{
1982 udc->usb_state = udc->resume_state;
1983 udc->resume_state = 0;
1984
1985 /* report resume to the driver */
1986 if (udc->driver) {
1987 if (udc->driver->resume) {
1988 spin_unlock(&udc->lock);
1989 udc->driver->resume(&udc->gadget);
1990 spin_lock(&udc->lock);
1991 }
1992 }
1993}
1994
1995static void irq_process_suspend(struct mv_udc *udc)
1996{
1997 udc->resume_state = udc->usb_state;
1998 udc->usb_state = USB_STATE_SUSPENDED;
1999
2000 if (udc->driver->suspend) {
2001 spin_unlock(&udc->lock);
2002 udc->driver->suspend(&udc->gadget);
2003 spin_lock(&udc->lock);
2004 }
2005}
2006
2007static void irq_process_port_change(struct mv_udc *udc)
2008{
2009 u32 portsc;
2010
2011 portsc = readl(&udc->op_regs->portsc[0]);
2012 if (!(portsc & PORTSCX_PORT_RESET)) {
2013 /* Get the speed */
2014 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
2015 switch (speed) {
2016 case PORTSCX_PORT_SPEED_HIGH:
2017 udc->gadget.speed = USB_SPEED_HIGH;
2018 break;
2019 case PORTSCX_PORT_SPEED_FULL:
2020 udc->gadget.speed = USB_SPEED_FULL;
2021 break;
2022 case PORTSCX_PORT_SPEED_LOW:
2023 udc->gadget.speed = USB_SPEED_LOW;
2024 break;
2025 default:
2026 udc->gadget.speed = USB_SPEED_UNKNOWN;
2027 break;
2028 }
2029 }
2030
2031 if (portsc & PORTSCX_PORT_SUSPEND) {
2032 udc->resume_state = udc->usb_state;
2033 udc->usb_state = USB_STATE_SUSPENDED;
2034 if (udc->driver->suspend) {
2035 spin_unlock(&udc->lock);
2036 udc->driver->suspend(&udc->gadget);
2037 spin_lock(&udc->lock);
2038 }
2039 }
2040
2041 if (!(portsc & PORTSCX_PORT_SUSPEND)
2042 && udc->usb_state == USB_STATE_SUSPENDED) {
2043 handle_bus_resume(udc);
2044 }
2045
2046 if (!udc->resume_state)
2047 udc->usb_state = USB_STATE_DEFAULT;
2048}
2049
2050static void irq_process_error(struct mv_udc *udc)
2051{
2052 /* Increment the error count */
2053 udc->errors++;
2054}
2055
2056static irqreturn_t mv_udc_irq(int irq, void *dev)
2057{
2058 struct mv_udc *udc = (struct mv_udc *)dev;
2059 u32 status, intr;
2060
309d6d2b
NZ		 2061 /* Disable ISR when stopped bit is set */
2062 if (udc->stopped)
2063 return IRQ_NONE;
2064
e7cddda4 2065 spin_lock(&udc->lock);
2066
2067 status = readl(&udc->op_regs->usbsts);
2068 intr = readl(&udc->op_regs->usbintr);
2069 status &= intr;
2070
2071 if (status == 0) {
2072 spin_unlock(&udc->lock);
2073 return IRQ_NONE;
2074 }
2075
25985edc 2076 /* Clear all the interrupts occurred */
e7cddda4 2077 writel(status, &udc->op_regs->usbsts);
2078
2079 if (status & USBSTS_ERR)
2080 irq_process_error(udc);
2081
2082 if (status & USBSTS_RESET)
2083 irq_process_reset(udc);
2084
2085 if (status & USBSTS_PORT_CHANGE)
2086 irq_process_port_change(udc);
2087
2088 if (status & USBSTS_INT)
2089 irq_process_tr_complete(udc);
2090
2091 if (status & USBSTS_SUSPEND)
2092 irq_process_suspend(udc);
2093
2094 spin_unlock(&udc->lock);
2095
2096 return IRQ_HANDLED;
2097}
2098
1aec033b
NZ		 2099static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2100{
2101 struct mv_udc *udc = (struct mv_udc *)dev;
2102
2103 /* polling VBUS and init phy may cause too much time*/
2104 if (udc->qwork)
2105 queue_work(udc->qwork, &udc->vbus_work);
2106
2107 return IRQ_HANDLED;
2108}
2109
2110static void mv_udc_vbus_work(struct work_struct *work)
2111{
2112 struct mv_udc *udc;
2113 unsigned int vbus;
2114
2115 udc = container_of(work, struct mv_udc, vbus_work);
2116 if (!udc->pdata->vbus)
2117 return;
2118
2119 vbus = udc->pdata->vbus->poll();
2120 dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2121
2122 if (vbus == VBUS_HIGH)
2123 mv_udc_vbus_session(&udc->gadget, 1);
2124 else if (vbus == VBUS_LOW)
2125 mv_udc_vbus_session(&udc->gadget, 0);
2126}
2127
e7cddda4 2128/* release device structure */
2129static void gadget_release(struct device *_dev)
2130{
2131 struct mv_udc *udc = the_controller;
2132
2133 complete(udc->done);
e7cddda4 2134}
2135
5d0b8d0f 2136static int __devexit mv_udc_remove(struct platform_device *dev)
e7cddda4 2137{
2138 struct mv_udc *udc = the_controller;
dde34cc5 2139 int clk_i;
e7cddda4 2140
0f91349b
SAS		 2141 usb_del_gadget_udc(&udc->gadget);
2142
1aec033b
NZ		 2143 if (udc->qwork) {
2144 flush_workqueue(udc->qwork);
2145 destroy_workqueue(udc->qwork);
2146 }
2147
487d54d1
NZ		 2148 /*
2149 * If we have transceiver inited,
2150 * then vbus irq will not be requested in udc driver.
2151 */
2152 if (udc->pdata && udc->pdata->vbus
2153 && udc->clock_gating && udc->transceiver == NULL)
1aec033b 2154 free_irq(udc->pdata->vbus->irq, &dev->dev);
e7cddda4 2155
2156 /* free memory allocated in probe */
2157 if (udc->dtd_pool)
2158 dma_pool_destroy(udc->dtd_pool);
2159
2160 if (udc->ep_dqh)
2161 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2162 udc->ep_dqh, udc->ep_dqh_dma);
2163
2164 kfree(udc->eps);
2165
2166 if (udc->irq)
2167 free_irq(udc->irq, &dev->dev);
2168
1aec033b
NZ		 2169 mv_udc_disable(udc);
2170
e7cddda4 2171 if (udc->cap_regs)
2172 iounmap(udc->cap_regs);
2173 udc->cap_regs = NULL;
2174
2175 if (udc->phy_regs)
2176 iounmap((void *)udc->phy_regs);
2177 udc->phy_regs = 0;
2178
2179 if (udc->status_req) {
2180 kfree(udc->status_req->req.buf);
2181 kfree(udc->status_req);
2182 }
2183
dde34cc5
NZ		 2184 for (clk_i = 0; clk_i <= udc->clknum; clk_i++)
2185 clk_put(udc->clk[clk_i]);
2186
e7cddda4 2187 device_unregister(&udc->gadget.dev);
2188
2189 /* free dev, wait for the release() finished */
dde34cc5
NZ		 2190 wait_for_completion(udc->done);
2191 kfree(udc);
e7cddda4 2192
2193 the_controller = NULL;
2194
2195 return 0;
2196}
2197
5d0b8d0f 2198static int __devinit mv_udc_probe(struct platform_device *dev)
e7cddda4 2199{
dde34cc5 2200 struct mv_usb_platform_data *pdata = dev->dev.platform_data;
e7cddda4 2201 struct mv_udc *udc;
2202 int retval = 0;
dde34cc5 2203 int clk_i = 0;
e7cddda4 2204 struct resource *r;
2205 size_t size;
2206
dde34cc5
NZ		 2207 if (pdata == NULL) {
2208 dev_err(&dev->dev, "missing platform_data\n");
2209 return -ENODEV;
2210 }
2211
2212 size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
2213 udc = kzalloc(size, GFP_KERNEL);
e7cddda4 2214 if (udc == NULL) {
2215 dev_err(&dev->dev, "failed to allocate memory for udc\n");
dde34cc5 2216 return -ENOMEM;
e7cddda4 2217 }
2218
dde34cc5
NZ		 2219 the_controller = udc;
2220 udc->done = &release_done;
2221 udc->pdata = dev->dev.platform_data;
e7cddda4 2222 spin_lock_init(&udc->lock);
2223
2224 udc->dev = dev;
2225
487d54d1
NZ		 2226#ifdef CONFIG_USB_OTG_UTILS
2227 if (pdata->mode == MV_USB_MODE_OTG)
2228 udc->transceiver = otg_get_transceiver();
2229#endif
2230
dde34cc5
NZ		 2231 udc->clknum = pdata->clknum;
2232 for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
2233 udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]);
2234 if (IS_ERR(udc->clk[clk_i])) {
2235 retval = PTR_ERR(udc->clk[clk_i]);
2236 goto err_put_clk;
2237 }
e7cddda4 2238 }
2239
dde34cc5 2240 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
e7cddda4 2241 if (r == NULL) {
2242 dev_err(&dev->dev, "no I/O memory resource defined\n");
2243 retval = -ENODEV;
dde34cc5 2244 goto err_put_clk;
e7cddda4 2245 }
2246
2247 udc->cap_regs = (struct mv_cap_regs __iomem *)
2248 ioremap(r->start, resource_size(r));
2249 if (udc->cap_regs == NULL) {
2250 dev_err(&dev->dev, "failed to map I/O memory\n");
2251 retval = -EBUSY;
dde34cc5 2252 goto err_put_clk;
e7cddda4 2253 }
2254
dde34cc5 2255 r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
e7cddda4 2256 if (r == NULL) {
2257 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
2258 retval = -ENODEV;
dde34cc5 2259 goto err_iounmap_capreg;
e7cddda4 2260 }
2261
2262 udc->phy_regs = (unsigned int)ioremap(r->start, resource_size(r));
2263 if (udc->phy_regs == 0) {
2264 dev_err(&dev->dev, "failed to map phy I/O memory\n");
2265 retval = -EBUSY;
dde34cc5 2266 goto err_iounmap_capreg;
e7cddda4 2267 }
2268
2269 /* we will acces controller register, so enable the clk */
85ff7bfb
NZ		 2270 retval = mv_udc_enable_internal(udc);
2271 if (retval)
2272 goto err_iounmap_phyreg;
e7cddda4 2273
2274 udc->op_regs = (struct mv_op_regs __iomem *)((u32)udc->cap_regs
2275 + (readl(&udc->cap_regs->caplength_hciversion)
2276 & CAPLENGTH_MASK));
2277 udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2278
4540a9ab
NZ		 2279 /*
2280 * some platform will use usb to download image, it may not disconnect
2281 * usb gadget before loading kernel. So first stop udc here.
2282 */
2283 udc_stop(udc);
2284 writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2285
e7cddda4 2286 size = udc->max_eps * sizeof(struct mv_dqh) *2;
2287 size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2288 udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
2289 &udc->ep_dqh_dma, GFP_KERNEL);
2290
2291 if (udc->ep_dqh == NULL) {
2292 dev_err(&dev->dev, "allocate dQH memory failed\n");
2293 retval = -ENOMEM;
dde34cc5 2294 goto err_disable_clock;
e7cddda4 2295 }
2296 udc->ep_dqh_size = size;
2297
2298 /* create dTD dma_pool resource */
2299 udc->dtd_pool = dma_pool_create("mv_dtd",
2300 &dev->dev,
2301 sizeof(struct mv_dtd),
2302 DTD_ALIGNMENT,
2303 DMA_BOUNDARY);
2304
2305 if (!udc->dtd_pool) {
2306 retval = -ENOMEM;
dde34cc5 2307 goto err_free_dma;
e7cddda4 2308 }
2309
2310 size = udc->max_eps * sizeof(struct mv_ep) *2;
2311 udc->eps = kzalloc(size, GFP_KERNEL);
2312 if (udc->eps == NULL) {
2313 dev_err(&dev->dev, "allocate ep memory failed\n");
2314 retval = -ENOMEM;
dde34cc5 2315 goto err_destroy_dma;
e7cddda4 2316 }
2317
2318 /* initialize ep0 status request structure */
2319 udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2320 if (!udc->status_req) {
2321 dev_err(&dev->dev, "allocate status_req memory failed\n");
2322 retval = -ENOMEM;
dde34cc5 2323 goto err_free_eps;
e7cddda4 2324 }
2325 INIT_LIST_HEAD(&udc->status_req->queue);
2326
2327 /* allocate a small amount of memory to get valid address */
2328 udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
46e172df 2329 udc->status_req->req.dma = DMA_ADDR_INVALID;
e7cddda4 2330
2331 udc->resume_state = USB_STATE_NOTATTACHED;
2332 udc->usb_state = USB_STATE_POWERED;
2333 udc->ep0_dir = EP_DIR_OUT;
2334 udc->remote_wakeup = 0;
2335
2336 r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2337 if (r == NULL) {
2338 dev_err(&dev->dev, "no IRQ resource defined\n");
2339 retval = -ENODEV;
dde34cc5 2340 goto err_free_status_req;
e7cddda4 2341 }
2342 udc->irq = r->start;
2343 if (request_irq(udc->irq, mv_udc_irq,
b5dd18d8 2344 IRQF_SHARED, driver_name, udc)) {
e7cddda4 2345 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2346 udc->irq);
2347 retval = -ENODEV;
dde34cc5 2348 goto err_free_status_req;
e7cddda4 2349 }
2350
2351 /* initialize gadget structure */
2352 udc->gadget.ops = &mv_ops; /* usb_gadget_ops */
2353 udc->gadget.ep0 = &udc->eps[0].ep; /* gadget ep0 */
2354 INIT_LIST_HEAD(&udc->gadget.ep_list); /* ep_list */
2355 udc->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
d327ab5b 2356 udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
e7cddda4 2357
2358 /* the "gadget" abstracts/virtualizes the controller */
2359 dev_set_name(&udc->gadget.dev, "gadget");
2360 udc->gadget.dev.parent = &dev->dev;
2361 udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2362 udc->gadget.dev.release = gadget_release;
2363 udc->gadget.name = driver_name; /* gadget name */
2364
2365 retval = device_register(&udc->gadget.dev);
2366 if (retval)
dde34cc5 2367 goto err_free_irq;
e7cddda4 2368
2369 eps_init(udc);
2370
1aec033b 2371 /* VBUS detect: we can disable/enable clock on demand.*/
487d54d1
NZ		 2372 if (udc->transceiver)
2373 udc->clock_gating = 1;
2374 else if (pdata->vbus) {
1aec033b
NZ		 2375 udc->clock_gating = 1;
2376 retval = request_threaded_irq(pdata->vbus->irq, NULL,
2377 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2378 if (retval) {
2379 dev_info(&dev->dev,
2380 "Can not request irq for VBUS, "
2381 "disable clock gating\n");
2382 udc->clock_gating = 0;
2383 }
2384
2385 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2386 if (!udc->qwork) {
2387 dev_err(&dev->dev, "cannot create workqueue\n");
2388 retval = -ENOMEM;
2389 goto err_unregister;
2390 }
2391
2392 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2393 }
2394
2395 /*
2396 * When clock gating is supported, we can disable clk and phy.
2397 * If not, it means that VBUS detection is not supported, we
2398 * have to enable vbus active all the time to let controller work.
2399 */
85ff7bfb
NZ		 2400 if (udc->clock_gating)
2401 mv_udc_disable_internal(udc);
2402 else
1aec033b 2403 udc->vbus_active = 1;
e7cddda4 2404
0f91349b 2405 retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
dde34cc5
NZ		 2406 if (retval)
2407 goto err_unregister;
2408
1aec033b
NZ		 2409 dev_info(&dev->dev, "successful probe UDC device %s clock gating.\n",
2410 udc->clock_gating ? "with" : "without");
2411
dde34cc5
NZ		 2412 return 0;
2413
2414err_unregister:
487d54d1
NZ		 2415 if (udc->pdata && udc->pdata->vbus
2416 && udc->clock_gating && udc->transceiver == NULL)
1aec033b 2417 free_irq(pdata->vbus->irq, &dev->dev);
dde34cc5
NZ		 2418 device_unregister(&udc->gadget.dev);
2419err_free_irq:
2420 free_irq(udc->irq, &dev->dev);
2421err_free_status_req:
2422 kfree(udc->status_req->req.buf);
2423 kfree(udc->status_req);
2424err_free_eps:
2425 kfree(udc->eps);
2426err_destroy_dma:
2427 dma_pool_destroy(udc->dtd_pool);
2428err_free_dma:
2429 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2430 udc->ep_dqh, udc->ep_dqh_dma);
2431err_disable_clock:
85ff7bfb 2432 mv_udc_disable_internal(udc);
dde34cc5
NZ		 2433err_iounmap_phyreg:
2434 iounmap((void *)udc->phy_regs);
2435err_iounmap_capreg:
2436 iounmap(udc->cap_regs);
2437err_put_clk:
2438 for (clk_i--; clk_i >= 0; clk_i--)
2439 clk_put(udc->clk[clk_i]);
2440 the_controller = NULL;
2441 kfree(udc);
e7cddda4 2442 return retval;
2443}
2444
2445#ifdef CONFIG_PM
cb424473 2446static int mv_udc_suspend(struct device *_dev)
e7cddda4 2447{
2448 struct mv_udc *udc = the_controller;
2449
2450 udc_stop(udc);
2451
2452 return 0;
2453}
2454
cb424473 2455static int mv_udc_resume(struct device *_dev)
e7cddda4 2456{
2457 struct mv_udc *udc = the_controller;
2458 int retval;
2459
dde34cc5
NZ		 2460 if (udc->pdata->phy_init) {
2461 retval = udc->pdata->phy_init(udc->phy_regs);
2462 if (retval) {
2463 dev_err(&udc->dev->dev,
2464 "init phy error %d when resume back\n",
2465 retval);
2466 return retval;
2467 }
e7cddda4 2468 }
dde34cc5 2469
e7cddda4 2470 udc_reset(udc);
2471 ep0_reset(udc);
2472 udc_start(udc);
2473
2474 return 0;
2475}
2476
2477static const struct dev_pm_ops mv_udc_pm_ops = {
2478 .suspend = mv_udc_suspend,
2479 .resume = mv_udc_resume,
2480};
2481#endif
2482
046b07ac
NZ		 2483static void mv_udc_shutdown(struct platform_device *dev)
2484{
2485 struct mv_udc *udc = the_controller;
2486 u32 mode;
2487
2488 /* reset controller mode to IDLE */
2489 mode = readl(&udc->op_regs->usbmode);
2490 mode &= ~3;
2491 writel(mode, &udc->op_regs->usbmode);
2492}
2493
e7cddda4 2494static struct platform_driver udc_driver = {
2495 .probe = mv_udc_probe,
2496 .remove = __exit_p(mv_udc_remove),
046b07ac 2497 .shutdown = mv_udc_shutdown,
e7cddda4 2498 .driver = {
2499 .owner = THIS_MODULE,
2500 .name = "pxa-u2o",
2501#ifdef CONFIG_PM
cb424473 2502 .pm = &mv_udc_pm_ops,
e7cddda4 2503#endif
2504 },
2505};
86081d7b 2506MODULE_ALIAS("platform:pxa-u2o");
e7cddda4 2507
2508MODULE_DESCRIPTION(DRIVER_DESC);
2509MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2510MODULE_VERSION(DRIVER_VERSION);
2511MODULE_LICENSE("GPL");
2512
2513
2514static int __init init(void)
2515{
2516 return platform_driver_register(&udc_driver);
2517}
2518module_init(init);
2519
2520
2521static void __exit cleanup(void)
2522{
2523 platform_driver_unregister(&udc_driver);
2524}
2525module_exit(cleanup);
2526
Linux kernel - Deliverables
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