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usb: gadget: omap_udc: remove useless print
[deliverable/linux.git] / drivers / usb / gadget / omap_udc.c
CommitLineData
1da177e4
LT		 1/*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
527ea73e
KP		 7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
1da177e4
LT		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
1da177e4
LT		 13 */
14
15#undef DEBUG
16#undef VERBOSE
17
1da177e4
LT		 18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/ioport.h>
21#include <linux/types.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
1da177e4
LT		 24#include <linux/slab.h>
25#include <linux/init.h>
26#include <linux/timer.h>
27#include <linux/list.h>
28#include <linux/interrupt.h>
29#include <linux/proc_fs.h>
30#include <linux/mm.h>
31#include <linux/moduleparam.h>
d052d1be 32#include <linux/platform_device.h>
5f848137 33#include <linux/usb/ch9.h>
9454a57a 34#include <linux/usb/gadget.h>
3a16f7b4 35#include <linux/usb/otg.h>
1da177e4 36#include <linux/dma-mapping.h>
e6a6e472 37#include <linux/clk.h>
268bb0ce 38#include <linux/prefetch.h>
80dd1358 39#include <linux/io.h>
1da177e4
LT		 40
41#include <asm/byteorder.h>
1da177e4 42#include <asm/irq.h>
1da177e4
LT		 43#include <asm/unaligned.h>
44#include <asm/mach-types.h>
45
ce491cf8
TL		 46#include <plat/dma.h>
47#include <plat/usb.h>
1da177e4
LT		 48
49#include "omap_udc.h"
50
51#undef USB_TRACE
52
53/* bulk DMA seems to be behaving for both IN and OUT */
54#define USE_DMA
55
56/* ISO too */
57#define USE_ISO
58
59#define DRIVER_DESC "OMAP UDC driver"
60#define DRIVER_VERSION "4 October 2004"
61
62#define DMA_ADDR_INVALID (~(dma_addr_t)0)
63
1da177e4
LT		 64/*
65 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
66 * D+ pullup to allow enumeration. That's too early for the gadget
67 * framework to use from usb_endpoint_enable(), which happens after
68 * enumeration as part of activating an interface. (But if we add an
69 * optional new "UDC not yet running" state to the gadget driver model,
70 * even just during driver binding, the endpoint autoconfig logic is the
71 * natural spot to manufacture new endpoints.)
72 *
73 * So instead of using endpoint enable calls to control the hardware setup,
74 * this driver defines a "fifo mode" parameter. It's used during driver
75 * initialization to choose among a set of pre-defined endpoint configs.
76 * See omap_udc_setup() for available modes, or to add others. That code
77 * lives in an init section, so use this driver as a module if you need
78 * to change the fifo mode after the kernel boots.
79 *
80 * Gadget drivers normally ignore endpoints they don't care about, and
81 * won't include them in configuration descriptors. That means only
82 * misbehaving hosts would even notice they exist.
83 */
84#ifdef USE_ISO
85static unsigned fifo_mode = 3;
86#else
80dd1358 87static unsigned fifo_mode;
1da177e4
LT		 88#endif
89
90/* "modprobe omap_udc fifo_mode=42", or else as a kernel
91 * boot parameter "omap_udc:fifo_mode=42"
92 */
80dd1358
FB		 93module_param(fifo_mode, uint, 0);
94MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
1da177e4
LT		 95
96#ifdef USE_DMA
90ab5ee9 97static bool use_dma = 1;
1da177e4
LT		 98
99/* "modprobe omap_udc use_dma=y", or else as a kernel
100 * boot parameter "omap_udc:use_dma=y"
101 */
80dd1358
FB		 102module_param(use_dma, bool, 0);
103MODULE_PARM_DESC(use_dma, "enable/disable DMA");
1da177e4
LT		 104#else /* !USE_DMA */
105
106/* save a bit of code */
107#define use_dma 0
108#endif /* !USE_DMA */
109
110
80dd1358
FB		 111static const char driver_name[] = "omap_udc";
112static const char driver_desc[] = DRIVER_DESC;
1da177e4
LT		 113
114/*-------------------------------------------------------------------------*/
115
116/* there's a notion of "current endpoint" for modifying endpoint
e6a6e472 117 * state, and PIO access to its FIFO.
1da177e4
LT		 118 */
119
120static void use_ep(struct omap_ep *ep, u16 select)
121{
122 u16 num = ep->bEndpointAddress & 0x0f;
123
124 if (ep->bEndpointAddress & USB_DIR_IN)
125 num |= UDC_EP_DIR;
f35ae634 126 omap_writew(num | select, UDC_EP_NUM);
1da177e4
LT		 127 /* when select, MUST deselect later !! */
128}
129
130static inline void deselect_ep(void)
131{
f35ae634
TL		 132 u16 w;
133
134 w = omap_readw(UDC_EP_NUM);
135 w &= ~UDC_EP_SEL;
136 omap_writew(w, UDC_EP_NUM);
1da177e4
LT		 137 /* 6 wait states before TX will happen */
138}
139
140static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
141
142/*-------------------------------------------------------------------------*/
143
144static int omap_ep_enable(struct usb_ep *_ep,
145 const struct usb_endpoint_descriptor *desc)
146{
147 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
148 struct omap_udc *udc;
149 unsigned long flags;
150 u16 maxp;
151
152 /* catch various bogus parameters */
f8bdae06 153 if (!_ep || !desc || ep->ep.desc
1da177e4
LT		 154 || desc->bDescriptorType != USB_DT_ENDPOINT
155 || ep->bEndpointAddress != desc->bEndpointAddress
29cc8897 156 || ep->maxpacket < usb_endpoint_maxp(desc)) {
441b62c1 157 DBG("%s, bad ep or descriptor\n", __func__);
1da177e4
LT		 158 return -EINVAL;
159 }
29cc8897 160 maxp = usb_endpoint_maxp(desc);
1da177e4
LT		 161 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
162 && maxp != ep->maxpacket)
29cc8897 163 || usb_endpoint_maxp(desc) > ep->maxpacket
1da177e4 164 || !desc->wMaxPacketSize) {
441b62c1 165 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
1da177e4
LT		 166 return -ERANGE;
167 }
168
169#ifdef USE_ISO
170 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
171 && desc->bInterval != 1)) {
172 /* hardware wants period = 1; USB allows 2^(Interval-1) */
173 DBG("%s, unsupported ISO period %dms\n", _ep->name,
174 1 << (desc->bInterval - 1));
175 return -EDOM;
176 }
177#else
178 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
179 DBG("%s, ISO nyet\n", _ep->name);
180 return -EDOM;
181 }
182#endif
183
184 /* xfer types must match, except that interrupt ~= bulk */
185 if (ep->bmAttributes != desc->bmAttributes
186 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
187 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
441b62c1 188 DBG("%s, %s type mismatch\n", __func__, _ep->name);
1da177e4
LT		 189 return -EINVAL;
190 }
191
192 udc = ep->udc;
193 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
441b62c1 194 DBG("%s, bogus device state\n", __func__);
1da177e4
LT		 195 return -ESHUTDOWN;
196 }
197
198 spin_lock_irqsave(&udc->lock, flags);
199
f8bdae06 200 ep->ep.desc = desc;
1da177e4
LT		 201 ep->irqs = 0;
202 ep->stopped = 0;
203 ep->ep.maxpacket = maxp;
204
205 /* set endpoint to initial state */
206 ep->dma_channel = 0;
207 ep->has_dma = 0;
208 ep->lch = -1;
209 use_ep(ep, UDC_EP_SEL);
f35ae634 210 omap_writew(udc->clr_halt, UDC_CTRL);
1da177e4
LT		 211 ep->ackwait = 0;
212 deselect_ep();
213
214 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
215 list_add(&ep->iso, &udc->iso);
216
217 /* maybe assign a DMA channel to this endpoint */
218 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
219 /* FIXME ISO can dma, but prefers first channel */
220 dma_channel_claim(ep, 0);
221
222 /* PIO OUT may RX packets */
223 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
224 && !ep->has_dma
225 && !(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 226 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 227 ep->ackwait = 1 + ep->double_buf;
228 }
229
230 spin_unlock_irqrestore(&udc->lock, flags);
231 VDBG("%s enabled\n", _ep->name);
232 return 0;
233}
234
235static void nuke(struct omap_ep *, int status);
236
237static int omap_ep_disable(struct usb_ep *_ep)
238{
239 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
240 unsigned long flags;
241
f8bdae06 242 if (!_ep || !ep->ep.desc) {
441b62c1 243 DBG("%s, %s not enabled\n", __func__,
1da177e4
LT		 244 _ep ? ep->ep.name : NULL);
245 return -EINVAL;
246 }
247
248 spin_lock_irqsave(&ep->udc->lock, flags);
f9c56cdd 249 ep->ep.desc = NULL;
80dd1358 250 nuke(ep, -ESHUTDOWN);
1da177e4
LT		 251 ep->ep.maxpacket = ep->maxpacket;
252 ep->has_dma = 0;
f35ae634 253 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 254 list_del_init(&ep->iso);
255 del_timer(&ep->timer);
256
257 spin_unlock_irqrestore(&ep->udc->lock, flags);
258
259 VDBG("%s disabled\n", _ep->name);
260 return 0;
261}
262
263/*-------------------------------------------------------------------------*/
264
265static struct usb_request *
55016f10 266omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1da177e4
LT		 267{
268 struct omap_req *req;
269
7039f422 270 req = kzalloc(sizeof(*req), gfp_flags);
1da177e4 271 if (req) {
1da177e4 272 req->req.dma = DMA_ADDR_INVALID;
80dd1358 273 INIT_LIST_HEAD(&req->queue);
1da177e4
LT		 274 }
275 return &req->req;
276}
277
278static void
279omap_free_request(struct usb_ep *ep, struct usb_request *_req)
280{
281 struct omap_req *req = container_of(_req, struct omap_req, req);
282
283 if (_req)
80dd1358 284 kfree(req);
1da177e4
LT		 285}
286
287/*-------------------------------------------------------------------------*/
288
1da177e4
LT		 289static void
290done(struct omap_ep *ep, struct omap_req *req, int status)
291{
292 unsigned stopped = ep->stopped;
293
294 list_del_init(&req->queue);
295
296 if (req->req.status == -EINPROGRESS)
297 req->req.status = status;
298 else
299 status = req->req.status;
300
301 if (use_dma && ep->has_dma) {
302 if (req->mapped) {
303 dma_unmap_single(ep->udc->gadget.dev.parent,
304 req->req.dma, req->req.length,
305 (ep->bEndpointAddress & USB_DIR_IN)
306 ? DMA_TO_DEVICE
307 : DMA_FROM_DEVICE);
308 req->req.dma = DMA_ADDR_INVALID;
309 req->mapped = 0;
310 } else
311 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
312 req->req.dma, req->req.length,
313 (ep->bEndpointAddress & USB_DIR_IN)
314 ? DMA_TO_DEVICE
315 : DMA_FROM_DEVICE);
316 }
317
318#ifndef USB_TRACE
319 if (status && status != -ESHUTDOWN)
320#endif
321 VDBG("complete %s req %p stat %d len %u/%u\n",
322 ep->ep.name, &req->req, status,
323 req->req.actual, req->req.length);
324
325 /* don't modify queue heads during completion callback */
326 ep->stopped = 1;
327 spin_unlock(&ep->udc->lock);
328 req->req.complete(&ep->ep, &req->req);
329 spin_lock(&ep->udc->lock);
330 ep->stopped = stopped;
331}
332
333/*-------------------------------------------------------------------------*/
334
313980c9
DB		 335#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
336#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
1da177e4
LT		 337
338#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
339#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
340
e6a6e472 341static inline int
1da177e4
LT		 342write_packet(u8 *buf, struct omap_req *req, unsigned max)
343{
344 unsigned len;
345 u16 *wp;
346
347 len = min(req->req.length - req->req.actual, max);
348 req->req.actual += len;
349
350 max = len;
351 if (likely((((int)buf) & 1) == 0)) {
352 wp = (u16 *)buf;
353 while (max >= 2) {
f35ae634 354 omap_writew(*wp++, UDC_DATA);
1da177e4
LT		 355 max -= 2;
356 }
357 buf = (u8 *)wp;
358 }
359 while (max--)
f35ae634 360 omap_writeb(*buf++, UDC_DATA);
1da177e4
LT		 361 return len;
362}
363
80dd1358 364/* FIXME change r/w fifo calling convention */
1da177e4
LT		 365
366
80dd1358 367/* return: 0 = still running, 1 = completed, negative = errno */
1da177e4
LT		 368static int write_fifo(struct omap_ep *ep, struct omap_req *req)
369{
370 u8 *buf;
371 unsigned count;
372 int is_last;
373 u16 ep_stat;
374
375 buf = req->req.buf + req->req.actual;
376 prefetch(buf);
377
378 /* PIO-IN isn't double buffered except for iso */
f35ae634 379 ep_stat = omap_readw(UDC_STAT_FLG);
313980c9 380 if (ep_stat & UDC_FIFO_UNWRITABLE)
1da177e4
LT		 381 return 0;
382
383 count = ep->ep.maxpacket;
384 count = write_packet(buf, req, count);
f35ae634 385 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 386 ep->ackwait = 1;
387
388 /* last packet is often short (sometimes a zlp) */
389 if (count != ep->ep.maxpacket)
390 is_last = 1;
391 else if (req->req.length == req->req.actual
392 && !req->req.zero)
393 is_last = 1;
394 else
395 is_last = 0;
396
397 /* NOTE: requests complete when all IN data is in a
398 * FIFO (or sometimes later, if a zlp was needed).
399 * Use usb_ep_fifo_status() where needed.
400 */
401 if (is_last)
402 done(ep, req, 0);
403 return is_last;
404}
405
e6a6e472 406static inline int
1da177e4
LT		 407read_packet(u8 *buf, struct omap_req *req, unsigned avail)
408{
409 unsigned len;
410 u16 *wp;
411
412 len = min(req->req.length - req->req.actual, avail);
413 req->req.actual += len;
414 avail = len;
415
416 if (likely((((int)buf) & 1) == 0)) {
417 wp = (u16 *)buf;
418 while (avail >= 2) {
f35ae634 419 *wp++ = omap_readw(UDC_DATA);
1da177e4
LT		 420 avail -= 2;
421 }
422 buf = (u8 *)wp;
423 }
424 while (avail--)
f35ae634 425 *buf++ = omap_readb(UDC_DATA);
1da177e4
LT		 426 return len;
427}
428
80dd1358 429/* return: 0 = still running, 1 = queue empty, negative = errno */
1da177e4
LT		 430static int read_fifo(struct omap_ep *ep, struct omap_req *req)
431{
432 u8 *buf;
433 unsigned count, avail;
434 int is_last;
435
436 buf = req->req.buf + req->req.actual;
437 prefetchw(buf);
438
439 for (;;) {
f35ae634 440 u16 ep_stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 441
442 is_last = 0;
443 if (ep_stat & FIFO_EMPTY) {
444 if (!ep->double_buf)
445 break;
446 ep->fnf = 1;
447 }
448 if (ep_stat & UDC_EP_HALTED)
449 break;
450
313980c9 451 if (ep_stat & UDC_FIFO_FULL)
1da177e4
LT		 452 avail = ep->ep.maxpacket;
453 else {
f35ae634 454 avail = omap_readw(UDC_RXFSTAT);
1da177e4
LT		 455 ep->fnf = ep->double_buf;
456 }
457 count = read_packet(buf, req, avail);
458
459 /* partial packet reads may not be errors */
460 if (count < ep->ep.maxpacket) {
461 is_last = 1;
462 /* overflowed this request? flush extra data */
463 if (count != avail) {
464 req->req.status = -EOVERFLOW;
465 avail -= count;
466 while (avail--)
f35ae634 467 omap_readw(UDC_DATA);
1da177e4
LT		 468 }
469 } else if (req->req.length == req->req.actual)
470 is_last = 1;
471 else
472 is_last = 0;
473
474 if (!ep->bEndpointAddress)
475 break;
476 if (is_last)
477 done(ep, req, 0);
478 break;
479 }
480 return is_last;
481}
482
483/*-------------------------------------------------------------------------*/
484
485static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
486{
487 dma_addr_t end;
488
489 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
490 * the last transfer's bytecount by more than a FIFO's worth.
491 */
492 if (cpu_is_omap15xx())
493 return 0;
494
0499bdeb 495 end = omap_get_dma_src_pos(ep->lch);
1da177e4
LT		 496 if (end == ep->dma_counter)
497 return 0;
498
499 end |= start & (0xffff << 16);
500 if (end < start)
501 end += 0x10000;
502 return end - start;
503}
504
1da177e4
LT		 505static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
506{
507 dma_addr_t end;
508
0499bdeb 509 end = omap_get_dma_dst_pos(ep->lch);
1da177e4
LT		 510 if (end == ep->dma_counter)
511 return 0;
512
513 end |= start & (0xffff << 16);
514 if (cpu_is_omap15xx())
515 end++;
516 if (end < start)
517 end += 0x10000;
518 return end - start;
519}
520
521
522/* Each USB transfer request using DMA maps to one or more DMA transfers.
523 * When DMA completion isn't request completion, the UDC continues with
524 * the next DMA transfer for that USB transfer.
525 */
526
527static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
528{
f35ae634 529 u16 txdma_ctrl, w;
1da177e4
LT		 530 unsigned length = req->req.length - req->req.actual;
531 const int sync_mode = cpu_is_omap15xx()
532 ? OMAP_DMA_SYNC_FRAME
533 : OMAP_DMA_SYNC_ELEMENT;
527ea73e
KP		 534 int dma_trigger = 0;
535
1da177e4 536 /* measure length in either bytes or packets */
65111084 537 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
1da177e4
LT		 538 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
539 txdma_ctrl = UDC_TXN_EOT | length;
540 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
527ea73e 541 length, 1, sync_mode, dma_trigger, 0);
1da177e4
LT		 542 } else {
543 length = min(length / ep->maxpacket,
544 (unsigned) UDC_TXN_TSC + 1);
e6a6e472 545 txdma_ctrl = length;
65111084 546 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
e6a6e472 547 ep->ep.maxpacket >> 1, length, sync_mode,
527ea73e 548 dma_trigger, 0);
1da177e4
LT		 549 length *= ep->maxpacket;
550 }
551 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
e6a6e472
DB		 552 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
553 0, 0);
1da177e4
LT		 554
555 omap_start_dma(ep->lch);
0499bdeb 556 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
f35ae634
TL		 557 w = omap_readw(UDC_DMA_IRQ_EN);
558 w |= UDC_TX_DONE_IE(ep->dma_channel);
559 omap_writew(w, UDC_DMA_IRQ_EN);
560 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
1da177e4
LT		 561 req->dma_bytes = length;
562}
563
564static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
565{
f35ae634
TL		 566 u16 w;
567
1da177e4
LT		 568 if (status == 0) {
569 req->req.actual += req->dma_bytes;
570
571 /* return if this request needs to send data or zlp */
572 if (req->req.actual < req->req.length)
573 return;
574 if (req->req.zero
575 && req->dma_bytes != 0
576 && (req->req.actual % ep->maxpacket) == 0)
577 return;
578 } else
579 req->req.actual += dma_src_len(ep, req->req.dma
580 + req->req.actual);
581
582 /* tx completion */
583 omap_stop_dma(ep->lch);
f35ae634
TL		 584 w = omap_readw(UDC_DMA_IRQ_EN);
585 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
586 omap_writew(w, UDC_DMA_IRQ_EN);
1da177e4
LT		 587 done(ep, req, status);
588}
589
590static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
591{
527ea73e
KP		 592 unsigned packets = req->req.length - req->req.actual;
593 int dma_trigger = 0;
f35ae634 594 u16 w;
527ea73e 595
ae372571
TL		 596 /* set up this DMA transfer, enable the fifo, start */
597 packets /= ep->ep.maxpacket;
598 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
599 req->dma_bytes = packets * ep->ep.maxpacket;
600 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
601 ep->ep.maxpacket >> 1, packets,
602 OMAP_DMA_SYNC_ELEMENT,
603 dma_trigger, 0);
1da177e4 604 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
e6a6e472
DB		 605 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
606 0, 0);
0499bdeb 607 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
1da177e4 608
f35ae634
TL		 609 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
610 w = omap_readw(UDC_DMA_IRQ_EN);
611 w |= UDC_RX_EOT_IE(ep->dma_channel);
612 omap_writew(w, UDC_DMA_IRQ_EN);
613 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
614 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 615
616 omap_start_dma(ep->lch);
617}
618
619static void
cb97c5c9 620finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
1da177e4 621{
f35ae634 622 u16 count, w;
1da177e4
LT		 623
624 if (status == 0)
625 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
626 count = dma_dest_len(ep, req->req.dma + req->req.actual);
627 count += req->req.actual;
cb97c5c9
DB		 628 if (one)
629 count--;
1da177e4
LT		 630 if (count <= req->req.length)
631 req->req.actual = count;
632
633 if (count != req->dma_bytes || status)
634 omap_stop_dma(ep->lch);
635
636 /* if this wasn't short, request may need another transfer */
637 else if (req->req.actual < req->req.length)
638 return;
639
640 /* rx completion */
f35ae634
TL		 641 w = omap_readw(UDC_DMA_IRQ_EN);
642 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
643 omap_writew(w, UDC_DMA_IRQ_EN);
1da177e4
LT		 644 done(ep, req, status);
645}
646
647static void dma_irq(struct omap_udc *udc, u16 irq_src)
648{
f35ae634 649 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
1da177e4
LT		 650 struct omap_ep *ep;
651 struct omap_req *req;
652
653 /* IN dma: tx to host */
654 if (irq_src & UDC_TXN_DONE) {
655 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
656 ep->irqs++;
657 /* can see TXN_DONE after dma abort */
658 if (!list_empty(&ep->queue)) {
659 req = container_of(ep->queue.next,
660 struct omap_req, queue);
661 finish_in_dma(ep, req, 0);
662 }
f35ae634 663 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
1da177e4 664
80dd1358 665 if (!list_empty(&ep->queue)) {
1da177e4
LT		 666 req = container_of(ep->queue.next,
667 struct omap_req, queue);
668 next_in_dma(ep, req);
669 }
670 }
671
672 /* OUT dma: rx from host */
673 if (irq_src & UDC_RXN_EOT) {
674 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
675 ep->irqs++;
676 /* can see RXN_EOT after dma abort */
677 if (!list_empty(&ep->queue)) {
678 req = container_of(ep->queue.next,
679 struct omap_req, queue);
cb97c5c9 680 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
1da177e4 681 }
f35ae634 682 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
1da177e4 683
80dd1358 684 if (!list_empty(&ep->queue)) {
1da177e4
LT		 685 req = container_of(ep->queue.next,
686 struct omap_req, queue);
687 next_out_dma(ep, req);
688 }
689 }
690
691 if (irq_src & UDC_RXN_CNT) {
692 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
693 ep->irqs++;
694 /* omap15xx does this unasked... */
695 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
f35ae634 696 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
1da177e4
LT		 697 }
698}
699
700static void dma_error(int lch, u16 ch_status, void *data)
701{
702 struct omap_ep *ep = data;
703
704 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
7ff879db 705 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
1da177e4
LT		 706 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
707
708 /* complete current transfer ... */
709}
710
711static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
712{
713 u16 reg;
714 int status, restart, is_in;
527ea73e 715 int dma_channel;
1da177e4
LT		 716
717 is_in = ep->bEndpointAddress & USB_DIR_IN;
718 if (is_in)
f35ae634 719 reg = omap_readw(UDC_TXDMA_CFG);
1da177e4 720 else
f35ae634 721 reg = omap_readw(UDC_RXDMA_CFG);
65111084 722 reg |= UDC_DMA_REQ; /* "pulse" activated */
1da177e4
LT		 723
724 ep->dma_channel = 0;
725 ep->lch = -1;
726 if (channel == 0 || channel > 3) {
727 if ((reg & 0x0f00) == 0)
728 channel = 3;
729 else if ((reg & 0x00f0) == 0)
730 channel = 2;
731 else if ((reg & 0x000f) == 0) /* preferred for ISO */
732 channel = 1;
733 else {
734 status = -EMLINK;
735 goto just_restart;
736 }
737 }
738 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
739 ep->dma_channel = channel;
740
741 if (is_in) {
ae372571 742 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
527ea73e 743 status = omap_request_dma(dma_channel,
1da177e4
LT		 744 ep->ep.name, dma_error, ep, &ep->lch);
745 if (status == 0) {
f35ae634 746 omap_writew(reg, UDC_TXDMA_CFG);
527ea73e 747 /* EMIFF or SDRC */
65111084
DB		 748 omap_set_dma_src_burst_mode(ep->lch,
749 OMAP_DMA_DATA_BURST_4);
750 omap_set_dma_src_data_pack(ep->lch, 1);
751 /* TIPB */
1da177e4
LT		 752 omap_set_dma_dest_params(ep->lch,
753 OMAP_DMA_PORT_TIPB,
754 OMAP_DMA_AMODE_CONSTANT,
c3e3208e 755 UDC_DATA_DMA,
e6a6e472 756 0, 0);
1da177e4
LT		 757 }
758 } else {
ae372571 759 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
527ea73e 760 status = omap_request_dma(dma_channel,
1da177e4
LT		 761 ep->ep.name, dma_error, ep, &ep->lch);
762 if (status == 0) {
f35ae634 763 omap_writew(reg, UDC_RXDMA_CFG);
65111084 764 /* TIPB */
1da177e4
LT		 765 omap_set_dma_src_params(ep->lch,
766 OMAP_DMA_PORT_TIPB,
767 OMAP_DMA_AMODE_CONSTANT,
c3e3208e 768 UDC_DATA_DMA,
e6a6e472 769 0, 0);
527ea73e 770 /* EMIFF or SDRC */
65111084
DB		 771 omap_set_dma_dest_burst_mode(ep->lch,
772 OMAP_DMA_DATA_BURST_4);
773 omap_set_dma_dest_data_pack(ep->lch, 1);
1da177e4
LT		 774 }
775 }
776 if (status)
777 ep->dma_channel = 0;
778 else {
779 ep->has_dma = 1;
780 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
781
782 /* channel type P: hw synch (fifo) */
ae372571 783 if (!cpu_is_omap15xx())
0499bdeb 784 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
1da177e4
LT		 785 }
786
787just_restart:
788 /* restart any queue, even if the claim failed */
789 restart = !ep->stopped && !list_empty(&ep->queue);
790
791 if (status)
792 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
793 restart ? " (restart)" : "");
794 else
795 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
796 is_in ? 't' : 'r',
797 ep->dma_channel - 1, ep->lch,
798 restart ? " (restart)" : "");
799
800 if (restart) {
801 struct omap_req *req;
802 req = container_of(ep->queue.next, struct omap_req, queue);
803 if (ep->has_dma)
804 (is_in ? next_in_dma : next_out_dma)(ep, req);
805 else {
806 use_ep(ep, UDC_EP_SEL);
807 (is_in ? write_fifo : read_fifo)(ep, req);
808 deselect_ep();
809 if (!is_in) {
f35ae634 810 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 811 ep->ackwait = 1 + ep->double_buf;
812 }
813 /* IN: 6 wait states before it'll tx */
814 }
815 }
816}
817
818static void dma_channel_release(struct omap_ep *ep)
819{
820 int shift = 4 * (ep->dma_channel - 1);
821 u16 mask = 0x0f << shift;
822 struct omap_req *req;
823 int active;
824
825 /* abort any active usb transfer request */
826 if (!list_empty(&ep->queue))
827 req = container_of(ep->queue.next, struct omap_req, queue);
828 else
313980c9 829 req = NULL;
1da177e4 830
0499bdeb 831 active = omap_get_dma_active_status(ep->lch);
1da177e4
LT		 832
833 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
834 active ? "active" : "idle",
835 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
836 ep->dma_channel - 1, req);
837
65111084
DB		 838 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
839 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
840 */
841
1da177e4
LT		 842 /* wait till current packet DMA finishes, and fifo empties */
843 if (ep->bEndpointAddress & USB_DIR_IN) {
f35ae634
TL		 844 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
845 UDC_TXDMA_CFG);
1da177e4
LT		 846
847 if (req) {
848 finish_in_dma(ep, req, -ECONNRESET);
849
850 /* clear FIFO; hosts probably won't empty it */
851 use_ep(ep, UDC_EP_SEL);
f35ae634 852 omap_writew(UDC_CLR_EP, UDC_CTRL);
1da177e4
LT		 853 deselect_ep();
854 }
f35ae634 855 while (omap_readw(UDC_TXDMA_CFG) & mask)
1da177e4
LT		 856 udelay(10);
857 } else {
f35ae634
TL		 858 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
859 UDC_RXDMA_CFG);
1da177e4
LT		 860
861 /* dma empties the fifo */
f35ae634 862 while (omap_readw(UDC_RXDMA_CFG) & mask)
1da177e4
LT		 863 udelay(10);
864 if (req)
cb97c5c9 865 finish_out_dma(ep, req, -ECONNRESET, 0);
1da177e4
LT		 866 }
867 omap_free_dma(ep->lch);
868 ep->dma_channel = 0;
869 ep->lch = -1;
870 /* has_dma still set, till endpoint is fully quiesced */
871}
872
873
874/*-------------------------------------------------------------------------*/
875
876static int
55016f10 877omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1da177e4
LT		 878{
879 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
880 struct omap_req *req = container_of(_req, struct omap_req, req);
881 struct omap_udc *udc;
882 unsigned long flags;
883 int is_iso = 0;
884
885 /* catch various bogus parameters */
886 if (!_req || !req->req.complete || !req->req.buf
887 || !list_empty(&req->queue)) {
441b62c1 888 DBG("%s, bad params\n", __func__);
1da177e4
LT		 889 return -EINVAL;
890 }
f8bdae06 891 if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
441b62c1 892 DBG("%s, bad ep\n", __func__);
1da177e4
LT		 893 return -EINVAL;
894 }
895 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
896 if (req->req.length > ep->ep.maxpacket)
897 return -EMSGSIZE;
898 is_iso = 1;
899 }
900
901 /* this isn't bogus, but OMAP DMA isn't the only hardware to
902 * have a hard time with partial packet reads... reject it.
903 */
904 if (use_dma
905 && ep->has_dma
906 && ep->bEndpointAddress != 0
907 && (ep->bEndpointAddress & USB_DIR_IN) == 0
908 && (req->req.length % ep->ep.maxpacket) != 0) {
441b62c1 909 DBG("%s, no partial packet OUT reads\n", __func__);
1da177e4
LT		 910 return -EMSGSIZE;
911 }
912
913 udc = ep->udc;
914 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
915 return -ESHUTDOWN;
916
917 if (use_dma && ep->has_dma) {
918 if (req->req.dma == DMA_ADDR_INVALID) {
919 req->req.dma = dma_map_single(
920 ep->udc->gadget.dev.parent,
921 req->req.buf,
922 req->req.length,
923 (ep->bEndpointAddress & USB_DIR_IN)
924 ? DMA_TO_DEVICE
925 : DMA_FROM_DEVICE);
926 req->mapped = 1;
927 } else {
928 dma_sync_single_for_device(
929 ep->udc->gadget.dev.parent,
930 req->req.dma, req->req.length,
931 (ep->bEndpointAddress & USB_DIR_IN)
932 ? DMA_TO_DEVICE
933 : DMA_FROM_DEVICE);
934 req->mapped = 0;
935 }
936 }
937
938 VDBG("%s queue req %p, len %d buf %p\n",
939 ep->ep.name, _req, _req->length, _req->buf);
940
941 spin_lock_irqsave(&udc->lock, flags);
942
943 req->req.status = -EINPROGRESS;
944 req->req.actual = 0;
945
946 /* maybe kickstart non-iso i/o queues */
f35ae634
TL		 947 if (is_iso) {
948 u16 w;
949
950 w = omap_readw(UDC_IRQ_EN);
951 w |= UDC_SOF_IE;
952 omap_writew(w, UDC_IRQ_EN);
953 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1da177e4
LT		 954 int is_in;
955
956 if (ep->bEndpointAddress == 0) {
80dd1358 957 if (!udc->ep0_pending || !list_empty(&ep->queue)) {
1da177e4
LT		 958 spin_unlock_irqrestore(&udc->lock, flags);
959 return -EL2HLT;
960 }
961
962 /* empty DATA stage? */
963 is_in = udc->ep0_in;
964 if (!req->req.length) {
965
966 /* chip became CONFIGURED or ADDRESSED
967 * earlier; drivers may already have queued
968 * requests to non-control endpoints
969 */
970 if (udc->ep0_set_config) {
f35ae634 971 u16 irq_en = omap_readw(UDC_IRQ_EN);
1da177e4
LT		 972
973 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
974 if (!udc->ep0_reset_config)
975 irq_en |= UDC_EPN_RX_IE
976 | UDC_EPN_TX_IE;
f35ae634 977 omap_writew(irq_en, UDC_IRQ_EN);
1da177e4
LT		 978 }
979
313980c9
DB		 980 /* STATUS for zero length DATA stages is
981 * always an IN ... even for IN transfers,
dc0d5c1e 982 * a weird case which seem to stall OMAP.
313980c9 983 */
80dd1358
FB		 984 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
985 UDC_EP_NUM);
f35ae634
TL		 986 omap_writew(UDC_CLR_EP, UDC_CTRL);
987 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
988 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 989
990 /* cleanup */
991 udc->ep0_pending = 0;
992 done(ep, req, 0);
313980c9 993 req = NULL;
1da177e4
LT		 994
995 /* non-empty DATA stage */
996 } else if (is_in) {
80dd1358
FB		 997 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
998 UDC_EP_NUM);
1da177e4
LT		 999 } else {
1000 if (udc->ep0_setup)
1001 goto irq_wait;
f35ae634 1002 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1da177e4
LT		 1003 }
1004 } else {
1005 is_in = ep->bEndpointAddress & USB_DIR_IN;
1006 if (!ep->has_dma)
1007 use_ep(ep, UDC_EP_SEL);
1008 /* if ISO: SOF IRQs must be enabled/disabled! */
1009 }
1010
1011 if (ep->has_dma)
1012 (is_in ? next_in_dma : next_out_dma)(ep, req);
1013 else if (req) {
1014 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
313980c9 1015 req = NULL;
1da177e4
LT		 1016 deselect_ep();
1017 if (!is_in) {
f35ae634 1018 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1019 ep->ackwait = 1 + ep->double_buf;
1020 }
1021 /* IN: 6 wait states before it'll tx */
1022 }
1023 }
1024
1025irq_wait:
1026 /* irq handler advances the queue */
313980c9 1027 if (req != NULL)
1da177e4
LT		 1028 list_add_tail(&req->queue, &ep->queue);
1029 spin_unlock_irqrestore(&udc->lock, flags);
1030
1031 return 0;
1032}
1033
1034static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1035{
1036 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1037 struct omap_req *req;
1038 unsigned long flags;
1039
1040 if (!_ep || !_req)
1041 return -EINVAL;
1042
1043 spin_lock_irqsave(&ep->udc->lock, flags);
1044
1045 /* make sure it's actually queued on this endpoint */
80dd1358 1046 list_for_each_entry(req, &ep->queue, queue) {
1da177e4
LT		 1047 if (&req->req == _req)
1048 break;
1049 }
1050 if (&req->req != _req) {
1051 spin_unlock_irqrestore(&ep->udc->lock, flags);
1052 return -EINVAL;
1053 }
1054
1055 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1056 int channel = ep->dma_channel;
1057
1058 /* releasing the channel cancels the request,
1059 * reclaiming the channel restarts the queue
1060 */
1061 dma_channel_release(ep);
1062 dma_channel_claim(ep, channel);
e6a6e472 1063 } else
1da177e4
LT		 1064 done(ep, req, -ECONNRESET);
1065 spin_unlock_irqrestore(&ep->udc->lock, flags);
1066 return 0;
1067}
1068
1069/*-------------------------------------------------------------------------*/
1070
1071static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1072{
1073 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1074 unsigned long flags;
1075 int status = -EOPNOTSUPP;
1076
1077 spin_lock_irqsave(&ep->udc->lock, flags);
1078
1079 /* just use protocol stalls for ep0; real halts are annoying */
1080 if (ep->bEndpointAddress == 0) {
1081 if (!ep->udc->ep0_pending)
1082 status = -EINVAL;
1083 else if (value) {
1084 if (ep->udc->ep0_set_config) {
b6c63937 1085 WARNING("error changing config?\n");
f35ae634 1086 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1087 }
f35ae634 1088 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1089 ep->udc->ep0_pending = 0;
1090 status = 0;
1091 } else /* NOP */
1092 status = 0;
1093
1094 /* otherwise, all active non-ISO endpoints can halt */
f8bdae06 1095 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1da177e4
LT		 1096
1097 /* IN endpoints must already be idle */
1098 if ((ep->bEndpointAddress & USB_DIR_IN)
e6a6e472 1099 && !list_empty(&ep->queue)) {
1da177e4
LT		 1100 status = -EAGAIN;
1101 goto done;
1102 }
1103
1104 if (value) {
1105 int channel;
1106
1107 if (use_dma && ep->dma_channel
1108 && !list_empty(&ep->queue)) {
1109 channel = ep->dma_channel;
1110 dma_channel_release(ep);
1111 } else
1112 channel = 0;
1113
1114 use_ep(ep, UDC_EP_SEL);
f35ae634
TL		 1115 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1116 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1117 status = 0;
1118 } else
1119 status = -EAGAIN;
1120 deselect_ep();
1121
1122 if (channel)
1123 dma_channel_claim(ep, channel);
1124 } else {
1125 use_ep(ep, 0);
f35ae634 1126 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1da177e4
LT		 1127 ep->ackwait = 0;
1128 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 1129 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1130 ep->ackwait = 1 + ep->double_buf;
1131 }
1132 }
1133 }
1134done:
1135 VDBG("%s %s halt stat %d\n", ep->ep.name,
1136 value ? "set" : "clear", status);
1137
1138 spin_unlock_irqrestore(&ep->udc->lock, flags);
1139 return status;
1140}
1141
1142static struct usb_ep_ops omap_ep_ops = {
1143 .enable = omap_ep_enable,
1144 .disable = omap_ep_disable,
1145
1146 .alloc_request = omap_alloc_request,
1147 .free_request = omap_free_request,
1148
1da177e4
LT		 1149 .queue = omap_ep_queue,
1150 .dequeue = omap_ep_dequeue,
1151
1152 .set_halt = omap_ep_set_halt,
80dd1358
FB		 1153 /* fifo_status ... report bytes in fifo */
1154 /* fifo_flush ... flush fifo */
1da177e4
LT		 1155};
1156
1157/*-------------------------------------------------------------------------*/
1158
1159static int omap_get_frame(struct usb_gadget *gadget)
1160{
f35ae634 1161 u16 sof = omap_readw(UDC_SOF);
1da177e4
LT		 1162 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1163}
1164
1165static int omap_wakeup(struct usb_gadget *gadget)
1166{
1167 struct omap_udc *udc;
1168 unsigned long flags;
1169 int retval = -EHOSTUNREACH;
1170
1171 udc = container_of(gadget, struct omap_udc, gadget);
1172
1173 spin_lock_irqsave(&udc->lock, flags);
1174 if (udc->devstat & UDC_SUS) {
1175 /* NOTE: OTG spec erratum says that OTG devices may
1176 * issue wakeups without host enable.
1177 */
1178 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1179 DBG("remote wakeup...\n");
f35ae634 1180 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1da177e4
LT		 1181 retval = 0;
1182 }
1183
1184 /* NOTE: non-OTG systems may use SRP TOO... */
1185 } else if (!(udc->devstat & UDC_ATT)) {
1186 if (udc->transceiver)
6e13c650 1187 retval = otg_start_srp(udc->transceiver->otg);
1da177e4
LT		 1188 }
1189 spin_unlock_irqrestore(&udc->lock, flags);
1190
1191 return retval;
1192}
1193
1194static int
1195omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1196{
1197 struct omap_udc *udc;
1198 unsigned long flags;
1199 u16 syscon1;
1200
1201 udc = container_of(gadget, struct omap_udc, gadget);
1202 spin_lock_irqsave(&udc->lock, flags);
f35ae634 1203 syscon1 = omap_readw(UDC_SYSCON1);
1da177e4
LT		 1204 if (is_selfpowered)
1205 syscon1 |= UDC_SELF_PWR;
1206 else
1207 syscon1 &= ~UDC_SELF_PWR;
f35ae634 1208 omap_writew(syscon1, UDC_SYSCON1);
1da177e4
LT		 1209 spin_unlock_irqrestore(&udc->lock, flags);
1210
1211 return 0;
1212}
1213
1214static int can_pullup(struct omap_udc *udc)
1215{
1216 return udc->driver && udc->softconnect && udc->vbus_active;
1217}
1218
1219static void pullup_enable(struct omap_udc *udc)
1220{
f35ae634
TL		 1221 u16 w;
1222
1223 w = omap_readw(UDC_SYSCON1);
1224 w |= UDC_PULLUP_EN;
1225 omap_writew(w, UDC_SYSCON1);
1226 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1227 u32 l;
1228
1229 l = omap_readl(OTG_CTRL);
1230 l |= OTG_BSESSVLD;
1231 omap_writel(l, OTG_CTRL);
1232 }
1233 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1da177e4
LT		 1234}
1235
1236static void pullup_disable(struct omap_udc *udc)
1237{
f35ae634
TL		 1238 u16 w;
1239
1240 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1241 u32 l;
1242
1243 l = omap_readl(OTG_CTRL);
1244 l &= ~OTG_BSESSVLD;
1245 omap_writel(l, OTG_CTRL);
1246 }
1247 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1248 w = omap_readw(UDC_SYSCON1);
1249 w &= ~UDC_PULLUP_EN;
1250 omap_writew(w, UDC_SYSCON1);
1da177e4
LT		 1251}
1252
e6a6e472
DB		 1253static struct omap_udc *udc;
1254
1255static void omap_udc_enable_clock(int enable)
1256{
1257 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1258 return;
1259
1260 if (enable) {
1261 clk_enable(udc->dc_clk);
1262 clk_enable(udc->hhc_clk);
1263 udelay(100);
1264 } else {
1265 clk_disable(udc->hhc_clk);
1266 clk_disable(udc->dc_clk);
1267 }
1268}
1269
1da177e4
LT		 1270/*
1271 * Called by whatever detects VBUS sessions: external transceiver
1272 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1273 */
1274static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1275{
1276 struct omap_udc *udc;
1277 unsigned long flags;
f35ae634 1278 u32 l;
1da177e4
LT		 1279
1280 udc = container_of(gadget, struct omap_udc, gadget);
1281 spin_lock_irqsave(&udc->lock, flags);
1282 VDBG("VBUS %s\n", is_active ? "on" : "off");
1283 udc->vbus_active = (is_active != 0);
1284 if (cpu_is_omap15xx()) {
1285 /* "software" detect, ignored if !VBUS_MODE_1510 */
f35ae634 1286 l = omap_readl(FUNC_MUX_CTRL_0);
1da177e4 1287 if (is_active)
f35ae634 1288 l |= VBUS_CTRL_1510;
1da177e4 1289 else
f35ae634
TL		 1290 l &= ~VBUS_CTRL_1510;
1291 omap_writel(l, FUNC_MUX_CTRL_0);
1da177e4 1292 }
e6a6e472
DB		 1293 if (udc->dc_clk != NULL && is_active) {
1294 if (!udc->clk_requested) {
1295 omap_udc_enable_clock(1);
1296 udc->clk_requested = 1;
1297 }
1298 }
1da177e4
LT		 1299 if (can_pullup(udc))
1300 pullup_enable(udc);
1301 else
1302 pullup_disable(udc);
e6a6e472
DB		 1303 if (udc->dc_clk != NULL && !is_active) {
1304 if (udc->clk_requested) {
1305 omap_udc_enable_clock(0);
1306 udc->clk_requested = 0;
1307 }
1308 }
1da177e4
LT		 1309 spin_unlock_irqrestore(&udc->lock, flags);
1310 return 0;
1311}
1312
1313static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1314{
1315 struct omap_udc *udc;
1316
1317 udc = container_of(gadget, struct omap_udc, gadget);
1318 if (udc->transceiver)
b96d3b08 1319 return usb_phy_set_power(udc->transceiver, mA);
1da177e4
LT		 1320 return -EOPNOTSUPP;
1321}
1322
1323static int omap_pullup(struct usb_gadget *gadget, int is_on)
1324{
1325 struct omap_udc *udc;
1326 unsigned long flags;
1327
1328 udc = container_of(gadget, struct omap_udc, gadget);
1329 spin_lock_irqsave(&udc->lock, flags);
1330 udc->softconnect = (is_on != 0);
1331 if (can_pullup(udc))
1332 pullup_enable(udc);
1333 else
1334 pullup_disable(udc);
1335 spin_unlock_irqrestore(&udc->lock, flags);
1336 return 0;
1337}
1338
0f91349b
SAS		 1339static int omap_udc_start(struct usb_gadget_driver *driver,
1340 int (*bind)(struct usb_gadget *));
1341static int omap_udc_stop(struct usb_gadget_driver *driver);
1342
1da177e4
LT		 1343static struct usb_gadget_ops omap_gadget_ops = {
1344 .get_frame = omap_get_frame,
1345 .wakeup = omap_wakeup,
1346 .set_selfpowered = omap_set_selfpowered,
1347 .vbus_session = omap_vbus_session,
1348 .vbus_draw = omap_vbus_draw,
1349 .pullup = omap_pullup,
0f91349b
SAS		 1350 .start = omap_udc_start,
1351 .stop = omap_udc_stop,
1da177e4
LT		 1352};
1353
1354/*-------------------------------------------------------------------------*/
1355
1356/* dequeue ALL requests; caller holds udc->lock */
1357static void nuke(struct omap_ep *ep, int status)
1358{
1359 struct omap_req *req;
1360
1361 ep->stopped = 1;
1362
1363 if (use_dma && ep->dma_channel)
1364 dma_channel_release(ep);
1365
1366 use_ep(ep, 0);
f35ae634 1367 omap_writew(UDC_CLR_EP, UDC_CTRL);
1da177e4 1368 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
f35ae634 1369 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1370
1371 while (!list_empty(&ep->queue)) {
1372 req = list_entry(ep->queue.next, struct omap_req, queue);
1373 done(ep, req, status);
1374 }
1375}
1376
1377/* caller holds udc->lock */
1378static void udc_quiesce(struct omap_udc *udc)
1379{
1380 struct omap_ep *ep;
1381
1382 udc->gadget.speed = USB_SPEED_UNKNOWN;
1383 nuke(&udc->ep[0], -ESHUTDOWN);
80dd1358 1384 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1da177e4
LT		 1385 nuke(ep, -ESHUTDOWN);
1386}
1387
1388/*-------------------------------------------------------------------------*/
1389
1390static void update_otg(struct omap_udc *udc)
1391{
1392 u16 devstat;
1393
9cfbba73 1394 if (!gadget_is_otg(&udc->gadget))
1da177e4
LT		 1395 return;
1396
f35ae634
TL		 1397 if (omap_readl(OTG_CTRL) & OTG_ID)
1398 devstat = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 1399 else
1400 devstat = 0;
1401
1402 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1403 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1404 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1405
1406 /* Enable HNP early, avoiding races on suspend irq path.
1407 * ASSUMES OTG state machine B_BUS_REQ input is true.
1408 */
f35ae634
TL		 1409 if (udc->gadget.b_hnp_enable) {
1410 u32 l;
1411
1412 l = omap_readl(OTG_CTRL);
1413 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1414 l &= ~OTG_PULLUP;
1415 omap_writel(l, OTG_CTRL);
1416 }
1da177e4
LT		 1417}
1418
1419static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1420{
1421 struct omap_ep *ep0 = &udc->ep[0];
313980c9 1422 struct omap_req *req = NULL;
1da177e4
LT		 1423
1424 ep0->irqs++;
1425
1426 /* Clear any pending requests and then scrub any rx/tx state
1427 * before starting to handle the SETUP request.
1428 */
1429 if (irq_src & UDC_SETUP) {
1430 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1431
1432 nuke(ep0, 0);
1433 if (ack) {
f35ae634 1434 omap_writew(ack, UDC_IRQ_SRC);
1da177e4
LT		 1435 irq_src = UDC_SETUP;
1436 }
1437 }
1438
e6a6e472 1439 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1da177e4
LT		 1440 * This driver uses only uses protocol stalls (ep0 never halts),
1441 * and if we got this far the gadget driver already had a
1442 * chance to stall. Tries to be forgiving of host oddities.
1443 *
1444 * NOTE: the last chance gadget drivers have to stall control
1445 * requests is during their request completion callback.
1446 */
1447 if (!list_empty(&ep0->queue))
1448 req = container_of(ep0->queue.next, struct omap_req, queue);
1449
1450 /* IN == TX to host */
1451 if (irq_src & UDC_EP0_TX) {
1452 int stat;
1453
f35ae634
TL		 1454 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1455 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1456 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1457 if (stat & UDC_ACK) {
1458 if (udc->ep0_in) {
1459 /* write next IN packet from response,
1460 * or set up the status stage.
1461 */
1462 if (req)
1463 stat = write_fifo(ep0, req);
f35ae634 1464 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1465 if (!req && udc->ep0_pending) {
f35ae634
TL		 1466 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1467 omap_writew(UDC_CLR_EP, UDC_CTRL);
1468 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1469 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1470 udc->ep0_pending = 0;
1471 } /* else: 6 wait states before it'll tx */
1472 } else {
1473 /* ack status stage of OUT transfer */
f35ae634 1474 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1475 if (req)
1476 done(ep0, req, 0);
1477 }
313980c9 1478 req = NULL;
1da177e4 1479 } else if (stat & UDC_STALL) {
f35ae634
TL		 1480 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1481 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1482 } else {
f35ae634 1483 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1484 }
1485 }
1486
1487 /* OUT == RX from host */
1488 if (irq_src & UDC_EP0_RX) {
1489 int stat;
1490
f35ae634
TL		 1491 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1492 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1493 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1494 if (stat & UDC_ACK) {
1495 if (!udc->ep0_in) {
1496 stat = 0;
1497 /* read next OUT packet of request, maybe
1498 * reactiviting the fifo; stall on errors.
1499 */
80dd1358
FB		 1500 stat = read_fifo(ep0, req);
1501 if (!req || stat < 0) {
f35ae634 1502 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1503 udc->ep0_pending = 0;
1504 stat = 0;
1505 } else if (stat == 0)
f35ae634
TL		 1506 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1507 omap_writew(0, UDC_EP_NUM);
e6a6e472 1508
1da177e4
LT		 1509 /* activate status stage */
1510 if (stat == 1) {
1511 done(ep0, req, 0);
1512 /* that may have STALLed ep0... */
f35ae634
TL		 1513 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1514 UDC_EP_NUM);
1515 omap_writew(UDC_CLR_EP, UDC_CTRL);
1516 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1517 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1518 udc->ep0_pending = 0;
1519 }
1520 } else {
1521 /* ack status stage of IN transfer */
f35ae634 1522 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1523 if (req)
1524 done(ep0, req, 0);
1525 }
1526 } else if (stat & UDC_STALL) {
f35ae634
TL		 1527 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1528 omap_writew(0, UDC_EP_NUM);
1da177e4 1529 } else {
f35ae634 1530 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1531 }
1532 }
1533
1534 /* SETUP starts all control transfers */
1535 if (irq_src & UDC_SETUP) {
1536 union u {
1537 u16 word[4];
1538 struct usb_ctrlrequest r;
1539 } u;
1540 int status = -EINVAL;
1541 struct omap_ep *ep;
1542
1543 /* read the (latest) SETUP message */
1544 do {
f35ae634 1545 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1da177e4 1546 /* two bytes at a time */
f35ae634
TL		 1547 u.word[0] = omap_readw(UDC_DATA);
1548 u.word[1] = omap_readw(UDC_DATA);
1549 u.word[2] = omap_readw(UDC_DATA);
1550 u.word[3] = omap_readw(UDC_DATA);
1551 omap_writew(0, UDC_EP_NUM);
1552 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1da177e4 1553
01ee7d70
DB		 1554#define w_value le16_to_cpu(u.r.wValue)
1555#define w_index le16_to_cpu(u.r.wIndex)
1556#define w_length le16_to_cpu(u.r.wLength)
65111084 1557
1da177e4
LT		 1558 /* Delegate almost all control requests to the gadget driver,
1559 * except for a handful of ch9 status/feature requests that
1560 * hardware doesn't autodecode _and_ the gadget API hides.
1561 */
1562 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1563 udc->ep0_set_config = 0;
1564 udc->ep0_pending = 1;
1565 ep0->stopped = 0;
1566 ep0->ackwait = 0;
1567 switch (u.r.bRequest) {
1568 case USB_REQ_SET_CONFIGURATION:
1569 /* udc needs to know when ep != 0 is valid */
1570 if (u.r.bRequestType != USB_RECIP_DEVICE)
1571 goto delegate;
65111084 1572 if (w_length != 0)
1da177e4
LT		 1573 goto do_stall;
1574 udc->ep0_set_config = 1;
65111084
DB		 1575 udc->ep0_reset_config = (w_value == 0);
1576 VDBG("set config %d\n", w_value);
1da177e4
LT		 1577
1578 /* update udc NOW since gadget driver may start
1579 * queueing requests immediately; clear config
1580 * later if it fails the request.
1581 */
1582 if (udc->ep0_reset_config)
f35ae634 1583 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1584 else
f35ae634 1585 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1da177e4
LT		 1586 update_otg(udc);
1587 goto delegate;
1588 case USB_REQ_CLEAR_FEATURE:
1589 /* clear endpoint halt */
1590 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1591 goto delegate;
65111084
DB		 1592 if (w_value != USB_ENDPOINT_HALT
1593 || w_length != 0)
1da177e4 1594 goto do_stall;
65111084 1595 ep = &udc->ep[w_index & 0xf];
1da177e4 1596 if (ep != ep0) {
65111084 1597 if (w_index & USB_DIR_IN)
1da177e4
LT		 1598 ep += 16;
1599 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
f8bdae06 1600 || !ep->ep.desc)
1da177e4
LT		 1601 goto do_stall;
1602 use_ep(ep, 0);
f35ae634 1603 omap_writew(udc->clr_halt, UDC_CTRL);
1da177e4
LT		 1604 ep->ackwait = 0;
1605 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 1606 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1607 ep->ackwait = 1 + ep->double_buf;
1608 }
313980c9
DB		 1609 /* NOTE: assumes the host behaves sanely,
1610 * only clearing real halts. Else we may
1611 * need to kill pending transfers and then
1612 * restart the queue... very messy for DMA!
1613 */
1da177e4
LT		 1614 }
1615 VDBG("%s halt cleared by host\n", ep->name);
1616 goto ep0out_status_stage;
1617 case USB_REQ_SET_FEATURE:
1618 /* set endpoint halt */
1619 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1620 goto delegate;
65111084
DB		 1621 if (w_value != USB_ENDPOINT_HALT
1622 || w_length != 0)
1da177e4 1623 goto do_stall;
65111084
DB		 1624 ep = &udc->ep[w_index & 0xf];
1625 if (w_index & USB_DIR_IN)
1da177e4
LT		 1626 ep += 16;
1627 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
f8bdae06 1628 || ep == ep0 || !ep->ep.desc)
1da177e4
LT		 1629 goto do_stall;
1630 if (use_dma && ep->has_dma) {
1631 /* this has rude side-effects (aborts) and
1632 * can't really work if DMA-IN is active
1633 */
80dd1358 1634 DBG("%s host set_halt, NYET\n", ep->name);
1da177e4
LT		 1635 goto do_stall;
1636 }
1637 use_ep(ep, 0);
1638 /* can't halt if fifo isn't empty... */
f35ae634
TL		 1639 omap_writew(UDC_CLR_EP, UDC_CTRL);
1640 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1641 VDBG("%s halted by host\n", ep->name);
1642ep0out_status_stage:
1643 status = 0;
f35ae634
TL		 1644 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1645 omap_writew(UDC_CLR_EP, UDC_CTRL);
1646 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1647 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1648 udc->ep0_pending = 0;
1649 break;
1650 case USB_REQ_GET_STATUS:
8a3c1f57
DB		 1651 /* USB_ENDPOINT_HALT status? */
1652 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1653 goto intf_status;
1654
1655 /* ep0 never stalls */
1656 if (!(w_index & 0xf))
1657 goto zero_status;
1658
1659 /* only active endpoints count */
1660 ep = &udc->ep[w_index & 0xf];
1661 if (w_index & USB_DIR_IN)
1662 ep += 16;
f8bdae06 1663 if (!ep->ep.desc)
8a3c1f57
DB		 1664 goto do_stall;
1665
1666 /* iso never stalls */
1667 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1668 goto zero_status;
1669
1670 /* FIXME don't assume non-halted endpoints!! */
1671 ERR("%s status, can't report\n", ep->ep.name);
1672 goto do_stall;
1673
1674intf_status:
1da177e4
LT		 1675 /* return interface status. if we were pedantic,
1676 * we'd detect non-existent interfaces, and stall.
1677 */
1678 if (u.r.bRequestType
1679 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1680 goto delegate;
8a3c1f57
DB		 1681
1682zero_status:
1da177e4 1683 /* return two zero bytes */
f35ae634
TL		 1684 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1685 omap_writew(0, UDC_DATA);
1686 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1687 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1688 status = 0;
65111084 1689 VDBG("GET_STATUS, interface %d\n", w_index);
1da177e4
LT		 1690 /* next, status stage */
1691 break;
1692 default:
1693delegate:
1694 /* activate the ep0out fifo right away */
65111084 1695 if (!udc->ep0_in && w_length) {
f35ae634
TL		 1696 omap_writew(0, UDC_EP_NUM);
1697 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1698 }
1699
1700 /* gadget drivers see class/vendor specific requests,
1701 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1702 * and more
1703 */
1704 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1705 u.r.bRequestType, u.r.bRequest,
65111084
DB		 1706 w_value, w_index, w_length);
1707
1708#undef w_value
1709#undef w_index
1710#undef w_length
1da177e4
LT		 1711
1712 /* The gadget driver may return an error here,
1713 * causing an immediate protocol stall.
1714 *
1715 * Else it must issue a response, either queueing a
1716 * response buffer for the DATA stage, or halting ep0
1717 * (causing a protocol stall, not a real halt). A
1718 * zero length buffer means no DATA stage.
1719 *
1720 * It's fine to issue that response after the setup()
1721 * call returns, and this IRQ was handled.
1722 */
1723 udc->ep0_setup = 1;
1724 spin_unlock(&udc->lock);
80dd1358 1725 status = udc->driver->setup(&udc->gadget, &u.r);
1da177e4
LT		 1726 spin_lock(&udc->lock);
1727 udc->ep0_setup = 0;
1728 }
1729
1730 if (status < 0) {
1731do_stall:
1732 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1733 u.r.bRequestType, u.r.bRequest, status);
1734 if (udc->ep0_set_config) {
1735 if (udc->ep0_reset_config)
b6c63937 1736 WARNING("error resetting config?\n");
1da177e4 1737 else
f35ae634 1738 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1739 }
f35ae634 1740 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1741 udc->ep0_pending = 0;
1742 }
1743 }
1744}
1745
1746/*-------------------------------------------------------------------------*/
1747
1748#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1749
1750static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1751{
1752 u16 devstat, change;
1753
f35ae634 1754 devstat = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 1755 change = devstat ^ udc->devstat;
1756 udc->devstat = devstat;
1757
1758 if (change & (UDC_USB_RESET|UDC_ATT)) {
1759 udc_quiesce(udc);
1760
1761 if (change & UDC_ATT) {
1762 /* driver for any external transceiver will
1763 * have called omap_vbus_session() already
1764 */
1765 if (devstat & UDC_ATT) {
1766 udc->gadget.speed = USB_SPEED_FULL;
1767 VDBG("connect\n");
1768 if (!udc->transceiver)
1769 pullup_enable(udc);
80dd1358 1770 /* if (driver->connect) call it */
1da177e4
LT		 1771 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1772 udc->gadget.speed = USB_SPEED_UNKNOWN;
1773 if (!udc->transceiver)
1774 pullup_disable(udc);
1775 DBG("disconnect, gadget %s\n",
1776 udc->driver->driver.name);
1777 if (udc->driver->disconnect) {
1778 spin_unlock(&udc->lock);
1779 udc->driver->disconnect(&udc->gadget);
1780 spin_lock(&udc->lock);
1781 }
1782 }
1783 change &= ~UDC_ATT;
1784 }
1785
1786 if (change & UDC_USB_RESET) {
1787 if (devstat & UDC_USB_RESET) {
1788 VDBG("RESET=1\n");
1789 } else {
1790 udc->gadget.speed = USB_SPEED_FULL;
1791 INFO("USB reset done, gadget %s\n",
1792 udc->driver->driver.name);
1793 /* ep0 traffic is legal from now on */
f35ae634
TL		 1794 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1795 UDC_IRQ_EN);
1da177e4
LT		 1796 }
1797 change &= ~UDC_USB_RESET;
1798 }
1799 }
1800 if (change & UDC_SUS) {
1801 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
80dd1358 1802 /* FIXME tell isp1301 to suspend/resume (?) */
1da177e4
LT		 1803 if (devstat & UDC_SUS) {
1804 VDBG("suspend\n");
1805 update_otg(udc);
1806 /* HNP could be under way already */
1807 if (udc->gadget.speed == USB_SPEED_FULL
1808 && udc->driver->suspend) {
1809 spin_unlock(&udc->lock);
1810 udc->driver->suspend(&udc->gadget);
1811 spin_lock(&udc->lock);
1812 }
4e67185a 1813 if (udc->transceiver)
b96d3b08
HK		 1814 usb_phy_set_suspend(
1815 udc->transceiver, 1);
1da177e4
LT		 1816 } else {
1817 VDBG("resume\n");
4e67185a 1818 if (udc->transceiver)
b96d3b08
HK		 1819 usb_phy_set_suspend(
1820 udc->transceiver, 0);
1da177e4
LT		 1821 if (udc->gadget.speed == USB_SPEED_FULL
1822 && udc->driver->resume) {
1823 spin_unlock(&udc->lock);
1824 udc->driver->resume(&udc->gadget);
1825 spin_lock(&udc->lock);
1826 }
1827 }
1828 }
1829 change &= ~UDC_SUS;
1830 }
1831 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1832 update_otg(udc);
1833 change &= ~OTG_FLAGS;
1834 }
1835
1836 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1837 if (change)
1838 VDBG("devstat %03x, ignore change %03x\n",
1839 devstat, change);
1840
f35ae634 1841 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1da177e4
LT		 1842}
1843
7d12e780 1844static irqreturn_t omap_udc_irq(int irq, void *_udc)
1da177e4
LT		 1845{
1846 struct omap_udc *udc = _udc;
1847 u16 irq_src;
1848 irqreturn_t status = IRQ_NONE;
1849 unsigned long flags;
1850
1851 spin_lock_irqsave(&udc->lock, flags);
f35ae634 1852 irq_src = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 1853
1854 /* Device state change (usb ch9 stuff) */
1855 if (irq_src & UDC_DS_CHG) {
1856 devstate_irq(_udc, irq_src);
1857 status = IRQ_HANDLED;
1858 irq_src &= ~UDC_DS_CHG;
1859 }
1860
1861 /* EP0 control transfers */
1862 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1863 ep0_irq(_udc, irq_src);
1864 status = IRQ_HANDLED;
1865 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1866 }
1867
1868 /* DMA transfer completion */
1869 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1870 dma_irq(_udc, irq_src);
1871 status = IRQ_HANDLED;
1872 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1873 }
1874
f35ae634 1875 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1da177e4
LT		 1876 if (irq_src)
1877 DBG("udc_irq, unhandled %03x\n", irq_src);
1878 spin_unlock_irqrestore(&udc->lock, flags);
1879
1880 return status;
1881}
1882
1883/* workaround for seemingly-lost IRQs for RX ACKs... */
1884#define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1885#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1886
1887static void pio_out_timer(unsigned long _ep)
1888{
1889 struct omap_ep *ep = (void *) _ep;
1890 unsigned long flags;
1891 u16 stat_flg;
1892
1893 spin_lock_irqsave(&ep->udc->lock, flags);
1894 if (!list_empty(&ep->queue) && ep->ackwait) {
e6a6e472 1895 use_ep(ep, UDC_EP_SEL);
f35ae634 1896 stat_flg = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1897
1898 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1899 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1900 struct omap_req *req;
1901
1902 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1903 req = container_of(ep->queue.next,
1904 struct omap_req, queue);
1da177e4 1905 (void) read_fifo(ep, req);
f35ae634
TL		 1906 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1907 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4 1908 ep->ackwait = 1 + ep->double_buf;
e6a6e472
DB		 1909 } else
1910 deselect_ep();
1da177e4
LT		 1911 }
1912 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1913 spin_unlock_irqrestore(&ep->udc->lock, flags);
1914}
1915
7d12e780 1916static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1da177e4
LT		 1917{
1918 u16 epn_stat, irq_src;
1919 irqreturn_t status = IRQ_NONE;
1920 struct omap_ep *ep;
1921 int epnum;
1922 struct omap_udc *udc = _dev;
1923 struct omap_req *req;
1924 unsigned long flags;
1925
1926 spin_lock_irqsave(&udc->lock, flags);
f35ae634
TL		 1927 epn_stat = omap_readw(UDC_EPN_STAT);
1928 irq_src = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 1929
1930 /* handle OUT first, to avoid some wasteful NAKs */
1931 if (irq_src & UDC_EPN_RX) {
1932 epnum = (epn_stat >> 8) & 0x0f;
f35ae634 1933 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1da177e4
LT		 1934 status = IRQ_HANDLED;
1935 ep = &udc->ep[epnum];
1936 ep->irqs++;
1937
f35ae634 1938 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1da177e4 1939 ep->fnf = 0;
f35ae634 1940 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1da177e4
LT		 1941 ep->ackwait--;
1942 if (!list_empty(&ep->queue)) {
1943 int stat;
1944 req = container_of(ep->queue.next,
1945 struct omap_req, queue);
1946 stat = read_fifo(ep, req);
1947 if (!ep->double_buf)
1948 ep->fnf = 1;
1949 }
1950 }
1951 /* min 6 clock delay before clearing EP_SEL ... */
f35ae634
TL		 1952 epn_stat = omap_readw(UDC_EPN_STAT);
1953 epn_stat = omap_readw(UDC_EPN_STAT);
1954 omap_writew(epnum, UDC_EP_NUM);
1da177e4
LT		 1955
1956 /* enabling fifo _after_ clearing ACK, contrary to docs,
1957 * reduces lossage; timer still needed though (sigh).
1958 */
1959 if (ep->fnf) {
f35ae634 1960 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1961 ep->ackwait = 1 + ep->double_buf;
1962 }
1963 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1964 }
1965
1966 /* then IN transfers */
1967 else if (irq_src & UDC_EPN_TX) {
1968 epnum = epn_stat & 0x0f;
f35ae634 1969 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1da177e4
LT		 1970 status = IRQ_HANDLED;
1971 ep = &udc->ep[16 + epnum];
1972 ep->irqs++;
1973
f35ae634
TL		 1974 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1975 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1da177e4
LT		 1976 ep->ackwait = 0;
1977 if (!list_empty(&ep->queue)) {
1978 req = container_of(ep->queue.next,
1979 struct omap_req, queue);
1980 (void) write_fifo(ep, req);
1981 }
1982 }
1983 /* min 6 clock delay before clearing EP_SEL ... */
f35ae634
TL		 1984 epn_stat = omap_readw(UDC_EPN_STAT);
1985 epn_stat = omap_readw(UDC_EPN_STAT);
1986 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1987 /* then 6 clocks before it'd tx */
1988 }
1989
1990 spin_unlock_irqrestore(&udc->lock, flags);
1991 return status;
1992}
1993
1994#ifdef USE_ISO
7d12e780 1995static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1da177e4
LT		 1996{
1997 struct omap_udc *udc = _dev;
1998 struct omap_ep *ep;
1999 int pending = 0;
2000 unsigned long flags;
2001
2002 spin_lock_irqsave(&udc->lock, flags);
2003
2004 /* handle all non-DMA ISO transfers */
80dd1358 2005 list_for_each_entry(ep, &udc->iso, iso) {
1da177e4
LT		 2006 u16 stat;
2007 struct omap_req *req;
2008
2009 if (ep->has_dma || list_empty(&ep->queue))
2010 continue;
2011 req = list_entry(ep->queue.next, struct omap_req, queue);
2012
2013 use_ep(ep, UDC_EP_SEL);
f35ae634 2014 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 2015
2016 /* NOTE: like the other controller drivers, this isn't
2017 * currently reporting lost or damaged frames.
2018 */
2019 if (ep->bEndpointAddress & USB_DIR_IN) {
2020 if (stat & UDC_MISS_IN)
2021 /* done(ep, req, -EPROTO) */;
2022 else
2023 write_fifo(ep, req);
2024 } else {
2025 int status = 0;
2026
2027 if (stat & UDC_NO_RXPACKET)
2028 status = -EREMOTEIO;
2029 else if (stat & UDC_ISO_ERR)
2030 status = -EILSEQ;
2031 else if (stat & UDC_DATA_FLUSH)
2032 status = -ENOSR;
2033
2034 if (status)
2035 /* done(ep, req, status) */;
2036 else
2037 read_fifo(ep, req);
2038 }
2039 deselect_ep();
2040 /* 6 wait states before next EP */
2041
2042 ep->irqs++;
2043 if (!list_empty(&ep->queue))
2044 pending = 1;
2045 }
f35ae634
TL		 2046 if (!pending) {
2047 u16 w;
2048
2049 w = omap_readw(UDC_IRQ_EN);
2050 w &= ~UDC_SOF_IE;
2051 omap_writew(w, UDC_IRQ_EN);
2052 }
2053 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
1da177e4
LT		 2054
2055 spin_unlock_irqrestore(&udc->lock, flags);
2056 return IRQ_HANDLED;
2057}
2058#endif
2059
2060/*-------------------------------------------------------------------------*/
2061
8a3c1f57 2062static inline int machine_without_vbus_sense(void)
e6a6e472 2063{
80dd1358 2064 return machine_is_omap_innovator()
e6a6e472 2065 || machine_is_omap_osk()
e6a6e472 2066 || machine_is_sx1()
80dd1358
FB		 2067 /* No known omap7xx boards with vbus sense */
2068 || cpu_is_omap7xx();
e6a6e472 2069}
1da177e4 2070
0f91349b 2071static int omap_udc_start(struct usb_gadget_driver *driver,
b0fca50f 2072 int (*bind)(struct usb_gadget *))
1da177e4
LT		 2073{
2074 int status = -ENODEV;
2075 struct omap_ep *ep;
2076 unsigned long flags;
2077
2078 /* basic sanity tests */
2079 if (!udc)
2080 return -ENODEV;
2081 if (!driver
80dd1358 2082 /* FIXME if otg, check: driver->is_otg */
7177aed4 2083 || driver->max_speed < USB_SPEED_FULL
b0fca50f 2084 || !bind || !driver->setup)
1da177e4
LT		 2085 return -EINVAL;
2086
2087 spin_lock_irqsave(&udc->lock, flags);
2088 if (udc->driver) {
2089 spin_unlock_irqrestore(&udc->lock, flags);
2090 return -EBUSY;
2091 }
2092
2093 /* reset state */
80dd1358 2094 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1da177e4
LT		 2095 ep->irqs = 0;
2096 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2097 continue;
2098 use_ep(ep, 0);
f35ae634 2099 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 2100 }
2101 udc->ep0_pending = 0;
2102 udc->ep[0].irqs = 0;
2103 udc->softconnect = 1;
2104
2105 /* hook up the driver */
313980c9 2106 driver->driver.bus = NULL;
1da177e4
LT		 2107 udc->driver = driver;
2108 udc->gadget.dev.driver = &driver->driver;
2109 spin_unlock_irqrestore(&udc->lock, flags);
2110
e6a6e472
DB		 2111 if (udc->dc_clk != NULL)
2112 omap_udc_enable_clock(1);
2113
b0fca50f 2114 status = bind(&udc->gadget);
1da177e4
LT		 2115 if (status) {
2116 DBG("bind to %s --> %d\n", driver->driver.name, status);
313980c9
DB		 2117 udc->gadget.dev.driver = NULL;
2118 udc->driver = NULL;
1da177e4
LT		 2119 goto done;
2120 }
2121 DBG("bound to driver %s\n", driver->driver.name);
2122
f35ae634 2123 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
1da177e4
LT		 2124
2125 /* connect to bus through transceiver */
2126 if (udc->transceiver) {
6e13c650
HK		 2127 status = otg_set_peripheral(udc->transceiver->otg,
2128 &udc->gadget);
1da177e4
LT		 2129 if (status < 0) {
2130 ERR("can't bind to transceiver\n");
6bea476c 2131 if (driver->unbind) {
80dd1358 2132 driver->unbind(&udc->gadget);
6bea476c
DB		 2133 udc->gadget.dev.driver = NULL;
2134 udc->driver = NULL;
2135 }
1da177e4
LT		 2136 goto done;
2137 }
2138 } else {
2139 if (can_pullup(udc))
80dd1358 2140 pullup_enable(udc);
1da177e4 2141 else
80dd1358 2142 pullup_disable(udc);
1da177e4
LT		 2143 }
2144
2145 /* boards that don't have VBUS sensing can't autogate 48MHz;
2146 * can't enter deep sleep while a gadget driver is active.
2147 */
8a3c1f57 2148 if (machine_without_vbus_sense())
1da177e4
LT		 2149 omap_vbus_session(&udc->gadget, 1);
2150
2151done:
e6a6e472
DB		 2152 if (udc->dc_clk != NULL)
2153 omap_udc_enable_clock(0);
1da177e4
LT		 2154 return status;
2155}
1da177e4 2156
0f91349b 2157static int omap_udc_stop(struct usb_gadget_driver *driver)
1da177e4
LT		 2158{
2159 unsigned long flags;
2160 int status = -ENODEV;
2161
2162 if (!udc)
2163 return -ENODEV;
6bea476c 2164 if (!driver || driver != udc->driver || !driver->unbind)
1da177e4
LT		 2165 return -EINVAL;
2166
e6a6e472
DB		 2167 if (udc->dc_clk != NULL)
2168 omap_udc_enable_clock(1);
2169
8a3c1f57 2170 if (machine_without_vbus_sense())
1da177e4
LT		 2171 omap_vbus_session(&udc->gadget, 0);
2172
2173 if (udc->transceiver)
6e13c650 2174 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
1da177e4
LT		 2175 else
2176 pullup_disable(udc);
2177
2178 spin_lock_irqsave(&udc->lock, flags);
2179 udc_quiesce(udc);
2180 spin_unlock_irqrestore(&udc->lock, flags);
2181
2182 driver->unbind(&udc->gadget);
313980c9
DB		 2183 udc->gadget.dev.driver = NULL;
2184 udc->driver = NULL;
1da177e4 2185
e6a6e472
DB		 2186 if (udc->dc_clk != NULL)
2187 omap_udc_enable_clock(0);
1da177e4
LT		 2188 DBG("unregistered driver '%s'\n", driver->driver.name);
2189 return status;
2190}
1da177e4
LT		 2191
2192/*-------------------------------------------------------------------------*/
2193
2194#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2195
2196#include <linux/seq_file.h>
2197
2198static const char proc_filename[] = "driver/udc";
2199
2200#define FOURBITS "%s%s%s%s"
80dd1358 2201#define EIGHTBITS "%s%s%s%s%s%s%s%s"
1da177e4
LT		 2202
2203static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2204{
2205 u16 stat_flg;
2206 struct omap_req *req;
2207 char buf[20];
2208
2209 use_ep(ep, 0);
2210
2211 if (use_dma && ep->has_dma)
2212 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2213 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2214 ep->dma_channel - 1, ep->lch);
2215 else
2216 buf[0] = 0;
2217
f35ae634 2218 stat_flg = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 2219 seq_printf(s,
2220 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2221 ep->name, buf,
2222 ep->double_buf ? "dbuf " : "",
80dd1358
FB		 2223 ({ char *s;
2224 switch (ep->ackwait) {
2225 case 0:
2226 s = "";
2227 break;
2228 case 1:
2229 s = "(ackw) ";
2230 break;
2231 case 2:
2232 s = "(ackw2) ";
2233 break;
2234 default:
2235 s = "(?) ";
2236 break;
2237 } s; }),
1da177e4
LT		 2238 ep->irqs, stat_flg,
2239 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2240 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2241 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2242 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2243 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2244 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2245 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2246 (stat_flg & UDC_STALL) ? "STALL " : "",
2247 (stat_flg & UDC_NAK) ? "NAK " : "",
2248 (stat_flg & UDC_ACK) ? "ACK " : "",
2249 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2250 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2251 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2252
80dd1358 2253 if (list_empty(&ep->queue))
1da177e4
LT		 2254 seq_printf(s, "\t(queue empty)\n");
2255 else
80dd1358 2256 list_for_each_entry(req, &ep->queue, queue) {
1da177e4
LT		 2257 unsigned length = req->req.actual;
2258
2259 if (use_dma && buf[0]) {
2260 length += ((ep->bEndpointAddress & USB_DIR_IN)
2261 ? dma_src_len : dma_dest_len)
2262 (ep, req->req.dma + length);
2263 buf[0] = 0;
2264 }
2265 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2266 &req->req, length,
2267 req->req.length, req->req.buf);
2268 }
2269}
2270
2271static char *trx_mode(unsigned m, int enabled)
2272{
2273 switch (m) {
80dd1358
FB		 2274 case 0:
2275 return enabled ? "*6wire" : "unused";
2276 case 1:
2277 return "4wire";
2278 case 2:
2279 return "3wire";
2280 case 3:
2281 return "6wire";
2282 default:
2283 return "unknown";
1da177e4
LT		 2284 }
2285}
2286
2287static int proc_otg_show(struct seq_file *s)
2288{
2289 u32 tmp;
4814ced5
PW		 2290 u32 trans = 0;
2291 char *ctrl_name = "(UNKNOWN)";
1da177e4 2292
e12cc345 2293 tmp = omap_readl(OTG_REV);
ae372571
TL		 2294 ctrl_name = "tranceiver_ctrl";
2295 trans = omap_readw(USB_TRANSCEIVER_CTRL);
e6a6e472
DB		 2296 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2297 tmp >> 4, tmp & 0xf, ctrl_name, trans);
f35ae634 2298 tmp = omap_readw(OTG_SYSCON_1);
1da177e4
LT		 2299 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2300 FOURBITS "\n", tmp,
2301 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2302 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
65111084 2303 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
1da177e4
LT		 2304 ? "internal"
2305 : trx_mode(USB0_TRX_MODE(tmp), 1),
2306 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2307 (tmp & HST_IDLE_EN) ? " !host" : "",
2308 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2309 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
f35ae634 2310 tmp = omap_readl(OTG_SYSCON_2);
1da177e4
LT		 2311 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2312 " b_ase_brst=%d hmc=%d\n", tmp,
2313 (tmp & OTG_EN) ? " otg_en" : "",
2314 (tmp & USBX_SYNCHRO) ? " synchro" : "",
80dd1358 2315 /* much more SRP stuff */
1da177e4
LT		 2316 (tmp & SRP_DATA) ? " srp_data" : "",
2317 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2318 (tmp & OTG_PADEN) ? " otg_paden" : "",
2319 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2320 (tmp & UHOST_EN) ? " uhost_en" : "",
2321 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2322 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2323 B_ASE_BRST(tmp),
2324 OTG_HMC(tmp));
f35ae634 2325 tmp = omap_readl(OTG_CTRL);
1da177e4
LT		 2326 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2327 (tmp & OTG_ASESSVLD) ? " asess" : "",
2328 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2329 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2330 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2331 (tmp & OTG_ID) ? " id" : "",
2332 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2333 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2334 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2335 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2336 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2337 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2338 (tmp & OTG_PULLDOWN) ? " down" : "",
2339 (tmp & OTG_PULLUP) ? " up" : "",
2340 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2341 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2342 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2343 (tmp & OTG_PU_ID) ? " pu_id" : ""
2344 );
f35ae634 2345 tmp = omap_readw(OTG_IRQ_EN);
1da177e4 2346 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
f35ae634 2347 tmp = omap_readw(OTG_IRQ_SRC);
1da177e4 2348 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
f35ae634 2349 tmp = omap_readw(OTG_OUTCTRL);
1da177e4 2350 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
f35ae634 2351 tmp = omap_readw(OTG_TEST);
1da177e4 2352 seq_printf(s, "otg_test %04x" "\n", tmp);
313980c9 2353 return 0;
1da177e4
LT		 2354}
2355
2356static int proc_udc_show(struct seq_file *s, void *_)
2357{
2358 u32 tmp;
2359 struct omap_ep *ep;
2360 unsigned long flags;
2361
2362 spin_lock_irqsave(&udc->lock, flags);
2363
2364 seq_printf(s, "%s, version: " DRIVER_VERSION
2365#ifdef USE_ISO
2366 " (iso)"
2367#endif
2368 "%s\n",
2369 driver_desc,
2370 use_dma ? " (dma)" : "");
2371
f35ae634 2372 tmp = omap_readw(UDC_REV) & 0xff;
1da177e4
LT		 2373 seq_printf(s,
2374 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2375 "hmc %d, transceiver %s\n",
2376 tmp >> 4, tmp & 0xf,
2377 fifo_mode,
2378 udc->driver ? udc->driver->driver.name : "(none)",
2379 HMC,
e6a6e472
DB		 2380 udc->transceiver
2381 ? udc->transceiver->label
ae372571 2382 : (cpu_is_omap1710()
e6a6e472 2383 ? "external" : "(none)"));
ae372571
TL		 2384 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2385 omap_readw(ULPD_CLOCK_CTRL),
2386 omap_readw(ULPD_SOFT_REQ),
2387 omap_readw(ULPD_STATUS_REQ));
1da177e4
LT		 2388
2389 /* OTG controller registers */
2390 if (!cpu_is_omap15xx())
2391 proc_otg_show(s);
2392
f35ae634 2393 tmp = omap_readw(UDC_SYSCON1);
1da177e4
LT		 2394 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2395 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2396 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2397 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2398 (tmp & UDC_NAK_EN) ? " nak" : "",
2399 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2400 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2401 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2402 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
80dd1358 2403 /* syscon2 is write-only */
1da177e4
LT		 2404
2405 /* UDC controller registers */
2406 if (!(tmp & UDC_PULLUP_EN)) {
2407 seq_printf(s, "(suspended)\n");
2408 spin_unlock_irqrestore(&udc->lock, flags);
2409 return 0;
2410 }
2411
f35ae634 2412 tmp = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 2413 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2414 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2415 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2416 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2417 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2418 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2419 (tmp & UDC_SUS) ? " SUS" : "",
2420 (tmp & UDC_CFG) ? " CFG" : "",
2421 (tmp & UDC_ADD) ? " ADD" : "",
2422 (tmp & UDC_DEF) ? " DEF" : "",
2423 (tmp & UDC_ATT) ? " ATT" : "");
f35ae634
TL		 2424 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2425 tmp = omap_readw(UDC_IRQ_EN);
1da177e4
LT		 2426 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2427 (tmp & UDC_SOF_IE) ? " sof" : "",
2428 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2429 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2430 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2431 (tmp & UDC_EP0_IE) ? " ep0" : "");
f35ae634 2432 tmp = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 2433 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2434 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2435 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2436 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
f35ae634 2437 (tmp & UDC_IRQ_SOF) ? " sof" : "",
1da177e4
LT		 2438 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2439 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2440 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2441 (tmp & UDC_SETUP) ? " setup" : "",
2442 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2443 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2444 if (use_dma) {
2445 unsigned i;
2446
f35ae634 2447 tmp = omap_readw(UDC_DMA_IRQ_EN);
1da177e4
LT		 2448 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2449 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2450 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2451 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2452
2453 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2454 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2455 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2456
2457 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2458 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2459 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2460
f35ae634 2461 tmp = omap_readw(UDC_RXDMA_CFG);
1da177e4
LT		 2462 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2463 if (tmp) {
2464 for (i = 0; i < 3; i++) {
2465 if ((tmp & (0x0f << (i * 4))) == 0)
2466 continue;
2467 seq_printf(s, "rxdma[%d] %04x\n", i,
f35ae634 2468 omap_readw(UDC_RXDMA(i + 1)));
1da177e4
LT		 2469 }
2470 }
f35ae634 2471 tmp = omap_readw(UDC_TXDMA_CFG);
1da177e4
LT		 2472 seq_printf(s, "txdma_cfg %04x\n", tmp);
2473 if (tmp) {
2474 for (i = 0; i < 3; i++) {
2475 if (!(tmp & (0x0f << (i * 4))))
2476 continue;
2477 seq_printf(s, "txdma[%d] %04x\n", i,
f35ae634 2478 omap_readw(UDC_TXDMA(i + 1)));
1da177e4
LT		 2479 }
2480 }
2481 }
2482
f35ae634 2483 tmp = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 2484 if (tmp & UDC_ATT) {
2485 proc_ep_show(s, &udc->ep[0]);
2486 if (tmp & UDC_ADD) {
80dd1358 2487 list_for_each_entry(ep, &udc->gadget.ep_list,
1da177e4 2488 ep.ep_list) {
f8bdae06 2489 if (ep->ep.desc)
1da177e4
LT		 2490 proc_ep_show(s, ep);
2491 }
2492 }
2493 }
2494 spin_unlock_irqrestore(&udc->lock, flags);
2495 return 0;
2496}
2497
2498static int proc_udc_open(struct inode *inode, struct file *file)
2499{
313980c9 2500 return single_open(file, proc_udc_show, NULL);
1da177e4
LT		 2501}
2502
066202dd 2503static const struct file_operations proc_ops = {
cdefa185 2504 .owner = THIS_MODULE,
1da177e4
LT		 2505 .open = proc_udc_open,
2506 .read = seq_read,
2507 .llseek = seq_lseek,
2508 .release = single_release,
2509};
2510
2511static void create_proc_file(void)
2512{
cdefa185 2513 proc_create(proc_filename, 0, NULL, &proc_ops);
1da177e4
LT		 2514}
2515
2516static void remove_proc_file(void)
2517{
313980c9 2518 remove_proc_entry(proc_filename, NULL);
1da177e4
LT		 2519}
2520
2521#else
2522
2523static inline void create_proc_file(void) {}
2524static inline void remove_proc_file(void) {}
2525
2526#endif
2527
2528/*-------------------------------------------------------------------------*/
2529
2530/* Before this controller can enumerate, we need to pick an endpoint
2531 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2532 * buffer space among the endpoints we'll be operating.
65111084
DB		 2533 *
2534 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
f35ae634 2535 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
65111084 2536 * capability yet though.
1da177e4
LT		 2537 */
2538static unsigned __init
2539omap_ep_setup(char *name, u8 addr, u8 type,
2540 unsigned buf, unsigned maxp, int dbuf)
2541{
2542 struct omap_ep *ep;
2543 u16 epn_rxtx = 0;
2544
2545 /* OUT endpoints first, then IN */
2546 ep = &udc->ep[addr & 0xf];
2547 if (addr & USB_DIR_IN)
2548 ep += 16;
2549
2550 /* in case of ep init table bugs */
2551 BUG_ON(ep->name[0]);
2552
2553 /* chip setup ... bit values are same for IN, OUT */
2554 if (type == USB_ENDPOINT_XFER_ISOC) {
2555 switch (maxp) {
80dd1358
FB		 2556 case 8:
2557 epn_rxtx = 0 << 12;
2558 break;
2559 case 16:
2560 epn_rxtx = 1 << 12;
2561 break;
2562 case 32:
2563 epn_rxtx = 2 << 12;
2564 break;
2565 case 64:
2566 epn_rxtx = 3 << 12;
2567 break;
2568 case 128:
2569 epn_rxtx = 4 << 12;
2570 break;
2571 case 256:
2572 epn_rxtx = 5 << 12;
2573 break;
2574 case 512:
2575 epn_rxtx = 6 << 12;
2576 break;
2577 default:
2578 BUG();
1da177e4
LT		 2579 }
2580 epn_rxtx |= UDC_EPN_RX_ISO;
2581 dbuf = 1;
2582 } else {
2583 /* double-buffering "not supported" on 15xx,
e6a6e472
DB		 2584 * and ignored for PIO-IN on newer chips
2585 * (for more reliable behavior)
1da177e4 2586 */
ae372571 2587 if (!use_dma || cpu_is_omap15xx())
1da177e4
LT		 2588 dbuf = 0;
2589
2590 switch (maxp) {
80dd1358
FB		 2591 case 8:
2592 epn_rxtx = 0 << 12;
2593 break;
2594 case 16:
2595 epn_rxtx = 1 << 12;
2596 break;
2597 case 32:
2598 epn_rxtx = 2 << 12;
2599 break;
2600 case 64:
2601 epn_rxtx = 3 << 12;
2602 break;
2603 default:
2604 BUG();
1da177e4
LT		 2605 }
2606 if (dbuf && addr)
2607 epn_rxtx |= UDC_EPN_RX_DB;
2608 init_timer(&ep->timer);
2609 ep->timer.function = pio_out_timer;
2610 ep->timer.data = (unsigned long) ep;
2611 }
2612 if (addr)
2613 epn_rxtx |= UDC_EPN_RX_VALID;
2614 BUG_ON(buf & 0x07);
2615 epn_rxtx |= buf >> 3;
2616
2617 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2618 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2619
2620 if (addr & USB_DIR_IN)
f35ae634 2621 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
1da177e4 2622 else
f35ae634 2623 omap_writew(epn_rxtx, UDC_EP_RX(addr));
1da177e4
LT		 2624
2625 /* next endpoint's buffer starts after this one's */
2626 buf += maxp;
2627 if (dbuf)
2628 buf += maxp;
2629 BUG_ON(buf > 2048);
2630
2631 /* set up driver data structures */
2632 BUG_ON(strlen(name) >= sizeof ep->name);
2633 strlcpy(ep->name, name, sizeof ep->name);
2634 INIT_LIST_HEAD(&ep->queue);
2635 INIT_LIST_HEAD(&ep->iso);
2636 ep->bEndpointAddress = addr;
2637 ep->bmAttributes = type;
2638 ep->double_buf = dbuf;
e6a6e472 2639 ep->udc = udc;
1da177e4
LT		 2640
2641 ep->ep.name = ep->name;
2642 ep->ep.ops = &omap_ep_ops;
2643 ep->ep.maxpacket = ep->maxpacket = maxp;
80dd1358 2644 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1da177e4
LT		 2645
2646 return buf;
2647}
2648
2649static void omap_udc_release(struct device *dev)
2650{
2651 complete(udc->done);
80dd1358 2652 kfree(udc);
313980c9 2653 udc = NULL;
1da177e4
LT		 2654}
2655
2656static int __init
86753811 2657omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
1da177e4
LT		 2658{
2659 unsigned tmp, buf;
2660
2661 /* abolish any previous hardware state */
f35ae634
TL		 2662 omap_writew(0, UDC_SYSCON1);
2663 omap_writew(0, UDC_IRQ_EN);
2664 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2665 omap_writew(0, UDC_DMA_IRQ_EN);
2666 omap_writew(0, UDC_RXDMA_CFG);
2667 omap_writew(0, UDC_TXDMA_CFG);
1da177e4
LT		 2668
2669 /* UDC_PULLUP_EN gates the chip clock */
80dd1358 2670 /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
1da177e4 2671
e94b1766 2672 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
1da177e4
LT		 2673 if (!udc)
2674 return -ENOMEM;
2675
80dd1358 2676 spin_lock_init(&udc->lock);
1da177e4
LT		 2677
2678 udc->gadget.ops = &omap_gadget_ops;
2679 udc->gadget.ep0 = &udc->ep[0].ep;
2680 INIT_LIST_HEAD(&udc->gadget.ep_list);
2681 INIT_LIST_HEAD(&udc->iso);
2682 udc->gadget.speed = USB_SPEED_UNKNOWN;
d327ab5b 2683 udc->gadget.max_speed = USB_SPEED_FULL;
1da177e4
LT		 2684 udc->gadget.name = driver_name;
2685
2686 device_initialize(&udc->gadget.dev);
0031a06e 2687 dev_set_name(&udc->gadget.dev, "gadget");
1da177e4
LT		 2688 udc->gadget.dev.release = omap_udc_release;
2689 udc->gadget.dev.parent = &odev->dev;
2690 if (use_dma)
2691 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2692
2693 udc->transceiver = xceiv;
2694
2695 /* ep0 is special; put it right after the SETUP buffer */
2696 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2697 8 /* after SETUP */, 64 /* maxpacket */, 0);
2698 list_del_init(&udc->ep[0].ep.ep_list);
2699
2700 /* initially disable all non-ep0 endpoints */
2701 for (tmp = 1; tmp < 15; tmp++) {
f35ae634
TL		 2702 omap_writew(0, UDC_EP_RX(tmp));
2703 omap_writew(0, UDC_EP_TX(tmp));
1da177e4
LT		 2704 }
2705
80dd1358 2706#define OMAP_BULK_EP(name, addr) \
1da177e4
LT		 2707 buf = omap_ep_setup(name "-bulk", addr, \
2708 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
80dd1358 2709#define OMAP_INT_EP(name, addr, maxp) \
1da177e4
LT		 2710 buf = omap_ep_setup(name "-int", addr, \
2711 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
80dd1358 2712#define OMAP_ISO_EP(name, addr, maxp) \
1da177e4
LT		 2713 buf = omap_ep_setup(name "-iso", addr, \
2714 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2715
2716 switch (fifo_mode) {
2717 case 0:
2718 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2719 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2720 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2721 break;
2722 case 1:
2723 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2724 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
313980c9
DB		 2725 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2726
1da177e4
LT		 2727 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2728 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
313980c9 2729 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
1da177e4
LT		 2730
2731 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2732 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
313980c9
DB		 2733 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2734
1da177e4
LT		 2735 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2736 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
313980c9 2737 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
1da177e4
LT		 2738
2739 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2740 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
313980c9
DB		 2741 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2742 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2743
1da177e4
LT		 2744 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2745 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
313980c9
DB		 2746 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2747 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2748
2749 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2750 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
1da177e4 2751
1da177e4
LT		 2752 break;
2753
2754#ifdef USE_ISO
2755 case 2: /* mixed iso/bulk */
2756 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2757 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2758 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2759 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2760
2761 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2762
2763 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2764 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2765 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2766 break;
2767 case 3: /* mixed bulk/iso */
2768 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2769 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2770 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2771
2772 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2773 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2774 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2775
2776 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2777 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2778 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2779 break;
2780#endif
2781
2782 /* add more modes as needed */
2783
2784 default:
2785 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2786 return -ENODEV;
2787 }
f35ae634 2788 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
1da177e4
LT		 2789 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2790 return 0;
2791}
2792
3ae5eaec 2793static int __init omap_udc_probe(struct platform_device *pdev)
1da177e4 2794{
1da177e4
LT		 2795 int status = -ENODEV;
2796 int hmc;
86753811 2797 struct usb_phy *xceiv = NULL;
313980c9 2798 const char *type = NULL;
3ae5eaec 2799 struct omap_usb_config *config = pdev->dev.platform_data;
ae372571
TL		 2800 struct clk *dc_clk = NULL;
2801 struct clk *hhc_clk = NULL;
1da177e4 2802
5b6d84b7
FB		 2803 if (cpu_is_omap7xx())
2804 use_dma = 0;
2805
1da177e4 2806 /* NOTE: "knows" the order of the resources! */
e6a6e472 2807 if (!request_mem_region(pdev->resource[0].start,
3ae5eaec 2808 pdev->resource[0].end - pdev->resource[0].start + 1,
1da177e4
LT		 2809 driver_name)) {
2810 DBG("request_mem_region failed\n");
2811 return -EBUSY;
2812 }
2813
e6a6e472
DB		 2814 if (cpu_is_omap16xx()) {
2815 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2816 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2817 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2818 /* can't use omap_udc_enable_clock yet */
2819 clk_enable(dc_clk);
2820 clk_enable(hhc_clk);
2821 udelay(100);
2822 }
2823
45f780a0
CM		 2824 if (cpu_is_omap7xx()) {
2825 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2826 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2827 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2828 /* can't use omap_udc_enable_clock yet */
2829 clk_enable(dc_clk);
2830 clk_enable(hhc_clk);
2831 udelay(100);
2832 }
2833
1da177e4 2834 INFO("OMAP UDC rev %d.%d%s\n",
f35ae634 2835 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
1da177e4
LT		 2836 config->otg ? ", Mini-AB" : "");
2837
2838 /* use the mode given to us by board init code */
2839 if (cpu_is_omap15xx()) {
2840 hmc = HMC_1510;
2841 type = "(unknown)";
2842
8a3c1f57 2843 if (machine_without_vbus_sense()) {
1da177e4
LT		 2844 /* just set up software VBUS detect, and then
2845 * later rig it so we always report VBUS.
2846 * FIXME without really sensing VBUS, we can't
2847 * know when to turn PULLUP_EN on/off; and that
2848 * means we always "need" the 48MHz clock.
2849 */
f35ae634
TL		 2850 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2851 tmp &= ~VBUS_CTRL_1510;
2852 omap_writel(tmp, FUNC_MUX_CTRL_0);
1da177e4
LT		 2853 tmp |= VBUS_MODE_1510;
2854 tmp &= ~VBUS_CTRL_1510;
f35ae634 2855 omap_writel(tmp, FUNC_MUX_CTRL_0);
1da177e4
LT		 2856 }
2857 } else {
65111084
DB		 2858 /* The transceiver may package some GPIO logic or handle
2859 * loopback and/or transceiverless setup; if we find one,
2860 * use it. Except for OTG, we don't _need_ to talk to one;
2861 * but not having one probably means no VBUS detection.
2862 */
b96d3b08 2863 xceiv = usb_get_transceiver();
65111084
DB		 2864 if (xceiv)
2865 type = xceiv->label;
2866 else if (config->otg) {
2867 DBG("OTG requires external transceiver!\n");
2868 goto cleanup0;
2869 }
2870
1da177e4 2871 hmc = HMC_1610;
e6a6e472 2872
1da177e4 2873 switch (hmc) {
313980c9
DB		 2874 case 0: /* POWERUP DEFAULT == 0 */
2875 case 4:
2876 case 12:
2877 case 20:
2878 if (!cpu_is_omap1710()) {
2879 type = "integrated";
2880 break;
2881 }
2882 /* FALL THROUGH */
1da177e4
LT		 2883 case 3:
2884 case 11:
2885 case 16:
2886 case 19:
2887 case 25:
1da177e4
LT		 2888 if (!xceiv) {
2889 DBG("external transceiver not registered!\n");
313980c9 2890 type = "unknown";
65111084 2891 }
1da177e4 2892 break;
1da177e4 2893 case 21: /* internal loopback */
313980c9 2894 type = "loopback";
1da177e4
LT		 2895 break;
2896 case 14: /* transceiverless */
65111084
DB		 2897 if (cpu_is_omap1710())
2898 goto bad_on_1710;
2899 /* FALL THROUGH */
2900 case 13:
2901 case 15:
313980c9 2902 type = "no";
1da177e4
LT		 2903 break;
2904
2905 default:
65111084 2906bad_on_1710:
1da177e4 2907 ERR("unrecognized UDC HMC mode %d\n", hmc);
65111084 2908 goto cleanup0;
1da177e4
LT		 2909 }
2910 }
ae372571 2911
313980c9 2912 INFO("hmc mode %d, %s transceiver\n", hmc, type);
1da177e4
LT		 2913
2914 /* a "gadget" abstracts/virtualizes the controller */
3ae5eaec 2915 status = omap_udc_setup(pdev, xceiv);
80dd1358 2916 if (status)
1da177e4 2917 goto cleanup0;
80dd1358 2918
313980c9 2919 xceiv = NULL;
80dd1358 2920 /* "udc" is now valid */
1da177e4
LT		 2921 pullup_disable(udc);
2922#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2923 udc->gadget.is_otg = (config->otg != 0);
2924#endif
2925
65111084 2926 /* starting with omap1710 es2.0, clear toggle is a separate bit */
f35ae634 2927 if (omap_readw(UDC_REV) >= 0x61)
65111084
DB		 2928 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2929 else
2930 udc->clr_halt = UDC_RESET_EP;
2931
1da177e4 2932 /* USB general purpose IRQ: ep0, state changes, dma, etc */
3ae5eaec 2933 status = request_irq(pdev->resource[1].start, omap_udc_irq,
80dd1358 2934 0, driver_name, udc);
1da177e4 2935 if (status != 0) {
e6a6e472
DB		 2936 ERR("can't get irq %d, err %d\n",
2937 (int) pdev->resource[1].start, status);
1da177e4
LT		 2938 goto cleanup1;
2939 }
2940
2941 /* USB "non-iso" IRQ (PIO for all but ep0) */
3ae5eaec 2942 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
80dd1358 2943 0, "omap_udc pio", udc);
1da177e4 2944 if (status != 0) {
e6a6e472
DB		 2945 ERR("can't get irq %d, err %d\n",
2946 (int) pdev->resource[2].start, status);
1da177e4
LT		 2947 goto cleanup2;
2948 }
2949#ifdef USE_ISO
3ae5eaec 2950 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
b5dd18d8 2951 0, "omap_udc iso", udc);
1da177e4 2952 if (status != 0) {
e6a6e472
DB		 2953 ERR("can't get irq %d, err %d\n",
2954 (int) pdev->resource[3].start, status);
1da177e4
LT		 2955 goto cleanup3;
2956 }
2957#endif
45f780a0 2958 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
e6a6e472
DB		 2959 udc->dc_clk = dc_clk;
2960 udc->hhc_clk = hhc_clk;
2961 clk_disable(hhc_clk);
2962 clk_disable(dc_clk);
2963 }
2964
1da177e4 2965 create_proc_file();
e6a6e472 2966 status = device_add(&udc->gadget.dev);
0f91349b
SAS		 2967 if (status)
2968 goto cleanup4;
2969
2970 status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
e6a6e472
DB		 2971 if (!status)
2972 return status;
2973 /* If fail, fall through */
0f91349b
SAS		 2974cleanup4:
2975 remove_proc_file();
2976
1da177e4
LT		 2977#ifdef USE_ISO
2978cleanup3:
3ae5eaec 2979 free_irq(pdev->resource[2].start, udc);
1da177e4
LT		 2980#endif
2981
2982cleanup2:
3ae5eaec 2983 free_irq(pdev->resource[1].start, udc);
1da177e4
LT		 2984
2985cleanup1:
80dd1358 2986 kfree(udc);
313980c9 2987 udc = NULL;
1da177e4
LT		 2988
2989cleanup0:
2990 if (xceiv)
b96d3b08 2991 usb_put_transceiver(xceiv);
e6a6e472 2992
ae372571 2993 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
e6a6e472
DB		 2994 clk_disable(hhc_clk);
2995 clk_disable(dc_clk);
2996 clk_put(hhc_clk);
2997 clk_put(dc_clk);
2998 }
2999
3ae5eaec
RK		 3000 release_mem_region(pdev->resource[0].start,
3001 pdev->resource[0].end - pdev->resource[0].start + 1);
e6a6e472 3002
1da177e4
LT		 3003 return status;
3004}
3005
3ae5eaec 3006static int __exit omap_udc_remove(struct platform_device *pdev)
1da177e4 3007{
6e9a4738 3008 DECLARE_COMPLETION_ONSTACK(done);
1da177e4
LT		 3009
3010 if (!udc)
3011 return -ENODEV;
0f91349b
SAS		 3012
3013 usb_del_gadget_udc(&udc->gadget);
6bea476c
DB		 3014 if (udc->driver)
3015 return -EBUSY;
1da177e4
LT		 3016
3017 udc->done = &done;
3018
3019 pullup_disable(udc);
3020 if (udc->transceiver) {
b96d3b08 3021 usb_put_transceiver(udc->transceiver);
313980c9 3022 udc->transceiver = NULL;
1da177e4 3023 }
f35ae634 3024 omap_writew(0, UDC_SYSCON1);
1da177e4
LT		 3025
3026 remove_proc_file();
3027
3028#ifdef USE_ISO
3ae5eaec 3029 free_irq(pdev->resource[3].start, udc);
1da177e4 3030#endif
3ae5eaec
RK		 3031 free_irq(pdev->resource[2].start, udc);
3032 free_irq(pdev->resource[1].start, udc);
1da177e4 3033
e6a6e472
DB		 3034 if (udc->dc_clk) {
3035 if (udc->clk_requested)
3036 omap_udc_enable_clock(0);
3037 clk_put(udc->hhc_clk);
3038 clk_put(udc->dc_clk);
3039 }
3040
3ae5eaec
RK		 3041 release_mem_region(pdev->resource[0].start,
3042 pdev->resource[0].end - pdev->resource[0].start + 1);
1da177e4
LT		 3043
3044 device_unregister(&udc->gadget.dev);
3045 wait_for_completion(&done);
3046
3047 return 0;
3048}
3049
313980c9
DB		 3050/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3051 * system is forced into deep sleep
3052 *
3053 * REVISIT we should probably reject suspend requests when there's a host
3054 * session active, rather than disconnecting, at least on boards that can
f35ae634 3055 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
313980c9
DB		 3056 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3057 * may involve talking to an external transceiver (e.g. isp1301).
3058 */
1d7beee3 3059
3ae5eaec 3060static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
1da177e4 3061{
313980c9
DB		 3062 u32 devstat;
3063
f35ae634 3064 devstat = omap_readw(UDC_DEVSTAT);
313980c9
DB		 3065
3066 /* we're requesting 48 MHz clock if the pullup is enabled
3067 * (== we're attached to the host) and we're not suspended,
3068 * which would prevent entry to deep sleep...
3069 */
3070 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
b6c63937 3071 WARNING("session active; suspend requires disconnect\n");
313980c9
DB		 3072 omap_pullup(&udc->gadget, 0);
3073 }
1da177e4 3074
1da177e4
LT		 3075 return 0;
3076}
3077
3ae5eaec 3078static int omap_udc_resume(struct platform_device *dev)
1da177e4 3079{
1da177e4 3080 DBG("resume + wakeup/SRP\n");
1da177e4
LT		 3081 omap_pullup(&udc->gadget, 1);
3082
3083 /* maybe the host would enumerate us if we nudged it */
3084 msleep(100);
3085 return omap_wakeup(&udc->gadget);
3086}
3087
3088/*-------------------------------------------------------------------------*/
3089
3ae5eaec 3090static struct platform_driver udc_driver = {
1da177e4
LT		 3091 .remove = __exit_p(omap_udc_remove),
3092 .suspend = omap_udc_suspend,
3093 .resume = omap_udc_resume,
3ae5eaec
RK		 3094 .driver = {
3095 .owner = THIS_MODULE,
3096 .name = (char *) driver_name,
3097 },
1da177e4
LT		 3098};
3099
3100static int __init udc_init(void)
3101{
864e28b4 3102 return platform_driver_probe(&udc_driver, omap_udc_probe);
1da177e4
LT		 3103}
3104module_init(udc_init);
3105
3106static void __exit udc_exit(void)
3107{
3ae5eaec 3108 platform_driver_unregister(&udc_driver);
1da177e4
LT		 3109}
3110module_exit(udc_exit);
3111
3112MODULE_DESCRIPTION(DRIVER_DESC);
3113MODULE_LICENSE("GPL");
f34c32f1 3114MODULE_ALIAS("platform:omap_udc");
Linux kernel - Deliverables
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