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usb: gadget: omap_udc: Remove omap2 support
[deliverable/linux.git] / drivers / usb / gadget / omap_udc.c
CommitLineData
1da177e4
LT		 1/*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
527ea73e
KP		 7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
1da177e4
LT		 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
1da177e4
LT		 13 */
14
15#undef DEBUG
16#undef VERBOSE
17
1da177e4
LT		 18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/ioport.h>
21#include <linux/types.h>
22#include <linux/errno.h>
23#include <linux/delay.h>
1da177e4
LT		 24#include <linux/slab.h>
25#include <linux/init.h>
26#include <linux/timer.h>
27#include <linux/list.h>
28#include <linux/interrupt.h>
29#include <linux/proc_fs.h>
30#include <linux/mm.h>
31#include <linux/moduleparam.h>
d052d1be 32#include <linux/platform_device.h>
5f848137 33#include <linux/usb/ch9.h>
9454a57a 34#include <linux/usb/gadget.h>
3a16f7b4 35#include <linux/usb/otg.h>
1da177e4 36#include <linux/dma-mapping.h>
e6a6e472 37#include <linux/clk.h>
268bb0ce 38#include <linux/prefetch.h>
1da177e4
LT		 39
40#include <asm/byteorder.h>
41#include <asm/io.h>
42#include <asm/irq.h>
1da177e4
LT		 43#include <asm/unaligned.h>
44#include <asm/mach-types.h>
45
ce491cf8
TL		 46#include <plat/dma.h>
47#include <plat/usb.h>
1da177e4
LT		 48
49#include "omap_udc.h"
50
51#undef USB_TRACE
52
53/* bulk DMA seems to be behaving for both IN and OUT */
54#define USE_DMA
55
56/* ISO too */
57#define USE_ISO
58
59#define DRIVER_DESC "OMAP UDC driver"
60#define DRIVER_VERSION "4 October 2004"
61
62#define DMA_ADDR_INVALID (~(dma_addr_t)0)
63
1da177e4
LT		 64/*
65 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
66 * D+ pullup to allow enumeration. That's too early for the gadget
67 * framework to use from usb_endpoint_enable(), which happens after
68 * enumeration as part of activating an interface. (But if we add an
69 * optional new "UDC not yet running" state to the gadget driver model,
70 * even just during driver binding, the endpoint autoconfig logic is the
71 * natural spot to manufacture new endpoints.)
72 *
73 * So instead of using endpoint enable calls to control the hardware setup,
74 * this driver defines a "fifo mode" parameter. It's used during driver
75 * initialization to choose among a set of pre-defined endpoint configs.
76 * See omap_udc_setup() for available modes, or to add others. That code
77 * lives in an init section, so use this driver as a module if you need
78 * to change the fifo mode after the kernel boots.
79 *
80 * Gadget drivers normally ignore endpoints they don't care about, and
81 * won't include them in configuration descriptors. That means only
82 * misbehaving hosts would even notice they exist.
83 */
84#ifdef USE_ISO
85static unsigned fifo_mode = 3;
86#else
87static unsigned fifo_mode = 0;
88#endif
89
90/* "modprobe omap_udc fifo_mode=42", or else as a kernel
91 * boot parameter "omap_udc:fifo_mode=42"
92 */
93module_param (fifo_mode, uint, 0);
e6a6e472 94MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
1da177e4
LT		 95
96#ifdef USE_DMA
90ab5ee9 97static bool use_dma = 1;
1da177e4
LT		 98
99/* "modprobe omap_udc use_dma=y", or else as a kernel
100 * boot parameter "omap_udc:use_dma=y"
101 */
102module_param (use_dma, bool, 0);
103MODULE_PARM_DESC (use_dma, "enable/disable DMA");
104#else /* !USE_DMA */
105
106/* save a bit of code */
107#define use_dma 0
108#endif /* !USE_DMA */
109
110
111static const char driver_name [] = "omap_udc";
112static const char driver_desc [] = DRIVER_DESC;
113
114/*-------------------------------------------------------------------------*/
115
116/* there's a notion of "current endpoint" for modifying endpoint
e6a6e472 117 * state, and PIO access to its FIFO.
1da177e4
LT		 118 */
119
120static void use_ep(struct omap_ep *ep, u16 select)
121{
122 u16 num = ep->bEndpointAddress & 0x0f;
123
124 if (ep->bEndpointAddress & USB_DIR_IN)
125 num |= UDC_EP_DIR;
f35ae634 126 omap_writew(num | select, UDC_EP_NUM);
1da177e4
LT		 127 /* when select, MUST deselect later !! */
128}
129
130static inline void deselect_ep(void)
131{
f35ae634
TL		 132 u16 w;
133
134 w = omap_readw(UDC_EP_NUM);
135 w &= ~UDC_EP_SEL;
136 omap_writew(w, UDC_EP_NUM);
1da177e4
LT		 137 /* 6 wait states before TX will happen */
138}
139
140static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
141
142/*-------------------------------------------------------------------------*/
143
144static int omap_ep_enable(struct usb_ep *_ep,
145 const struct usb_endpoint_descriptor *desc)
146{
147 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
148 struct omap_udc *udc;
149 unsigned long flags;
150 u16 maxp;
151
152 /* catch various bogus parameters */
f8bdae06 153 if (!_ep || !desc || ep->ep.desc
1da177e4
LT		 154 || desc->bDescriptorType != USB_DT_ENDPOINT
155 || ep->bEndpointAddress != desc->bEndpointAddress
29cc8897 156 || ep->maxpacket < usb_endpoint_maxp(desc)) {
441b62c1 157 DBG("%s, bad ep or descriptor\n", __func__);
1da177e4
LT		 158 return -EINVAL;
159 }
29cc8897 160 maxp = usb_endpoint_maxp(desc);
1da177e4
LT		 161 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
162 && maxp != ep->maxpacket)
29cc8897 163 || usb_endpoint_maxp(desc) > ep->maxpacket
1da177e4 164 || !desc->wMaxPacketSize) {
441b62c1 165 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
1da177e4
LT		 166 return -ERANGE;
167 }
168
169#ifdef USE_ISO
170 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
171 && desc->bInterval != 1)) {
172 /* hardware wants period = 1; USB allows 2^(Interval-1) */
173 DBG("%s, unsupported ISO period %dms\n", _ep->name,
174 1 << (desc->bInterval - 1));
175 return -EDOM;
176 }
177#else
178 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
179 DBG("%s, ISO nyet\n", _ep->name);
180 return -EDOM;
181 }
182#endif
183
184 /* xfer types must match, except that interrupt ~= bulk */
185 if (ep->bmAttributes != desc->bmAttributes
186 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
187 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
441b62c1 188 DBG("%s, %s type mismatch\n", __func__, _ep->name);
1da177e4
LT		 189 return -EINVAL;
190 }
191
192 udc = ep->udc;
193 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
441b62c1 194 DBG("%s, bogus device state\n", __func__);
1da177e4
LT		 195 return -ESHUTDOWN;
196 }
197
198 spin_lock_irqsave(&udc->lock, flags);
199
f8bdae06 200 ep->ep.desc = desc;
1da177e4
LT		 201 ep->irqs = 0;
202 ep->stopped = 0;
203 ep->ep.maxpacket = maxp;
204
205 /* set endpoint to initial state */
206 ep->dma_channel = 0;
207 ep->has_dma = 0;
208 ep->lch = -1;
209 use_ep(ep, UDC_EP_SEL);
f35ae634 210 omap_writew(udc->clr_halt, UDC_CTRL);
1da177e4
LT		 211 ep->ackwait = 0;
212 deselect_ep();
213
214 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
215 list_add(&ep->iso, &udc->iso);
216
217 /* maybe assign a DMA channel to this endpoint */
218 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
219 /* FIXME ISO can dma, but prefers first channel */
220 dma_channel_claim(ep, 0);
221
222 /* PIO OUT may RX packets */
223 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
224 && !ep->has_dma
225 && !(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 226 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 227 ep->ackwait = 1 + ep->double_buf;
228 }
229
230 spin_unlock_irqrestore(&udc->lock, flags);
231 VDBG("%s enabled\n", _ep->name);
232 return 0;
233}
234
235static void nuke(struct omap_ep *, int status);
236
237static int omap_ep_disable(struct usb_ep *_ep)
238{
239 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
240 unsigned long flags;
241
f8bdae06 242 if (!_ep || !ep->ep.desc) {
441b62c1 243 DBG("%s, %s not enabled\n", __func__,
1da177e4
LT		 244 _ep ? ep->ep.name : NULL);
245 return -EINVAL;
246 }
247
248 spin_lock_irqsave(&ep->udc->lock, flags);
f9c56cdd 249 ep->ep.desc = NULL;
1da177e4
LT		 250 nuke (ep, -ESHUTDOWN);
251 ep->ep.maxpacket = ep->maxpacket;
252 ep->has_dma = 0;
f35ae634 253 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 254 list_del_init(&ep->iso);
255 del_timer(&ep->timer);
256
257 spin_unlock_irqrestore(&ep->udc->lock, flags);
258
259 VDBG("%s disabled\n", _ep->name);
260 return 0;
261}
262
263/*-------------------------------------------------------------------------*/
264
265static struct usb_request *
55016f10 266omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1da177e4
LT		 267{
268 struct omap_req *req;
269
7039f422 270 req = kzalloc(sizeof(*req), gfp_flags);
1da177e4 271 if (req) {
1da177e4
LT		 272 req->req.dma = DMA_ADDR_INVALID;
273 INIT_LIST_HEAD (&req->queue);
274 }
275 return &req->req;
276}
277
278static void
279omap_free_request(struct usb_ep *ep, struct usb_request *_req)
280{
281 struct omap_req *req = container_of(_req, struct omap_req, req);
282
283 if (_req)
284 kfree (req);
285}
286
287/*-------------------------------------------------------------------------*/
288
1da177e4
LT		 289static void
290done(struct omap_ep *ep, struct omap_req *req, int status)
291{
292 unsigned stopped = ep->stopped;
293
294 list_del_init(&req->queue);
295
296 if (req->req.status == -EINPROGRESS)
297 req->req.status = status;
298 else
299 status = req->req.status;
300
301 if (use_dma && ep->has_dma) {
302 if (req->mapped) {
303 dma_unmap_single(ep->udc->gadget.dev.parent,
304 req->req.dma, req->req.length,
305 (ep->bEndpointAddress & USB_DIR_IN)
306 ? DMA_TO_DEVICE
307 : DMA_FROM_DEVICE);
308 req->req.dma = DMA_ADDR_INVALID;
309 req->mapped = 0;
310 } else
311 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
312 req->req.dma, req->req.length,
313 (ep->bEndpointAddress & USB_DIR_IN)
314 ? DMA_TO_DEVICE
315 : DMA_FROM_DEVICE);
316 }
317
318#ifndef USB_TRACE
319 if (status && status != -ESHUTDOWN)
320#endif
321 VDBG("complete %s req %p stat %d len %u/%u\n",
322 ep->ep.name, &req->req, status,
323 req->req.actual, req->req.length);
324
325 /* don't modify queue heads during completion callback */
326 ep->stopped = 1;
327 spin_unlock(&ep->udc->lock);
328 req->req.complete(&ep->ep, &req->req);
329 spin_lock(&ep->udc->lock);
330 ep->stopped = stopped;
331}
332
333/*-------------------------------------------------------------------------*/
334
313980c9
DB		 335#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
336#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
1da177e4
LT		 337
338#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
339#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
340
e6a6e472 341static inline int
1da177e4
LT		 342write_packet(u8 *buf, struct omap_req *req, unsigned max)
343{
344 unsigned len;
345 u16 *wp;
346
347 len = min(req->req.length - req->req.actual, max);
348 req->req.actual += len;
349
350 max = len;
351 if (likely((((int)buf) & 1) == 0)) {
352 wp = (u16 *)buf;
353 while (max >= 2) {
f35ae634 354 omap_writew(*wp++, UDC_DATA);
1da177e4
LT		 355 max -= 2;
356 }
357 buf = (u8 *)wp;
358 }
359 while (max--)
f35ae634 360 omap_writeb(*buf++, UDC_DATA);
1da177e4
LT		 361 return len;
362}
363
364// FIXME change r/w fifo calling convention
365
366
367// return: 0 = still running, 1 = completed, negative = errno
368static int write_fifo(struct omap_ep *ep, struct omap_req *req)
369{
370 u8 *buf;
371 unsigned count;
372 int is_last;
373 u16 ep_stat;
374
375 buf = req->req.buf + req->req.actual;
376 prefetch(buf);
377
378 /* PIO-IN isn't double buffered except for iso */
f35ae634 379 ep_stat = omap_readw(UDC_STAT_FLG);
313980c9 380 if (ep_stat & UDC_FIFO_UNWRITABLE)
1da177e4
LT		 381 return 0;
382
383 count = ep->ep.maxpacket;
384 count = write_packet(buf, req, count);
f35ae634 385 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 386 ep->ackwait = 1;
387
388 /* last packet is often short (sometimes a zlp) */
389 if (count != ep->ep.maxpacket)
390 is_last = 1;
391 else if (req->req.length == req->req.actual
392 && !req->req.zero)
393 is_last = 1;
394 else
395 is_last = 0;
396
397 /* NOTE: requests complete when all IN data is in a
398 * FIFO (or sometimes later, if a zlp was needed).
399 * Use usb_ep_fifo_status() where needed.
400 */
401 if (is_last)
402 done(ep, req, 0);
403 return is_last;
404}
405
e6a6e472 406static inline int
1da177e4
LT		 407read_packet(u8 *buf, struct omap_req *req, unsigned avail)
408{
409 unsigned len;
410 u16 *wp;
411
412 len = min(req->req.length - req->req.actual, avail);
413 req->req.actual += len;
414 avail = len;
415
416 if (likely((((int)buf) & 1) == 0)) {
417 wp = (u16 *)buf;
418 while (avail >= 2) {
f35ae634 419 *wp++ = omap_readw(UDC_DATA);
1da177e4
LT		 420 avail -= 2;
421 }
422 buf = (u8 *)wp;
423 }
424 while (avail--)
f35ae634 425 *buf++ = omap_readb(UDC_DATA);
1da177e4
LT		 426 return len;
427}
428
429// return: 0 = still running, 1 = queue empty, negative = errno
430static int read_fifo(struct omap_ep *ep, struct omap_req *req)
431{
432 u8 *buf;
433 unsigned count, avail;
434 int is_last;
435
436 buf = req->req.buf + req->req.actual;
437 prefetchw(buf);
438
439 for (;;) {
f35ae634 440 u16 ep_stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 441
442 is_last = 0;
443 if (ep_stat & FIFO_EMPTY) {
444 if (!ep->double_buf)
445 break;
446 ep->fnf = 1;
447 }
448 if (ep_stat & UDC_EP_HALTED)
449 break;
450
313980c9 451 if (ep_stat & UDC_FIFO_FULL)
1da177e4
LT		 452 avail = ep->ep.maxpacket;
453 else {
f35ae634 454 avail = omap_readw(UDC_RXFSTAT);
1da177e4
LT		 455 ep->fnf = ep->double_buf;
456 }
457 count = read_packet(buf, req, avail);
458
459 /* partial packet reads may not be errors */
460 if (count < ep->ep.maxpacket) {
461 is_last = 1;
462 /* overflowed this request? flush extra data */
463 if (count != avail) {
464 req->req.status = -EOVERFLOW;
465 avail -= count;
466 while (avail--)
f35ae634 467 omap_readw(UDC_DATA);
1da177e4
LT		 468 }
469 } else if (req->req.length == req->req.actual)
470 is_last = 1;
471 else
472 is_last = 0;
473
474 if (!ep->bEndpointAddress)
475 break;
476 if (is_last)
477 done(ep, req, 0);
478 break;
479 }
480 return is_last;
481}
482
483/*-------------------------------------------------------------------------*/
484
485static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
486{
487 dma_addr_t end;
488
489 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
490 * the last transfer's bytecount by more than a FIFO's worth.
491 */
492 if (cpu_is_omap15xx())
493 return 0;
494
0499bdeb 495 end = omap_get_dma_src_pos(ep->lch);
1da177e4
LT		 496 if (end == ep->dma_counter)
497 return 0;
498
499 end |= start & (0xffff << 16);
500 if (end < start)
501 end += 0x10000;
502 return end - start;
503}
504
1da177e4
LT		 505static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
506{
507 dma_addr_t end;
508
0499bdeb 509 end = omap_get_dma_dst_pos(ep->lch);
1da177e4
LT		 510 if (end == ep->dma_counter)
511 return 0;
512
513 end |= start & (0xffff << 16);
514 if (cpu_is_omap15xx())
515 end++;
516 if (end < start)
517 end += 0x10000;
518 return end - start;
519}
520
521
522/* Each USB transfer request using DMA maps to one or more DMA transfers.
523 * When DMA completion isn't request completion, the UDC continues with
524 * the next DMA transfer for that USB transfer.
525 */
526
527static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
528{
f35ae634 529 u16 txdma_ctrl, w;
1da177e4
LT		 530 unsigned length = req->req.length - req->req.actual;
531 const int sync_mode = cpu_is_omap15xx()
532 ? OMAP_DMA_SYNC_FRAME
533 : OMAP_DMA_SYNC_ELEMENT;
527ea73e
KP		 534 int dma_trigger = 0;
535
1da177e4 536 /* measure length in either bytes or packets */
65111084 537 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
1da177e4
LT		 538 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
539 txdma_ctrl = UDC_TXN_EOT | length;
540 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
527ea73e 541 length, 1, sync_mode, dma_trigger, 0);
1da177e4
LT		 542 } else {
543 length = min(length / ep->maxpacket,
544 (unsigned) UDC_TXN_TSC + 1);
e6a6e472 545 txdma_ctrl = length;
65111084 546 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
e6a6e472 547 ep->ep.maxpacket >> 1, length, sync_mode,
527ea73e 548 dma_trigger, 0);
1da177e4
LT		 549 length *= ep->maxpacket;
550 }
551 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
e6a6e472
DB		 552 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
553 0, 0);
1da177e4
LT		 554
555 omap_start_dma(ep->lch);
0499bdeb 556 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
f35ae634
TL		 557 w = omap_readw(UDC_DMA_IRQ_EN);
558 w |= UDC_TX_DONE_IE(ep->dma_channel);
559 omap_writew(w, UDC_DMA_IRQ_EN);
560 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
1da177e4
LT		 561 req->dma_bytes = length;
562}
563
564static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
565{
f35ae634
TL		 566 u16 w;
567
1da177e4
LT		 568 if (status == 0) {
569 req->req.actual += req->dma_bytes;
570
571 /* return if this request needs to send data or zlp */
572 if (req->req.actual < req->req.length)
573 return;
574 if (req->req.zero
575 && req->dma_bytes != 0
576 && (req->req.actual % ep->maxpacket) == 0)
577 return;
578 } else
579 req->req.actual += dma_src_len(ep, req->req.dma
580 + req->req.actual);
581
582 /* tx completion */
583 omap_stop_dma(ep->lch);
f35ae634
TL		 584 w = omap_readw(UDC_DMA_IRQ_EN);
585 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
586 omap_writew(w, UDC_DMA_IRQ_EN);
1da177e4
LT		 587 done(ep, req, status);
588}
589
590static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
591{
527ea73e
KP		 592 unsigned packets = req->req.length - req->req.actual;
593 int dma_trigger = 0;
f35ae634 594 u16 w;
527ea73e 595
ae372571
TL		 596 /* set up this DMA transfer, enable the fifo, start */
597 packets /= ep->ep.maxpacket;
598 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
599 req->dma_bytes = packets * ep->ep.maxpacket;
600 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
601 ep->ep.maxpacket >> 1, packets,
602 OMAP_DMA_SYNC_ELEMENT,
603 dma_trigger, 0);
1da177e4 604 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
e6a6e472
DB		 605 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
606 0, 0);
0499bdeb 607 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
1da177e4 608
f35ae634
TL		 609 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
610 w = omap_readw(UDC_DMA_IRQ_EN);
611 w |= UDC_RX_EOT_IE(ep->dma_channel);
612 omap_writew(w, UDC_DMA_IRQ_EN);
613 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
614 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 615
616 omap_start_dma(ep->lch);
617}
618
619static void
cb97c5c9 620finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
1da177e4 621{
f35ae634 622 u16 count, w;
1da177e4
LT		 623
624 if (status == 0)
625 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
626 count = dma_dest_len(ep, req->req.dma + req->req.actual);
627 count += req->req.actual;
cb97c5c9
DB		 628 if (one)
629 count--;
1da177e4
LT		 630 if (count <= req->req.length)
631 req->req.actual = count;
632
633 if (count != req->dma_bytes || status)
634 omap_stop_dma(ep->lch);
635
636 /* if this wasn't short, request may need another transfer */
637 else if (req->req.actual < req->req.length)
638 return;
639
640 /* rx completion */
f35ae634
TL		 641 w = omap_readw(UDC_DMA_IRQ_EN);
642 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
643 omap_writew(w, UDC_DMA_IRQ_EN);
1da177e4
LT		 644 done(ep, req, status);
645}
646
647static void dma_irq(struct omap_udc *udc, u16 irq_src)
648{
f35ae634 649 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
1da177e4
LT		 650 struct omap_ep *ep;
651 struct omap_req *req;
652
653 /* IN dma: tx to host */
654 if (irq_src & UDC_TXN_DONE) {
655 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
656 ep->irqs++;
657 /* can see TXN_DONE after dma abort */
658 if (!list_empty(&ep->queue)) {
659 req = container_of(ep->queue.next,
660 struct omap_req, queue);
661 finish_in_dma(ep, req, 0);
662 }
f35ae634 663 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
1da177e4
LT		 664
665 if (!list_empty (&ep->queue)) {
666 req = container_of(ep->queue.next,
667 struct omap_req, queue);
668 next_in_dma(ep, req);
669 }
670 }
671
672 /* OUT dma: rx from host */
673 if (irq_src & UDC_RXN_EOT) {
674 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
675 ep->irqs++;
676 /* can see RXN_EOT after dma abort */
677 if (!list_empty(&ep->queue)) {
678 req = container_of(ep->queue.next,
679 struct omap_req, queue);
cb97c5c9 680 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
1da177e4 681 }
f35ae634 682 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
1da177e4
LT		 683
684 if (!list_empty (&ep->queue)) {
685 req = container_of(ep->queue.next,
686 struct omap_req, queue);
687 next_out_dma(ep, req);
688 }
689 }
690
691 if (irq_src & UDC_RXN_CNT) {
692 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
693 ep->irqs++;
694 /* omap15xx does this unasked... */
695 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
f35ae634 696 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
1da177e4
LT		 697 }
698}
699
700static void dma_error(int lch, u16 ch_status, void *data)
701{
702 struct omap_ep *ep = data;
703
704 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
7ff879db 705 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
1da177e4
LT		 706 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
707
708 /* complete current transfer ... */
709}
710
711static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
712{
713 u16 reg;
714 int status, restart, is_in;
527ea73e 715 int dma_channel;
1da177e4
LT		 716
717 is_in = ep->bEndpointAddress & USB_DIR_IN;
718 if (is_in)
f35ae634 719 reg = omap_readw(UDC_TXDMA_CFG);
1da177e4 720 else
f35ae634 721 reg = omap_readw(UDC_RXDMA_CFG);
65111084 722 reg |= UDC_DMA_REQ; /* "pulse" activated */
1da177e4
LT		 723
724 ep->dma_channel = 0;
725 ep->lch = -1;
726 if (channel == 0 || channel > 3) {
727 if ((reg & 0x0f00) == 0)
728 channel = 3;
729 else if ((reg & 0x00f0) == 0)
730 channel = 2;
731 else if ((reg & 0x000f) == 0) /* preferred for ISO */
732 channel = 1;
733 else {
734 status = -EMLINK;
735 goto just_restart;
736 }
737 }
738 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
739 ep->dma_channel = channel;
740
741 if (is_in) {
ae372571 742 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
527ea73e 743 status = omap_request_dma(dma_channel,
1da177e4
LT		 744 ep->ep.name, dma_error, ep, &ep->lch);
745 if (status == 0) {
f35ae634 746 omap_writew(reg, UDC_TXDMA_CFG);
527ea73e 747 /* EMIFF or SDRC */
65111084
DB		 748 omap_set_dma_src_burst_mode(ep->lch,
749 OMAP_DMA_DATA_BURST_4);
750 omap_set_dma_src_data_pack(ep->lch, 1);
751 /* TIPB */
1da177e4
LT		 752 omap_set_dma_dest_params(ep->lch,
753 OMAP_DMA_PORT_TIPB,
754 OMAP_DMA_AMODE_CONSTANT,
c3e3208e 755 UDC_DATA_DMA,
e6a6e472 756 0, 0);
1da177e4
LT		 757 }
758 } else {
ae372571 759 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
527ea73e 760 status = omap_request_dma(dma_channel,
1da177e4
LT		 761 ep->ep.name, dma_error, ep, &ep->lch);
762 if (status == 0) {
f35ae634 763 omap_writew(reg, UDC_RXDMA_CFG);
65111084 764 /* TIPB */
1da177e4
LT		 765 omap_set_dma_src_params(ep->lch,
766 OMAP_DMA_PORT_TIPB,
767 OMAP_DMA_AMODE_CONSTANT,
c3e3208e 768 UDC_DATA_DMA,
e6a6e472 769 0, 0);
527ea73e 770 /* EMIFF or SDRC */
65111084
DB		 771 omap_set_dma_dest_burst_mode(ep->lch,
772 OMAP_DMA_DATA_BURST_4);
773 omap_set_dma_dest_data_pack(ep->lch, 1);
1da177e4
LT		 774 }
775 }
776 if (status)
777 ep->dma_channel = 0;
778 else {
779 ep->has_dma = 1;
780 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
781
782 /* channel type P: hw synch (fifo) */
ae372571 783 if (!cpu_is_omap15xx())
0499bdeb 784 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
1da177e4
LT		 785 }
786
787just_restart:
788 /* restart any queue, even if the claim failed */
789 restart = !ep->stopped && !list_empty(&ep->queue);
790
791 if (status)
792 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
793 restart ? " (restart)" : "");
794 else
795 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
796 is_in ? 't' : 'r',
797 ep->dma_channel - 1, ep->lch,
798 restart ? " (restart)" : "");
799
800 if (restart) {
801 struct omap_req *req;
802 req = container_of(ep->queue.next, struct omap_req, queue);
803 if (ep->has_dma)
804 (is_in ? next_in_dma : next_out_dma)(ep, req);
805 else {
806 use_ep(ep, UDC_EP_SEL);
807 (is_in ? write_fifo : read_fifo)(ep, req);
808 deselect_ep();
809 if (!is_in) {
f35ae634 810 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 811 ep->ackwait = 1 + ep->double_buf;
812 }
813 /* IN: 6 wait states before it'll tx */
814 }
815 }
816}
817
818static void dma_channel_release(struct omap_ep *ep)
819{
820 int shift = 4 * (ep->dma_channel - 1);
821 u16 mask = 0x0f << shift;
822 struct omap_req *req;
823 int active;
824
825 /* abort any active usb transfer request */
826 if (!list_empty(&ep->queue))
827 req = container_of(ep->queue.next, struct omap_req, queue);
828 else
313980c9 829 req = NULL;
1da177e4 830
0499bdeb 831 active = omap_get_dma_active_status(ep->lch);
1da177e4
LT		 832
833 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
834 active ? "active" : "idle",
835 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
836 ep->dma_channel - 1, req);
837
65111084
DB		 838 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
839 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
840 */
841
1da177e4
LT		 842 /* wait till current packet DMA finishes, and fifo empties */
843 if (ep->bEndpointAddress & USB_DIR_IN) {
f35ae634
TL		 844 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
845 UDC_TXDMA_CFG);
1da177e4
LT		 846
847 if (req) {
848 finish_in_dma(ep, req, -ECONNRESET);
849
850 /* clear FIFO; hosts probably won't empty it */
851 use_ep(ep, UDC_EP_SEL);
f35ae634 852 omap_writew(UDC_CLR_EP, UDC_CTRL);
1da177e4
LT		 853 deselect_ep();
854 }
f35ae634 855 while (omap_readw(UDC_TXDMA_CFG) & mask)
1da177e4
LT		 856 udelay(10);
857 } else {
f35ae634
TL		 858 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
859 UDC_RXDMA_CFG);
1da177e4
LT		 860
861 /* dma empties the fifo */
f35ae634 862 while (omap_readw(UDC_RXDMA_CFG) & mask)
1da177e4
LT		 863 udelay(10);
864 if (req)
cb97c5c9 865 finish_out_dma(ep, req, -ECONNRESET, 0);
1da177e4
LT		 866 }
867 omap_free_dma(ep->lch);
868 ep->dma_channel = 0;
869 ep->lch = -1;
870 /* has_dma still set, till endpoint is fully quiesced */
871}
872
873
874/*-------------------------------------------------------------------------*/
875
876static int
55016f10 877omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1da177e4
LT		 878{
879 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
880 struct omap_req *req = container_of(_req, struct omap_req, req);
881 struct omap_udc *udc;
882 unsigned long flags;
883 int is_iso = 0;
884
885 /* catch various bogus parameters */
886 if (!_req || !req->req.complete || !req->req.buf
887 || !list_empty(&req->queue)) {
441b62c1 888 DBG("%s, bad params\n", __func__);
1da177e4
LT		 889 return -EINVAL;
890 }
f8bdae06 891 if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
441b62c1 892 DBG("%s, bad ep\n", __func__);
1da177e4
LT		 893 return -EINVAL;
894 }
895 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
896 if (req->req.length > ep->ep.maxpacket)
897 return -EMSGSIZE;
898 is_iso = 1;
899 }
900
901 /* this isn't bogus, but OMAP DMA isn't the only hardware to
902 * have a hard time with partial packet reads... reject it.
903 */
904 if (use_dma
905 && ep->has_dma
906 && ep->bEndpointAddress != 0
907 && (ep->bEndpointAddress & USB_DIR_IN) == 0
908 && (req->req.length % ep->ep.maxpacket) != 0) {
441b62c1 909 DBG("%s, no partial packet OUT reads\n", __func__);
1da177e4
LT		 910 return -EMSGSIZE;
911 }
912
913 udc = ep->udc;
914 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
915 return -ESHUTDOWN;
916
917 if (use_dma && ep->has_dma) {
918 if (req->req.dma == DMA_ADDR_INVALID) {
919 req->req.dma = dma_map_single(
920 ep->udc->gadget.dev.parent,
921 req->req.buf,
922 req->req.length,
923 (ep->bEndpointAddress & USB_DIR_IN)
924 ? DMA_TO_DEVICE
925 : DMA_FROM_DEVICE);
926 req->mapped = 1;
927 } else {
928 dma_sync_single_for_device(
929 ep->udc->gadget.dev.parent,
930 req->req.dma, req->req.length,
931 (ep->bEndpointAddress & USB_DIR_IN)
932 ? DMA_TO_DEVICE
933 : DMA_FROM_DEVICE);
934 req->mapped = 0;
935 }
936 }
937
938 VDBG("%s queue req %p, len %d buf %p\n",
939 ep->ep.name, _req, _req->length, _req->buf);
940
941 spin_lock_irqsave(&udc->lock, flags);
942
943 req->req.status = -EINPROGRESS;
944 req->req.actual = 0;
945
946 /* maybe kickstart non-iso i/o queues */
f35ae634
TL		 947 if (is_iso) {
948 u16 w;
949
950 w = omap_readw(UDC_IRQ_EN);
951 w |= UDC_SOF_IE;
952 omap_writew(w, UDC_IRQ_EN);
953 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1da177e4
LT		 954 int is_in;
955
956 if (ep->bEndpointAddress == 0) {
957 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
958 spin_unlock_irqrestore(&udc->lock, flags);
959 return -EL2HLT;
960 }
961
962 /* empty DATA stage? */
963 is_in = udc->ep0_in;
964 if (!req->req.length) {
965
966 /* chip became CONFIGURED or ADDRESSED
967 * earlier; drivers may already have queued
968 * requests to non-control endpoints
969 */
970 if (udc->ep0_set_config) {
f35ae634 971 u16 irq_en = omap_readw(UDC_IRQ_EN);
1da177e4
LT		 972
973 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
974 if (!udc->ep0_reset_config)
975 irq_en |= UDC_EPN_RX_IE
976 | UDC_EPN_TX_IE;
f35ae634 977 omap_writew(irq_en, UDC_IRQ_EN);
1da177e4
LT		 978 }
979
313980c9
DB		 980 /* STATUS for zero length DATA stages is
981 * always an IN ... even for IN transfers,
dc0d5c1e 982 * a weird case which seem to stall OMAP.
313980c9 983 */
f35ae634
TL		 984 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
985 omap_writew(UDC_CLR_EP, UDC_CTRL);
986 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
987 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 988
989 /* cleanup */
990 udc->ep0_pending = 0;
991 done(ep, req, 0);
313980c9 992 req = NULL;
1da177e4
LT		 993
994 /* non-empty DATA stage */
995 } else if (is_in) {
f35ae634 996 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 997 } else {
998 if (udc->ep0_setup)
999 goto irq_wait;
f35ae634 1000 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1da177e4
LT		 1001 }
1002 } else {
1003 is_in = ep->bEndpointAddress & USB_DIR_IN;
1004 if (!ep->has_dma)
1005 use_ep(ep, UDC_EP_SEL);
1006 /* if ISO: SOF IRQs must be enabled/disabled! */
1007 }
1008
1009 if (ep->has_dma)
1010 (is_in ? next_in_dma : next_out_dma)(ep, req);
1011 else if (req) {
1012 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
313980c9 1013 req = NULL;
1da177e4
LT		 1014 deselect_ep();
1015 if (!is_in) {
f35ae634 1016 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1017 ep->ackwait = 1 + ep->double_buf;
1018 }
1019 /* IN: 6 wait states before it'll tx */
1020 }
1021 }
1022
1023irq_wait:
1024 /* irq handler advances the queue */
313980c9 1025 if (req != NULL)
1da177e4
LT		 1026 list_add_tail(&req->queue, &ep->queue);
1027 spin_unlock_irqrestore(&udc->lock, flags);
1028
1029 return 0;
1030}
1031
1032static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1033{
1034 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1035 struct omap_req *req;
1036 unsigned long flags;
1037
1038 if (!_ep || !_req)
1039 return -EINVAL;
1040
1041 spin_lock_irqsave(&ep->udc->lock, flags);
1042
1043 /* make sure it's actually queued on this endpoint */
1044 list_for_each_entry (req, &ep->queue, queue) {
1045 if (&req->req == _req)
1046 break;
1047 }
1048 if (&req->req != _req) {
1049 spin_unlock_irqrestore(&ep->udc->lock, flags);
1050 return -EINVAL;
1051 }
1052
1053 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1054 int channel = ep->dma_channel;
1055
1056 /* releasing the channel cancels the request,
1057 * reclaiming the channel restarts the queue
1058 */
1059 dma_channel_release(ep);
1060 dma_channel_claim(ep, channel);
e6a6e472 1061 } else
1da177e4
LT		 1062 done(ep, req, -ECONNRESET);
1063 spin_unlock_irqrestore(&ep->udc->lock, flags);
1064 return 0;
1065}
1066
1067/*-------------------------------------------------------------------------*/
1068
1069static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1070{
1071 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1072 unsigned long flags;
1073 int status = -EOPNOTSUPP;
1074
1075 spin_lock_irqsave(&ep->udc->lock, flags);
1076
1077 /* just use protocol stalls for ep0; real halts are annoying */
1078 if (ep->bEndpointAddress == 0) {
1079 if (!ep->udc->ep0_pending)
1080 status = -EINVAL;
1081 else if (value) {
1082 if (ep->udc->ep0_set_config) {
b6c63937 1083 WARNING("error changing config?\n");
f35ae634 1084 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1085 }
f35ae634 1086 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1087 ep->udc->ep0_pending = 0;
1088 status = 0;
1089 } else /* NOP */
1090 status = 0;
1091
1092 /* otherwise, all active non-ISO endpoints can halt */
f8bdae06 1093 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1da177e4
LT		 1094
1095 /* IN endpoints must already be idle */
1096 if ((ep->bEndpointAddress & USB_DIR_IN)
e6a6e472 1097 && !list_empty(&ep->queue)) {
1da177e4
LT		 1098 status = -EAGAIN;
1099 goto done;
1100 }
1101
1102 if (value) {
1103 int channel;
1104
1105 if (use_dma && ep->dma_channel
1106 && !list_empty(&ep->queue)) {
1107 channel = ep->dma_channel;
1108 dma_channel_release(ep);
1109 } else
1110 channel = 0;
1111
1112 use_ep(ep, UDC_EP_SEL);
f35ae634
TL		 1113 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1114 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1115 status = 0;
1116 } else
1117 status = -EAGAIN;
1118 deselect_ep();
1119
1120 if (channel)
1121 dma_channel_claim(ep, channel);
1122 } else {
1123 use_ep(ep, 0);
f35ae634 1124 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1da177e4
LT		 1125 ep->ackwait = 0;
1126 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 1127 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1128 ep->ackwait = 1 + ep->double_buf;
1129 }
1130 }
1131 }
1132done:
1133 VDBG("%s %s halt stat %d\n", ep->ep.name,
1134 value ? "set" : "clear", status);
1135
1136 spin_unlock_irqrestore(&ep->udc->lock, flags);
1137 return status;
1138}
1139
1140static struct usb_ep_ops omap_ep_ops = {
1141 .enable = omap_ep_enable,
1142 .disable = omap_ep_disable,
1143
1144 .alloc_request = omap_alloc_request,
1145 .free_request = omap_free_request,
1146
1da177e4
LT		 1147 .queue = omap_ep_queue,
1148 .dequeue = omap_ep_dequeue,
1149
1150 .set_halt = omap_ep_set_halt,
1151 // fifo_status ... report bytes in fifo
1152 // fifo_flush ... flush fifo
1153};
1154
1155/*-------------------------------------------------------------------------*/
1156
1157static int omap_get_frame(struct usb_gadget *gadget)
1158{
f35ae634 1159 u16 sof = omap_readw(UDC_SOF);
1da177e4
LT		 1160 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1161}
1162
1163static int omap_wakeup(struct usb_gadget *gadget)
1164{
1165 struct omap_udc *udc;
1166 unsigned long flags;
1167 int retval = -EHOSTUNREACH;
1168
1169 udc = container_of(gadget, struct omap_udc, gadget);
1170
1171 spin_lock_irqsave(&udc->lock, flags);
1172 if (udc->devstat & UDC_SUS) {
1173 /* NOTE: OTG spec erratum says that OTG devices may
1174 * issue wakeups without host enable.
1175 */
1176 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1177 DBG("remote wakeup...\n");
f35ae634 1178 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1da177e4
LT		 1179 retval = 0;
1180 }
1181
1182 /* NOTE: non-OTG systems may use SRP TOO... */
1183 } else if (!(udc->devstat & UDC_ATT)) {
1184 if (udc->transceiver)
6e13c650 1185 retval = otg_start_srp(udc->transceiver->otg);
1da177e4
LT		 1186 }
1187 spin_unlock_irqrestore(&udc->lock, flags);
1188
1189 return retval;
1190}
1191
1192static int
1193omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1194{
1195 struct omap_udc *udc;
1196 unsigned long flags;
1197 u16 syscon1;
1198
1199 udc = container_of(gadget, struct omap_udc, gadget);
1200 spin_lock_irqsave(&udc->lock, flags);
f35ae634 1201 syscon1 = omap_readw(UDC_SYSCON1);
1da177e4
LT		 1202 if (is_selfpowered)
1203 syscon1 |= UDC_SELF_PWR;
1204 else
1205 syscon1 &= ~UDC_SELF_PWR;
f35ae634 1206 omap_writew(syscon1, UDC_SYSCON1);
1da177e4
LT		 1207 spin_unlock_irqrestore(&udc->lock, flags);
1208
1209 return 0;
1210}
1211
1212static int can_pullup(struct omap_udc *udc)
1213{
1214 return udc->driver && udc->softconnect && udc->vbus_active;
1215}
1216
1217static void pullup_enable(struct omap_udc *udc)
1218{
f35ae634
TL		 1219 u16 w;
1220
1221 w = omap_readw(UDC_SYSCON1);
1222 w |= UDC_PULLUP_EN;
1223 omap_writew(w, UDC_SYSCON1);
1224 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1225 u32 l;
1226
1227 l = omap_readl(OTG_CTRL);
1228 l |= OTG_BSESSVLD;
1229 omap_writel(l, OTG_CTRL);
1230 }
1231 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1da177e4
LT		 1232}
1233
1234static void pullup_disable(struct omap_udc *udc)
1235{
f35ae634
TL		 1236 u16 w;
1237
1238 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1239 u32 l;
1240
1241 l = omap_readl(OTG_CTRL);
1242 l &= ~OTG_BSESSVLD;
1243 omap_writel(l, OTG_CTRL);
1244 }
1245 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1246 w = omap_readw(UDC_SYSCON1);
1247 w &= ~UDC_PULLUP_EN;
1248 omap_writew(w, UDC_SYSCON1);
1da177e4
LT		 1249}
1250
e6a6e472
DB		 1251static struct omap_udc *udc;
1252
1253static void omap_udc_enable_clock(int enable)
1254{
1255 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1256 return;
1257
1258 if (enable) {
1259 clk_enable(udc->dc_clk);
1260 clk_enable(udc->hhc_clk);
1261 udelay(100);
1262 } else {
1263 clk_disable(udc->hhc_clk);
1264 clk_disable(udc->dc_clk);
1265 }
1266}
1267
1da177e4
LT		 1268/*
1269 * Called by whatever detects VBUS sessions: external transceiver
1270 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1271 */
1272static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1273{
1274 struct omap_udc *udc;
1275 unsigned long flags;
f35ae634 1276 u32 l;
1da177e4
LT		 1277
1278 udc = container_of(gadget, struct omap_udc, gadget);
1279 spin_lock_irqsave(&udc->lock, flags);
1280 VDBG("VBUS %s\n", is_active ? "on" : "off");
1281 udc->vbus_active = (is_active != 0);
1282 if (cpu_is_omap15xx()) {
1283 /* "software" detect, ignored if !VBUS_MODE_1510 */
f35ae634 1284 l = omap_readl(FUNC_MUX_CTRL_0);
1da177e4 1285 if (is_active)
f35ae634 1286 l |= VBUS_CTRL_1510;
1da177e4 1287 else
f35ae634
TL		 1288 l &= ~VBUS_CTRL_1510;
1289 omap_writel(l, FUNC_MUX_CTRL_0);
1da177e4 1290 }
e6a6e472
DB		 1291 if (udc->dc_clk != NULL && is_active) {
1292 if (!udc->clk_requested) {
1293 omap_udc_enable_clock(1);
1294 udc->clk_requested = 1;
1295 }
1296 }
1da177e4
LT		 1297 if (can_pullup(udc))
1298 pullup_enable(udc);
1299 else
1300 pullup_disable(udc);
e6a6e472
DB		 1301 if (udc->dc_clk != NULL && !is_active) {
1302 if (udc->clk_requested) {
1303 omap_udc_enable_clock(0);
1304 udc->clk_requested = 0;
1305 }
1306 }
1da177e4
LT		 1307 spin_unlock_irqrestore(&udc->lock, flags);
1308 return 0;
1309}
1310
1311static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1312{
1313 struct omap_udc *udc;
1314
1315 udc = container_of(gadget, struct omap_udc, gadget);
1316 if (udc->transceiver)
b96d3b08 1317 return usb_phy_set_power(udc->transceiver, mA);
1da177e4
LT		 1318 return -EOPNOTSUPP;
1319}
1320
1321static int omap_pullup(struct usb_gadget *gadget, int is_on)
1322{
1323 struct omap_udc *udc;
1324 unsigned long flags;
1325
1326 udc = container_of(gadget, struct omap_udc, gadget);
1327 spin_lock_irqsave(&udc->lock, flags);
1328 udc->softconnect = (is_on != 0);
1329 if (can_pullup(udc))
1330 pullup_enable(udc);
1331 else
1332 pullup_disable(udc);
1333 spin_unlock_irqrestore(&udc->lock, flags);
1334 return 0;
1335}
1336
0f91349b
SAS		 1337static int omap_udc_start(struct usb_gadget_driver *driver,
1338 int (*bind)(struct usb_gadget *));
1339static int omap_udc_stop(struct usb_gadget_driver *driver);
1340
1da177e4
LT		 1341static struct usb_gadget_ops omap_gadget_ops = {
1342 .get_frame = omap_get_frame,
1343 .wakeup = omap_wakeup,
1344 .set_selfpowered = omap_set_selfpowered,
1345 .vbus_session = omap_vbus_session,
1346 .vbus_draw = omap_vbus_draw,
1347 .pullup = omap_pullup,
0f91349b
SAS		 1348 .start = omap_udc_start,
1349 .stop = omap_udc_stop,
1da177e4
LT		 1350};
1351
1352/*-------------------------------------------------------------------------*/
1353
1354/* dequeue ALL requests; caller holds udc->lock */
1355static void nuke(struct omap_ep *ep, int status)
1356{
1357 struct omap_req *req;
1358
1359 ep->stopped = 1;
1360
1361 if (use_dma && ep->dma_channel)
1362 dma_channel_release(ep);
1363
1364 use_ep(ep, 0);
f35ae634 1365 omap_writew(UDC_CLR_EP, UDC_CTRL);
1da177e4 1366 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
f35ae634 1367 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1368
1369 while (!list_empty(&ep->queue)) {
1370 req = list_entry(ep->queue.next, struct omap_req, queue);
1371 done(ep, req, status);
1372 }
1373}
1374
1375/* caller holds udc->lock */
1376static void udc_quiesce(struct omap_udc *udc)
1377{
1378 struct omap_ep *ep;
1379
1380 udc->gadget.speed = USB_SPEED_UNKNOWN;
1381 nuke(&udc->ep[0], -ESHUTDOWN);
1382 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1383 nuke(ep, -ESHUTDOWN);
1384}
1385
1386/*-------------------------------------------------------------------------*/
1387
1388static void update_otg(struct omap_udc *udc)
1389{
1390 u16 devstat;
1391
9cfbba73 1392 if (!gadget_is_otg(&udc->gadget))
1da177e4
LT		 1393 return;
1394
f35ae634
TL		 1395 if (omap_readl(OTG_CTRL) & OTG_ID)
1396 devstat = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 1397 else
1398 devstat = 0;
1399
1400 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1401 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1402 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1403
1404 /* Enable HNP early, avoiding races on suspend irq path.
1405 * ASSUMES OTG state machine B_BUS_REQ input is true.
1406 */
f35ae634
TL		 1407 if (udc->gadget.b_hnp_enable) {
1408 u32 l;
1409
1410 l = omap_readl(OTG_CTRL);
1411 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1412 l &= ~OTG_PULLUP;
1413 omap_writel(l, OTG_CTRL);
1414 }
1da177e4
LT		 1415}
1416
1417static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1418{
1419 struct omap_ep *ep0 = &udc->ep[0];
313980c9 1420 struct omap_req *req = NULL;
1da177e4
LT		 1421
1422 ep0->irqs++;
1423
1424 /* Clear any pending requests and then scrub any rx/tx state
1425 * before starting to handle the SETUP request.
1426 */
1427 if (irq_src & UDC_SETUP) {
1428 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1429
1430 nuke(ep0, 0);
1431 if (ack) {
f35ae634 1432 omap_writew(ack, UDC_IRQ_SRC);
1da177e4
LT		 1433 irq_src = UDC_SETUP;
1434 }
1435 }
1436
e6a6e472 1437 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1da177e4
LT		 1438 * This driver uses only uses protocol stalls (ep0 never halts),
1439 * and if we got this far the gadget driver already had a
1440 * chance to stall. Tries to be forgiving of host oddities.
1441 *
1442 * NOTE: the last chance gadget drivers have to stall control
1443 * requests is during their request completion callback.
1444 */
1445 if (!list_empty(&ep0->queue))
1446 req = container_of(ep0->queue.next, struct omap_req, queue);
1447
1448 /* IN == TX to host */
1449 if (irq_src & UDC_EP0_TX) {
1450 int stat;
1451
f35ae634
TL		 1452 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1453 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1454 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1455 if (stat & UDC_ACK) {
1456 if (udc->ep0_in) {
1457 /* write next IN packet from response,
1458 * or set up the status stage.
1459 */
1460 if (req)
1461 stat = write_fifo(ep0, req);
f35ae634 1462 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1463 if (!req && udc->ep0_pending) {
f35ae634
TL		 1464 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1465 omap_writew(UDC_CLR_EP, UDC_CTRL);
1466 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1467 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1468 udc->ep0_pending = 0;
1469 } /* else: 6 wait states before it'll tx */
1470 } else {
1471 /* ack status stage of OUT transfer */
f35ae634 1472 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1473 if (req)
1474 done(ep0, req, 0);
1475 }
313980c9 1476 req = NULL;
1da177e4 1477 } else if (stat & UDC_STALL) {
f35ae634
TL		 1478 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1479 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1480 } else {
f35ae634 1481 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1482 }
1483 }
1484
1485 /* OUT == RX from host */
1486 if (irq_src & UDC_EP0_RX) {
1487 int stat;
1488
f35ae634
TL		 1489 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1490 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1491 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1492 if (stat & UDC_ACK) {
1493 if (!udc->ep0_in) {
1494 stat = 0;
1495 /* read next OUT packet of request, maybe
1496 * reactiviting the fifo; stall on errors.
1497 */
1498 if (!req || (stat = read_fifo(ep0, req)) < 0) {
f35ae634 1499 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1500 udc->ep0_pending = 0;
1501 stat = 0;
1502 } else if (stat == 0)
f35ae634
TL		 1503 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1504 omap_writew(0, UDC_EP_NUM);
e6a6e472 1505
1da177e4
LT		 1506 /* activate status stage */
1507 if (stat == 1) {
1508 done(ep0, req, 0);
1509 /* that may have STALLed ep0... */
f35ae634
TL		 1510 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1511 UDC_EP_NUM);
1512 omap_writew(UDC_CLR_EP, UDC_CTRL);
1513 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1514 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1515 udc->ep0_pending = 0;
1516 }
1517 } else {
1518 /* ack status stage of IN transfer */
f35ae634 1519 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1520 if (req)
1521 done(ep0, req, 0);
1522 }
1523 } else if (stat & UDC_STALL) {
f35ae634
TL		 1524 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1525 omap_writew(0, UDC_EP_NUM);
1da177e4 1526 } else {
f35ae634 1527 omap_writew(0, UDC_EP_NUM);
1da177e4
LT		 1528 }
1529 }
1530
1531 /* SETUP starts all control transfers */
1532 if (irq_src & UDC_SETUP) {
1533 union u {
1534 u16 word[4];
1535 struct usb_ctrlrequest r;
1536 } u;
1537 int status = -EINVAL;
1538 struct omap_ep *ep;
1539
1540 /* read the (latest) SETUP message */
1541 do {
f35ae634 1542 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1da177e4 1543 /* two bytes at a time */
f35ae634
TL		 1544 u.word[0] = omap_readw(UDC_DATA);
1545 u.word[1] = omap_readw(UDC_DATA);
1546 u.word[2] = omap_readw(UDC_DATA);
1547 u.word[3] = omap_readw(UDC_DATA);
1548 omap_writew(0, UDC_EP_NUM);
1549 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1da177e4 1550
01ee7d70
DB		 1551#define w_value le16_to_cpu(u.r.wValue)
1552#define w_index le16_to_cpu(u.r.wIndex)
1553#define w_length le16_to_cpu(u.r.wLength)
65111084 1554
1da177e4
LT		 1555 /* Delegate almost all control requests to the gadget driver,
1556 * except for a handful of ch9 status/feature requests that
1557 * hardware doesn't autodecode _and_ the gadget API hides.
1558 */
1559 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1560 udc->ep0_set_config = 0;
1561 udc->ep0_pending = 1;
1562 ep0->stopped = 0;
1563 ep0->ackwait = 0;
1564 switch (u.r.bRequest) {
1565 case USB_REQ_SET_CONFIGURATION:
1566 /* udc needs to know when ep != 0 is valid */
1567 if (u.r.bRequestType != USB_RECIP_DEVICE)
1568 goto delegate;
65111084 1569 if (w_length != 0)
1da177e4
LT		 1570 goto do_stall;
1571 udc->ep0_set_config = 1;
65111084
DB		 1572 udc->ep0_reset_config = (w_value == 0);
1573 VDBG("set config %d\n", w_value);
1da177e4
LT		 1574
1575 /* update udc NOW since gadget driver may start
1576 * queueing requests immediately; clear config
1577 * later if it fails the request.
1578 */
1579 if (udc->ep0_reset_config)
f35ae634 1580 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1581 else
f35ae634 1582 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1da177e4
LT		 1583 update_otg(udc);
1584 goto delegate;
1585 case USB_REQ_CLEAR_FEATURE:
1586 /* clear endpoint halt */
1587 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1588 goto delegate;
65111084
DB		 1589 if (w_value != USB_ENDPOINT_HALT
1590 || w_length != 0)
1da177e4 1591 goto do_stall;
65111084 1592 ep = &udc->ep[w_index & 0xf];
1da177e4 1593 if (ep != ep0) {
65111084 1594 if (w_index & USB_DIR_IN)
1da177e4
LT		 1595 ep += 16;
1596 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
f8bdae06 1597 || !ep->ep.desc)
1da177e4
LT		 1598 goto do_stall;
1599 use_ep(ep, 0);
f35ae634 1600 omap_writew(udc->clr_halt, UDC_CTRL);
1da177e4
LT		 1601 ep->ackwait = 0;
1602 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
f35ae634 1603 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1604 ep->ackwait = 1 + ep->double_buf;
1605 }
313980c9
DB		 1606 /* NOTE: assumes the host behaves sanely,
1607 * only clearing real halts. Else we may
1608 * need to kill pending transfers and then
1609 * restart the queue... very messy for DMA!
1610 */
1da177e4
LT		 1611 }
1612 VDBG("%s halt cleared by host\n", ep->name);
1613 goto ep0out_status_stage;
1614 case USB_REQ_SET_FEATURE:
1615 /* set endpoint halt */
1616 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1617 goto delegate;
65111084
DB		 1618 if (w_value != USB_ENDPOINT_HALT
1619 || w_length != 0)
1da177e4 1620 goto do_stall;
65111084
DB		 1621 ep = &udc->ep[w_index & 0xf];
1622 if (w_index & USB_DIR_IN)
1da177e4
LT		 1623 ep += 16;
1624 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
f8bdae06 1625 || ep == ep0 || !ep->ep.desc)
1da177e4
LT		 1626 goto do_stall;
1627 if (use_dma && ep->has_dma) {
1628 /* this has rude side-effects (aborts) and
1629 * can't really work if DMA-IN is active
1630 */
1631 DBG("%s host set_halt, NYET \n", ep->name);
1632 goto do_stall;
1633 }
1634 use_ep(ep, 0);
1635 /* can't halt if fifo isn't empty... */
f35ae634
TL		 1636 omap_writew(UDC_CLR_EP, UDC_CTRL);
1637 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 1638 VDBG("%s halted by host\n", ep->name);
1639ep0out_status_stage:
1640 status = 0;
f35ae634
TL		 1641 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1642 omap_writew(UDC_CLR_EP, UDC_CTRL);
1643 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1644 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1645 udc->ep0_pending = 0;
1646 break;
1647 case USB_REQ_GET_STATUS:
8a3c1f57
DB		 1648 /* USB_ENDPOINT_HALT status? */
1649 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1650 goto intf_status;
1651
1652 /* ep0 never stalls */
1653 if (!(w_index & 0xf))
1654 goto zero_status;
1655
1656 /* only active endpoints count */
1657 ep = &udc->ep[w_index & 0xf];
1658 if (w_index & USB_DIR_IN)
1659 ep += 16;
f8bdae06 1660 if (!ep->ep.desc)
8a3c1f57
DB		 1661 goto do_stall;
1662
1663 /* iso never stalls */
1664 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1665 goto zero_status;
1666
1667 /* FIXME don't assume non-halted endpoints!! */
1668 ERR("%s status, can't report\n", ep->ep.name);
1669 goto do_stall;
1670
1671intf_status:
1da177e4
LT		 1672 /* return interface status. if we were pedantic,
1673 * we'd detect non-existent interfaces, and stall.
1674 */
1675 if (u.r.bRequestType
1676 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1677 goto delegate;
8a3c1f57
DB		 1678
1679zero_status:
1da177e4 1680 /* return two zero bytes */
f35ae634
TL		 1681 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1682 omap_writew(0, UDC_DATA);
1683 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1684 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1da177e4 1685 status = 0;
65111084 1686 VDBG("GET_STATUS, interface %d\n", w_index);
1da177e4
LT		 1687 /* next, status stage */
1688 break;
1689 default:
1690delegate:
1691 /* activate the ep0out fifo right away */
65111084 1692 if (!udc->ep0_in && w_length) {
f35ae634
TL		 1693 omap_writew(0, UDC_EP_NUM);
1694 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1695 }
1696
1697 /* gadget drivers see class/vendor specific requests,
1698 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1699 * and more
1700 */
1701 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1702 u.r.bRequestType, u.r.bRequest,
65111084
DB		 1703 w_value, w_index, w_length);
1704
1705#undef w_value
1706#undef w_index
1707#undef w_length
1da177e4
LT		 1708
1709 /* The gadget driver may return an error here,
1710 * causing an immediate protocol stall.
1711 *
1712 * Else it must issue a response, either queueing a
1713 * response buffer for the DATA stage, or halting ep0
1714 * (causing a protocol stall, not a real halt). A
1715 * zero length buffer means no DATA stage.
1716 *
1717 * It's fine to issue that response after the setup()
1718 * call returns, and this IRQ was handled.
1719 */
1720 udc->ep0_setup = 1;
1721 spin_unlock(&udc->lock);
1722 status = udc->driver->setup (&udc->gadget, &u.r);
1723 spin_lock(&udc->lock);
1724 udc->ep0_setup = 0;
1725 }
1726
1727 if (status < 0) {
1728do_stall:
1729 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1730 u.r.bRequestType, u.r.bRequest, status);
1731 if (udc->ep0_set_config) {
1732 if (udc->ep0_reset_config)
b6c63937 1733 WARNING("error resetting config?\n");
1da177e4 1734 else
f35ae634 1735 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1da177e4 1736 }
f35ae634 1737 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1da177e4
LT		 1738 udc->ep0_pending = 0;
1739 }
1740 }
1741}
1742
1743/*-------------------------------------------------------------------------*/
1744
1745#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1746
1747static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1748{
1749 u16 devstat, change;
1750
f35ae634 1751 devstat = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 1752 change = devstat ^ udc->devstat;
1753 udc->devstat = devstat;
1754
1755 if (change & (UDC_USB_RESET|UDC_ATT)) {
1756 udc_quiesce(udc);
1757
1758 if (change & UDC_ATT) {
1759 /* driver for any external transceiver will
1760 * have called omap_vbus_session() already
1761 */
1762 if (devstat & UDC_ATT) {
1763 udc->gadget.speed = USB_SPEED_FULL;
1764 VDBG("connect\n");
1765 if (!udc->transceiver)
1766 pullup_enable(udc);
1767 // if (driver->connect) call it
1768 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1769 udc->gadget.speed = USB_SPEED_UNKNOWN;
1770 if (!udc->transceiver)
1771 pullup_disable(udc);
1772 DBG("disconnect, gadget %s\n",
1773 udc->driver->driver.name);
1774 if (udc->driver->disconnect) {
1775 spin_unlock(&udc->lock);
1776 udc->driver->disconnect(&udc->gadget);
1777 spin_lock(&udc->lock);
1778 }
1779 }
1780 change &= ~UDC_ATT;
1781 }
1782
1783 if (change & UDC_USB_RESET) {
1784 if (devstat & UDC_USB_RESET) {
1785 VDBG("RESET=1\n");
1786 } else {
1787 udc->gadget.speed = USB_SPEED_FULL;
1788 INFO("USB reset done, gadget %s\n",
1789 udc->driver->driver.name);
1790 /* ep0 traffic is legal from now on */
f35ae634
TL		 1791 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1792 UDC_IRQ_EN);
1da177e4
LT		 1793 }
1794 change &= ~UDC_USB_RESET;
1795 }
1796 }
1797 if (change & UDC_SUS) {
1798 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1799 // FIXME tell isp1301 to suspend/resume (?)
1800 if (devstat & UDC_SUS) {
1801 VDBG("suspend\n");
1802 update_otg(udc);
1803 /* HNP could be under way already */
1804 if (udc->gadget.speed == USB_SPEED_FULL
1805 && udc->driver->suspend) {
1806 spin_unlock(&udc->lock);
1807 udc->driver->suspend(&udc->gadget);
1808 spin_lock(&udc->lock);
1809 }
4e67185a 1810 if (udc->transceiver)
b96d3b08
HK		 1811 usb_phy_set_suspend(
1812 udc->transceiver, 1);
1da177e4
LT		 1813 } else {
1814 VDBG("resume\n");
4e67185a 1815 if (udc->transceiver)
b96d3b08
HK		 1816 usb_phy_set_suspend(
1817 udc->transceiver, 0);
1da177e4
LT		 1818 if (udc->gadget.speed == USB_SPEED_FULL
1819 && udc->driver->resume) {
1820 spin_unlock(&udc->lock);
1821 udc->driver->resume(&udc->gadget);
1822 spin_lock(&udc->lock);
1823 }
1824 }
1825 }
1826 change &= ~UDC_SUS;
1827 }
1828 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1829 update_otg(udc);
1830 change &= ~OTG_FLAGS;
1831 }
1832
1833 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1834 if (change)
1835 VDBG("devstat %03x, ignore change %03x\n",
1836 devstat, change);
1837
f35ae634 1838 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1da177e4
LT		 1839}
1840
7d12e780 1841static irqreturn_t omap_udc_irq(int irq, void *_udc)
1da177e4
LT		 1842{
1843 struct omap_udc *udc = _udc;
1844 u16 irq_src;
1845 irqreturn_t status = IRQ_NONE;
1846 unsigned long flags;
1847
1848 spin_lock_irqsave(&udc->lock, flags);
f35ae634 1849 irq_src = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 1850
1851 /* Device state change (usb ch9 stuff) */
1852 if (irq_src & UDC_DS_CHG) {
1853 devstate_irq(_udc, irq_src);
1854 status = IRQ_HANDLED;
1855 irq_src &= ~UDC_DS_CHG;
1856 }
1857
1858 /* EP0 control transfers */
1859 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1860 ep0_irq(_udc, irq_src);
1861 status = IRQ_HANDLED;
1862 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1863 }
1864
1865 /* DMA transfer completion */
1866 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1867 dma_irq(_udc, irq_src);
1868 status = IRQ_HANDLED;
1869 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1870 }
1871
f35ae634 1872 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1da177e4
LT		 1873 if (irq_src)
1874 DBG("udc_irq, unhandled %03x\n", irq_src);
1875 spin_unlock_irqrestore(&udc->lock, flags);
1876
1877 return status;
1878}
1879
1880/* workaround for seemingly-lost IRQs for RX ACKs... */
1881#define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1882#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1883
1884static void pio_out_timer(unsigned long _ep)
1885{
1886 struct omap_ep *ep = (void *) _ep;
1887 unsigned long flags;
1888 u16 stat_flg;
1889
1890 spin_lock_irqsave(&ep->udc->lock, flags);
1891 if (!list_empty(&ep->queue) && ep->ackwait) {
e6a6e472 1892 use_ep(ep, UDC_EP_SEL);
f35ae634 1893 stat_flg = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 1894
1895 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1896 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1897 struct omap_req *req;
1898
1899 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1900 req = container_of(ep->queue.next,
1901 struct omap_req, queue);
1da177e4 1902 (void) read_fifo(ep, req);
f35ae634
TL		 1903 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1904 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4 1905 ep->ackwait = 1 + ep->double_buf;
e6a6e472
DB		 1906 } else
1907 deselect_ep();
1da177e4
LT		 1908 }
1909 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1910 spin_unlock_irqrestore(&ep->udc->lock, flags);
1911}
1912
7d12e780 1913static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1da177e4
LT		 1914{
1915 u16 epn_stat, irq_src;
1916 irqreturn_t status = IRQ_NONE;
1917 struct omap_ep *ep;
1918 int epnum;
1919 struct omap_udc *udc = _dev;
1920 struct omap_req *req;
1921 unsigned long flags;
1922
1923 spin_lock_irqsave(&udc->lock, flags);
f35ae634
TL		 1924 epn_stat = omap_readw(UDC_EPN_STAT);
1925 irq_src = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 1926
1927 /* handle OUT first, to avoid some wasteful NAKs */
1928 if (irq_src & UDC_EPN_RX) {
1929 epnum = (epn_stat >> 8) & 0x0f;
f35ae634 1930 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1da177e4
LT		 1931 status = IRQ_HANDLED;
1932 ep = &udc->ep[epnum];
1933 ep->irqs++;
1934
f35ae634 1935 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1da177e4 1936 ep->fnf = 0;
f35ae634 1937 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1da177e4
LT		 1938 ep->ackwait--;
1939 if (!list_empty(&ep->queue)) {
1940 int stat;
1941 req = container_of(ep->queue.next,
1942 struct omap_req, queue);
1943 stat = read_fifo(ep, req);
1944 if (!ep->double_buf)
1945 ep->fnf = 1;
1946 }
1947 }
1948 /* min 6 clock delay before clearing EP_SEL ... */
f35ae634
TL		 1949 epn_stat = omap_readw(UDC_EPN_STAT);
1950 epn_stat = omap_readw(UDC_EPN_STAT);
1951 omap_writew(epnum, UDC_EP_NUM);
1da177e4
LT		 1952
1953 /* enabling fifo _after_ clearing ACK, contrary to docs,
1954 * reduces lossage; timer still needed though (sigh).
1955 */
1956 if (ep->fnf) {
f35ae634 1957 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1da177e4
LT		 1958 ep->ackwait = 1 + ep->double_buf;
1959 }
1960 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1961 }
1962
1963 /* then IN transfers */
1964 else if (irq_src & UDC_EPN_TX) {
1965 epnum = epn_stat & 0x0f;
f35ae634 1966 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1da177e4
LT		 1967 status = IRQ_HANDLED;
1968 ep = &udc->ep[16 + epnum];
1969 ep->irqs++;
1970
f35ae634
TL		 1971 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1972 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1da177e4
LT		 1973 ep->ackwait = 0;
1974 if (!list_empty(&ep->queue)) {
1975 req = container_of(ep->queue.next,
1976 struct omap_req, queue);
1977 (void) write_fifo(ep, req);
1978 }
1979 }
1980 /* min 6 clock delay before clearing EP_SEL ... */
f35ae634
TL		 1981 epn_stat = omap_readw(UDC_EPN_STAT);
1982 epn_stat = omap_readw(UDC_EPN_STAT);
1983 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1da177e4
LT		 1984 /* then 6 clocks before it'd tx */
1985 }
1986
1987 spin_unlock_irqrestore(&udc->lock, flags);
1988 return status;
1989}
1990
1991#ifdef USE_ISO
7d12e780 1992static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1da177e4
LT		 1993{
1994 struct omap_udc *udc = _dev;
1995 struct omap_ep *ep;
1996 int pending = 0;
1997 unsigned long flags;
1998
1999 spin_lock_irqsave(&udc->lock, flags);
2000
2001 /* handle all non-DMA ISO transfers */
2002 list_for_each_entry (ep, &udc->iso, iso) {
2003 u16 stat;
2004 struct omap_req *req;
2005
2006 if (ep->has_dma || list_empty(&ep->queue))
2007 continue;
2008 req = list_entry(ep->queue.next, struct omap_req, queue);
2009
2010 use_ep(ep, UDC_EP_SEL);
f35ae634 2011 stat = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 2012
2013 /* NOTE: like the other controller drivers, this isn't
2014 * currently reporting lost or damaged frames.
2015 */
2016 if (ep->bEndpointAddress & USB_DIR_IN) {
2017 if (stat & UDC_MISS_IN)
2018 /* done(ep, req, -EPROTO) */;
2019 else
2020 write_fifo(ep, req);
2021 } else {
2022 int status = 0;
2023
2024 if (stat & UDC_NO_RXPACKET)
2025 status = -EREMOTEIO;
2026 else if (stat & UDC_ISO_ERR)
2027 status = -EILSEQ;
2028 else if (stat & UDC_DATA_FLUSH)
2029 status = -ENOSR;
2030
2031 if (status)
2032 /* done(ep, req, status) */;
2033 else
2034 read_fifo(ep, req);
2035 }
2036 deselect_ep();
2037 /* 6 wait states before next EP */
2038
2039 ep->irqs++;
2040 if (!list_empty(&ep->queue))
2041 pending = 1;
2042 }
f35ae634
TL		 2043 if (!pending) {
2044 u16 w;
2045
2046 w = omap_readw(UDC_IRQ_EN);
2047 w &= ~UDC_SOF_IE;
2048 omap_writew(w, UDC_IRQ_EN);
2049 }
2050 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
1da177e4
LT		 2051
2052 spin_unlock_irqrestore(&udc->lock, flags);
2053 return IRQ_HANDLED;
2054}
2055#endif
2056
2057/*-------------------------------------------------------------------------*/
2058
8a3c1f57 2059static inline int machine_without_vbus_sense(void)
e6a6e472
DB		 2060{
2061 return (machine_is_omap_innovator()
2062 || machine_is_omap_osk()
e6a6e472 2063 || machine_is_sx1()
45f780a0 2064 || cpu_is_omap7xx() /* No known omap7xx boards with vbus sense */
e6a6e472
DB		 2065 );
2066}
1da177e4 2067
0f91349b 2068static int omap_udc_start(struct usb_gadget_driver *driver,
b0fca50f 2069 int (*bind)(struct usb_gadget *))
1da177e4
LT		 2070{
2071 int status = -ENODEV;
2072 struct omap_ep *ep;
2073 unsigned long flags;
2074
2075 /* basic sanity tests */
2076 if (!udc)
2077 return -ENODEV;
2078 if (!driver
2079 // FIXME if otg, check: driver->is_otg
7177aed4 2080 || driver->max_speed < USB_SPEED_FULL
b0fca50f 2081 || !bind || !driver->setup)
1da177e4
LT		 2082 return -EINVAL;
2083
2084 spin_lock_irqsave(&udc->lock, flags);
2085 if (udc->driver) {
2086 spin_unlock_irqrestore(&udc->lock, flags);
2087 return -EBUSY;
2088 }
2089
2090 /* reset state */
2091 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2092 ep->irqs = 0;
2093 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2094 continue;
2095 use_ep(ep, 0);
f35ae634 2096 omap_writew(UDC_SET_HALT, UDC_CTRL);
1da177e4
LT		 2097 }
2098 udc->ep0_pending = 0;
2099 udc->ep[0].irqs = 0;
2100 udc->softconnect = 1;
2101
2102 /* hook up the driver */
313980c9 2103 driver->driver.bus = NULL;
1da177e4
LT		 2104 udc->driver = driver;
2105 udc->gadget.dev.driver = &driver->driver;
2106 spin_unlock_irqrestore(&udc->lock, flags);
2107
e6a6e472
DB		 2108 if (udc->dc_clk != NULL)
2109 omap_udc_enable_clock(1);
2110
b0fca50f 2111 status = bind(&udc->gadget);
1da177e4
LT		 2112 if (status) {
2113 DBG("bind to %s --> %d\n", driver->driver.name, status);
313980c9
DB		 2114 udc->gadget.dev.driver = NULL;
2115 udc->driver = NULL;
1da177e4
LT		 2116 goto done;
2117 }
2118 DBG("bound to driver %s\n", driver->driver.name);
2119
f35ae634 2120 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
1da177e4
LT		 2121
2122 /* connect to bus through transceiver */
2123 if (udc->transceiver) {
6e13c650
HK		 2124 status = otg_set_peripheral(udc->transceiver->otg,
2125 &udc->gadget);
1da177e4
LT		 2126 if (status < 0) {
2127 ERR("can't bind to transceiver\n");
6bea476c
DB		 2128 if (driver->unbind) {
2129 driver->unbind (&udc->gadget);
2130 udc->gadget.dev.driver = NULL;
2131 udc->driver = NULL;
2132 }
1da177e4
LT		 2133 goto done;
2134 }
2135 } else {
2136 if (can_pullup(udc))
2137 pullup_enable (udc);
2138 else
2139 pullup_disable (udc);
2140 }
2141
2142 /* boards that don't have VBUS sensing can't autogate 48MHz;
2143 * can't enter deep sleep while a gadget driver is active.
2144 */
8a3c1f57 2145 if (machine_without_vbus_sense())
1da177e4
LT		 2146 omap_vbus_session(&udc->gadget, 1);
2147
2148done:
e6a6e472
DB		 2149 if (udc->dc_clk != NULL)
2150 omap_udc_enable_clock(0);
1da177e4
LT		 2151 return status;
2152}
1da177e4 2153
0f91349b 2154static int omap_udc_stop(struct usb_gadget_driver *driver)
1da177e4
LT		 2155{
2156 unsigned long flags;
2157 int status = -ENODEV;
2158
2159 if (!udc)
2160 return -ENODEV;
6bea476c 2161 if (!driver || driver != udc->driver || !driver->unbind)
1da177e4
LT		 2162 return -EINVAL;
2163
e6a6e472
DB		 2164 if (udc->dc_clk != NULL)
2165 omap_udc_enable_clock(1);
2166
8a3c1f57 2167 if (machine_without_vbus_sense())
1da177e4
LT		 2168 omap_vbus_session(&udc->gadget, 0);
2169
2170 if (udc->transceiver)
6e13c650 2171 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
1da177e4
LT		 2172 else
2173 pullup_disable(udc);
2174
2175 spin_lock_irqsave(&udc->lock, flags);
2176 udc_quiesce(udc);
2177 spin_unlock_irqrestore(&udc->lock, flags);
2178
2179 driver->unbind(&udc->gadget);
313980c9
DB		 2180 udc->gadget.dev.driver = NULL;
2181 udc->driver = NULL;
1da177e4 2182
e6a6e472
DB		 2183 if (udc->dc_clk != NULL)
2184 omap_udc_enable_clock(0);
1da177e4
LT		 2185 DBG("unregistered driver '%s'\n", driver->driver.name);
2186 return status;
2187}
1da177e4
LT		 2188
2189/*-------------------------------------------------------------------------*/
2190
2191#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2192
2193#include <linux/seq_file.h>
2194
2195static const char proc_filename[] = "driver/udc";
2196
2197#define FOURBITS "%s%s%s%s"
2198#define EIGHTBITS FOURBITS FOURBITS
2199
2200static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2201{
2202 u16 stat_flg;
2203 struct omap_req *req;
2204 char buf[20];
2205
2206 use_ep(ep, 0);
2207
2208 if (use_dma && ep->has_dma)
2209 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2210 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2211 ep->dma_channel - 1, ep->lch);
2212 else
2213 buf[0] = 0;
2214
f35ae634 2215 stat_flg = omap_readw(UDC_STAT_FLG);
1da177e4
LT		 2216 seq_printf(s,
2217 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2218 ep->name, buf,
2219 ep->double_buf ? "dbuf " : "",
2220 ({char *s; switch(ep->ackwait){
2221 case 0: s = ""; break;
2222 case 1: s = "(ackw) "; break;
2223 case 2: s = "(ackw2) "; break;
2224 default: s = "(?) "; break;
2225 } s;}),
2226 ep->irqs, stat_flg,
2227 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2228 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2229 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2230 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2231 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2232 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2233 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2234 (stat_flg & UDC_STALL) ? "STALL " : "",
2235 (stat_flg & UDC_NAK) ? "NAK " : "",
2236 (stat_flg & UDC_ACK) ? "ACK " : "",
2237 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2238 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2239 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2240
2241 if (list_empty (&ep->queue))
2242 seq_printf(s, "\t(queue empty)\n");
2243 else
2244 list_for_each_entry (req, &ep->queue, queue) {
2245 unsigned length = req->req.actual;
2246
2247 if (use_dma && buf[0]) {
2248 length += ((ep->bEndpointAddress & USB_DIR_IN)
2249 ? dma_src_len : dma_dest_len)
2250 (ep, req->req.dma + length);
2251 buf[0] = 0;
2252 }
2253 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2254 &req->req, length,
2255 req->req.length, req->req.buf);
2256 }
2257}
2258
2259static char *trx_mode(unsigned m, int enabled)
2260{
2261 switch (m) {
2262 case 0: return enabled ? "*6wire" : "unused";
2263 case 1: return "4wire";
2264 case 2: return "3wire";
e6a6e472 2265 case 3: return "6wire";
1da177e4
LT		 2266 default: return "unknown";
2267 }
2268}
2269
2270static int proc_otg_show(struct seq_file *s)
2271{
2272 u32 tmp;
4814ced5
PW		 2273 u32 trans = 0;
2274 char *ctrl_name = "(UNKNOWN)";
1da177e4 2275
e12cc345 2276 tmp = omap_readl(OTG_REV);
ae372571
TL		 2277 ctrl_name = "tranceiver_ctrl";
2278 trans = omap_readw(USB_TRANSCEIVER_CTRL);
e6a6e472
DB		 2279 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2280 tmp >> 4, tmp & 0xf, ctrl_name, trans);
f35ae634 2281 tmp = omap_readw(OTG_SYSCON_1);
1da177e4
LT		 2282 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2283 FOURBITS "\n", tmp,
2284 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2285 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
65111084 2286 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
1da177e4
LT		 2287 ? "internal"
2288 : trx_mode(USB0_TRX_MODE(tmp), 1),
2289 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2290 (tmp & HST_IDLE_EN) ? " !host" : "",
2291 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2292 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
f35ae634 2293 tmp = omap_readl(OTG_SYSCON_2);
1da177e4
LT		 2294 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2295 " b_ase_brst=%d hmc=%d\n", tmp,
2296 (tmp & OTG_EN) ? " otg_en" : "",
2297 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2298 // much more SRP stuff
2299 (tmp & SRP_DATA) ? " srp_data" : "",
2300 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2301 (tmp & OTG_PADEN) ? " otg_paden" : "",
2302 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2303 (tmp & UHOST_EN) ? " uhost_en" : "",
2304 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2305 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2306 B_ASE_BRST(tmp),
2307 OTG_HMC(tmp));
f35ae634 2308 tmp = omap_readl(OTG_CTRL);
1da177e4
LT		 2309 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2310 (tmp & OTG_ASESSVLD) ? " asess" : "",
2311 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2312 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2313 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2314 (tmp & OTG_ID) ? " id" : "",
2315 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2316 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2317 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2318 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2319 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2320 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2321 (tmp & OTG_PULLDOWN) ? " down" : "",
2322 (tmp & OTG_PULLUP) ? " up" : "",
2323 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2324 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2325 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2326 (tmp & OTG_PU_ID) ? " pu_id" : ""
2327 );
f35ae634 2328 tmp = omap_readw(OTG_IRQ_EN);
1da177e4 2329 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
f35ae634 2330 tmp = omap_readw(OTG_IRQ_SRC);
1da177e4 2331 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
f35ae634 2332 tmp = omap_readw(OTG_OUTCTRL);
1da177e4 2333 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
f35ae634 2334 tmp = omap_readw(OTG_TEST);
1da177e4 2335 seq_printf(s, "otg_test %04x" "\n", tmp);
313980c9 2336 return 0;
1da177e4
LT		 2337}
2338
2339static int proc_udc_show(struct seq_file *s, void *_)
2340{
2341 u32 tmp;
2342 struct omap_ep *ep;
2343 unsigned long flags;
2344
2345 spin_lock_irqsave(&udc->lock, flags);
2346
2347 seq_printf(s, "%s, version: " DRIVER_VERSION
2348#ifdef USE_ISO
2349 " (iso)"
2350#endif
2351 "%s\n",
2352 driver_desc,
2353 use_dma ? " (dma)" : "");
2354
f35ae634 2355 tmp = omap_readw(UDC_REV) & 0xff;
1da177e4
LT		 2356 seq_printf(s,
2357 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2358 "hmc %d, transceiver %s\n",
2359 tmp >> 4, tmp & 0xf,
2360 fifo_mode,
2361 udc->driver ? udc->driver->driver.name : "(none)",
2362 HMC,
e6a6e472
DB		 2363 udc->transceiver
2364 ? udc->transceiver->label
ae372571 2365 : (cpu_is_omap1710()
e6a6e472 2366 ? "external" : "(none)"));
ae372571
TL		 2367 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2368 omap_readw(ULPD_CLOCK_CTRL),
2369 omap_readw(ULPD_SOFT_REQ),
2370 omap_readw(ULPD_STATUS_REQ));
1da177e4
LT		 2371
2372 /* OTG controller registers */
2373 if (!cpu_is_omap15xx())
2374 proc_otg_show(s);
2375
f35ae634 2376 tmp = omap_readw(UDC_SYSCON1);
1da177e4
LT		 2377 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2378 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2379 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2380 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2381 (tmp & UDC_NAK_EN) ? " nak" : "",
2382 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2383 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2384 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2385 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2386 // syscon2 is write-only
2387
2388 /* UDC controller registers */
2389 if (!(tmp & UDC_PULLUP_EN)) {
2390 seq_printf(s, "(suspended)\n");
2391 spin_unlock_irqrestore(&udc->lock, flags);
2392 return 0;
2393 }
2394
f35ae634 2395 tmp = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 2396 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2397 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2398 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2399 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2400 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2401 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2402 (tmp & UDC_SUS) ? " SUS" : "",
2403 (tmp & UDC_CFG) ? " CFG" : "",
2404 (tmp & UDC_ADD) ? " ADD" : "",
2405 (tmp & UDC_DEF) ? " DEF" : "",
2406 (tmp & UDC_ATT) ? " ATT" : "");
f35ae634
TL		 2407 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2408 tmp = omap_readw(UDC_IRQ_EN);
1da177e4
LT		 2409 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2410 (tmp & UDC_SOF_IE) ? " sof" : "",
2411 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2412 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2413 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2414 (tmp & UDC_EP0_IE) ? " ep0" : "");
f35ae634 2415 tmp = omap_readw(UDC_IRQ_SRC);
1da177e4
LT		 2416 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2417 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2418 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2419 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
f35ae634 2420 (tmp & UDC_IRQ_SOF) ? " sof" : "",
1da177e4
LT		 2421 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2422 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2423 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2424 (tmp & UDC_SETUP) ? " setup" : "",
2425 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2426 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2427 if (use_dma) {
2428 unsigned i;
2429
f35ae634 2430 tmp = omap_readw(UDC_DMA_IRQ_EN);
1da177e4
LT		 2431 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2432 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2433 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2434 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2435
2436 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2437 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2438 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2439
2440 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2441 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2442 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2443
f35ae634 2444 tmp = omap_readw(UDC_RXDMA_CFG);
1da177e4
LT		 2445 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2446 if (tmp) {
2447 for (i = 0; i < 3; i++) {
2448 if ((tmp & (0x0f << (i * 4))) == 0)
2449 continue;
2450 seq_printf(s, "rxdma[%d] %04x\n", i,
f35ae634 2451 omap_readw(UDC_RXDMA(i + 1)));
1da177e4
LT		 2452 }
2453 }
f35ae634 2454 tmp = omap_readw(UDC_TXDMA_CFG);
1da177e4
LT		 2455 seq_printf(s, "txdma_cfg %04x\n", tmp);
2456 if (tmp) {
2457 for (i = 0; i < 3; i++) {
2458 if (!(tmp & (0x0f << (i * 4))))
2459 continue;
2460 seq_printf(s, "txdma[%d] %04x\n", i,
f35ae634 2461 omap_readw(UDC_TXDMA(i + 1)));
1da177e4
LT		 2462 }
2463 }
2464 }
2465
f35ae634 2466 tmp = omap_readw(UDC_DEVSTAT);
1da177e4
LT		 2467 if (tmp & UDC_ATT) {
2468 proc_ep_show(s, &udc->ep[0]);
2469 if (tmp & UDC_ADD) {
2470 list_for_each_entry (ep, &udc->gadget.ep_list,
2471 ep.ep_list) {
f8bdae06 2472 if (ep->ep.desc)
1da177e4
LT		 2473 proc_ep_show(s, ep);
2474 }
2475 }
2476 }
2477 spin_unlock_irqrestore(&udc->lock, flags);
2478 return 0;
2479}
2480
2481static int proc_udc_open(struct inode *inode, struct file *file)
2482{
313980c9 2483 return single_open(file, proc_udc_show, NULL);
1da177e4
LT		 2484}
2485
066202dd 2486static const struct file_operations proc_ops = {
cdefa185 2487 .owner = THIS_MODULE,
1da177e4
LT		 2488 .open = proc_udc_open,
2489 .read = seq_read,
2490 .llseek = seq_lseek,
2491 .release = single_release,
2492};
2493
2494static void create_proc_file(void)
2495{
cdefa185 2496 proc_create(proc_filename, 0, NULL, &proc_ops);
1da177e4
LT		 2497}
2498
2499static void remove_proc_file(void)
2500{
313980c9 2501 remove_proc_entry(proc_filename, NULL);
1da177e4
LT		 2502}
2503
2504#else
2505
2506static inline void create_proc_file(void) {}
2507static inline void remove_proc_file(void) {}
2508
2509#endif
2510
2511/*-------------------------------------------------------------------------*/
2512
2513/* Before this controller can enumerate, we need to pick an endpoint
2514 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2515 * buffer space among the endpoints we'll be operating.
65111084
DB		 2516 *
2517 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
f35ae634 2518 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
65111084 2519 * capability yet though.
1da177e4
LT		 2520 */
2521static unsigned __init
2522omap_ep_setup(char *name, u8 addr, u8 type,
2523 unsigned buf, unsigned maxp, int dbuf)
2524{
2525 struct omap_ep *ep;
2526 u16 epn_rxtx = 0;
2527
2528 /* OUT endpoints first, then IN */
2529 ep = &udc->ep[addr & 0xf];
2530 if (addr & USB_DIR_IN)
2531 ep += 16;
2532
2533 /* in case of ep init table bugs */
2534 BUG_ON(ep->name[0]);
2535
2536 /* chip setup ... bit values are same for IN, OUT */
2537 if (type == USB_ENDPOINT_XFER_ISOC) {
2538 switch (maxp) {
2539 case 8: epn_rxtx = 0 << 12; break;
2540 case 16: epn_rxtx = 1 << 12; break;
2541 case 32: epn_rxtx = 2 << 12; break;
2542 case 64: epn_rxtx = 3 << 12; break;
2543 case 128: epn_rxtx = 4 << 12; break;
2544 case 256: epn_rxtx = 5 << 12; break;
2545 case 512: epn_rxtx = 6 << 12; break;
2546 default: BUG();
2547 }
2548 epn_rxtx |= UDC_EPN_RX_ISO;
2549 dbuf = 1;
2550 } else {
2551 /* double-buffering "not supported" on 15xx,
e6a6e472
DB		 2552 * and ignored for PIO-IN on newer chips
2553 * (for more reliable behavior)
1da177e4 2554 */
ae372571 2555 if (!use_dma || cpu_is_omap15xx())
1da177e4
LT		 2556 dbuf = 0;
2557
2558 switch (maxp) {
2559 case 8: epn_rxtx = 0 << 12; break;
2560 case 16: epn_rxtx = 1 << 12; break;
2561 case 32: epn_rxtx = 2 << 12; break;
2562 case 64: epn_rxtx = 3 << 12; break;
2563 default: BUG();
2564 }
2565 if (dbuf && addr)
2566 epn_rxtx |= UDC_EPN_RX_DB;
2567 init_timer(&ep->timer);
2568 ep->timer.function = pio_out_timer;
2569 ep->timer.data = (unsigned long) ep;
2570 }
2571 if (addr)
2572 epn_rxtx |= UDC_EPN_RX_VALID;
2573 BUG_ON(buf & 0x07);
2574 epn_rxtx |= buf >> 3;
2575
2576 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2577 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2578
2579 if (addr & USB_DIR_IN)
f35ae634 2580 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
1da177e4 2581 else
f35ae634 2582 omap_writew(epn_rxtx, UDC_EP_RX(addr));
1da177e4
LT		 2583
2584 /* next endpoint's buffer starts after this one's */
2585 buf += maxp;
2586 if (dbuf)
2587 buf += maxp;
2588 BUG_ON(buf > 2048);
2589
2590 /* set up driver data structures */
2591 BUG_ON(strlen(name) >= sizeof ep->name);
2592 strlcpy(ep->name, name, sizeof ep->name);
2593 INIT_LIST_HEAD(&ep->queue);
2594 INIT_LIST_HEAD(&ep->iso);
2595 ep->bEndpointAddress = addr;
2596 ep->bmAttributes = type;
2597 ep->double_buf = dbuf;
e6a6e472 2598 ep->udc = udc;
1da177e4
LT		 2599
2600 ep->ep.name = ep->name;
2601 ep->ep.ops = &omap_ep_ops;
2602 ep->ep.maxpacket = ep->maxpacket = maxp;
2603 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2604
2605 return buf;
2606}
2607
2608static void omap_udc_release(struct device *dev)
2609{
2610 complete(udc->done);
2611 kfree (udc);
313980c9 2612 udc = NULL;
1da177e4
LT		 2613}
2614
2615static int __init
86753811 2616omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
1da177e4
LT		 2617{
2618 unsigned tmp, buf;
2619
2620 /* abolish any previous hardware state */
f35ae634
TL		 2621 omap_writew(0, UDC_SYSCON1);
2622 omap_writew(0, UDC_IRQ_EN);
2623 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2624 omap_writew(0, UDC_DMA_IRQ_EN);
2625 omap_writew(0, UDC_RXDMA_CFG);
2626 omap_writew(0, UDC_TXDMA_CFG);
1da177e4
LT		 2627
2628 /* UDC_PULLUP_EN gates the chip clock */
f35ae634 2629 // OTG_SYSCON_1 |= DEV_IDLE_EN;
1da177e4 2630
e94b1766 2631 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
1da177e4
LT		 2632 if (!udc)
2633 return -ENOMEM;
2634
1da177e4
LT		 2635 spin_lock_init (&udc->lock);
2636
2637 udc->gadget.ops = &omap_gadget_ops;
2638 udc->gadget.ep0 = &udc->ep[0].ep;
2639 INIT_LIST_HEAD(&udc->gadget.ep_list);
2640 INIT_LIST_HEAD(&udc->iso);
2641 udc->gadget.speed = USB_SPEED_UNKNOWN;
d327ab5b 2642 udc->gadget.max_speed = USB_SPEED_FULL;
1da177e4
LT		 2643 udc->gadget.name = driver_name;
2644
2645 device_initialize(&udc->gadget.dev);
0031a06e 2646 dev_set_name(&udc->gadget.dev, "gadget");
1da177e4
LT		 2647 udc->gadget.dev.release = omap_udc_release;
2648 udc->gadget.dev.parent = &odev->dev;
2649 if (use_dma)
2650 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2651
2652 udc->transceiver = xceiv;
2653
2654 /* ep0 is special; put it right after the SETUP buffer */
2655 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2656 8 /* after SETUP */, 64 /* maxpacket */, 0);
2657 list_del_init(&udc->ep[0].ep.ep_list);
2658
2659 /* initially disable all non-ep0 endpoints */
2660 for (tmp = 1; tmp < 15; tmp++) {
f35ae634
TL		 2661 omap_writew(0, UDC_EP_RX(tmp));
2662 omap_writew(0, UDC_EP_TX(tmp));
1da177e4
LT		 2663 }
2664
2665#define OMAP_BULK_EP(name,addr) \
2666 buf = omap_ep_setup(name "-bulk", addr, \
2667 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2668#define OMAP_INT_EP(name,addr, maxp) \
2669 buf = omap_ep_setup(name "-int", addr, \
2670 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2671#define OMAP_ISO_EP(name,addr, maxp) \
2672 buf = omap_ep_setup(name "-iso", addr, \
2673 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2674
2675 switch (fifo_mode) {
2676 case 0:
2677 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2678 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2679 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2680 break;
2681 case 1:
2682 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2683 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
313980c9
DB		 2684 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2685
1da177e4
LT		 2686 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2687 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
313980c9 2688 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
1da177e4
LT		 2689
2690 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2691 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
313980c9
DB		 2692 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2693
1da177e4
LT		 2694 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2695 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
313980c9 2696 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
1da177e4
LT		 2697
2698 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2699 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
313980c9
DB		 2700 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2701 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2702
1da177e4
LT		 2703 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2704 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
313980c9
DB		 2705 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2706 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2707
2708 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2709 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
1da177e4 2710
1da177e4
LT		 2711 break;
2712
2713#ifdef USE_ISO
2714 case 2: /* mixed iso/bulk */
2715 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2716 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2717 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2718 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2719
2720 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2721
2722 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2723 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2724 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2725 break;
2726 case 3: /* mixed bulk/iso */
2727 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2728 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2729 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2730
2731 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2732 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2733 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2734
2735 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2736 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2737 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2738 break;
2739#endif
2740
2741 /* add more modes as needed */
2742
2743 default:
2744 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2745 return -ENODEV;
2746 }
f35ae634 2747 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
1da177e4
LT		 2748 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2749 return 0;
2750}
2751
3ae5eaec 2752static int __init omap_udc_probe(struct platform_device *pdev)
1da177e4 2753{
1da177e4
LT		 2754 int status = -ENODEV;
2755 int hmc;
86753811 2756 struct usb_phy *xceiv = NULL;
313980c9 2757 const char *type = NULL;
3ae5eaec 2758 struct omap_usb_config *config = pdev->dev.platform_data;
ae372571
TL		 2759 struct clk *dc_clk = NULL;
2760 struct clk *hhc_clk = NULL;
1da177e4
LT		 2761
2762 /* NOTE: "knows" the order of the resources! */
e6a6e472 2763 if (!request_mem_region(pdev->resource[0].start,
3ae5eaec 2764 pdev->resource[0].end - pdev->resource[0].start + 1,
1da177e4
LT		 2765 driver_name)) {
2766 DBG("request_mem_region failed\n");
2767 return -EBUSY;
2768 }
2769
e6a6e472
DB		 2770 if (cpu_is_omap16xx()) {
2771 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2772 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2773 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2774 /* can't use omap_udc_enable_clock yet */
2775 clk_enable(dc_clk);
2776 clk_enable(hhc_clk);
2777 udelay(100);
2778 }
2779
45f780a0
CM		 2780 if (cpu_is_omap7xx()) {
2781 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2782 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2783 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2784 /* can't use omap_udc_enable_clock yet */
2785 clk_enable(dc_clk);
2786 clk_enable(hhc_clk);
2787 udelay(100);
2788 }
2789
1da177e4 2790 INFO("OMAP UDC rev %d.%d%s\n",
f35ae634 2791 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
1da177e4
LT		 2792 config->otg ? ", Mini-AB" : "");
2793
2794 /* use the mode given to us by board init code */
2795 if (cpu_is_omap15xx()) {
2796 hmc = HMC_1510;
2797 type = "(unknown)";
2798
8a3c1f57 2799 if (machine_without_vbus_sense()) {
1da177e4
LT		 2800 /* just set up software VBUS detect, and then
2801 * later rig it so we always report VBUS.
2802 * FIXME without really sensing VBUS, we can't
2803 * know when to turn PULLUP_EN on/off; and that
2804 * means we always "need" the 48MHz clock.
2805 */
f35ae634
TL		 2806 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2807 tmp &= ~VBUS_CTRL_1510;
2808 omap_writel(tmp, FUNC_MUX_CTRL_0);
1da177e4
LT		 2809 tmp |= VBUS_MODE_1510;
2810 tmp &= ~VBUS_CTRL_1510;
f35ae634 2811 omap_writel(tmp, FUNC_MUX_CTRL_0);
1da177e4
LT		 2812 }
2813 } else {
65111084
DB		 2814 /* The transceiver may package some GPIO logic or handle
2815 * loopback and/or transceiverless setup; if we find one,
2816 * use it. Except for OTG, we don't _need_ to talk to one;
2817 * but not having one probably means no VBUS detection.
2818 */
b96d3b08 2819 xceiv = usb_get_transceiver();
65111084
DB		 2820 if (xceiv)
2821 type = xceiv->label;
2822 else if (config->otg) {
2823 DBG("OTG requires external transceiver!\n");
2824 goto cleanup0;
2825 }
2826
1da177e4 2827 hmc = HMC_1610;
e6a6e472 2828
1da177e4 2829 switch (hmc) {
313980c9
DB		 2830 case 0: /* POWERUP DEFAULT == 0 */
2831 case 4:
2832 case 12:
2833 case 20:
2834 if (!cpu_is_omap1710()) {
2835 type = "integrated";
2836 break;
2837 }
2838 /* FALL THROUGH */
1da177e4
LT		 2839 case 3:
2840 case 11:
2841 case 16:
2842 case 19:
2843 case 25:
1da177e4
LT		 2844 if (!xceiv) {
2845 DBG("external transceiver not registered!\n");
313980c9 2846 type = "unknown";
65111084 2847 }
1da177e4 2848 break;
1da177e4 2849 case 21: /* internal loopback */
313980c9 2850 type = "loopback";
1da177e4
LT		 2851 break;
2852 case 14: /* transceiverless */
65111084
DB		 2853 if (cpu_is_omap1710())
2854 goto bad_on_1710;
2855 /* FALL THROUGH */
2856 case 13:
2857 case 15:
313980c9 2858 type = "no";
1da177e4
LT		 2859 break;
2860
2861 default:
65111084 2862bad_on_1710:
1da177e4 2863 ERR("unrecognized UDC HMC mode %d\n", hmc);
65111084 2864 goto cleanup0;
1da177e4
LT		 2865 }
2866 }
ae372571 2867
313980c9 2868 INFO("hmc mode %d, %s transceiver\n", hmc, type);
1da177e4
LT		 2869
2870 /* a "gadget" abstracts/virtualizes the controller */
3ae5eaec 2871 status = omap_udc_setup(pdev, xceiv);
1da177e4
LT		 2872 if (status) {
2873 goto cleanup0;
2874 }
313980c9 2875 xceiv = NULL;
1da177e4
LT		 2876 // "udc" is now valid
2877 pullup_disable(udc);
2878#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2879 udc->gadget.is_otg = (config->otg != 0);
2880#endif
2881
65111084 2882 /* starting with omap1710 es2.0, clear toggle is a separate bit */
f35ae634 2883 if (omap_readw(UDC_REV) >= 0x61)
65111084
DB		 2884 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2885 else
2886 udc->clr_halt = UDC_RESET_EP;
2887
1da177e4 2888 /* USB general purpose IRQ: ep0, state changes, dma, etc */
3ae5eaec 2889 status = request_irq(pdev->resource[1].start, omap_udc_irq,
d54b5caa 2890 IRQF_SAMPLE_RANDOM, driver_name, udc);
1da177e4 2891 if (status != 0) {
e6a6e472
DB		 2892 ERR("can't get irq %d, err %d\n",
2893 (int) pdev->resource[1].start, status);
1da177e4
LT		 2894 goto cleanup1;
2895 }
2896
2897 /* USB "non-iso" IRQ (PIO for all but ep0) */
3ae5eaec 2898 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
d54b5caa 2899 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
1da177e4 2900 if (status != 0) {
e6a6e472
DB		 2901 ERR("can't get irq %d, err %d\n",
2902 (int) pdev->resource[2].start, status);
1da177e4
LT		 2903 goto cleanup2;
2904 }
2905#ifdef USE_ISO
3ae5eaec 2906 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
b5dd18d8 2907 0, "omap_udc iso", udc);
1da177e4 2908 if (status != 0) {
e6a6e472
DB		 2909 ERR("can't get irq %d, err %d\n",
2910 (int) pdev->resource[3].start, status);
1da177e4
LT		 2911 goto cleanup3;
2912 }
2913#endif
45f780a0 2914 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
e6a6e472
DB		 2915 udc->dc_clk = dc_clk;
2916 udc->hhc_clk = hhc_clk;
2917 clk_disable(hhc_clk);
2918 clk_disable(dc_clk);
2919 }
2920
1da177e4 2921 create_proc_file();
e6a6e472 2922 status = device_add(&udc->gadget.dev);
0f91349b
SAS		 2923 if (status)
2924 goto cleanup4;
2925
2926 status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
e6a6e472
DB		 2927 if (!status)
2928 return status;
2929 /* If fail, fall through */
0f91349b
SAS		 2930cleanup4:
2931 remove_proc_file();
2932
1da177e4
LT		 2933#ifdef USE_ISO
2934cleanup3:
3ae5eaec 2935 free_irq(pdev->resource[2].start, udc);
1da177e4
LT		 2936#endif
2937
2938cleanup2:
3ae5eaec 2939 free_irq(pdev->resource[1].start, udc);
1da177e4
LT		 2940
2941cleanup1:
2942 kfree (udc);
313980c9 2943 udc = NULL;
1da177e4
LT		 2944
2945cleanup0:
2946 if (xceiv)
b96d3b08 2947 usb_put_transceiver(xceiv);
e6a6e472 2948
ae372571 2949 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
e6a6e472
DB		 2950 clk_disable(hhc_clk);
2951 clk_disable(dc_clk);
2952 clk_put(hhc_clk);
2953 clk_put(dc_clk);
2954 }
2955
3ae5eaec
RK		 2956 release_mem_region(pdev->resource[0].start,
2957 pdev->resource[0].end - pdev->resource[0].start + 1);
e6a6e472 2958
1da177e4
LT		 2959 return status;
2960}
2961
3ae5eaec 2962static int __exit omap_udc_remove(struct platform_device *pdev)
1da177e4 2963{
6e9a4738 2964 DECLARE_COMPLETION_ONSTACK(done);
1da177e4
LT		 2965
2966 if (!udc)
2967 return -ENODEV;
0f91349b
SAS		 2968
2969 usb_del_gadget_udc(&udc->gadget);
6bea476c
DB		 2970 if (udc->driver)
2971 return -EBUSY;
1da177e4
LT		 2972
2973 udc->done = &done;
2974
2975 pullup_disable(udc);
2976 if (udc->transceiver) {
b96d3b08 2977 usb_put_transceiver(udc->transceiver);
313980c9 2978 udc->transceiver = NULL;
1da177e4 2979 }
f35ae634 2980 omap_writew(0, UDC_SYSCON1);
1da177e4
LT		 2981
2982 remove_proc_file();
2983
2984#ifdef USE_ISO
3ae5eaec 2985 free_irq(pdev->resource[3].start, udc);
1da177e4 2986#endif
3ae5eaec
RK		 2987 free_irq(pdev->resource[2].start, udc);
2988 free_irq(pdev->resource[1].start, udc);
1da177e4 2989
e6a6e472
DB		 2990 if (udc->dc_clk) {
2991 if (udc->clk_requested)
2992 omap_udc_enable_clock(0);
2993 clk_put(udc->hhc_clk);
2994 clk_put(udc->dc_clk);
2995 }
2996
3ae5eaec
RK		 2997 release_mem_region(pdev->resource[0].start,
2998 pdev->resource[0].end - pdev->resource[0].start + 1);
1da177e4
LT		 2999
3000 device_unregister(&udc->gadget.dev);
3001 wait_for_completion(&done);
3002
3003 return 0;
3004}
3005
313980c9
DB		 3006/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3007 * system is forced into deep sleep
3008 *
3009 * REVISIT we should probably reject suspend requests when there's a host
3010 * session active, rather than disconnecting, at least on boards that can
f35ae634 3011 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
313980c9
DB		 3012 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3013 * may involve talking to an external transceiver (e.g. isp1301).
3014 */
1d7beee3 3015
3ae5eaec 3016static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
1da177e4 3017{
313980c9
DB		 3018 u32 devstat;
3019
f35ae634 3020 devstat = omap_readw(UDC_DEVSTAT);
313980c9
DB		 3021
3022 /* we're requesting 48 MHz clock if the pullup is enabled
3023 * (== we're attached to the host) and we're not suspended,
3024 * which would prevent entry to deep sleep...
3025 */
3026 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
b6c63937 3027 WARNING("session active; suspend requires disconnect\n");
313980c9
DB		 3028 omap_pullup(&udc->gadget, 0);
3029 }
1da177e4 3030
1da177e4
LT		 3031 return 0;
3032}
3033
3ae5eaec 3034static int omap_udc_resume(struct platform_device *dev)
1da177e4 3035{
1da177e4 3036 DBG("resume + wakeup/SRP\n");
1da177e4
LT		 3037 omap_pullup(&udc->gadget, 1);
3038
3039 /* maybe the host would enumerate us if we nudged it */
3040 msleep(100);
3041 return omap_wakeup(&udc->gadget);
3042}
3043
3044/*-------------------------------------------------------------------------*/
3045
3ae5eaec 3046static struct platform_driver udc_driver = {
1da177e4
LT		 3047 .remove = __exit_p(omap_udc_remove),
3048 .suspend = omap_udc_suspend,
3049 .resume = omap_udc_resume,
3ae5eaec
RK		 3050 .driver = {
3051 .owner = THIS_MODULE,
3052 .name = (char *) driver_name,
3053 },
1da177e4
LT		 3054};
3055
3056static int __init udc_init(void)
3057{
45f780a0
CM		 3058 /* Disable DMA for omap7xx -- it doesn't work right. */
3059 if (cpu_is_omap7xx())
3060 use_dma = 0;
3061
1da177e4
LT		 3062 INFO("%s, version: " DRIVER_VERSION
3063#ifdef USE_ISO
3064 " (iso)"
3065#endif
3066 "%s\n", driver_desc,
3067 use_dma ? " (dma)" : "");
864e28b4 3068 return platform_driver_probe(&udc_driver, omap_udc_probe);
1da177e4
LT		 3069}
3070module_init(udc_init);
3071
3072static void __exit udc_exit(void)
3073{
3ae5eaec 3074 platform_driver_unregister(&udc_driver);
1da177e4
LT		 3075}
3076module_exit(udc_exit);
3077
3078MODULE_DESCRIPTION(DRIVER_DESC);
3079MODULE_LICENSE("GPL");
f34c32f1 3080MODULE_ALIAS("platform:omap_udc");
Linux kernel - Deliverables
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