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UHCI: Fix problem caused by lack of terminating QH
[deliverable/linux.git] / drivers / usb / gadget / omap_udc.c
CommitLineData
1da177e4
LT		 1/*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#undef DEBUG
23#undef VERBOSE
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/ioport.h>
28#include <linux/types.h>
29#include <linux/errno.h>
30#include <linux/delay.h>
1da177e4
LT		 31#include <linux/slab.h>
32#include <linux/init.h>
33#include <linux/timer.h>
34#include <linux/list.h>
35#include <linux/interrupt.h>
36#include <linux/proc_fs.h>
37#include <linux/mm.h>
38#include <linux/moduleparam.h>
d052d1be 39#include <linux/platform_device.h>
5f848137 40#include <linux/usb/ch9.h>
1da177e4 41#include <linux/usb_gadget.h>
3a16f7b4 42#include <linux/usb/otg.h>
1da177e4 43#include <linux/dma-mapping.h>
e6a6e472 44#include <linux/clk.h>
1da177e4
LT		 45
46#include <asm/byteorder.h>
47#include <asm/io.h>
48#include <asm/irq.h>
49#include <asm/system.h>
50#include <asm/unaligned.h>
51#include <asm/mach-types.h>
52
53#include <asm/arch/dma.h>
1da177e4
LT		 54#include <asm/arch/usb.h>
55
56#include "omap_udc.h"
57
58#undef USB_TRACE
59
60/* bulk DMA seems to be behaving for both IN and OUT */
61#define USE_DMA
62
e6a6e472
DB		 63/* FIXME: OMAP2 currently has some problem in DMA mode */
64#ifdef CONFIG_ARCH_OMAP2
65#undef USE_DMA
66#endif
67
1da177e4
LT		 68/* ISO too */
69#define USE_ISO
70
71#define DRIVER_DESC "OMAP UDC driver"
72#define DRIVER_VERSION "4 October 2004"
73
74#define DMA_ADDR_INVALID (~(dma_addr_t)0)
75
76
77/*
78 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
79 * D+ pullup to allow enumeration. That's too early for the gadget
80 * framework to use from usb_endpoint_enable(), which happens after
81 * enumeration as part of activating an interface. (But if we add an
82 * optional new "UDC not yet running" state to the gadget driver model,
83 * even just during driver binding, the endpoint autoconfig logic is the
84 * natural spot to manufacture new endpoints.)
85 *
86 * So instead of using endpoint enable calls to control the hardware setup,
87 * this driver defines a "fifo mode" parameter. It's used during driver
88 * initialization to choose among a set of pre-defined endpoint configs.
89 * See omap_udc_setup() for available modes, or to add others. That code
90 * lives in an init section, so use this driver as a module if you need
91 * to change the fifo mode after the kernel boots.
92 *
93 * Gadget drivers normally ignore endpoints they don't care about, and
94 * won't include them in configuration descriptors. That means only
95 * misbehaving hosts would even notice they exist.
96 */
97#ifdef USE_ISO
98static unsigned fifo_mode = 3;
99#else
100static unsigned fifo_mode = 0;
101#endif
102
103/* "modprobe omap_udc fifo_mode=42", or else as a kernel
104 * boot parameter "omap_udc:fifo_mode=42"
105 */
106module_param (fifo_mode, uint, 0);
e6a6e472 107MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
1da177e4
LT		 108
109#ifdef USE_DMA
110static unsigned use_dma = 1;
111
112/* "modprobe omap_udc use_dma=y", or else as a kernel
113 * boot parameter "omap_udc:use_dma=y"
114 */
115module_param (use_dma, bool, 0);
116MODULE_PARM_DESC (use_dma, "enable/disable DMA");
117#else /* !USE_DMA */
118
119/* save a bit of code */
120#define use_dma 0
121#endif /* !USE_DMA */
122
123
124static const char driver_name [] = "omap_udc";
125static const char driver_desc [] = DRIVER_DESC;
126
127/*-------------------------------------------------------------------------*/
128
129/* there's a notion of "current endpoint" for modifying endpoint
e6a6e472 130 * state, and PIO access to its FIFO.
1da177e4
LT		 131 */
132
133static void use_ep(struct omap_ep *ep, u16 select)
134{
135 u16 num = ep->bEndpointAddress & 0x0f;
136
137 if (ep->bEndpointAddress & USB_DIR_IN)
138 num |= UDC_EP_DIR;
139 UDC_EP_NUM_REG = num | select;
140 /* when select, MUST deselect later !! */
141}
142
143static inline void deselect_ep(void)
144{
145 UDC_EP_NUM_REG &= ~UDC_EP_SEL;
146 /* 6 wait states before TX will happen */
147}
148
149static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
150
151/*-------------------------------------------------------------------------*/
152
153static int omap_ep_enable(struct usb_ep *_ep,
154 const struct usb_endpoint_descriptor *desc)
155{
156 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
157 struct omap_udc *udc;
158 unsigned long flags;
159 u16 maxp;
160
161 /* catch various bogus parameters */
162 if (!_ep || !desc || ep->desc
163 || desc->bDescriptorType != USB_DT_ENDPOINT
164 || ep->bEndpointAddress != desc->bEndpointAddress
165 || ep->maxpacket < le16_to_cpu
166 (desc->wMaxPacketSize)) {
167 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
168 return -EINVAL;
169 }
170 maxp = le16_to_cpu (desc->wMaxPacketSize);
171 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
172 && maxp != ep->maxpacket)
65111084 173 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
1da177e4
LT		 174 || !desc->wMaxPacketSize) {
175 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
176 return -ERANGE;
177 }
178
179#ifdef USE_ISO
180 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
181 && desc->bInterval != 1)) {
182 /* hardware wants period = 1; USB allows 2^(Interval-1) */
183 DBG("%s, unsupported ISO period %dms\n", _ep->name,
184 1 << (desc->bInterval - 1));
185 return -EDOM;
186 }
187#else
188 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
189 DBG("%s, ISO nyet\n", _ep->name);
190 return -EDOM;
191 }
192#endif
193
194 /* xfer types must match, except that interrupt ~= bulk */
195 if (ep->bmAttributes != desc->bmAttributes
196 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
197 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
198 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
199 return -EINVAL;
200 }
201
202 udc = ep->udc;
203 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
204 DBG("%s, bogus device state\n", __FUNCTION__);
205 return -ESHUTDOWN;
206 }
207
208 spin_lock_irqsave(&udc->lock, flags);
209
210 ep->desc = desc;
211 ep->irqs = 0;
212 ep->stopped = 0;
213 ep->ep.maxpacket = maxp;
214
215 /* set endpoint to initial state */
216 ep->dma_channel = 0;
217 ep->has_dma = 0;
218 ep->lch = -1;
219 use_ep(ep, UDC_EP_SEL);
65111084 220 UDC_CTRL_REG = udc->clr_halt;
1da177e4
LT		 221 ep->ackwait = 0;
222 deselect_ep();
223
224 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
225 list_add(&ep->iso, &udc->iso);
226
227 /* maybe assign a DMA channel to this endpoint */
228 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
229 /* FIXME ISO can dma, but prefers first channel */
230 dma_channel_claim(ep, 0);
231
232 /* PIO OUT may RX packets */
233 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
234 && !ep->has_dma
235 && !(ep->bEndpointAddress & USB_DIR_IN)) {
236 UDC_CTRL_REG = UDC_SET_FIFO_EN;
237 ep->ackwait = 1 + ep->double_buf;
238 }
239
240 spin_unlock_irqrestore(&udc->lock, flags);
241 VDBG("%s enabled\n", _ep->name);
242 return 0;
243}
244
245static void nuke(struct omap_ep *, int status);
246
247static int omap_ep_disable(struct usb_ep *_ep)
248{
249 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
250 unsigned long flags;
251
252 if (!_ep || !ep->desc) {
253 DBG("%s, %s not enabled\n", __FUNCTION__,
254 _ep ? ep->ep.name : NULL);
255 return -EINVAL;
256 }
257
258 spin_lock_irqsave(&ep->udc->lock, flags);
313980c9 259 ep->desc = NULL;
1da177e4
LT		 260 nuke (ep, -ESHUTDOWN);
261 ep->ep.maxpacket = ep->maxpacket;
262 ep->has_dma = 0;
263 UDC_CTRL_REG = UDC_SET_HALT;
264 list_del_init(&ep->iso);
265 del_timer(&ep->timer);
266
267 spin_unlock_irqrestore(&ep->udc->lock, flags);
268
269 VDBG("%s disabled\n", _ep->name);
270 return 0;
271}
272
273/*-------------------------------------------------------------------------*/
274
275static struct usb_request *
55016f10 276omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1da177e4
LT		 277{
278 struct omap_req *req;
279
7039f422 280 req = kzalloc(sizeof(*req), gfp_flags);
1da177e4 281 if (req) {
1da177e4
LT		 282 req->req.dma = DMA_ADDR_INVALID;
283 INIT_LIST_HEAD (&req->queue);
284 }
285 return &req->req;
286}
287
288static void
289omap_free_request(struct usb_ep *ep, struct usb_request *_req)
290{
291 struct omap_req *req = container_of(_req, struct omap_req, req);
292
293 if (_req)
294 kfree (req);
295}
296
297/*-------------------------------------------------------------------------*/
298
299static void *
300omap_alloc_buffer(
301 struct usb_ep *_ep,
302 unsigned bytes,
303 dma_addr_t *dma,
55016f10 304 gfp_t gfp_flags
1da177e4
LT		 305)
306{
307 void *retval;
308 struct omap_ep *ep;
309
310 ep = container_of(_ep, struct omap_ep, ep);
311 if (use_dma && ep->has_dma) {
312 static int warned;
313 if (!warned && bytes < PAGE_SIZE) {
314 dev_warn(ep->udc->gadget.dev.parent,
315 "using dma_alloc_coherent for "
316 "small allocations wastes memory\n");
317 warned++;
318 }
319 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
320 bytes, dma, gfp_flags);
321 }
322
323 retval = kmalloc(bytes, gfp_flags);
324 if (retval)
325 *dma = virt_to_phys(retval);
326 return retval;
327}
328
329static void omap_free_buffer(
330 struct usb_ep *_ep,
331 void *buf,
332 dma_addr_t dma,
333 unsigned bytes
334)
335{
336 struct omap_ep *ep;
337
338 ep = container_of(_ep, struct omap_ep, ep);
339 if (use_dma && _ep && ep->has_dma)
340 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
341 else
342 kfree (buf);
343}
344
345/*-------------------------------------------------------------------------*/
346
347static void
348done(struct omap_ep *ep, struct omap_req *req, int status)
349{
350 unsigned stopped = ep->stopped;
351
352 list_del_init(&req->queue);
353
354 if (req->req.status == -EINPROGRESS)
355 req->req.status = status;
356 else
357 status = req->req.status;
358
359 if (use_dma && ep->has_dma) {
360 if (req->mapped) {
361 dma_unmap_single(ep->udc->gadget.dev.parent,
362 req->req.dma, req->req.length,
363 (ep->bEndpointAddress & USB_DIR_IN)
364 ? DMA_TO_DEVICE
365 : DMA_FROM_DEVICE);
366 req->req.dma = DMA_ADDR_INVALID;
367 req->mapped = 0;
368 } else
369 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
370 req->req.dma, req->req.length,
371 (ep->bEndpointAddress & USB_DIR_IN)
372 ? DMA_TO_DEVICE
373 : DMA_FROM_DEVICE);
374 }
375
376#ifndef USB_TRACE
377 if (status && status != -ESHUTDOWN)
378#endif
379 VDBG("complete %s req %p stat %d len %u/%u\n",
380 ep->ep.name, &req->req, status,
381 req->req.actual, req->req.length);
382
383 /* don't modify queue heads during completion callback */
384 ep->stopped = 1;
385 spin_unlock(&ep->udc->lock);
386 req->req.complete(&ep->ep, &req->req);
387 spin_lock(&ep->udc->lock);
388 ep->stopped = stopped;
389}
390
391/*-------------------------------------------------------------------------*/
392
313980c9
DB		 393#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
394#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
1da177e4
LT		 395
396#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
397#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
398
e6a6e472 399static inline int
1da177e4
LT		 400write_packet(u8 *buf, struct omap_req *req, unsigned max)
401{
402 unsigned len;
403 u16 *wp;
404
405 len = min(req->req.length - req->req.actual, max);
406 req->req.actual += len;
407
408 max = len;
409 if (likely((((int)buf) & 1) == 0)) {
410 wp = (u16 *)buf;
411 while (max >= 2) {
412 UDC_DATA_REG = *wp++;
413 max -= 2;
414 }
415 buf = (u8 *)wp;
416 }
417 while (max--)
418 *(volatile u8 *)&UDC_DATA_REG = *buf++;
419 return len;
420}
421
422// FIXME change r/w fifo calling convention
423
424
425// return: 0 = still running, 1 = completed, negative = errno
426static int write_fifo(struct omap_ep *ep, struct omap_req *req)
427{
428 u8 *buf;
429 unsigned count;
430 int is_last;
431 u16 ep_stat;
432
433 buf = req->req.buf + req->req.actual;
434 prefetch(buf);
435
436 /* PIO-IN isn't double buffered except for iso */
437 ep_stat = UDC_STAT_FLG_REG;
313980c9 438 if (ep_stat & UDC_FIFO_UNWRITABLE)
1da177e4
LT		 439 return 0;
440
441 count = ep->ep.maxpacket;
442 count = write_packet(buf, req, count);
443 UDC_CTRL_REG = UDC_SET_FIFO_EN;
444 ep->ackwait = 1;
445
446 /* last packet is often short (sometimes a zlp) */
447 if (count != ep->ep.maxpacket)
448 is_last = 1;
449 else if (req->req.length == req->req.actual
450 && !req->req.zero)
451 is_last = 1;
452 else
453 is_last = 0;
454
455 /* NOTE: requests complete when all IN data is in a
456 * FIFO (or sometimes later, if a zlp was needed).
457 * Use usb_ep_fifo_status() where needed.
458 */
459 if (is_last)
460 done(ep, req, 0);
461 return is_last;
462}
463
e6a6e472 464static inline int
1da177e4
LT		 465read_packet(u8 *buf, struct omap_req *req, unsigned avail)
466{
467 unsigned len;
468 u16 *wp;
469
470 len = min(req->req.length - req->req.actual, avail);
471 req->req.actual += len;
472 avail = len;
473
474 if (likely((((int)buf) & 1) == 0)) {
475 wp = (u16 *)buf;
476 while (avail >= 2) {
477 *wp++ = UDC_DATA_REG;
478 avail -= 2;
479 }
480 buf = (u8 *)wp;
481 }
482 while (avail--)
483 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
484 return len;
485}
486
487// return: 0 = still running, 1 = queue empty, negative = errno
488static int read_fifo(struct omap_ep *ep, struct omap_req *req)
489{
490 u8 *buf;
491 unsigned count, avail;
492 int is_last;
493
494 buf = req->req.buf + req->req.actual;
495 prefetchw(buf);
496
497 for (;;) {
498 u16 ep_stat = UDC_STAT_FLG_REG;
499
500 is_last = 0;
501 if (ep_stat & FIFO_EMPTY) {
502 if (!ep->double_buf)
503 break;
504 ep->fnf = 1;
505 }
506 if (ep_stat & UDC_EP_HALTED)
507 break;
508
313980c9 509 if (ep_stat & UDC_FIFO_FULL)
1da177e4
LT		 510 avail = ep->ep.maxpacket;
511 else {
512 avail = UDC_RXFSTAT_REG;
513 ep->fnf = ep->double_buf;
514 }
515 count = read_packet(buf, req, avail);
516
517 /* partial packet reads may not be errors */
518 if (count < ep->ep.maxpacket) {
519 is_last = 1;
520 /* overflowed this request? flush extra data */
521 if (count != avail) {
522 req->req.status = -EOVERFLOW;
523 avail -= count;
524 while (avail--)
525 (void) *(volatile u8 *)&UDC_DATA_REG;
526 }
527 } else if (req->req.length == req->req.actual)
528 is_last = 1;
529 else
530 is_last = 0;
531
532 if (!ep->bEndpointAddress)
533 break;
534 if (is_last)
535 done(ep, req, 0);
536 break;
537 }
538 return is_last;
539}
540
541/*-------------------------------------------------------------------------*/
542
65111084
DB		 543static inline dma_addr_t dma_csac(unsigned lch)
544{
545 dma_addr_t csac;
546
547 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
548 * read before the DMA controller finished disabling the channel.
549 */
e6a6e472 550 csac = OMAP_DMA_CSAC_REG(lch);
65111084 551 if (csac == 0)
e6a6e472 552 csac = OMAP_DMA_CSAC_REG(lch);
65111084
DB		 553 return csac;
554}
555
556static inline dma_addr_t dma_cdac(unsigned lch)
557{
558 dma_addr_t cdac;
559
560 /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
561 * read before the DMA controller finished disabling the channel.
562 */
e6a6e472 563 cdac = OMAP_DMA_CDAC_REG(lch);
65111084 564 if (cdac == 0)
e6a6e472 565 cdac = OMAP_DMA_CDAC_REG(lch);
65111084
DB		 566 return cdac;
567}
568
1da177e4
LT		 569static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
570{
571 dma_addr_t end;
572
573 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
574 * the last transfer's bytecount by more than a FIFO's worth.
575 */
576 if (cpu_is_omap15xx())
577 return 0;
578
65111084 579 end = dma_csac(ep->lch);
1da177e4
LT		 580 if (end == ep->dma_counter)
581 return 0;
582
583 end |= start & (0xffff << 16);
584 if (end < start)
585 end += 0x10000;
586 return end - start;
587}
588
589#define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
e6a6e472 590 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
65111084 591 : dma_cdac(x))
1da177e4
LT		 592
593static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
594{
595 dma_addr_t end;
596
65111084 597 end = DMA_DEST_LAST(ep->lch);
1da177e4
LT		 598 if (end == ep->dma_counter)
599 return 0;
600
601 end |= start & (0xffff << 16);
602 if (cpu_is_omap15xx())
603 end++;
604 if (end < start)
605 end += 0x10000;
606 return end - start;
607}
608
609
610/* Each USB transfer request using DMA maps to one or more DMA transfers.
611 * When DMA completion isn't request completion, the UDC continues with
612 * the next DMA transfer for that USB transfer.
613 */
614
615static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
616{
617 u16 txdma_ctrl;
618 unsigned length = req->req.length - req->req.actual;
619 const int sync_mode = cpu_is_omap15xx()
620 ? OMAP_DMA_SYNC_FRAME
621 : OMAP_DMA_SYNC_ELEMENT;
622
623 /* measure length in either bytes or packets */
65111084 624 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
1da177e4
LT		 625 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
626 txdma_ctrl = UDC_TXN_EOT | length;
627 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
e6a6e472 628 length, 1, sync_mode, 0, 0);
1da177e4
LT		 629 } else {
630 length = min(length / ep->maxpacket,
631 (unsigned) UDC_TXN_TSC + 1);
e6a6e472 632 txdma_ctrl = length;
65111084 633 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
e6a6e472
DB		 634 ep->ep.maxpacket >> 1, length, sync_mode,
635 0, 0);
1da177e4
LT		 636 length *= ep->maxpacket;
637 }
638 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
e6a6e472
DB		 639 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
640 0, 0);
1da177e4
LT		 641
642 omap_start_dma(ep->lch);
65111084 643 ep->dma_counter = dma_csac(ep->lch);
1da177e4
LT		 644 UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
645 UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
646 req->dma_bytes = length;
647}
648
649static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
650{
651 if (status == 0) {
652 req->req.actual += req->dma_bytes;
653
654 /* return if this request needs to send data or zlp */
655 if (req->req.actual < req->req.length)
656 return;
657 if (req->req.zero
658 && req->dma_bytes != 0
659 && (req->req.actual % ep->maxpacket) == 0)
660 return;
661 } else
662 req->req.actual += dma_src_len(ep, req->req.dma
663 + req->req.actual);
664
665 /* tx completion */
666 omap_stop_dma(ep->lch);
667 UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
668 done(ep, req, status);
669}
670
671static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
672{
673 unsigned packets;
674
675 /* NOTE: we filtered out "short reads" before, so we know
676 * the buffer has only whole numbers of packets.
677 */
678
679 /* set up this DMA transfer, enable the fifo, start */
680 packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
681 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
682 req->dma_bytes = packets * ep->ep.maxpacket;
65111084
DB		 683 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
684 ep->ep.maxpacket >> 1, packets,
e6a6e472
DB		 685 OMAP_DMA_SYNC_ELEMENT,
686 0, 0);
1da177e4 687 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
e6a6e472
DB		 688 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
689 0, 0);
65111084 690 ep->dma_counter = DMA_DEST_LAST(ep->lch);
1da177e4
LT		 691
692 UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
693 UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
694 UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
695 UDC_CTRL_REG = UDC_SET_FIFO_EN;
696
697 omap_start_dma(ep->lch);
698}
699
700static void
cb97c5c9 701finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
1da177e4
LT		 702{
703 u16 count;
704
705 if (status == 0)
706 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
707 count = dma_dest_len(ep, req->req.dma + req->req.actual);
708 count += req->req.actual;
cb97c5c9
DB		 709 if (one)
710 count--;
1da177e4
LT		 711 if (count <= req->req.length)
712 req->req.actual = count;
713
714 if (count != req->dma_bytes || status)
715 omap_stop_dma(ep->lch);
716
717 /* if this wasn't short, request may need another transfer */
718 else if (req->req.actual < req->req.length)
719 return;
720
721 /* rx completion */
722 UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
723 done(ep, req, status);
724}
725
726static void dma_irq(struct omap_udc *udc, u16 irq_src)
727{
728 u16 dman_stat = UDC_DMAN_STAT_REG;
729 struct omap_ep *ep;
730 struct omap_req *req;
731
732 /* IN dma: tx to host */
733 if (irq_src & UDC_TXN_DONE) {
734 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
735 ep->irqs++;
736 /* can see TXN_DONE after dma abort */
737 if (!list_empty(&ep->queue)) {
738 req = container_of(ep->queue.next,
739 struct omap_req, queue);
740 finish_in_dma(ep, req, 0);
741 }
742 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
743
744 if (!list_empty (&ep->queue)) {
745 req = container_of(ep->queue.next,
746 struct omap_req, queue);
747 next_in_dma(ep, req);
748 }
749 }
750
751 /* OUT dma: rx from host */
752 if (irq_src & UDC_RXN_EOT) {
753 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
754 ep->irqs++;
755 /* can see RXN_EOT after dma abort */
756 if (!list_empty(&ep->queue)) {
757 req = container_of(ep->queue.next,
758 struct omap_req, queue);
cb97c5c9 759 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
1da177e4
LT		 760 }
761 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
762
763 if (!list_empty (&ep->queue)) {
764 req = container_of(ep->queue.next,
765 struct omap_req, queue);
766 next_out_dma(ep, req);
767 }
768 }
769
770 if (irq_src & UDC_RXN_CNT) {
771 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
772 ep->irqs++;
773 /* omap15xx does this unasked... */
774 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
775 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
776 }
777}
778
779static void dma_error(int lch, u16 ch_status, void *data)
780{
781 struct omap_ep *ep = data;
782
783 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
7ff879db 784 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
1da177e4
LT		 785 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
786
787 /* complete current transfer ... */
788}
789
790static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
791{
792 u16 reg;
793 int status, restart, is_in;
794
795 is_in = ep->bEndpointAddress & USB_DIR_IN;
796 if (is_in)
797 reg = UDC_TXDMA_CFG_REG;
798 else
799 reg = UDC_RXDMA_CFG_REG;
65111084 800 reg |= UDC_DMA_REQ; /* "pulse" activated */
1da177e4
LT		 801
802 ep->dma_channel = 0;
803 ep->lch = -1;
804 if (channel == 0 || channel > 3) {
805 if ((reg & 0x0f00) == 0)
806 channel = 3;
807 else if ((reg & 0x00f0) == 0)
808 channel = 2;
809 else if ((reg & 0x000f) == 0) /* preferred for ISO */
810 channel = 1;
811 else {
812 status = -EMLINK;
813 goto just_restart;
814 }
815 }
816 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
817 ep->dma_channel = channel;
818
819 if (is_in) {
820 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
821 ep->ep.name, dma_error, ep, &ep->lch);
822 if (status == 0) {
823 UDC_TXDMA_CFG_REG = reg;
65111084
DB		 824 /* EMIFF */
825 omap_set_dma_src_burst_mode(ep->lch,
826 OMAP_DMA_DATA_BURST_4);
827 omap_set_dma_src_data_pack(ep->lch, 1);
828 /* TIPB */
1da177e4
LT		 829 omap_set_dma_dest_params(ep->lch,
830 OMAP_DMA_PORT_TIPB,
831 OMAP_DMA_AMODE_CONSTANT,
e6a6e472
DB		 832 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
833 0, 0);
1da177e4
LT		 834 }
835 } else {
836 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
837 ep->ep.name, dma_error, ep, &ep->lch);
838 if (status == 0) {
839 UDC_RXDMA_CFG_REG = reg;
65111084 840 /* TIPB */
1da177e4
LT		 841 omap_set_dma_src_params(ep->lch,
842 OMAP_DMA_PORT_TIPB,
843 OMAP_DMA_AMODE_CONSTANT,
e6a6e472
DB		 844 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
845 0, 0);
65111084
DB		 846 /* EMIFF */
847 omap_set_dma_dest_burst_mode(ep->lch,
848 OMAP_DMA_DATA_BURST_4);
849 omap_set_dma_dest_data_pack(ep->lch, 1);
1da177e4
LT		 850 }
851 }
852 if (status)
853 ep->dma_channel = 0;
854 else {
855 ep->has_dma = 1;
856 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
857
858 /* channel type P: hw synch (fifo) */
859 if (!cpu_is_omap15xx())
e6a6e472 860 OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
1da177e4
LT		 861 }
862
863just_restart:
864 /* restart any queue, even if the claim failed */
865 restart = !ep->stopped && !list_empty(&ep->queue);
866
867 if (status)
868 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
869 restart ? " (restart)" : "");
870 else
871 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
872 is_in ? 't' : 'r',
873 ep->dma_channel - 1, ep->lch,
874 restart ? " (restart)" : "");
875
876 if (restart) {
877 struct omap_req *req;
878 req = container_of(ep->queue.next, struct omap_req, queue);
879 if (ep->has_dma)
880 (is_in ? next_in_dma : next_out_dma)(ep, req);
881 else {
882 use_ep(ep, UDC_EP_SEL);
883 (is_in ? write_fifo : read_fifo)(ep, req);
884 deselect_ep();
885 if (!is_in) {
886 UDC_CTRL_REG = UDC_SET_FIFO_EN;
887 ep->ackwait = 1 + ep->double_buf;
888 }
889 /* IN: 6 wait states before it'll tx */
890 }
891 }
892}
893
894static void dma_channel_release(struct omap_ep *ep)
895{
896 int shift = 4 * (ep->dma_channel - 1);
897 u16 mask = 0x0f << shift;
898 struct omap_req *req;
899 int active;
900
901 /* abort any active usb transfer request */
902 if (!list_empty(&ep->queue))
903 req = container_of(ep->queue.next, struct omap_req, queue);
904 else
313980c9 905 req = NULL;
1da177e4 906
e6a6e472 907 active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
1da177e4
LT		 908
909 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
910 active ? "active" : "idle",
911 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
912 ep->dma_channel - 1, req);
913
65111084
DB		 914 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
915 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
916 */
917
1da177e4
LT		 918 /* wait till current packet DMA finishes, and fifo empties */
919 if (ep->bEndpointAddress & USB_DIR_IN) {
65111084 920 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
1da177e4
LT		 921
922 if (req) {
923 finish_in_dma(ep, req, -ECONNRESET);
924
925 /* clear FIFO; hosts probably won't empty it */
926 use_ep(ep, UDC_EP_SEL);
927 UDC_CTRL_REG = UDC_CLR_EP;
928 deselect_ep();
929 }
930 while (UDC_TXDMA_CFG_REG & mask)
931 udelay(10);
932 } else {
65111084 933 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
1da177e4
LT		 934
935 /* dma empties the fifo */
936 while (UDC_RXDMA_CFG_REG & mask)
937 udelay(10);
938 if (req)
cb97c5c9 939 finish_out_dma(ep, req, -ECONNRESET, 0);
1da177e4
LT		 940 }
941 omap_free_dma(ep->lch);
942 ep->dma_channel = 0;
943 ep->lch = -1;
944 /* has_dma still set, till endpoint is fully quiesced */
945}
946
947
948/*-------------------------------------------------------------------------*/
949
950static int
55016f10 951omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1da177e4
LT		 952{
953 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
954 struct omap_req *req = container_of(_req, struct omap_req, req);
955 struct omap_udc *udc;
956 unsigned long flags;
957 int is_iso = 0;
958
959 /* catch various bogus parameters */
960 if (!_req || !req->req.complete || !req->req.buf
961 || !list_empty(&req->queue)) {
962 DBG("%s, bad params\n", __FUNCTION__);
963 return -EINVAL;
964 }
965 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
966 DBG("%s, bad ep\n", __FUNCTION__);
967 return -EINVAL;
968 }
969 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
970 if (req->req.length > ep->ep.maxpacket)
971 return -EMSGSIZE;
972 is_iso = 1;
973 }
974
975 /* this isn't bogus, but OMAP DMA isn't the only hardware to
976 * have a hard time with partial packet reads... reject it.
977 */
978 if (use_dma
979 && ep->has_dma
980 && ep->bEndpointAddress != 0
981 && (ep->bEndpointAddress & USB_DIR_IN) == 0
982 && (req->req.length % ep->ep.maxpacket) != 0) {
983 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
984 return -EMSGSIZE;
985 }
986
987 udc = ep->udc;
988 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
989 return -ESHUTDOWN;
990
991 if (use_dma && ep->has_dma) {
992 if (req->req.dma == DMA_ADDR_INVALID) {
993 req->req.dma = dma_map_single(
994 ep->udc->gadget.dev.parent,
995 req->req.buf,
996 req->req.length,
997 (ep->bEndpointAddress & USB_DIR_IN)
998 ? DMA_TO_DEVICE
999 : DMA_FROM_DEVICE);
1000 req->mapped = 1;
1001 } else {
1002 dma_sync_single_for_device(
1003 ep->udc->gadget.dev.parent,
1004 req->req.dma, req->req.length,
1005 (ep->bEndpointAddress & USB_DIR_IN)
1006 ? DMA_TO_DEVICE
1007 : DMA_FROM_DEVICE);
1008 req->mapped = 0;
1009 }
1010 }
1011
1012 VDBG("%s queue req %p, len %d buf %p\n",
1013 ep->ep.name, _req, _req->length, _req->buf);
1014
1015 spin_lock_irqsave(&udc->lock, flags);
1016
1017 req->req.status = -EINPROGRESS;
1018 req->req.actual = 0;
1019
1020 /* maybe kickstart non-iso i/o queues */
1021 if (is_iso)
1022 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1023 else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1024 int is_in;
1025
1026 if (ep->bEndpointAddress == 0) {
1027 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1028 spin_unlock_irqrestore(&udc->lock, flags);
1029 return -EL2HLT;
1030 }
1031
1032 /* empty DATA stage? */
1033 is_in = udc->ep0_in;
1034 if (!req->req.length) {
1035
1036 /* chip became CONFIGURED or ADDRESSED
1037 * earlier; drivers may already have queued
1038 * requests to non-control endpoints
1039 */
1040 if (udc->ep0_set_config) {
1041 u16 irq_en = UDC_IRQ_EN_REG;
1042
1043 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1044 if (!udc->ep0_reset_config)
1045 irq_en |= UDC_EPN_RX_IE
1046 | UDC_EPN_TX_IE;
1047 UDC_IRQ_EN_REG = irq_en;
1048 }
1049
313980c9
DB		 1050 /* STATUS for zero length DATA stages is
1051 * always an IN ... even for IN transfers,
1052 * a wierd case which seem to stall OMAP.
1053 */
1054 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1da177e4
LT		 1055 UDC_CTRL_REG = UDC_CLR_EP;
1056 UDC_CTRL_REG = UDC_SET_FIFO_EN;
313980c9 1057 UDC_EP_NUM_REG = UDC_EP_DIR;
1da177e4
LT		 1058
1059 /* cleanup */
1060 udc->ep0_pending = 0;
1061 done(ep, req, 0);
313980c9 1062 req = NULL;
1da177e4
LT		 1063
1064 /* non-empty DATA stage */
1065 } else if (is_in) {
1066 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1067 } else {
1068 if (udc->ep0_setup)
1069 goto irq_wait;
1070 UDC_EP_NUM_REG = UDC_EP_SEL;
1071 }
1072 } else {
1073 is_in = ep->bEndpointAddress & USB_DIR_IN;
1074 if (!ep->has_dma)
1075 use_ep(ep, UDC_EP_SEL);
1076 /* if ISO: SOF IRQs must be enabled/disabled! */
1077 }
1078
1079 if (ep->has_dma)
1080 (is_in ? next_in_dma : next_out_dma)(ep, req);
1081 else if (req) {
1082 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
313980c9 1083 req = NULL;
1da177e4
LT		 1084 deselect_ep();
1085 if (!is_in) {
1086 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1087 ep->ackwait = 1 + ep->double_buf;
1088 }
1089 /* IN: 6 wait states before it'll tx */
1090 }
1091 }
1092
1093irq_wait:
1094 /* irq handler advances the queue */
313980c9 1095 if (req != NULL)
1da177e4
LT		 1096 list_add_tail(&req->queue, &ep->queue);
1097 spin_unlock_irqrestore(&udc->lock, flags);
1098
1099 return 0;
1100}
1101
1102static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1103{
1104 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1105 struct omap_req *req;
1106 unsigned long flags;
1107
1108 if (!_ep || !_req)
1109 return -EINVAL;
1110
1111 spin_lock_irqsave(&ep->udc->lock, flags);
1112
1113 /* make sure it's actually queued on this endpoint */
1114 list_for_each_entry (req, &ep->queue, queue) {
1115 if (&req->req == _req)
1116 break;
1117 }
1118 if (&req->req != _req) {
1119 spin_unlock_irqrestore(&ep->udc->lock, flags);
1120 return -EINVAL;
1121 }
1122
1123 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1124 int channel = ep->dma_channel;
1125
1126 /* releasing the channel cancels the request,
1127 * reclaiming the channel restarts the queue
1128 */
1129 dma_channel_release(ep);
1130 dma_channel_claim(ep, channel);
e6a6e472 1131 } else
1da177e4
LT		 1132 done(ep, req, -ECONNRESET);
1133 spin_unlock_irqrestore(&ep->udc->lock, flags);
1134 return 0;
1135}
1136
1137/*-------------------------------------------------------------------------*/
1138
1139static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1140{
1141 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1142 unsigned long flags;
1143 int status = -EOPNOTSUPP;
1144
1145 spin_lock_irqsave(&ep->udc->lock, flags);
1146
1147 /* just use protocol stalls for ep0; real halts are annoying */
1148 if (ep->bEndpointAddress == 0) {
1149 if (!ep->udc->ep0_pending)
1150 status = -EINVAL;
1151 else if (value) {
1152 if (ep->udc->ep0_set_config) {
1153 WARN("error changing config?\n");
1154 UDC_SYSCON2_REG = UDC_CLR_CFG;
1155 }
1156 UDC_SYSCON2_REG = UDC_STALL_CMD;
1157 ep->udc->ep0_pending = 0;
1158 status = 0;
1159 } else /* NOP */
1160 status = 0;
1161
1162 /* otherwise, all active non-ISO endpoints can halt */
1163 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1164
1165 /* IN endpoints must already be idle */
1166 if ((ep->bEndpointAddress & USB_DIR_IN)
e6a6e472 1167 && !list_empty(&ep->queue)) {
1da177e4
LT		 1168 status = -EAGAIN;
1169 goto done;
1170 }
1171
1172 if (value) {
1173 int channel;
1174
1175 if (use_dma && ep->dma_channel
1176 && !list_empty(&ep->queue)) {
1177 channel = ep->dma_channel;
1178 dma_channel_release(ep);
1179 } else
1180 channel = 0;
1181
1182 use_ep(ep, UDC_EP_SEL);
1183 if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1184 UDC_CTRL_REG = UDC_SET_HALT;
1185 status = 0;
1186 } else
1187 status = -EAGAIN;
1188 deselect_ep();
1189
1190 if (channel)
1191 dma_channel_claim(ep, channel);
1192 } else {
1193 use_ep(ep, 0);
65111084 1194 UDC_CTRL_REG = ep->udc->clr_halt;
1da177e4
LT		 1195 ep->ackwait = 0;
1196 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1197 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1198 ep->ackwait = 1 + ep->double_buf;
1199 }
1200 }
1201 }
1202done:
1203 VDBG("%s %s halt stat %d\n", ep->ep.name,
1204 value ? "set" : "clear", status);
1205
1206 spin_unlock_irqrestore(&ep->udc->lock, flags);
1207 return status;
1208}
1209
1210static struct usb_ep_ops omap_ep_ops = {
1211 .enable = omap_ep_enable,
1212 .disable = omap_ep_disable,
1213
1214 .alloc_request = omap_alloc_request,
1215 .free_request = omap_free_request,
1216
1217 .alloc_buffer = omap_alloc_buffer,
1218 .free_buffer = omap_free_buffer,
1219
1220 .queue = omap_ep_queue,
1221 .dequeue = omap_ep_dequeue,
1222
1223 .set_halt = omap_ep_set_halt,
1224 // fifo_status ... report bytes in fifo
1225 // fifo_flush ... flush fifo
1226};
1227
1228/*-------------------------------------------------------------------------*/
1229
1230static int omap_get_frame(struct usb_gadget *gadget)
1231{
1232 u16 sof = UDC_SOF_REG;
1233 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1234}
1235
1236static int omap_wakeup(struct usb_gadget *gadget)
1237{
1238 struct omap_udc *udc;
1239 unsigned long flags;
1240 int retval = -EHOSTUNREACH;
1241
1242 udc = container_of(gadget, struct omap_udc, gadget);
1243
1244 spin_lock_irqsave(&udc->lock, flags);
1245 if (udc->devstat & UDC_SUS) {
1246 /* NOTE: OTG spec erratum says that OTG devices may
1247 * issue wakeups without host enable.
1248 */
1249 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1250 DBG("remote wakeup...\n");
1251 UDC_SYSCON2_REG = UDC_RMT_WKP;
1252 retval = 0;
1253 }
1254
1255 /* NOTE: non-OTG systems may use SRP TOO... */
1256 } else if (!(udc->devstat & UDC_ATT)) {
1257 if (udc->transceiver)
1258 retval = otg_start_srp(udc->transceiver);
1259 }
1260 spin_unlock_irqrestore(&udc->lock, flags);
1261
1262 return retval;
1263}
1264
1265static int
1266omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1267{
1268 struct omap_udc *udc;
1269 unsigned long flags;
1270 u16 syscon1;
1271
1272 udc = container_of(gadget, struct omap_udc, gadget);
1273 spin_lock_irqsave(&udc->lock, flags);
1274 syscon1 = UDC_SYSCON1_REG;
1275 if (is_selfpowered)
1276 syscon1 |= UDC_SELF_PWR;
1277 else
1278 syscon1 &= ~UDC_SELF_PWR;
1279 UDC_SYSCON1_REG = syscon1;
1280 spin_unlock_irqrestore(&udc->lock, flags);
1281
1282 return 0;
1283}
1284
1285static int can_pullup(struct omap_udc *udc)
1286{
1287 return udc->driver && udc->softconnect && udc->vbus_active;
1288}
1289
1290static void pullup_enable(struct omap_udc *udc)
1291{
313980c9
DB		 1292 udc->gadget.dev.parent->power.power_state = PMSG_ON;
1293 udc->gadget.dev.power.power_state = PMSG_ON;
1da177e4
LT		 1294 UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1295#ifndef CONFIG_USB_OTG
1296 if (!cpu_is_omap15xx())
1297 OTG_CTRL_REG |= OTG_BSESSVLD;
1298#endif
1299 UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1300}
1301
1302static void pullup_disable(struct omap_udc *udc)
1303{
1304#ifndef CONFIG_USB_OTG
1305 if (!cpu_is_omap15xx())
1306 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1307#endif
1308 UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1309 UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1310}
1311
e6a6e472
DB		 1312static struct omap_udc *udc;
1313
1314static void omap_udc_enable_clock(int enable)
1315{
1316 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1317 return;
1318
1319 if (enable) {
1320 clk_enable(udc->dc_clk);
1321 clk_enable(udc->hhc_clk);
1322 udelay(100);
1323 } else {
1324 clk_disable(udc->hhc_clk);
1325 clk_disable(udc->dc_clk);
1326 }
1327}
1328
1da177e4
LT		 1329/*
1330 * Called by whatever detects VBUS sessions: external transceiver
1331 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1332 */
1333static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1334{
1335 struct omap_udc *udc;
1336 unsigned long flags;
1337
1338 udc = container_of(gadget, struct omap_udc, gadget);
1339 spin_lock_irqsave(&udc->lock, flags);
1340 VDBG("VBUS %s\n", is_active ? "on" : "off");
1341 udc->vbus_active = (is_active != 0);
1342 if (cpu_is_omap15xx()) {
1343 /* "software" detect, ignored if !VBUS_MODE_1510 */
1344 if (is_active)
1345 FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1346 else
1347 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1348 }
e6a6e472
DB		 1349 if (udc->dc_clk != NULL && is_active) {
1350 if (!udc->clk_requested) {
1351 omap_udc_enable_clock(1);
1352 udc->clk_requested = 1;
1353 }
1354 }
1da177e4
LT		 1355 if (can_pullup(udc))
1356 pullup_enable(udc);
1357 else
1358 pullup_disable(udc);
e6a6e472
DB		 1359 if (udc->dc_clk != NULL && !is_active) {
1360 if (udc->clk_requested) {
1361 omap_udc_enable_clock(0);
1362 udc->clk_requested = 0;
1363 }
1364 }
1da177e4
LT		 1365 spin_unlock_irqrestore(&udc->lock, flags);
1366 return 0;
1367}
1368
1369static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1370{
1371 struct omap_udc *udc;
1372
1373 udc = container_of(gadget, struct omap_udc, gadget);
1374 if (udc->transceiver)
1375 return otg_set_power(udc->transceiver, mA);
1376 return -EOPNOTSUPP;
1377}
1378
1379static int omap_pullup(struct usb_gadget *gadget, int is_on)
1380{
1381 struct omap_udc *udc;
1382 unsigned long flags;
1383
1384 udc = container_of(gadget, struct omap_udc, gadget);
1385 spin_lock_irqsave(&udc->lock, flags);
1386 udc->softconnect = (is_on != 0);
1387 if (can_pullup(udc))
1388 pullup_enable(udc);
1389 else
1390 pullup_disable(udc);
1391 spin_unlock_irqrestore(&udc->lock, flags);
1392 return 0;
1393}
1394
1395static struct usb_gadget_ops omap_gadget_ops = {
1396 .get_frame = omap_get_frame,
1397 .wakeup = omap_wakeup,
1398 .set_selfpowered = omap_set_selfpowered,
1399 .vbus_session = omap_vbus_session,
1400 .vbus_draw = omap_vbus_draw,
1401 .pullup = omap_pullup,
1402};
1403
1404/*-------------------------------------------------------------------------*/
1405
1406/* dequeue ALL requests; caller holds udc->lock */
1407static void nuke(struct omap_ep *ep, int status)
1408{
1409 struct omap_req *req;
1410
1411 ep->stopped = 1;
1412
1413 if (use_dma && ep->dma_channel)
1414 dma_channel_release(ep);
1415
1416 use_ep(ep, 0);
1417 UDC_CTRL_REG = UDC_CLR_EP;
1418 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1419 UDC_CTRL_REG = UDC_SET_HALT;
1420
1421 while (!list_empty(&ep->queue)) {
1422 req = list_entry(ep->queue.next, struct omap_req, queue);
1423 done(ep, req, status);
1424 }
1425}
1426
1427/* caller holds udc->lock */
1428static void udc_quiesce(struct omap_udc *udc)
1429{
1430 struct omap_ep *ep;
1431
1432 udc->gadget.speed = USB_SPEED_UNKNOWN;
1433 nuke(&udc->ep[0], -ESHUTDOWN);
1434 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1435 nuke(ep, -ESHUTDOWN);
1436}
1437
1438/*-------------------------------------------------------------------------*/
1439
1440static void update_otg(struct omap_udc *udc)
1441{
1442 u16 devstat;
1443
1444 if (!udc->gadget.is_otg)
1445 return;
1446
1447 if (OTG_CTRL_REG & OTG_ID)
1448 devstat = UDC_DEVSTAT_REG;
1449 else
1450 devstat = 0;
1451
1452 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1453 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1454 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1455
1456 /* Enable HNP early, avoiding races on suspend irq path.
1457 * ASSUMES OTG state machine B_BUS_REQ input is true.
1458 */
1459 if (udc->gadget.b_hnp_enable)
1460 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1461 & ~OTG_PULLUP;
1462}
1463
1464static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1465{
1466 struct omap_ep *ep0 = &udc->ep[0];
313980c9 1467 struct omap_req *req = NULL;
1da177e4
LT		 1468
1469 ep0->irqs++;
1470
1471 /* Clear any pending requests and then scrub any rx/tx state
1472 * before starting to handle the SETUP request.
1473 */
1474 if (irq_src & UDC_SETUP) {
1475 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1476
1477 nuke(ep0, 0);
1478 if (ack) {
1479 UDC_IRQ_SRC_REG = ack;
1480 irq_src = UDC_SETUP;
1481 }
1482 }
1483
e6a6e472 1484 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1da177e4
LT		 1485 * This driver uses only uses protocol stalls (ep0 never halts),
1486 * and if we got this far the gadget driver already had a
1487 * chance to stall. Tries to be forgiving of host oddities.
1488 *
1489 * NOTE: the last chance gadget drivers have to stall control
1490 * requests is during their request completion callback.
1491 */
1492 if (!list_empty(&ep0->queue))
1493 req = container_of(ep0->queue.next, struct omap_req, queue);
1494
1495 /* IN == TX to host */
1496 if (irq_src & UDC_EP0_TX) {
1497 int stat;
1498
1499 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1500 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1501 stat = UDC_STAT_FLG_REG;
1502 if (stat & UDC_ACK) {
1503 if (udc->ep0_in) {
1504 /* write next IN packet from response,
1505 * or set up the status stage.
1506 */
1507 if (req)
1508 stat = write_fifo(ep0, req);
1509 UDC_EP_NUM_REG = UDC_EP_DIR;
1510 if (!req && udc->ep0_pending) {
1511 UDC_EP_NUM_REG = UDC_EP_SEL;
1512 UDC_CTRL_REG = UDC_CLR_EP;
1513 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1514 UDC_EP_NUM_REG = 0;
1515 udc->ep0_pending = 0;
1516 } /* else: 6 wait states before it'll tx */
1517 } else {
1518 /* ack status stage of OUT transfer */
1519 UDC_EP_NUM_REG = UDC_EP_DIR;
1520 if (req)
1521 done(ep0, req, 0);
1522 }
313980c9 1523 req = NULL;
1da177e4
LT		 1524 } else if (stat & UDC_STALL) {
1525 UDC_CTRL_REG = UDC_CLR_HALT;
1526 UDC_EP_NUM_REG = UDC_EP_DIR;
1527 } else {
1528 UDC_EP_NUM_REG = UDC_EP_DIR;
1529 }
1530 }
1531
1532 /* OUT == RX from host */
1533 if (irq_src & UDC_EP0_RX) {
1534 int stat;
1535
1536 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1537 UDC_EP_NUM_REG = UDC_EP_SEL;
1538 stat = UDC_STAT_FLG_REG;
1539 if (stat & UDC_ACK) {
1540 if (!udc->ep0_in) {
1541 stat = 0;
1542 /* read next OUT packet of request, maybe
1543 * reactiviting the fifo; stall on errors.
1544 */
1545 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1546 UDC_SYSCON2_REG = UDC_STALL_CMD;
1547 udc->ep0_pending = 0;
1548 stat = 0;
1549 } else if (stat == 0)
1550 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1551 UDC_EP_NUM_REG = 0;
e6a6e472 1552
1da177e4
LT		 1553 /* activate status stage */
1554 if (stat == 1) {
1555 done(ep0, req, 0);
1556 /* that may have STALLed ep0... */
1557 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1558 UDC_CTRL_REG = UDC_CLR_EP;
1559 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1560 UDC_EP_NUM_REG = UDC_EP_DIR;
1561 udc->ep0_pending = 0;
1562 }
1563 } else {
1564 /* ack status stage of IN transfer */
1565 UDC_EP_NUM_REG = 0;
1566 if (req)
1567 done(ep0, req, 0);
1568 }
1569 } else if (stat & UDC_STALL) {
1570 UDC_CTRL_REG = UDC_CLR_HALT;
1571 UDC_EP_NUM_REG = 0;
1572 } else {
1573 UDC_EP_NUM_REG = 0;
1574 }
1575 }
1576
1577 /* SETUP starts all control transfers */
1578 if (irq_src & UDC_SETUP) {
1579 union u {
1580 u16 word[4];
1581 struct usb_ctrlrequest r;
1582 } u;
1583 int status = -EINVAL;
1584 struct omap_ep *ep;
1585
1586 /* read the (latest) SETUP message */
1587 do {
1588 UDC_EP_NUM_REG = UDC_SETUP_SEL;
1589 /* two bytes at a time */
1590 u.word[0] = UDC_DATA_REG;
1591 u.word[1] = UDC_DATA_REG;
1592 u.word[2] = UDC_DATA_REG;
1593 u.word[3] = UDC_DATA_REG;
1594 UDC_EP_NUM_REG = 0;
1595 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1da177e4 1596
65111084
DB		 1597#define w_value le16_to_cpup (&u.r.wValue)
1598#define w_index le16_to_cpup (&u.r.wIndex)
1599#define w_length le16_to_cpup (&u.r.wLength)
1600
1da177e4
LT		 1601 /* Delegate almost all control requests to the gadget driver,
1602 * except for a handful of ch9 status/feature requests that
1603 * hardware doesn't autodecode _and_ the gadget API hides.
1604 */
1605 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1606 udc->ep0_set_config = 0;
1607 udc->ep0_pending = 1;
1608 ep0->stopped = 0;
1609 ep0->ackwait = 0;
1610 switch (u.r.bRequest) {
1611 case USB_REQ_SET_CONFIGURATION:
1612 /* udc needs to know when ep != 0 is valid */
1613 if (u.r.bRequestType != USB_RECIP_DEVICE)
1614 goto delegate;
65111084 1615 if (w_length != 0)
1da177e4
LT		 1616 goto do_stall;
1617 udc->ep0_set_config = 1;
65111084
DB		 1618 udc->ep0_reset_config = (w_value == 0);
1619 VDBG("set config %d\n", w_value);
1da177e4
LT		 1620
1621 /* update udc NOW since gadget driver may start
1622 * queueing requests immediately; clear config
1623 * later if it fails the request.
1624 */
1625 if (udc->ep0_reset_config)
1626 UDC_SYSCON2_REG = UDC_CLR_CFG;
1627 else
1628 UDC_SYSCON2_REG = UDC_DEV_CFG;
1629 update_otg(udc);
1630 goto delegate;
1631 case USB_REQ_CLEAR_FEATURE:
1632 /* clear endpoint halt */
1633 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1634 goto delegate;
65111084
DB		 1635 if (w_value != USB_ENDPOINT_HALT
1636 || w_length != 0)
1da177e4 1637 goto do_stall;
65111084 1638 ep = &udc->ep[w_index & 0xf];
1da177e4 1639 if (ep != ep0) {
65111084 1640 if (w_index & USB_DIR_IN)
1da177e4
LT		 1641 ep += 16;
1642 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1643 || !ep->desc)
1644 goto do_stall;
1645 use_ep(ep, 0);
65111084 1646 UDC_CTRL_REG = udc->clr_halt;
1da177e4
LT		 1647 ep->ackwait = 0;
1648 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1649 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1650 ep->ackwait = 1 + ep->double_buf;
1651 }
313980c9
DB		 1652 /* NOTE: assumes the host behaves sanely,
1653 * only clearing real halts. Else we may
1654 * need to kill pending transfers and then
1655 * restart the queue... very messy for DMA!
1656 */
1da177e4
LT		 1657 }
1658 VDBG("%s halt cleared by host\n", ep->name);
1659 goto ep0out_status_stage;
1660 case USB_REQ_SET_FEATURE:
1661 /* set endpoint halt */
1662 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1663 goto delegate;
65111084
DB		 1664 if (w_value != USB_ENDPOINT_HALT
1665 || w_length != 0)
1da177e4 1666 goto do_stall;
65111084
DB		 1667 ep = &udc->ep[w_index & 0xf];
1668 if (w_index & USB_DIR_IN)
1da177e4
LT		 1669 ep += 16;
1670 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1671 || ep == ep0 || !ep->desc)
1672 goto do_stall;
1673 if (use_dma && ep->has_dma) {
1674 /* this has rude side-effects (aborts) and
1675 * can't really work if DMA-IN is active
1676 */
1677 DBG("%s host set_halt, NYET \n", ep->name);
1678 goto do_stall;
1679 }
1680 use_ep(ep, 0);
1681 /* can't halt if fifo isn't empty... */
1682 UDC_CTRL_REG = UDC_CLR_EP;
1683 UDC_CTRL_REG = UDC_SET_HALT;
1684 VDBG("%s halted by host\n", ep->name);
1685ep0out_status_stage:
1686 status = 0;
1687 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1688 UDC_CTRL_REG = UDC_CLR_EP;
1689 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1690 UDC_EP_NUM_REG = UDC_EP_DIR;
1691 udc->ep0_pending = 0;
1692 break;
1693 case USB_REQ_GET_STATUS:
1694 /* return interface status. if we were pedantic,
1695 * we'd detect non-existent interfaces, and stall.
1696 */
1697 if (u.r.bRequestType
1698 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1699 goto delegate;
1700 /* return two zero bytes */
1701 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1702 UDC_DATA_REG = 0;
1703 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1704 UDC_EP_NUM_REG = UDC_EP_DIR;
1705 status = 0;
65111084 1706 VDBG("GET_STATUS, interface %d\n", w_index);
1da177e4
LT		 1707 /* next, status stage */
1708 break;
1709 default:
1710delegate:
1711 /* activate the ep0out fifo right away */
65111084 1712 if (!udc->ep0_in && w_length) {
1da177e4
LT		 1713 UDC_EP_NUM_REG = 0;
1714 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1715 }
1716
1717 /* gadget drivers see class/vendor specific requests,
1718 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1719 * and more
1720 */
1721 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1722 u.r.bRequestType, u.r.bRequest,
65111084
DB		 1723 w_value, w_index, w_length);
1724
1725#undef w_value
1726#undef w_index
1727#undef w_length
1da177e4
LT		 1728
1729 /* The gadget driver may return an error here,
1730 * causing an immediate protocol stall.
1731 *
1732 * Else it must issue a response, either queueing a
1733 * response buffer for the DATA stage, or halting ep0
1734 * (causing a protocol stall, not a real halt). A
1735 * zero length buffer means no DATA stage.
1736 *
1737 * It's fine to issue that response after the setup()
1738 * call returns, and this IRQ was handled.
1739 */
1740 udc->ep0_setup = 1;
1741 spin_unlock(&udc->lock);
1742 status = udc->driver->setup (&udc->gadget, &u.r);
1743 spin_lock(&udc->lock);
1744 udc->ep0_setup = 0;
1745 }
1746
1747 if (status < 0) {
1748do_stall:
1749 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1750 u.r.bRequestType, u.r.bRequest, status);
1751 if (udc->ep0_set_config) {
1752 if (udc->ep0_reset_config)
1753 WARN("error resetting config?\n");
1754 else
1755 UDC_SYSCON2_REG = UDC_CLR_CFG;
1756 }
1757 UDC_SYSCON2_REG = UDC_STALL_CMD;
1758 udc->ep0_pending = 0;
1759 }
1760 }
1761}
1762
1763/*-------------------------------------------------------------------------*/
1764
1765#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1766
1767static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1768{
1769 u16 devstat, change;
1770
1771 devstat = UDC_DEVSTAT_REG;
1772 change = devstat ^ udc->devstat;
1773 udc->devstat = devstat;
1774
1775 if (change & (UDC_USB_RESET|UDC_ATT)) {
1776 udc_quiesce(udc);
1777
1778 if (change & UDC_ATT) {
1779 /* driver for any external transceiver will
1780 * have called omap_vbus_session() already
1781 */
1782 if (devstat & UDC_ATT) {
1783 udc->gadget.speed = USB_SPEED_FULL;
1784 VDBG("connect\n");
1785 if (!udc->transceiver)
1786 pullup_enable(udc);
1787 // if (driver->connect) call it
1788 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1789 udc->gadget.speed = USB_SPEED_UNKNOWN;
1790 if (!udc->transceiver)
1791 pullup_disable(udc);
1792 DBG("disconnect, gadget %s\n",
1793 udc->driver->driver.name);
1794 if (udc->driver->disconnect) {
1795 spin_unlock(&udc->lock);
1796 udc->driver->disconnect(&udc->gadget);
1797 spin_lock(&udc->lock);
1798 }
1799 }
1800 change &= ~UDC_ATT;
1801 }
1802
1803 if (change & UDC_USB_RESET) {
1804 if (devstat & UDC_USB_RESET) {
1805 VDBG("RESET=1\n");
1806 } else {
1807 udc->gadget.speed = USB_SPEED_FULL;
1808 INFO("USB reset done, gadget %s\n",
1809 udc->driver->driver.name);
1810 /* ep0 traffic is legal from now on */
1811 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1812 }
1813 change &= ~UDC_USB_RESET;
1814 }
1815 }
1816 if (change & UDC_SUS) {
1817 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1818 // FIXME tell isp1301 to suspend/resume (?)
1819 if (devstat & UDC_SUS) {
1820 VDBG("suspend\n");
1821 update_otg(udc);
1822 /* HNP could be under way already */
1823 if (udc->gadget.speed == USB_SPEED_FULL
1824 && udc->driver->suspend) {
1825 spin_unlock(&udc->lock);
1826 udc->driver->suspend(&udc->gadget);
1827 spin_lock(&udc->lock);
1828 }
4e67185a
JY		 1829 if (udc->transceiver)
1830 otg_set_suspend(udc->transceiver, 1);
1da177e4
LT		 1831 } else {
1832 VDBG("resume\n");
4e67185a
JY		 1833 if (udc->transceiver)
1834 otg_set_suspend(udc->transceiver, 0);
1da177e4
LT		 1835 if (udc->gadget.speed == USB_SPEED_FULL
1836 && udc->driver->resume) {
1837 spin_unlock(&udc->lock);
1838 udc->driver->resume(&udc->gadget);
1839 spin_lock(&udc->lock);
1840 }
1841 }
1842 }
1843 change &= ~UDC_SUS;
1844 }
1845 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1846 update_otg(udc);
1847 change &= ~OTG_FLAGS;
1848 }
1849
1850 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1851 if (change)
1852 VDBG("devstat %03x, ignore change %03x\n",
1853 devstat, change);
1854
1855 UDC_IRQ_SRC_REG = UDC_DS_CHG;
1856}
1857
7d12e780 1858static irqreturn_t omap_udc_irq(int irq, void *_udc)
1da177e4
LT		 1859{
1860 struct omap_udc *udc = _udc;
1861 u16 irq_src;
1862 irqreturn_t status = IRQ_NONE;
1863 unsigned long flags;
1864
1865 spin_lock_irqsave(&udc->lock, flags);
1866 irq_src = UDC_IRQ_SRC_REG;
1867
1868 /* Device state change (usb ch9 stuff) */
1869 if (irq_src & UDC_DS_CHG) {
1870 devstate_irq(_udc, irq_src);
1871 status = IRQ_HANDLED;
1872 irq_src &= ~UDC_DS_CHG;
1873 }
1874
1875 /* EP0 control transfers */
1876 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1877 ep0_irq(_udc, irq_src);
1878 status = IRQ_HANDLED;
1879 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1880 }
1881
1882 /* DMA transfer completion */
1883 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1884 dma_irq(_udc, irq_src);
1885 status = IRQ_HANDLED;
1886 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1887 }
1888
1889 irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1890 if (irq_src)
1891 DBG("udc_irq, unhandled %03x\n", irq_src);
1892 spin_unlock_irqrestore(&udc->lock, flags);
1893
1894 return status;
1895}
1896
1897/* workaround for seemingly-lost IRQs for RX ACKs... */
1898#define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1899#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1900
1901static void pio_out_timer(unsigned long _ep)
1902{
1903 struct omap_ep *ep = (void *) _ep;
1904 unsigned long flags;
1905 u16 stat_flg;
1906
1907 spin_lock_irqsave(&ep->udc->lock, flags);
1908 if (!list_empty(&ep->queue) && ep->ackwait) {
e6a6e472 1909 use_ep(ep, UDC_EP_SEL);
1da177e4
LT		 1910 stat_flg = UDC_STAT_FLG_REG;
1911
1912 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1913 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1914 struct omap_req *req;
1915
1916 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1917 req = container_of(ep->queue.next,
1918 struct omap_req, queue);
1da177e4
LT		 1919 (void) read_fifo(ep, req);
1920 UDC_EP_NUM_REG = ep->bEndpointAddress;
1921 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1922 ep->ackwait = 1 + ep->double_buf;
e6a6e472
DB		 1923 } else
1924 deselect_ep();
1da177e4
LT		 1925 }
1926 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1927 spin_unlock_irqrestore(&ep->udc->lock, flags);
1928}
1929
7d12e780 1930static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1da177e4
LT		 1931{
1932 u16 epn_stat, irq_src;
1933 irqreturn_t status = IRQ_NONE;
1934 struct omap_ep *ep;
1935 int epnum;
1936 struct omap_udc *udc = _dev;
1937 struct omap_req *req;
1938 unsigned long flags;
1939
1940 spin_lock_irqsave(&udc->lock, flags);
1941 epn_stat = UDC_EPN_STAT_REG;
1942 irq_src = UDC_IRQ_SRC_REG;
1943
1944 /* handle OUT first, to avoid some wasteful NAKs */
1945 if (irq_src & UDC_EPN_RX) {
1946 epnum = (epn_stat >> 8) & 0x0f;
1947 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1948 status = IRQ_HANDLED;
1949 ep = &udc->ep[epnum];
1950 ep->irqs++;
1951
1952 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1953 ep->fnf = 0;
1954 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1955 ep->ackwait--;
1956 if (!list_empty(&ep->queue)) {
1957 int stat;
1958 req = container_of(ep->queue.next,
1959 struct omap_req, queue);
1960 stat = read_fifo(ep, req);
1961 if (!ep->double_buf)
1962 ep->fnf = 1;
1963 }
1964 }
1965 /* min 6 clock delay before clearing EP_SEL ... */
1966 epn_stat = UDC_EPN_STAT_REG;
1967 epn_stat = UDC_EPN_STAT_REG;
1968 UDC_EP_NUM_REG = epnum;
1969
1970 /* enabling fifo _after_ clearing ACK, contrary to docs,
1971 * reduces lossage; timer still needed though (sigh).
1972 */
1973 if (ep->fnf) {
1974 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1975 ep->ackwait = 1 + ep->double_buf;
1976 }
1977 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1978 }
1979
1980 /* then IN transfers */
1981 else if (irq_src & UDC_EPN_TX) {
1982 epnum = epn_stat & 0x0f;
1983 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1984 status = IRQ_HANDLED;
1985 ep = &udc->ep[16 + epnum];
1986 ep->irqs++;
1987
1988 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1989 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1990 ep->ackwait = 0;
1991 if (!list_empty(&ep->queue)) {
1992 req = container_of(ep->queue.next,
1993 struct omap_req, queue);
1994 (void) write_fifo(ep, req);
1995 }
1996 }
1997 /* min 6 clock delay before clearing EP_SEL ... */
1998 epn_stat = UDC_EPN_STAT_REG;
1999 epn_stat = UDC_EPN_STAT_REG;
2000 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
2001 /* then 6 clocks before it'd tx */
2002 }
2003
2004 spin_unlock_irqrestore(&udc->lock, flags);
2005 return status;
2006}
2007
2008#ifdef USE_ISO
7d12e780 2009static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1da177e4
LT		 2010{
2011 struct omap_udc *udc = _dev;
2012 struct omap_ep *ep;
2013 int pending = 0;
2014 unsigned long flags;
2015
2016 spin_lock_irqsave(&udc->lock, flags);
2017
2018 /* handle all non-DMA ISO transfers */
2019 list_for_each_entry (ep, &udc->iso, iso) {
2020 u16 stat;
2021 struct omap_req *req;
2022
2023 if (ep->has_dma || list_empty(&ep->queue))
2024 continue;
2025 req = list_entry(ep->queue.next, struct omap_req, queue);
2026
2027 use_ep(ep, UDC_EP_SEL);
2028 stat = UDC_STAT_FLG_REG;
2029
2030 /* NOTE: like the other controller drivers, this isn't
2031 * currently reporting lost or damaged frames.
2032 */
2033 if (ep->bEndpointAddress & USB_DIR_IN) {
2034 if (stat & UDC_MISS_IN)
2035 /* done(ep, req, -EPROTO) */;
2036 else
2037 write_fifo(ep, req);
2038 } else {
2039 int status = 0;
2040
2041 if (stat & UDC_NO_RXPACKET)
2042 status = -EREMOTEIO;
2043 else if (stat & UDC_ISO_ERR)
2044 status = -EILSEQ;
2045 else if (stat & UDC_DATA_FLUSH)
2046 status = -ENOSR;
2047
2048 if (status)
2049 /* done(ep, req, status) */;
2050 else
2051 read_fifo(ep, req);
2052 }
2053 deselect_ep();
2054 /* 6 wait states before next EP */
2055
2056 ep->irqs++;
2057 if (!list_empty(&ep->queue))
2058 pending = 1;
2059 }
2060 if (!pending)
2061 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2062 UDC_IRQ_SRC_REG = UDC_SOF;
2063
2064 spin_unlock_irqrestore(&udc->lock, flags);
2065 return IRQ_HANDLED;
2066}
2067#endif
2068
2069/*-------------------------------------------------------------------------*/
2070
e6a6e472
DB		 2071static inline int machine_needs_vbus_session(void)
2072{
2073 return (machine_is_omap_innovator()
2074 || machine_is_omap_osk()
2075 || machine_is_omap_apollon()
2076#ifndef CONFIG_MACH_OMAP_H4_OTG
2077 || machine_is_omap_h4()
2078#endif
2079 || machine_is_sx1()
2080 );
2081}
1da177e4
LT		 2082
2083int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2084{
2085 int status = -ENODEV;
2086 struct omap_ep *ep;
2087 unsigned long flags;
2088
2089 /* basic sanity tests */
2090 if (!udc)
2091 return -ENODEV;
2092 if (!driver
2093 // FIXME if otg, check: driver->is_otg
2094 || driver->speed < USB_SPEED_FULL
2095 || !driver->bind
1da177e4
LT		 2096 || !driver->setup)
2097 return -EINVAL;
2098
2099 spin_lock_irqsave(&udc->lock, flags);
2100 if (udc->driver) {
2101 spin_unlock_irqrestore(&udc->lock, flags);
2102 return -EBUSY;
2103 }
2104
2105 /* reset state */
2106 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2107 ep->irqs = 0;
2108 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2109 continue;
2110 use_ep(ep, 0);
2111 UDC_CTRL_REG = UDC_SET_HALT;
2112 }
2113 udc->ep0_pending = 0;
2114 udc->ep[0].irqs = 0;
2115 udc->softconnect = 1;
2116
2117 /* hook up the driver */
313980c9 2118 driver->driver.bus = NULL;
1da177e4
LT		 2119 udc->driver = driver;
2120 udc->gadget.dev.driver = &driver->driver;
2121 spin_unlock_irqrestore(&udc->lock, flags);
2122
e6a6e472
DB		 2123 if (udc->dc_clk != NULL)
2124 omap_udc_enable_clock(1);
2125
1da177e4
LT		 2126 status = driver->bind (&udc->gadget);
2127 if (status) {
2128 DBG("bind to %s --> %d\n", driver->driver.name, status);
313980c9
DB		 2129 udc->gadget.dev.driver = NULL;
2130 udc->driver = NULL;
1da177e4
LT		 2131 goto done;
2132 }
2133 DBG("bound to driver %s\n", driver->driver.name);
2134
2135 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2136
2137 /* connect to bus through transceiver */
2138 if (udc->transceiver) {
2139 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2140 if (status < 0) {
2141 ERR("can't bind to transceiver\n");
6bea476c
DB		 2142 if (driver->unbind) {
2143 driver->unbind (&udc->gadget);
2144 udc->gadget.dev.driver = NULL;
2145 udc->driver = NULL;
2146 }
1da177e4
LT		 2147 goto done;
2148 }
2149 } else {
2150 if (can_pullup(udc))
2151 pullup_enable (udc);
2152 else
2153 pullup_disable (udc);
2154 }
2155
2156 /* boards that don't have VBUS sensing can't autogate 48MHz;
2157 * can't enter deep sleep while a gadget driver is active.
2158 */
e6a6e472 2159 if (machine_needs_vbus_session())
1da177e4
LT		 2160 omap_vbus_session(&udc->gadget, 1);
2161
2162done:
e6a6e472
DB		 2163 if (udc->dc_clk != NULL)
2164 omap_udc_enable_clock(0);
1da177e4
LT		 2165 return status;
2166}
2167EXPORT_SYMBOL(usb_gadget_register_driver);
2168
2169int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2170{
2171 unsigned long flags;
2172 int status = -ENODEV;
2173
2174 if (!udc)
2175 return -ENODEV;
6bea476c 2176 if (!driver || driver != udc->driver || !driver->unbind)
1da177e4
LT		 2177 return -EINVAL;
2178
e6a6e472
DB		 2179 if (udc->dc_clk != NULL)
2180 omap_udc_enable_clock(1);
2181
2182 if (machine_needs_vbus_session())
1da177e4
LT		 2183 omap_vbus_session(&udc->gadget, 0);
2184
2185 if (udc->transceiver)
313980c9 2186 (void) otg_set_peripheral(udc->transceiver, NULL);
1da177e4
LT		 2187 else
2188 pullup_disable(udc);
2189
2190 spin_lock_irqsave(&udc->lock, flags);
2191 udc_quiesce(udc);
2192 spin_unlock_irqrestore(&udc->lock, flags);
2193
2194 driver->unbind(&udc->gadget);
313980c9
DB		 2195 udc->gadget.dev.driver = NULL;
2196 udc->driver = NULL;
1da177e4 2197
e6a6e472
DB		 2198 if (udc->dc_clk != NULL)
2199 omap_udc_enable_clock(0);
1da177e4
LT		 2200 DBG("unregistered driver '%s'\n", driver->driver.name);
2201 return status;
2202}
2203EXPORT_SYMBOL(usb_gadget_unregister_driver);
2204
2205
2206/*-------------------------------------------------------------------------*/
2207
2208#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2209
2210#include <linux/seq_file.h>
2211
2212static const char proc_filename[] = "driver/udc";
2213
2214#define FOURBITS "%s%s%s%s"
2215#define EIGHTBITS FOURBITS FOURBITS
2216
2217static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2218{
2219 u16 stat_flg;
2220 struct omap_req *req;
2221 char buf[20];
2222
2223 use_ep(ep, 0);
2224
2225 if (use_dma && ep->has_dma)
2226 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2227 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2228 ep->dma_channel - 1, ep->lch);
2229 else
2230 buf[0] = 0;
2231
2232 stat_flg = UDC_STAT_FLG_REG;
2233 seq_printf(s,
2234 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2235 ep->name, buf,
2236 ep->double_buf ? "dbuf " : "",
2237 ({char *s; switch(ep->ackwait){
2238 case 0: s = ""; break;
2239 case 1: s = "(ackw) "; break;
2240 case 2: s = "(ackw2) "; break;
2241 default: s = "(?) "; break;
2242 } s;}),
2243 ep->irqs, stat_flg,
2244 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2245 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2246 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2247 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2248 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2249 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2250 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2251 (stat_flg & UDC_STALL) ? "STALL " : "",
2252 (stat_flg & UDC_NAK) ? "NAK " : "",
2253 (stat_flg & UDC_ACK) ? "ACK " : "",
2254 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2255 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2256 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2257
2258 if (list_empty (&ep->queue))
2259 seq_printf(s, "\t(queue empty)\n");
2260 else
2261 list_for_each_entry (req, &ep->queue, queue) {
2262 unsigned length = req->req.actual;
2263
2264 if (use_dma && buf[0]) {
2265 length += ((ep->bEndpointAddress & USB_DIR_IN)
2266 ? dma_src_len : dma_dest_len)
2267 (ep, req->req.dma + length);
2268 buf[0] = 0;
2269 }
2270 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2271 &req->req, length,
2272 req->req.length, req->req.buf);
2273 }
2274}
2275
2276static char *trx_mode(unsigned m, int enabled)
2277{
2278 switch (m) {
2279 case 0: return enabled ? "*6wire" : "unused";
2280 case 1: return "4wire";
2281 case 2: return "3wire";
e6a6e472 2282 case 3: return "6wire";
1da177e4
LT		 2283 default: return "unknown";
2284 }
2285}
2286
2287static int proc_otg_show(struct seq_file *s)
2288{
2289 u32 tmp;
2290 u32 trans;
e6a6e472 2291 char *ctrl_name;
1da177e4
LT		 2292
2293 tmp = OTG_REV_REG;
e6a6e472
DB		 2294 if (cpu_is_omap24xx()) {
2295 ctrl_name = "control_devconf";
2296 trans = CONTROL_DEVCONF_REG;
2297 } else {
2298 ctrl_name = "tranceiver_ctrl";
2299 trans = USB_TRANSCEIVER_CTRL_REG;
2300 }
2301 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2302 tmp >> 4, tmp & 0xf, ctrl_name, trans);
1da177e4
LT		 2303 tmp = OTG_SYSCON_1_REG;
2304 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2305 FOURBITS "\n", tmp,
2306 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2307 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
65111084 2308 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
1da177e4
LT		 2309 ? "internal"
2310 : trx_mode(USB0_TRX_MODE(tmp), 1),
2311 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2312 (tmp & HST_IDLE_EN) ? " !host" : "",
2313 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2314 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2315 tmp = OTG_SYSCON_2_REG;
2316 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2317 " b_ase_brst=%d hmc=%d\n", tmp,
2318 (tmp & OTG_EN) ? " otg_en" : "",
2319 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2320 // much more SRP stuff
2321 (tmp & SRP_DATA) ? " srp_data" : "",
2322 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2323 (tmp & OTG_PADEN) ? " otg_paden" : "",
2324 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2325 (tmp & UHOST_EN) ? " uhost_en" : "",
2326 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2327 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2328 B_ASE_BRST(tmp),
2329 OTG_HMC(tmp));
2330 tmp = OTG_CTRL_REG;
2331 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2332 (tmp & OTG_ASESSVLD) ? " asess" : "",
2333 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2334 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2335 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2336 (tmp & OTG_ID) ? " id" : "",
2337 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2338 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2339 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2340 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2341 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2342 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2343 (tmp & OTG_PULLDOWN) ? " down" : "",
2344 (tmp & OTG_PULLUP) ? " up" : "",
2345 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2346 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2347 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2348 (tmp & OTG_PU_ID) ? " pu_id" : ""
2349 );
2350 tmp = OTG_IRQ_EN_REG;
2351 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2352 tmp = OTG_IRQ_SRC_REG;
2353 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2354 tmp = OTG_OUTCTRL_REG;
2355 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2356 tmp = OTG_TEST_REG;
2357 seq_printf(s, "otg_test %04x" "\n", tmp);
313980c9 2358 return 0;
1da177e4
LT		 2359}
2360
2361static int proc_udc_show(struct seq_file *s, void *_)
2362{
2363 u32 tmp;
2364 struct omap_ep *ep;
2365 unsigned long flags;
2366
2367 spin_lock_irqsave(&udc->lock, flags);
2368
2369 seq_printf(s, "%s, version: " DRIVER_VERSION
2370#ifdef USE_ISO
2371 " (iso)"
2372#endif
2373 "%s\n",
2374 driver_desc,
2375 use_dma ? " (dma)" : "");
2376
e6a6e472 2377 tmp = UDC_REV_REG & 0xff;
1da177e4
LT		 2378 seq_printf(s,
2379 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2380 "hmc %d, transceiver %s\n",
2381 tmp >> 4, tmp & 0xf,
2382 fifo_mode,
2383 udc->driver ? udc->driver->driver.name : "(none)",
2384 HMC,
e6a6e472
DB		 2385 udc->transceiver
2386 ? udc->transceiver->label
2387 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2388 ? "external" : "(none)"));
2389 if (cpu_class_is_omap1()) {
2390 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2391 __REG16(ULPD_CLOCK_CTRL),
2392 __REG16(ULPD_SOFT_REQ),
2393 __REG16(ULPD_STATUS_REQ));
2394 }
1da177e4
LT		 2395
2396 /* OTG controller registers */
2397 if (!cpu_is_omap15xx())
2398 proc_otg_show(s);
2399
2400 tmp = UDC_SYSCON1_REG;
2401 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2402 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2403 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2404 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2405 (tmp & UDC_NAK_EN) ? " nak" : "",
2406 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2407 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2408 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2409 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2410 // syscon2 is write-only
2411
2412 /* UDC controller registers */
2413 if (!(tmp & UDC_PULLUP_EN)) {
2414 seq_printf(s, "(suspended)\n");
2415 spin_unlock_irqrestore(&udc->lock, flags);
2416 return 0;
2417 }
2418
2419 tmp = UDC_DEVSTAT_REG;
2420 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2421 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2422 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2423 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2424 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2425 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2426 (tmp & UDC_SUS) ? " SUS" : "",
2427 (tmp & UDC_CFG) ? " CFG" : "",
2428 (tmp & UDC_ADD) ? " ADD" : "",
2429 (tmp & UDC_DEF) ? " DEF" : "",
2430 (tmp & UDC_ATT) ? " ATT" : "");
2431 seq_printf(s, "sof %04x\n", UDC_SOF_REG);
2432 tmp = UDC_IRQ_EN_REG;
2433 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2434 (tmp & UDC_SOF_IE) ? " sof" : "",
2435 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2436 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2437 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2438 (tmp & UDC_EP0_IE) ? " ep0" : "");
2439 tmp = UDC_IRQ_SRC_REG;
2440 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2441 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2442 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2443 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2444 (tmp & UDC_SOF) ? " sof" : "",
2445 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2446 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2447 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2448 (tmp & UDC_SETUP) ? " setup" : "",
2449 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2450 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2451 if (use_dma) {
2452 unsigned i;
2453
2454 tmp = UDC_DMA_IRQ_EN_REG;
2455 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2456 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2457 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2458 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2459
2460 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2461 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2462 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2463
2464 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2465 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2466 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2467
2468 tmp = UDC_RXDMA_CFG_REG;
2469 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2470 if (tmp) {
2471 for (i = 0; i < 3; i++) {
2472 if ((tmp & (0x0f << (i * 4))) == 0)
2473 continue;
2474 seq_printf(s, "rxdma[%d] %04x\n", i,
2475 UDC_RXDMA_REG(i + 1));
2476 }
2477 }
2478 tmp = UDC_TXDMA_CFG_REG;
2479 seq_printf(s, "txdma_cfg %04x\n", tmp);
2480 if (tmp) {
2481 for (i = 0; i < 3; i++) {
2482 if (!(tmp & (0x0f << (i * 4))))
2483 continue;
2484 seq_printf(s, "txdma[%d] %04x\n", i,
2485 UDC_TXDMA_REG(i + 1));
2486 }
2487 }
2488 }
2489
2490 tmp = UDC_DEVSTAT_REG;
2491 if (tmp & UDC_ATT) {
2492 proc_ep_show(s, &udc->ep[0]);
2493 if (tmp & UDC_ADD) {
2494 list_for_each_entry (ep, &udc->gadget.ep_list,
2495 ep.ep_list) {
2496 if (ep->desc)
2497 proc_ep_show(s, ep);
2498 }
2499 }
2500 }
2501 spin_unlock_irqrestore(&udc->lock, flags);
2502 return 0;
2503}
2504
2505static int proc_udc_open(struct inode *inode, struct file *file)
2506{
313980c9 2507 return single_open(file, proc_udc_show, NULL);
1da177e4
LT		 2508}
2509
066202dd 2510static const struct file_operations proc_ops = {
1da177e4
LT		 2511 .open = proc_udc_open,
2512 .read = seq_read,
2513 .llseek = seq_lseek,
2514 .release = single_release,
2515};
2516
2517static void create_proc_file(void)
2518{
2519 struct proc_dir_entry *pde;
2520
2521 pde = create_proc_entry (proc_filename, 0, NULL);
2522 if (pde)
2523 pde->proc_fops = &proc_ops;
2524}
2525
2526static void remove_proc_file(void)
2527{
313980c9 2528 remove_proc_entry(proc_filename, NULL);
1da177e4
LT		 2529}
2530
2531#else
2532
2533static inline void create_proc_file(void) {}
2534static inline void remove_proc_file(void) {}
2535
2536#endif
2537
2538/*-------------------------------------------------------------------------*/
2539
2540/* Before this controller can enumerate, we need to pick an endpoint
2541 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2542 * buffer space among the endpoints we'll be operating.
65111084
DB		 2543 *
2544 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2545 * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that
2546 * capability yet though.
1da177e4
LT		 2547 */
2548static unsigned __init
2549omap_ep_setup(char *name, u8 addr, u8 type,
2550 unsigned buf, unsigned maxp, int dbuf)
2551{
2552 struct omap_ep *ep;
2553 u16 epn_rxtx = 0;
2554
2555 /* OUT endpoints first, then IN */
2556 ep = &udc->ep[addr & 0xf];
2557 if (addr & USB_DIR_IN)
2558 ep += 16;
2559
2560 /* in case of ep init table bugs */
2561 BUG_ON(ep->name[0]);
2562
2563 /* chip setup ... bit values are same for IN, OUT */
2564 if (type == USB_ENDPOINT_XFER_ISOC) {
2565 switch (maxp) {
2566 case 8: epn_rxtx = 0 << 12; break;
2567 case 16: epn_rxtx = 1 << 12; break;
2568 case 32: epn_rxtx = 2 << 12; break;
2569 case 64: epn_rxtx = 3 << 12; break;
2570 case 128: epn_rxtx = 4 << 12; break;
2571 case 256: epn_rxtx = 5 << 12; break;
2572 case 512: epn_rxtx = 6 << 12; break;
2573 default: BUG();
2574 }
2575 epn_rxtx |= UDC_EPN_RX_ISO;
2576 dbuf = 1;
2577 } else {
2578 /* double-buffering "not supported" on 15xx,
e6a6e472
DB		 2579 * and ignored for PIO-IN on newer chips
2580 * (for more reliable behavior)
1da177e4 2581 */
e6a6e472 2582 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
1da177e4
LT		 2583 dbuf = 0;
2584
2585 switch (maxp) {
2586 case 8: epn_rxtx = 0 << 12; break;
2587 case 16: epn_rxtx = 1 << 12; break;
2588 case 32: epn_rxtx = 2 << 12; break;
2589 case 64: epn_rxtx = 3 << 12; break;
2590 default: BUG();
2591 }
2592 if (dbuf && addr)
2593 epn_rxtx |= UDC_EPN_RX_DB;
2594 init_timer(&ep->timer);
2595 ep->timer.function = pio_out_timer;
2596 ep->timer.data = (unsigned long) ep;
2597 }
2598 if (addr)
2599 epn_rxtx |= UDC_EPN_RX_VALID;
2600 BUG_ON(buf & 0x07);
2601 epn_rxtx |= buf >> 3;
2602
2603 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2604 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2605
2606 if (addr & USB_DIR_IN)
2607 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2608 else
2609 UDC_EP_RX_REG(addr) = epn_rxtx;
2610
2611 /* next endpoint's buffer starts after this one's */
2612 buf += maxp;
2613 if (dbuf)
2614 buf += maxp;
2615 BUG_ON(buf > 2048);
2616
2617 /* set up driver data structures */
2618 BUG_ON(strlen(name) >= sizeof ep->name);
2619 strlcpy(ep->name, name, sizeof ep->name);
2620 INIT_LIST_HEAD(&ep->queue);
2621 INIT_LIST_HEAD(&ep->iso);
2622 ep->bEndpointAddress = addr;
2623 ep->bmAttributes = type;
2624 ep->double_buf = dbuf;
e6a6e472 2625 ep->udc = udc;
1da177e4
LT		 2626
2627 ep->ep.name = ep->name;
2628 ep->ep.ops = &omap_ep_ops;
2629 ep->ep.maxpacket = ep->maxpacket = maxp;
2630 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2631
2632 return buf;
2633}
2634
2635static void omap_udc_release(struct device *dev)
2636{
2637 complete(udc->done);
2638 kfree (udc);
313980c9 2639 udc = NULL;
1da177e4
LT		 2640}
2641
2642static int __init
2643omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2644{
2645 unsigned tmp, buf;
2646
2647 /* abolish any previous hardware state */
2648 UDC_SYSCON1_REG = 0;
2649 UDC_IRQ_EN_REG = 0;
2650 UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2651 UDC_DMA_IRQ_EN_REG = 0;
2652 UDC_RXDMA_CFG_REG = 0;
2653 UDC_TXDMA_CFG_REG = 0;
2654
2655 /* UDC_PULLUP_EN gates the chip clock */
2656 // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2657
e94b1766 2658 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
1da177e4
LT		 2659 if (!udc)
2660 return -ENOMEM;
2661
1da177e4
LT		 2662 spin_lock_init (&udc->lock);
2663
2664 udc->gadget.ops = &omap_gadget_ops;
2665 udc->gadget.ep0 = &udc->ep[0].ep;
2666 INIT_LIST_HEAD(&udc->gadget.ep_list);
2667 INIT_LIST_HEAD(&udc->iso);
2668 udc->gadget.speed = USB_SPEED_UNKNOWN;
2669 udc->gadget.name = driver_name;
2670
2671 device_initialize(&udc->gadget.dev);
2672 strcpy (udc->gadget.dev.bus_id, "gadget");
2673 udc->gadget.dev.release = omap_udc_release;
2674 udc->gadget.dev.parent = &odev->dev;
2675 if (use_dma)
2676 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2677
2678 udc->transceiver = xceiv;
2679
2680 /* ep0 is special; put it right after the SETUP buffer */
2681 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2682 8 /* after SETUP */, 64 /* maxpacket */, 0);
2683 list_del_init(&udc->ep[0].ep.ep_list);
2684
2685 /* initially disable all non-ep0 endpoints */
2686 for (tmp = 1; tmp < 15; tmp++) {
2687 UDC_EP_RX_REG(tmp) = 0;
2688 UDC_EP_TX_REG(tmp) = 0;
2689 }
2690
2691#define OMAP_BULK_EP(name,addr) \
2692 buf = omap_ep_setup(name "-bulk", addr, \
2693 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2694#define OMAP_INT_EP(name,addr, maxp) \
2695 buf = omap_ep_setup(name "-int", addr, \
2696 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2697#define OMAP_ISO_EP(name,addr, maxp) \
2698 buf = omap_ep_setup(name "-iso", addr, \
2699 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2700
2701 switch (fifo_mode) {
2702 case 0:
2703 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2704 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2705 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2706 break;
2707 case 1:
2708 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2709 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
313980c9
DB		 2710 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2711
1da177e4
LT		 2712 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2713 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
313980c9 2714 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
1da177e4
LT		 2715
2716 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2717 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
313980c9
DB		 2718 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2719
1da177e4
LT		 2720 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2721 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
313980c9 2722 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
1da177e4
LT		 2723
2724 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2725 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
313980c9
DB		 2726 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2727 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2728
1da177e4
LT		 2729 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2730 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
313980c9
DB		 2731 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2732 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2733
2734 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2735 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
1da177e4 2736
1da177e4
LT		 2737 break;
2738
2739#ifdef USE_ISO
2740 case 2: /* mixed iso/bulk */
2741 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2742 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2743 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2744 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2745
2746 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2747
2748 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2749 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2750 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2751 break;
2752 case 3: /* mixed bulk/iso */
2753 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2754 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2755 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2756
2757 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2758 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2759 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2760
2761 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2762 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2763 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2764 break;
2765#endif
2766
2767 /* add more modes as needed */
2768
2769 default:
2770 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2771 return -ENODEV;
2772 }
2773 UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2774 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2775 return 0;
2776}
2777
3ae5eaec 2778static int __init omap_udc_probe(struct platform_device *pdev)
1da177e4 2779{
1da177e4
LT		 2780 int status = -ENODEV;
2781 int hmc;
313980c9
DB		 2782 struct otg_transceiver *xceiv = NULL;
2783 const char *type = NULL;
3ae5eaec 2784 struct omap_usb_config *config = pdev->dev.platform_data;
e6a6e472
DB		 2785 struct clk *dc_clk;
2786 struct clk *hhc_clk;
1da177e4
LT		 2787
2788 /* NOTE: "knows" the order of the resources! */
e6a6e472 2789 if (!request_mem_region(pdev->resource[0].start,
3ae5eaec 2790 pdev->resource[0].end - pdev->resource[0].start + 1,
1da177e4
LT		 2791 driver_name)) {
2792 DBG("request_mem_region failed\n");
2793 return -EBUSY;
2794 }
2795
e6a6e472
DB		 2796 if (cpu_is_omap16xx()) {
2797 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2798 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2799 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2800 /* can't use omap_udc_enable_clock yet */
2801 clk_enable(dc_clk);
2802 clk_enable(hhc_clk);
2803 udelay(100);
2804 }
2805
2806 if (cpu_is_omap24xx()) {
2807 dc_clk = clk_get(&pdev->dev, "usb_fck");
2808 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2809 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2810 /* can't use omap_udc_enable_clock yet */
2811 clk_enable(dc_clk);
2812 clk_enable(hhc_clk);
2813 udelay(100);
2814 }
2815
1da177e4
LT		 2816 INFO("OMAP UDC rev %d.%d%s\n",
2817 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2818 config->otg ? ", Mini-AB" : "");
2819
2820 /* use the mode given to us by board init code */
2821 if (cpu_is_omap15xx()) {
2822 hmc = HMC_1510;
2823 type = "(unknown)";
2824
e6a6e472 2825 if (machine_is_omap_innovator() || machine_is_sx1()) {
1da177e4
LT		 2826 /* just set up software VBUS detect, and then
2827 * later rig it so we always report VBUS.
2828 * FIXME without really sensing VBUS, we can't
2829 * know when to turn PULLUP_EN on/off; and that
2830 * means we always "need" the 48MHz clock.
2831 */
2832 u32 tmp = FUNC_MUX_CTRL_0_REG;
2833
2834 FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2835 tmp |= VBUS_MODE_1510;
2836 tmp &= ~VBUS_CTRL_1510;
2837 FUNC_MUX_CTRL_0_REG = tmp;
2838 }
2839 } else {
65111084
DB		 2840 /* The transceiver may package some GPIO logic or handle
2841 * loopback and/or transceiverless setup; if we find one,
2842 * use it. Except for OTG, we don't _need_ to talk to one;
2843 * but not having one probably means no VBUS detection.
2844 */
2845 xceiv = otg_get_transceiver();
2846 if (xceiv)
2847 type = xceiv->label;
2848 else if (config->otg) {
2849 DBG("OTG requires external transceiver!\n");
2850 goto cleanup0;
2851 }
2852
1da177e4 2853 hmc = HMC_1610;
e6a6e472
DB		 2854
2855 if (cpu_is_omap24xx()) {
2856 /* this could be transceiverless in one of the
2857 * "we don't need to know" modes.
2858 */
2859 type = "external";
2860 goto known;
2861 }
2862
1da177e4 2863 switch (hmc) {
313980c9
DB		 2864 case 0: /* POWERUP DEFAULT == 0 */
2865 case 4:
2866 case 12:
2867 case 20:
2868 if (!cpu_is_omap1710()) {
2869 type = "integrated";
2870 break;
2871 }
2872 /* FALL THROUGH */
1da177e4
LT		 2873 case 3:
2874 case 11:
2875 case 16:
2876 case 19:
2877 case 25:
1da177e4
LT		 2878 if (!xceiv) {
2879 DBG("external transceiver not registered!\n");
313980c9 2880 type = "unknown";
65111084 2881 }
1da177e4 2882 break;
1da177e4 2883 case 21: /* internal loopback */
313980c9 2884 type = "loopback";
1da177e4
LT		 2885 break;
2886 case 14: /* transceiverless */
65111084
DB		 2887 if (cpu_is_omap1710())
2888 goto bad_on_1710;
2889 /* FALL THROUGH */
2890 case 13:
2891 case 15:
313980c9 2892 type = "no";
1da177e4
LT		 2893 break;
2894
2895 default:
65111084 2896bad_on_1710:
1da177e4 2897 ERR("unrecognized UDC HMC mode %d\n", hmc);
65111084 2898 goto cleanup0;
1da177e4
LT		 2899 }
2900 }
e6a6e472 2901known:
313980c9 2902 INFO("hmc mode %d, %s transceiver\n", hmc, type);
1da177e4
LT		 2903
2904 /* a "gadget" abstracts/virtualizes the controller */
3ae5eaec 2905 status = omap_udc_setup(pdev, xceiv);
1da177e4
LT		 2906 if (status) {
2907 goto cleanup0;
2908 }
313980c9 2909 xceiv = NULL;
1da177e4
LT		 2910 // "udc" is now valid
2911 pullup_disable(udc);
2912#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2913 udc->gadget.is_otg = (config->otg != 0);
2914#endif
2915
65111084
DB		 2916 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2917 if (UDC_REV_REG >= 0x61)
2918 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2919 else
2920 udc->clr_halt = UDC_RESET_EP;
2921
1da177e4 2922 /* USB general purpose IRQ: ep0, state changes, dma, etc */
3ae5eaec 2923 status = request_irq(pdev->resource[1].start, omap_udc_irq,
d54b5caa 2924 IRQF_SAMPLE_RANDOM, driver_name, udc);
1da177e4 2925 if (status != 0) {
e6a6e472
DB		 2926 ERR("can't get irq %d, err %d\n",
2927 (int) pdev->resource[1].start, status);
1da177e4
LT		 2928 goto cleanup1;
2929 }
2930
2931 /* USB "non-iso" IRQ (PIO for all but ep0) */
3ae5eaec 2932 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
d54b5caa 2933 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
1da177e4 2934 if (status != 0) {
e6a6e472
DB		 2935 ERR("can't get irq %d, err %d\n",
2936 (int) pdev->resource[2].start, status);
1da177e4
LT		 2937 goto cleanup2;
2938 }
2939#ifdef USE_ISO
3ae5eaec 2940 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
d54b5caa 2941 IRQF_DISABLED, "omap_udc iso", udc);
1da177e4 2942 if (status != 0) {
e6a6e472
DB		 2943 ERR("can't get irq %d, err %d\n",
2944 (int) pdev->resource[3].start, status);
1da177e4
LT		 2945 goto cleanup3;
2946 }
2947#endif
e6a6e472
DB		 2948 if (cpu_is_omap16xx()) {
2949 udc->dc_clk = dc_clk;
2950 udc->hhc_clk = hhc_clk;
2951 clk_disable(hhc_clk);
2952 clk_disable(dc_clk);
2953 }
2954
2955 if (cpu_is_omap24xx()) {
2956 udc->dc_clk = dc_clk;
2957 udc->hhc_clk = hhc_clk;
2958 /* FIXME OMAP2 don't release hhc & dc clock */
2959#if 0
2960 clk_disable(hhc_clk);
2961 clk_disable(dc_clk);
2962#endif
2963 }
1da177e4
LT		 2964
2965 create_proc_file();
e6a6e472
DB		 2966 status = device_add(&udc->gadget.dev);
2967 if (!status)
2968 return status;
2969 /* If fail, fall through */
1da177e4
LT		 2970#ifdef USE_ISO
2971cleanup3:
3ae5eaec 2972 free_irq(pdev->resource[2].start, udc);
1da177e4
LT		 2973#endif
2974
2975cleanup2:
3ae5eaec 2976 free_irq(pdev->resource[1].start, udc);
1da177e4
LT		 2977
2978cleanup1:
2979 kfree (udc);
313980c9 2980 udc = NULL;
1da177e4
LT		 2981
2982cleanup0:
2983 if (xceiv)
2984 put_device(xceiv->dev);
e6a6e472
DB		 2985
2986 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
2987 clk_disable(hhc_clk);
2988 clk_disable(dc_clk);
2989 clk_put(hhc_clk);
2990 clk_put(dc_clk);
2991 }
2992
3ae5eaec
RK		 2993 release_mem_region(pdev->resource[0].start,
2994 pdev->resource[0].end - pdev->resource[0].start + 1);
e6a6e472 2995
1da177e4
LT		 2996 return status;
2997}
2998
3ae5eaec 2999static int __exit omap_udc_remove(struct platform_device *pdev)
1da177e4 3000{
6e9a4738 3001 DECLARE_COMPLETION_ONSTACK(done);
1da177e4
LT		 3002
3003 if (!udc)
3004 return -ENODEV;
6bea476c
DB		 3005 if (udc->driver)
3006 return -EBUSY;
1da177e4
LT		 3007
3008 udc->done = &done;
3009
3010 pullup_disable(udc);
3011 if (udc->transceiver) {
3012 put_device(udc->transceiver->dev);
313980c9 3013 udc->transceiver = NULL;
1da177e4
LT		 3014 }
3015 UDC_SYSCON1_REG = 0;
3016
3017 remove_proc_file();
3018
3019#ifdef USE_ISO
3ae5eaec 3020 free_irq(pdev->resource[3].start, udc);
1da177e4 3021#endif
3ae5eaec
RK		 3022 free_irq(pdev->resource[2].start, udc);
3023 free_irq(pdev->resource[1].start, udc);
1da177e4 3024
e6a6e472
DB		 3025 if (udc->dc_clk) {
3026 if (udc->clk_requested)
3027 omap_udc_enable_clock(0);
3028 clk_put(udc->hhc_clk);
3029 clk_put(udc->dc_clk);
3030 }
3031
3ae5eaec
RK		 3032 release_mem_region(pdev->resource[0].start,
3033 pdev->resource[0].end - pdev->resource[0].start + 1);
1da177e4
LT		 3034
3035 device_unregister(&udc->gadget.dev);
3036 wait_for_completion(&done);
3037
3038 return 0;
3039}
3040
313980c9
DB		 3041/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3042 * system is forced into deep sleep
3043 *
3044 * REVISIT we should probably reject suspend requests when there's a host
3045 * session active, rather than disconnecting, at least on boards that can
3046 * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to
3047 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3048 * may involve talking to an external transceiver (e.g. isp1301).
3049 */
1d7beee3 3050
3ae5eaec 3051static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
1da177e4 3052{
313980c9
DB		 3053 u32 devstat;
3054
313980c9
DB		 3055 devstat = UDC_DEVSTAT_REG;
3056
3057 /* we're requesting 48 MHz clock if the pullup is enabled
3058 * (== we're attached to the host) and we're not suspended,
3059 * which would prevent entry to deep sleep...
3060 */
3061 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3062 WARN("session active; suspend requires disconnect\n");
3063 omap_pullup(&udc->gadget, 0);
3064 }
1da177e4 3065
ba9d35fb
PM		 3066 udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3067 udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
1da177e4
LT		 3068 return 0;
3069}
3070
3ae5eaec 3071static int omap_udc_resume(struct platform_device *dev)
1da177e4 3072{
1da177e4 3073 DBG("resume + wakeup/SRP\n");
1da177e4
LT		 3074 omap_pullup(&udc->gadget, 1);
3075
3076 /* maybe the host would enumerate us if we nudged it */
3077 msleep(100);
3078 return omap_wakeup(&udc->gadget);
3079}
3080
3081/*-------------------------------------------------------------------------*/
3082
3ae5eaec 3083static struct platform_driver udc_driver = {
1da177e4
LT		 3084 .probe = omap_udc_probe,
3085 .remove = __exit_p(omap_udc_remove),
3086 .suspend = omap_udc_suspend,
3087 .resume = omap_udc_resume,
3ae5eaec
RK		 3088 .driver = {
3089 .owner = THIS_MODULE,
3090 .name = (char *) driver_name,
3091 },
1da177e4
LT		 3092};
3093
3094static int __init udc_init(void)
3095{
3096 INFO("%s, version: " DRIVER_VERSION
3097#ifdef USE_ISO
3098 " (iso)"
3099#endif
3100 "%s\n", driver_desc,
3101 use_dma ? " (dma)" : "");
3ae5eaec 3102 return platform_driver_register(&udc_driver);
1da177e4
LT		 3103}
3104module_init(udc_init);
3105
3106static void __exit udc_exit(void)
3107{
3ae5eaec 3108 platform_driver_unregister(&udc_driver);
1da177e4
LT		 3109}
3110module_exit(udc_exit);
3111
3112MODULE_DESCRIPTION(DRIVER_DESC);
3113MODULE_LICENSE("GPL");
3114
Linux kernel - Deliverables
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