projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: gadget: pch_udc: Detecting VBUS through GPIO
[deliverable/linux.git] / drivers / usb / gadget / pch_udc.c
CommitLineData
f646cf94 1/*
09b658dc 2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
f646cf94
TO		 3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
f646cf94
TO		 7 */
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/delay.h>
13#include <linux/errno.h>
14#include <linux/list.h>
15#include <linux/interrupt.h>
16#include <linux/usb/ch9.h>
17#include <linux/usb/gadget.h>
dd63180b
TM		 18#include <linux/gpio.h>
19
20/* GPIO port for VBUS detecting */
21static int vbus_gpio_port = -1; /* GPIO port number (-1:Not used) */
22
23#define PCH_VBUS_PERIOD 3000 /* VBUS polling period (msec) */
24#define PCH_VBUS_INTERVAL 10 /* VBUS polling interval (msec) */
f646cf94
TO		 25
26/* Address offset of Registers */
27#define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
28
29#define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
30#define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
31#define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
32#define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
33#define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
34#define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
35#define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
36
37#define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
38#define UDC_DEVCTL_ADDR 0x404 /* Device control */
39#define UDC_DEVSTS_ADDR 0x408 /* Device status */
40#define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
41#define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
42#define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
43#define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
44#define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
45#define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
46#define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
47#define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
48
49/* Endpoint control register */
50/* Bit position */
51#define UDC_EPCTL_MRXFLUSH (1 << 12)
52#define UDC_EPCTL_RRDY (1 << 9)
53#define UDC_EPCTL_CNAK (1 << 8)
54#define UDC_EPCTL_SNAK (1 << 7)
55#define UDC_EPCTL_NAK (1 << 6)
56#define UDC_EPCTL_P (1 << 3)
57#define UDC_EPCTL_F (1 << 1)
58#define UDC_EPCTL_S (1 << 0)
59#define UDC_EPCTL_ET_SHIFT 4
60/* Mask patern */
61#define UDC_EPCTL_ET_MASK 0x00000030
62/* Value for ET field */
63#define UDC_EPCTL_ET_CONTROL 0
64#define UDC_EPCTL_ET_ISO 1
65#define UDC_EPCTL_ET_BULK 2
66#define UDC_EPCTL_ET_INTERRUPT 3
67
68/* Endpoint status register */
69/* Bit position */
70#define UDC_EPSTS_XFERDONE (1 << 27)
71#define UDC_EPSTS_RSS (1 << 26)
72#define UDC_EPSTS_RCS (1 << 25)
73#define UDC_EPSTS_TXEMPTY (1 << 24)
74#define UDC_EPSTS_TDC (1 << 10)
75#define UDC_EPSTS_HE (1 << 9)
76#define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
77#define UDC_EPSTS_BNA (1 << 7)
78#define UDC_EPSTS_IN (1 << 6)
79#define UDC_EPSTS_OUT_SHIFT 4
80/* Mask patern */
81#define UDC_EPSTS_OUT_MASK 0x00000030
82#define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
83/* Value for OUT field */
84#define UDC_EPSTS_OUT_SETUP 2
85#define UDC_EPSTS_OUT_DATA 1
86
87/* Device configuration register */
88/* Bit position */
89#define UDC_DEVCFG_CSR_PRG (1 << 17)
90#define UDC_DEVCFG_SP (1 << 3)
91/* SPD Valee */
92#define UDC_DEVCFG_SPD_HS 0x0
93#define UDC_DEVCFG_SPD_FS 0x1
94#define UDC_DEVCFG_SPD_LS 0x2
95
96/* Device control register */
97/* Bit position */
98#define UDC_DEVCTL_THLEN_SHIFT 24
99#define UDC_DEVCTL_BRLEN_SHIFT 16
100#define UDC_DEVCTL_CSR_DONE (1 << 13)
101#define UDC_DEVCTL_SD (1 << 10)
102#define UDC_DEVCTL_MODE (1 << 9)
103#define UDC_DEVCTL_BREN (1 << 8)
104#define UDC_DEVCTL_THE (1 << 7)
105#define UDC_DEVCTL_DU (1 << 4)
106#define UDC_DEVCTL_TDE (1 << 3)
107#define UDC_DEVCTL_RDE (1 << 2)
108#define UDC_DEVCTL_RES (1 << 0)
109
110/* Device status register */
111/* Bit position */
112#define UDC_DEVSTS_TS_SHIFT 18
113#define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
114#define UDC_DEVSTS_ALT_SHIFT 8
115#define UDC_DEVSTS_INTF_SHIFT 4
116#define UDC_DEVSTS_CFG_SHIFT 0
117/* Mask patern */
118#define UDC_DEVSTS_TS_MASK 0xfffc0000
119#define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
120#define UDC_DEVSTS_ALT_MASK 0x00000f00
121#define UDC_DEVSTS_INTF_MASK 0x000000f0
122#define UDC_DEVSTS_CFG_MASK 0x0000000f
123/* value for maximum speed for SPEED field */
124#define UDC_DEVSTS_ENUM_SPEED_FULL 1
125#define UDC_DEVSTS_ENUM_SPEED_HIGH 0
126#define UDC_DEVSTS_ENUM_SPEED_LOW 2
127#define UDC_DEVSTS_ENUM_SPEED_FULLX 3
128
129/* Device irq register */
130/* Bit position */
131#define UDC_DEVINT_RWKP (1 << 7)
132#define UDC_DEVINT_ENUM (1 << 6)
133#define UDC_DEVINT_SOF (1 << 5)
134#define UDC_DEVINT_US (1 << 4)
135#define UDC_DEVINT_UR (1 << 3)
136#define UDC_DEVINT_ES (1 << 2)
137#define UDC_DEVINT_SI (1 << 1)
138#define UDC_DEVINT_SC (1 << 0)
139/* Mask patern */
140#define UDC_DEVINT_MSK 0x7f
141
142/* Endpoint irq register */
143/* Bit position */
144#define UDC_EPINT_IN_SHIFT 0
145#define UDC_EPINT_OUT_SHIFT 16
146#define UDC_EPINT_IN_EP0 (1 << 0)
147#define UDC_EPINT_OUT_EP0 (1 << 16)
148/* Mask patern */
149#define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
150
151/* UDC_CSR_BUSY Status register */
152/* Bit position */
153#define UDC_CSR_BUSY (1 << 0)
154
155/* SOFT RESET register */
156/* Bit position */
157#define UDC_PSRST (1 << 1)
158#define UDC_SRST (1 << 0)
159
160/* USB_DEVICE endpoint register */
161/* Bit position */
162#define UDC_CSR_NE_NUM_SHIFT 0
163#define UDC_CSR_NE_DIR_SHIFT 4
164#define UDC_CSR_NE_TYPE_SHIFT 5
165#define UDC_CSR_NE_CFG_SHIFT 7
166#define UDC_CSR_NE_INTF_SHIFT 11
167#define UDC_CSR_NE_ALT_SHIFT 15
168#define UDC_CSR_NE_MAX_PKT_SHIFT 19
169/* Mask patern */
170#define UDC_CSR_NE_NUM_MASK 0x0000000f
171#define UDC_CSR_NE_DIR_MASK 0x00000010
172#define UDC_CSR_NE_TYPE_MASK 0x00000060
173#define UDC_CSR_NE_CFG_MASK 0x00000780
174#define UDC_CSR_NE_INTF_MASK 0x00007800
175#define UDC_CSR_NE_ALT_MASK 0x00078000
176#define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
177
178#define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
179#define PCH_UDC_EPINT(in, num)\
180 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
181
182/* Index of endpoint */
183#define UDC_EP0IN_IDX 0
184#define UDC_EP0OUT_IDX 1
185#define UDC_EPIN_IDX(ep) (ep * 2)
186#define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
187#define PCH_UDC_EP0 0
188#define PCH_UDC_EP1 1
189#define PCH_UDC_EP2 2
190#define PCH_UDC_EP3 3
191
192/* Number of endpoint */
193#define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
194#define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
195/* Length Value */
196#define PCH_UDC_BRLEN 0x0F /* Burst length */
197#define PCH_UDC_THLEN 0x1F /* Threshold length */
198/* Value of EP Buffer Size */
abab0c67
TO		 199#define UDC_EP0IN_BUFF_SIZE 16
200#define UDC_EPIN_BUFF_SIZE 256
201#define UDC_EP0OUT_BUFF_SIZE 16
202#define UDC_EPOUT_BUFF_SIZE 256
f646cf94
TO		 203/* Value of EP maximum packet size */
204#define UDC_EP0IN_MAX_PKT_SIZE 64
205#define UDC_EP0OUT_MAX_PKT_SIZE 64
206#define UDC_BULK_MAX_PKT_SIZE 512
207
208/* DMA */
209#define DMA_DIR_RX 1 /* DMA for data receive */
210#define DMA_DIR_TX 2 /* DMA for data transmit */
211#define DMA_ADDR_INVALID (~(dma_addr_t)0)
212#define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
213
214/**
215 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
216 * for data
217 * @status: Status quadlet
218 * @reserved: Reserved
219 * @dataptr: Buffer descriptor
220 * @next: Next descriptor
221 */
222struct pch_udc_data_dma_desc {
223 u32 status;
224 u32 reserved;
225 u32 dataptr;
226 u32 next;
227};
228
229/**
230 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
231 * for control data
232 * @status: Status
233 * @reserved: Reserved
234 * @data12: First setup word
235 * @data34: Second setup word
236 */
237struct pch_udc_stp_dma_desc {
238 u32 status;
239 u32 reserved;
240 struct usb_ctrlrequest request;
241} __attribute((packed));
242
243/* DMA status definitions */
244/* Buffer status */
245#define PCH_UDC_BUFF_STS 0xC0000000
246#define PCH_UDC_BS_HST_RDY 0x00000000
247#define PCH_UDC_BS_DMA_BSY 0x40000000
248#define PCH_UDC_BS_DMA_DONE 0x80000000
249#define PCH_UDC_BS_HST_BSY 0xC0000000
250/* Rx/Tx Status */
251#define PCH_UDC_RXTX_STS 0x30000000
252#define PCH_UDC_RTS_SUCC 0x00000000
253#define PCH_UDC_RTS_DESERR 0x10000000
254#define PCH_UDC_RTS_BUFERR 0x30000000
255/* Last Descriptor Indication */
256#define PCH_UDC_DMA_LAST 0x08000000
257/* Number of Rx/Tx Bytes Mask */
258#define PCH_UDC_RXTX_BYTES 0x0000ffff
259
260/**
261 * struct pch_udc_cfg_data - Structure to hold current configuration
262 * and interface information
263 * @cur_cfg: current configuration in use
264 * @cur_intf: current interface in use
265 * @cur_alt: current alt interface in use
266 */
267struct pch_udc_cfg_data {
268 u16 cur_cfg;
269 u16 cur_intf;
270 u16 cur_alt;
271};
272
273/**
274 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
275 * @ep: embedded ep request
276 * @td_stp_phys: for setup request
277 * @td_data_phys: for data request
278 * @td_stp: for setup request
279 * @td_data: for data request
280 * @dev: reference to device struct
281 * @offset_addr: offset address of ep register
282 * @desc: for this ep
283 * @queue: queue for requests
284 * @num: endpoint number
285 * @in: endpoint is IN
286 * @halted: endpoint halted?
287 * @epsts: Endpoint status
288 */
289struct pch_udc_ep {
290 struct usb_ep ep;
291 dma_addr_t td_stp_phys;
292 dma_addr_t td_data_phys;
293 struct pch_udc_stp_dma_desc *td_stp;
294 struct pch_udc_data_dma_desc *td_data;
295 struct pch_udc_dev *dev;
296 unsigned long offset_addr;
297 const struct usb_endpoint_descriptor *desc;
298 struct list_head queue;
299 unsigned num:5,
300 in:1,
301 halted:1;
302 unsigned long epsts;
303};
304
dd63180b
TM		 305/**
306 * struct pch_vbus_gpio_data - Structure holding GPIO informaton
307 * for detecting VBUS
308 * @port: gpio port number
309 * @irq_work_fall Structure for WorkQueue
310 */
311struct pch_vbus_gpio_data {
312 int port;
313 struct work_struct irq_work_fall;
314};
315
f646cf94
TO		 316/**
317 * struct pch_udc_dev - Structure holding complete information
318 * of the PCH USB device
319 * @gadget: gadget driver data
320 * @driver: reference to gadget driver bound
321 * @pdev: reference to the PCI device
322 * @ep: array of endpoints
323 * @lock: protects all state
324 * @active: enabled the PCI device
325 * @stall: stall requested
326 * @prot_stall: protcol stall requested
327 * @irq_registered: irq registered with system
328 * @mem_region: device memory mapped
329 * @registered: driver regsitered with system
330 * @suspended: driver in suspended state
331 * @connected: gadget driver associated
1c575d2d 332 * @vbus_session: required vbus_session state
f646cf94
TO		 333 * @set_cfg_not_acked: pending acknowledgement 4 setup
334 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
335 * @data_requests: DMA pool for data requests
336 * @stp_requests: DMA pool for setup requests
337 * @dma_addr: DMA pool for received
338 * @ep0out_buf: Buffer for DMA
339 * @setup_data: Received setup data
340 * @phys_addr: of device memory
341 * @base_addr: for mapped device memory
342 * @irq: IRQ line for the device
343 * @cfg_data: current cfg, intf, and alt in use
dd63180b 344 * @vbus_gpio: GPIO informaton for detecting VBUS
f646cf94
TO		 345 */
346struct pch_udc_dev {
347 struct usb_gadget gadget;
348 struct usb_gadget_driver *driver;
349 struct pci_dev *pdev;
350 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
49e20834 351 spinlock_t lock; /* protects all state */
f646cf94
TO		 352 unsigned active:1,
353 stall:1,
354 prot_stall:1,
355 irq_registered:1,
356 mem_region:1,
357 registered:1,
358 suspended:1,
359 connected:1,
1c575d2d 360 vbus_session:1,
f646cf94
TO		 361 set_cfg_not_acked:1,
362 waiting_zlp_ack:1;
363 struct pci_pool *data_requests;
364 struct pci_pool *stp_requests;
365 dma_addr_t dma_addr;
abab0c67 366 void *ep0out_buf;
f646cf94
TO		 367 struct usb_ctrlrequest setup_data;
368 unsigned long phys_addr;
369 void __iomem *base_addr;
370 unsigned irq;
dd63180b
TM		 371 struct pch_udc_cfg_data cfg_data;
372 struct pch_vbus_gpio_data vbus_gpio;
f646cf94
TO		 373};
374
375#define PCH_UDC_PCI_BAR 1
376#define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
06f1b971
TM		 377#define PCI_VENDOR_ID_ROHM 0x10DB
378#define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
731ad81e 379#define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808
f646cf94
TO		 380
381static const char ep0_string[] = "ep0in";
382static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
383struct pch_udc_dev *pch_udc; /* pointer to device object */
90ab5ee9 384static bool speed_fs;
f646cf94
TO		 385module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
386MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
387
388/**
389 * struct pch_udc_request - Structure holding a PCH USB device request packet
390 * @req: embedded ep request
391 * @td_data_phys: phys. address
392 * @td_data: first dma desc. of chain
393 * @td_data_last: last dma desc. of chain
394 * @queue: associated queue
395 * @dma_going: DMA in progress for request
396 * @dma_mapped: DMA memory mapped for request
397 * @dma_done: DMA completed for request
398 * @chain_len: chain length
c17f459c
TO		 399 * @buf: Buffer memory for align adjustment
400 * @dma: DMA memory for align adjustment
f646cf94
TO		 401 */
402struct pch_udc_request {
403 struct usb_request req;
404 dma_addr_t td_data_phys;
405 struct pch_udc_data_dma_desc *td_data;
406 struct pch_udc_data_dma_desc *td_data_last;
407 struct list_head queue;
408 unsigned dma_going:1,
409 dma_mapped:1,
410 dma_done:1;
411 unsigned chain_len;
c17f459c
TO		 412 void *buf;
413 dma_addr_t dma;
f646cf94
TO		 414};
415
416static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
417{
418 return ioread32(dev->base_addr + reg);
419}
420
421static inline void pch_udc_writel(struct pch_udc_dev *dev,
422 unsigned long val, unsigned long reg)
423{
424 iowrite32(val, dev->base_addr + reg);
425}
426
427static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
428 unsigned long reg,
429 unsigned long bitmask)
430{
431 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
432}
433
434static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
435 unsigned long reg,
436 unsigned long bitmask)
437{
438 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
439}
440
441static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
442{
443 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
444}
445
446static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
447 unsigned long val, unsigned long reg)
448{
449 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
450}
451
452static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
453 unsigned long reg,
454 unsigned long bitmask)
455{
456 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
457}
458
459static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
460 unsigned long reg,
461 unsigned long bitmask)
462{
463 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
464}
465
466/**
467 * pch_udc_csr_busy() - Wait till idle.
468 * @dev: Reference to pch_udc_dev structure
469 */
470static void pch_udc_csr_busy(struct pch_udc_dev *dev)
471{
472 unsigned int count = 200;
473
474 /* Wait till idle */
475 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
476 && --count)
477 cpu_relax();
478 if (!count)
479 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
480}
481
482/**
483 * pch_udc_write_csr() - Write the command and status registers.
484 * @dev: Reference to pch_udc_dev structure
485 * @val: value to be written to CSR register
486 * @addr: address of CSR register
487 */
488static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
489 unsigned int ep)
490{
491 unsigned long reg = PCH_UDC_CSR(ep);
492
493 pch_udc_csr_busy(dev); /* Wait till idle */
494 pch_udc_writel(dev, val, reg);
495 pch_udc_csr_busy(dev); /* Wait till idle */
496}
497
498/**
499 * pch_udc_read_csr() - Read the command and status registers.
500 * @dev: Reference to pch_udc_dev structure
501 * @addr: address of CSR register
502 *
503 * Return codes: content of CSR register
504 */
505static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
506{
507 unsigned long reg = PCH_UDC_CSR(ep);
508
509 pch_udc_csr_busy(dev); /* Wait till idle */
510 pch_udc_readl(dev, reg); /* Dummy read */
511 pch_udc_csr_busy(dev); /* Wait till idle */
512 return pch_udc_readl(dev, reg);
513}
514
515/**
516 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
517 * @dev: Reference to pch_udc_dev structure
518 */
519static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
520{
521 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
522 mdelay(1);
523 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
524}
525
526/**
527 * pch_udc_get_frame() - Get the current frame from device status register
528 * @dev: Reference to pch_udc_dev structure
529 * Retern current frame
530 */
531static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
532{
533 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
534 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
535}
536
537/**
538 * pch_udc_clear_selfpowered() - Clear the self power control
539 * @dev: Reference to pch_udc_regs structure
540 */
541static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
542{
543 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
544}
545
546/**
547 * pch_udc_set_selfpowered() - Set the self power control
548 * @dev: Reference to pch_udc_regs structure
549 */
550static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
551{
552 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
553}
554
555/**
556 * pch_udc_set_disconnect() - Set the disconnect status.
557 * @dev: Reference to pch_udc_regs structure
558 */
559static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
560{
561 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
562}
563
564/**
565 * pch_udc_clear_disconnect() - Clear the disconnect status.
566 * @dev: Reference to pch_udc_regs structure
567 */
568static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
569{
570 /* Clear the disconnect */
571 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
572 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
573 mdelay(1);
574 /* Resume USB signalling */
575 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
576}
577
1c575d2d
TM		 578/**
579 * pch_udc_reconnect() - This API initializes usb device controller,
580 * and clear the disconnect status.
581 * @dev: Reference to pch_udc_regs structure
582 */
583static void pch_udc_init(struct pch_udc_dev *dev);
584static void pch_udc_reconnect(struct pch_udc_dev *dev)
585{
586 pch_udc_init(dev);
587
588 /* enable device interrupts */
589 /* pch_udc_enable_interrupts() */
590 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
83331040 591 UDC_DEVINT_UR | UDC_DEVINT_ENUM);
1c575d2d
TM		 592
593 /* Clear the disconnect */
594 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
595 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
596 mdelay(1);
597 /* Resume USB signalling */
598 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
599}
600
f646cf94
TO		 601/**
602 * pch_udc_vbus_session() - set or clearr the disconnect status.
603 * @dev: Reference to pch_udc_regs structure
604 * @is_active: Parameter specifying the action
605 * 0: indicating VBUS power is ending
606 * !0: indicating VBUS power is starting
607 */
608static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
609 int is_active)
610{
1c575d2d
TM		 611 if (is_active) {
612 pch_udc_reconnect(dev);
613 dev->vbus_session = 1;
614 } else {
615 if (dev->driver && dev->driver->disconnect) {
616 spin_unlock(&dev->lock);
617 dev->driver->disconnect(&dev->gadget);
618 spin_lock(&dev->lock);
619 }
f646cf94 620 pch_udc_set_disconnect(dev);
1c575d2d
TM		 621 dev->vbus_session = 0;
622 }
f646cf94
TO		 623}
624
625/**
626 * pch_udc_ep_set_stall() - Set the stall of endpoint
627 * @ep: Reference to structure of type pch_udc_ep_regs
628 */
629static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
630{
631 if (ep->in) {
632 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
633 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
634 } else {
635 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
636 }
637}
638
639/**
640 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
641 * @ep: Reference to structure of type pch_udc_ep_regs
642 */
643static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
644{
645 /* Clear the stall */
646 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
647 /* Clear NAK by writing CNAK */
648 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
649}
650
651/**
652 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
653 * @ep: Reference to structure of type pch_udc_ep_regs
654 * @type: Type of endpoint
655 */
656static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
657 u8 type)
658{
659 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
660 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
661}
662
663/**
664 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
665 * @ep: Reference to structure of type pch_udc_ep_regs
c17f459c 666 * @buf_size: The buffer word size
f646cf94
TO		 667 */
668static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
669 u32 buf_size, u32 ep_in)
670{
671 u32 data;
672 if (ep_in) {
673 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
674 data = (data & 0xffff0000) | (buf_size & 0xffff);
675 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
676 } else {
677 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
678 data = (buf_size << 16) | (data & 0xffff);
679 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
680 }
681}
682
683/**
684 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
685 * @ep: Reference to structure of type pch_udc_ep_regs
c17f459c 686 * @pkt_size: The packet byte size
f646cf94
TO		 687 */
688static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
689{
690 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
691 data = (data & 0xffff0000) | (pkt_size & 0xffff);
692 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
693}
694
695/**
696 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
697 * @ep: Reference to structure of type pch_udc_ep_regs
698 * @addr: Address of the register
699 */
700static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
701{
702 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
703}
704
705/**
706 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
707 * @ep: Reference to structure of type pch_udc_ep_regs
708 * @addr: Address of the register
709 */
710static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
711{
712 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
713}
714
715/**
716 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
717 * @ep: Reference to structure of type pch_udc_ep_regs
718 */
719static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
720{
721 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
722}
723
724/**
725 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
726 * @ep: Reference to structure of type pch_udc_ep_regs
727 */
728static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
729{
730 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
731}
732
733/**
734 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
735 * @ep: Reference to structure of type pch_udc_ep_regs
736 */
737static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
738{
739 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
740}
741
742/**
743 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
744 * register depending on the direction specified
745 * @dev: Reference to structure of type pch_udc_regs
746 * @dir: whether Tx or Rx
747 * DMA_DIR_RX: Receive
748 * DMA_DIR_TX: Transmit
749 */
750static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
751{
752 if (dir == DMA_DIR_RX)
753 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
754 else if (dir == DMA_DIR_TX)
755 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
756}
757
758/**
759 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
760 * register depending on the direction specified
761 * @dev: Reference to structure of type pch_udc_regs
762 * @dir: Whether Tx or Rx
763 * DMA_DIR_RX: Receive
764 * DMA_DIR_TX: Transmit
765 */
766static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
767{
768 if (dir == DMA_DIR_RX)
769 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
770 else if (dir == DMA_DIR_TX)
771 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
772}
773
774/**
775 * pch_udc_set_csr_done() - Set the device control register
776 * CSR done field (bit 13)
777 * @dev: reference to structure of type pch_udc_regs
778 */
779static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
780{
781 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
782}
783
784/**
785 * pch_udc_disable_interrupts() - Disables the specified interrupts
786 * @dev: Reference to structure of type pch_udc_regs
787 * @mask: Mask to disable interrupts
788 */
789static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
790 u32 mask)
791{
792 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
793}
794
795/**
796 * pch_udc_enable_interrupts() - Enable the specified interrupts
797 * @dev: Reference to structure of type pch_udc_regs
798 * @mask: Mask to enable interrupts
799 */
800static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
801 u32 mask)
802{
803 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
804}
805
806/**
807 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
808 * @dev: Reference to structure of type pch_udc_regs
809 * @mask: Mask to disable interrupts
810 */
811static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
812 u32 mask)
813{
814 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
815}
816
817/**
818 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
819 * @dev: Reference to structure of type pch_udc_regs
820 * @mask: Mask to enable interrupts
821 */
822static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
823 u32 mask)
824{
825 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
826}
827
828/**
829 * pch_udc_read_device_interrupts() - Read the device interrupts
830 * @dev: Reference to structure of type pch_udc_regs
831 * Retern The device interrupts
832 */
833static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
834{
835 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
836}
837
838/**
839 * pch_udc_write_device_interrupts() - Write device interrupts
840 * @dev: Reference to structure of type pch_udc_regs
841 * @val: The value to be written to interrupt register
842 */
843static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
844 u32 val)
845{
846 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
847}
848
849/**
850 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
851 * @dev: Reference to structure of type pch_udc_regs
852 * Retern The endpoint interrupt
853 */
854static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
855{
856 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
857}
858
859/**
860 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
861 * @dev: Reference to structure of type pch_udc_regs
862 * @val: The value to be written to interrupt register
863 */
864static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
865 u32 val)
866{
867 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
868}
869
870/**
871 * pch_udc_read_device_status() - Read the device status
872 * @dev: Reference to structure of type pch_udc_regs
873 * Retern The device status
874 */
875static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
876{
877 return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
878}
879
880/**
881 * pch_udc_read_ep_control() - Read the endpoint control
882 * @ep: Reference to structure of type pch_udc_ep_regs
883 * Retern The endpoint control register value
884 */
885static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
886{
887 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
888}
889
890/**
891 * pch_udc_clear_ep_control() - Clear the endpoint control register
892 * @ep: Reference to structure of type pch_udc_ep_regs
893 * Retern The endpoint control register value
894 */
895static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
896{
897 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
898}
899
900/**
901 * pch_udc_read_ep_status() - Read the endpoint status
902 * @ep: Reference to structure of type pch_udc_ep_regs
903 * Retern The endpoint status
904 */
905static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
906{
907 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
908}
909
910/**
911 * pch_udc_clear_ep_status() - Clear the endpoint status
912 * @ep: Reference to structure of type pch_udc_ep_regs
913 * @stat: Endpoint status
914 */
915static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
916 u32 stat)
917{
918 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
919}
920
921/**
922 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
923 * of the endpoint control register
924 * @ep: Reference to structure of type pch_udc_ep_regs
925 */
926static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
927{
928 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
929}
930
931/**
932 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
933 * of the endpoint control register
934 * @ep: reference to structure of type pch_udc_ep_regs
935 */
936static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
937{
938 unsigned int loopcnt = 0;
939 struct pch_udc_dev *dev = ep->dev;
940
941 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
942 return;
943 if (!ep->in) {
944 loopcnt = 10000;
945 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
946 --loopcnt)
947 udelay(5);
948 if (!loopcnt)
949 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
950 __func__);
951 }
952 loopcnt = 10000;
953 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
954 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
955 udelay(5);
956 }
957 if (!loopcnt)
958 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
959 __func__, ep->num, (ep->in ? "in" : "out"));
960}
961
962/**
963 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
964 * @ep: reference to structure of type pch_udc_ep_regs
965 * @dir: direction of endpoint
966 * 0: endpoint is OUT
967 * !0: endpoint is IN
968 */
969static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
970{
f646cf94
TO		 971 if (dir) { /* IN ep */
972 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
973 return;
974 }
f646cf94
TO		 975}
976
977/**
978 * pch_udc_ep_enable() - This api enables endpoint
979 * @regs: Reference to structure pch_udc_ep_regs
980 * @desc: endpoint descriptor
981 */
982static void pch_udc_ep_enable(struct pch_udc_ep *ep,
983 struct pch_udc_cfg_data *cfg,
984 const struct usb_endpoint_descriptor *desc)
985{
986 u32 val = 0;
987 u32 buff_size = 0;
988
989 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
990 if (ep->in)
991 buff_size = UDC_EPIN_BUFF_SIZE;
992 else
993 buff_size = UDC_EPOUT_BUFF_SIZE;
994 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
29cc8897 995 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
f646cf94
TO		 996 pch_udc_ep_set_nak(ep);
997 pch_udc_ep_fifo_flush(ep, ep->in);
998 /* Configure the endpoint */
999 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
1000 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
1001 UDC_CSR_NE_TYPE_SHIFT) |
1002 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
1003 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
1004 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
29cc8897 1005 usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
f646cf94
TO		 1006
1007 if (ep->in)
1008 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
1009 else
1010 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
1011}
1012
1013/**
1014 * pch_udc_ep_disable() - This api disables endpoint
1015 * @regs: Reference to structure pch_udc_ep_regs
1016 */
1017static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1018{
1019 if (ep->in) {
1020 /* flush the fifo */
1021 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1022 /* set NAK */
1023 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1024 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1025 } else {
1026 /* set NAK */
1027 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1028 }
1029 /* reset desc pointer */
1030 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1031}
1032
1033/**
1034 * pch_udc_wait_ep_stall() - Wait EP stall.
1035 * @dev: Reference to pch_udc_dev structure
1036 */
1037static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1038{
1039 unsigned int count = 10000;
1040
1041 /* Wait till idle */
1042 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1043 udelay(5);
1044 if (!count)
1045 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1046}
1047
1048/**
1049 * pch_udc_init() - This API initializes usb device controller
1050 * @dev: Rreference to pch_udc_regs structure
1051 */
1052static void pch_udc_init(struct pch_udc_dev *dev)
1053{
1054 if (NULL == dev) {
1055 pr_err("%s: Invalid address\n", __func__);
1056 return;
1057 }
1058 /* Soft Reset and Reset PHY */
1059 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1060 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1061 mdelay(1);
1062 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1063 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1064 mdelay(1);
1065 /* mask and clear all device interrupts */
1066 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1067 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1068
1069 /* mask and clear all ep interrupts */
1070 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1071 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1072
1073 /* enable dynamic CSR programmingi, self powered and device speed */
1074 if (speed_fs)
1075 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1076 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1077 else /* defaul high speed */
1078 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1079 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1080 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1081 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1082 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1083 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1084 UDC_DEVCTL_THE);
1085}
1086
1087/**
1088 * pch_udc_exit() - This API exit usb device controller
1089 * @dev: Reference to pch_udc_regs structure
1090 */
1091static void pch_udc_exit(struct pch_udc_dev *dev)
1092{
1093 /* mask all device interrupts */
1094 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1095 /* mask all ep interrupts */
1096 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1097 /* put device in disconnected state */
1098 pch_udc_set_disconnect(dev);
1099}
1100
1101/**
1102 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1103 * @gadget: Reference to the gadget driver
1104 *
1105 * Return codes:
1106 * 0: Success
1107 * -EINVAL: If the gadget passed is NULL
1108 */
1109static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1110{
1111 struct pch_udc_dev *dev;
1112
1113 if (!gadget)
1114 return -EINVAL;
1115 dev = container_of(gadget, struct pch_udc_dev, gadget);
1116 return pch_udc_get_frame(dev);
1117}
1118
1119/**
1120 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1121 * @gadget: Reference to the gadget driver
1122 *
1123 * Return codes:
1124 * 0: Success
1125 * -EINVAL: If the gadget passed is NULL
1126 */
1127static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1128{
1129 struct pch_udc_dev *dev;
1130 unsigned long flags;
1131
1132 if (!gadget)
1133 return -EINVAL;
1134 dev = container_of(gadget, struct pch_udc_dev, gadget);
1135 spin_lock_irqsave(&dev->lock, flags);
1136 pch_udc_rmt_wakeup(dev);
1137 spin_unlock_irqrestore(&dev->lock, flags);
1138 return 0;
1139}
1140
1141/**
1142 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1143 * is self powered or not
1144 * @gadget: Reference to the gadget driver
1145 * @value: Specifies self powered or not
1146 *
1147 * Return codes:
1148 * 0: Success
1149 * -EINVAL: If the gadget passed is NULL
1150 */
1151static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1152{
1153 struct pch_udc_dev *dev;
1154
1155 if (!gadget)
1156 return -EINVAL;
1157 dev = container_of(gadget, struct pch_udc_dev, gadget);
1158 if (value)
1159 pch_udc_set_selfpowered(dev);
1160 else
1161 pch_udc_clear_selfpowered(dev);
1162 return 0;
1163}
1164
1165/**
1166 * pch_udc_pcd_pullup() - This API is invoked to make the device
1167 * visible/invisible to the host
1168 * @gadget: Reference to the gadget driver
1169 * @is_on: Specifies whether the pull up is made active or inactive
1170 *
1171 * Return codes:
1172 * 0: Success
1173 * -EINVAL: If the gadget passed is NULL
1174 */
1175static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1176{
1177 struct pch_udc_dev *dev;
1178
1179 if (!gadget)
1180 return -EINVAL;
1181 dev = container_of(gadget, struct pch_udc_dev, gadget);
1c575d2d
TM		 1182 if (is_on) {
1183 pch_udc_reconnect(dev);
1184 } else {
1185 if (dev->driver && dev->driver->disconnect) {
1186 spin_unlock(&dev->lock);
1187 dev->driver->disconnect(&dev->gadget);
1188 spin_lock(&dev->lock);
1189 }
1190 pch_udc_set_disconnect(dev);
1191 }
1192
f646cf94
TO		 1193 return 0;
1194}
1195
1196/**
1197 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1198 * transceiver (or GPIO) that
1199 * detects a VBUS power session starting/ending
1200 * @gadget: Reference to the gadget driver
1201 * @is_active: specifies whether the session is starting or ending
1202 *
1203 * Return codes:
1204 * 0: Success
1205 * -EINVAL: If the gadget passed is NULL
1206 */
1207static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1208{
1209 struct pch_udc_dev *dev;
1210
1211 if (!gadget)
1212 return -EINVAL;
1213 dev = container_of(gadget, struct pch_udc_dev, gadget);
1214 pch_udc_vbus_session(dev, is_active);
1215 return 0;
1216}
1217
1218/**
1219 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1220 * SET_CONFIGURATION calls to
1221 * specify how much power the device can consume
1222 * @gadget: Reference to the gadget driver
1223 * @mA: specifies the current limit in 2mA unit
1224 *
1225 * Return codes:
1226 * -EINVAL: If the gadget passed is NULL
1227 * -EOPNOTSUPP:
1228 */
1229static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1230{
1231 return -EOPNOTSUPP;
1232}
1233
0f91349b
SAS		 1234static int pch_udc_start(struct usb_gadget_driver *driver,
1235 int (*bind)(struct usb_gadget *));
1236static int pch_udc_stop(struct usb_gadget_driver *driver);
f646cf94
TO		 1237static const struct usb_gadget_ops pch_udc_ops = {
1238 .get_frame = pch_udc_pcd_get_frame,
1239 .wakeup = pch_udc_pcd_wakeup,
1240 .set_selfpowered = pch_udc_pcd_selfpowered,
1241 .pullup = pch_udc_pcd_pullup,
1242 .vbus_session = pch_udc_pcd_vbus_session,
1243 .vbus_draw = pch_udc_pcd_vbus_draw,
0f91349b
SAS		 1244 .start = pch_udc_start,
1245 .stop = pch_udc_stop,
f646cf94
TO		 1246};
1247
dd63180b
TM		 1248/**
1249 * pch_vbus_gpio_get_value() - This API gets value of GPIO port as VBUS status.
1250 * @dev: Reference to the driver structure
1251 *
1252 * Return value:
1253 * 1: VBUS is high
1254 * 0: VBUS is low
1255 * -1: It is not enable to detect VBUS using GPIO
1256 */
1257static int pch_vbus_gpio_get_value(struct pch_udc_dev *dev)
1258{
1259 int vbus = 0;
1260
1261 if (dev->vbus_gpio.port)
1262 vbus = gpio_get_value(dev->vbus_gpio.port) ? 1 : 0;
1263 else
1264 vbus = -1;
1265
1266 return vbus;
1267}
1268
1269/**
1270 * pch_vbus_gpio_work_fall() - This API keeps watch on VBUS becoming Low.
1271 * If VBUS is Low, disconnect is processed
1272 * @irq_work: Structure for WorkQueue
1273 *
1274 */
1275static void pch_vbus_gpio_work_fall(struct work_struct *irq_work)
1276{
1277 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1278 struct pch_vbus_gpio_data, irq_work_fall);
1279 struct pch_udc_dev *dev =
1280 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1281 int vbus_saved = -1;
1282 int vbus;
1283 int count;
1284
1285 if (!dev->vbus_gpio.port)
1286 return;
1287
1288 for (count = 0; count < (PCH_VBUS_PERIOD / PCH_VBUS_INTERVAL);
1289 count++) {
1290 vbus = pch_vbus_gpio_get_value(dev);
1291
1292 if ((vbus_saved == vbus) && (vbus == 0)) {
1293 dev_dbg(&dev->pdev->dev, "VBUS fell");
1294 if (dev->driver
1295 && dev->driver->disconnect) {
1296 dev->driver->disconnect(
1297 &dev->gadget);
1298 }
1299 pch_udc_reconnect(dev);
1300 dev_dbg(&dev->pdev->dev, "VBUS fell");
1301 return;
1302 }
1303 vbus_saved = vbus;
1304 mdelay(PCH_VBUS_INTERVAL);
1305 }
1306}
1307
1308/**
1309 * pch_vbus_gpio_init() - This API initializes GPIO port detecting VBUS.
1310 * @dev: Reference to the driver structure
1311 * @vbus_gpio Number of GPIO port to detect gpio
1312 *
1313 * Return codes:
1314 * 0: Success
1315 * -EINVAL: GPIO port is invalid or can't be initialized.
1316 */
1317static int pch_vbus_gpio_init(struct pch_udc_dev *dev, int vbus_gpio_port)
1318{
1319 int err;
1320
1321 dev->vbus_gpio.port = 0;
1322
1323 if (vbus_gpio_port <= -1)
1324 return -EINVAL;
1325
1326 err = gpio_is_valid(vbus_gpio_port);
1327 if (!err) {
1328 pr_err("%s: gpio port %d is invalid\n",
1329 __func__, vbus_gpio_port);
1330 return -EINVAL;
1331 }
1332
1333 err = gpio_request(vbus_gpio_port, "pch_vbus");
1334 if (err) {
1335 pr_err("%s: can't request gpio port %d, err: %d\n",
1336 __func__, vbus_gpio_port, err);
1337 return -EINVAL;
1338 }
1339
1340 dev->vbus_gpio.port = vbus_gpio_port;
1341 gpio_direction_input(vbus_gpio_port);
1342 INIT_WORK(&dev->vbus_gpio.irq_work_fall, pch_vbus_gpio_work_fall);
1343
1344 return 0;
1345}
1346
1347/**
1348 * pch_vbus_gpio_free() - This API frees resources of GPIO port
1349 * @dev: Reference to the driver structure
1350 */
1351static void pch_vbus_gpio_free(struct pch_udc_dev *dev)
1352{
1353 if (dev->vbus_gpio.port)
1354 gpio_free(dev->vbus_gpio.port);
1355}
1356
f646cf94
TO		 1357/**
1358 * complete_req() - This API is invoked from the driver when processing
1359 * of a request is complete
1360 * @ep: Reference to the endpoint structure
1361 * @req: Reference to the request structure
1362 * @status: Indicates the success/failure of completion
1363 */
1364static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1365 int status)
1366{
1367 struct pch_udc_dev *dev;
1368 unsigned halted = ep->halted;
1369
1370 list_del_init(&req->queue);
1371
1372 /* set new status if pending */
1373 if (req->req.status == -EINPROGRESS)
1374 req->req.status = status;
1375 else
1376 status = req->req.status;
1377
1378 dev = ep->dev;
1379 if (req->dma_mapped) {
c17f459c
TO		 1380 if (req->dma == DMA_ADDR_INVALID) {
1381 if (ep->in)
1382 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1383 req->req.length,
1384 DMA_TO_DEVICE);
1385 else
1386 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1387 req->req.length,
1388 DMA_FROM_DEVICE);
1389 req->req.dma = DMA_ADDR_INVALID;
1390 } else {
1391 if (ep->in)
1392 dma_unmap_single(&dev->pdev->dev, req->dma,
1393 req->req.length,
1394 DMA_TO_DEVICE);
1395 else {
1396 dma_unmap_single(&dev->pdev->dev, req->dma,
1397 req->req.length,
1398 DMA_FROM_DEVICE);
1399 memcpy(req->req.buf, req->buf, req->req.length);
1400 }
1401 kfree(req->buf);
1402 req->dma = DMA_ADDR_INVALID;
1403 }
f646cf94 1404 req->dma_mapped = 0;
f646cf94
TO		 1405 }
1406 ep->halted = 1;
1407 spin_unlock(&dev->lock);
1408 if (!ep->in)
1409 pch_udc_ep_clear_rrdy(ep);
1410 req->req.complete(&ep->ep, &req->req);
1411 spin_lock(&dev->lock);
1412 ep->halted = halted;
1413}
1414
1415/**
1416 * empty_req_queue() - This API empties the request queue of an endpoint
1417 * @ep: Reference to the endpoint structure
1418 */
1419static void empty_req_queue(struct pch_udc_ep *ep)
1420{
1421 struct pch_udc_request *req;
1422
1423 ep->halted = 1;
1424 while (!list_empty(&ep->queue)) {
1425 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1426 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1427 }
1428}
1429
1430/**
1431 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1432 * for the request
1433 * @dev Reference to the driver structure
1434 * @req Reference to the request to be freed
1435 *
1436 * Return codes:
1437 * 0: Success
1438 */
1439static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1440 struct pch_udc_request *req)
1441{
1442 struct pch_udc_data_dma_desc *td = req->td_data;
1443 unsigned i = req->chain_len;
1444
c17f459c
TO		 1445 dma_addr_t addr2;
1446 dma_addr_t addr = (dma_addr_t)td->next;
1447 td->next = 0x00;
f646cf94 1448 for (; i > 1; --i) {
f646cf94
TO		 1449 /* do not free first desc., will be done by free for request */
1450 td = phys_to_virt(addr);
c17f459c 1451 addr2 = (dma_addr_t)td->next;
f646cf94 1452 pci_pool_free(dev->data_requests, td, addr);
c17f459c
TO		 1453 td->next = 0x00;
1454 addr = addr2;
f646cf94 1455 }
c17f459c 1456 req->chain_len = 1;
f646cf94
TO		 1457}
1458
1459/**
1460 * pch_udc_create_dma_chain() - This function creates or reinitializes
1461 * a DMA chain
1462 * @ep: Reference to the endpoint structure
1463 * @req: Reference to the request
1464 * @buf_len: The buffer length
1465 * @gfp_flags: Flags to be used while mapping the data buffer
1466 *
1467 * Return codes:
1468 * 0: success,
1469 * -ENOMEM: pci_pool_alloc invocation fails
1470 */
1471static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1472 struct pch_udc_request *req,
1473 unsigned long buf_len,
1474 gfp_t gfp_flags)
1475{
1476 struct pch_udc_data_dma_desc *td = req->td_data, *last;
1477 unsigned long bytes = req->req.length, i = 0;
1478 dma_addr_t dma_addr;
1479 unsigned len = 1;
1480
1481 if (req->chain_len > 1)
1482 pch_udc_free_dma_chain(ep->dev, req);
1483
c17f459c
TO		 1484 if (req->dma == DMA_ADDR_INVALID)
1485 td->dataptr = req->req.dma;
1486 else
1487 td->dataptr = req->dma;
f646cf94 1488
c17f459c
TO		 1489 td->status = PCH_UDC_BS_HST_BSY;
1490 for (; ; bytes -= buf_len, ++len) {
1491 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
f646cf94
TO		 1492 if (bytes <= buf_len)
1493 break;
f646cf94
TO		 1494 last = td;
1495 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1496 &dma_addr);
1497 if (!td)
1498 goto nomem;
f646cf94 1499 i += buf_len;
c17f459c 1500 td->dataptr = req->td_data->dataptr + i;
f646cf94
TO		 1501 last->next = dma_addr;
1502 }
1503
1504 req->td_data_last = td;
1505 td->status |= PCH_UDC_DMA_LAST;
1506 td->next = req->td_data_phys;
1507 req->chain_len = len;
1508 return 0;
1509
1510nomem:
1511 if (len > 1) {
1512 req->chain_len = len;
1513 pch_udc_free_dma_chain(ep->dev, req);
1514 }
1515 req->chain_len = 1;
1516 return -ENOMEM;
1517}
1518
1519/**
1520 * prepare_dma() - This function creates and initializes the DMA chain
1521 * for the request
1522 * @ep: Reference to the endpoint structure
1523 * @req: Reference to the request
1524 * @gfp: Flag to be used while mapping the data buffer
1525 *
1526 * Return codes:
1527 * 0: Success
1528 * Other 0: linux error number on failure
1529 */
1530static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1531 gfp_t gfp)
1532{
1533 int retval;
1534
f646cf94
TO		 1535 /* Allocate and create a DMA chain */
1536 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1537 if (retval) {
c17f459c 1538 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
f646cf94
TO		 1539 return retval;
1540 }
c17f459c 1541 if (ep->in)
f646cf94 1542 req->td_data->status = (req->td_data->status &
c17f459c 1543 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
f646cf94
TO		 1544 return 0;
1545}
1546
1547/**
1548 * process_zlp() - This function process zero length packets
1549 * from the gadget driver
1550 * @ep: Reference to the endpoint structure
1551 * @req: Reference to the request
1552 */
1553static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1554{
1555 struct pch_udc_dev *dev = ep->dev;
1556
1557 /* IN zlp's are handled by hardware */
1558 complete_req(ep, req, 0);
1559
1560 /* if set_config or set_intf is waiting for ack by zlp
1561 * then set CSR_DONE
1562 */
1563 if (dev->set_cfg_not_acked) {
1564 pch_udc_set_csr_done(dev);
1565 dev->set_cfg_not_acked = 0;
1566 }
1567 /* setup command is ACK'ed now by zlp */
1568 if (!dev->stall && dev->waiting_zlp_ack) {
1569 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1570 dev->waiting_zlp_ack = 0;
1571 }
1572}
1573
1574/**
1575 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1576 * @ep: Reference to the endpoint structure
1577 * @req: Reference to the request structure
1578 */
1579static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1580 struct pch_udc_request *req)
1581{
1582 struct pch_udc_data_dma_desc *td_data;
1583
1584 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1585 td_data = req->td_data;
f646cf94
TO		 1586 /* Set the status bits for all descriptors */
1587 while (1) {
1588 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1589 PCH_UDC_BS_HST_RDY;
1590 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1591 break;
1592 td_data = phys_to_virt(td_data->next);
1593 }
1594 /* Write the descriptor pointer */
1595 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1596 req->dma_going = 1;
1597 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1598 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1599 pch_udc_ep_clear_nak(ep);
1600 pch_udc_ep_set_rrdy(ep);
1601}
1602
1603/**
1604 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1605 * from gadget driver
1606 * @usbep: Reference to the USB endpoint structure
1607 * @desc: Reference to the USB endpoint descriptor structure
1608 *
1609 * Return codes:
1610 * 0: Success
1611 * -EINVAL:
1612 * -ESHUTDOWN:
1613 */
1614static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1615 const struct usb_endpoint_descriptor *desc)
1616{
1617 struct pch_udc_ep *ep;
1618 struct pch_udc_dev *dev;
1619 unsigned long iflags;
1620
1621 if (!usbep || (usbep->name == ep0_string) || !desc ||
1622 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1623 return -EINVAL;
1624
1625 ep = container_of(usbep, struct pch_udc_ep, ep);
1626 dev = ep->dev;
1627 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1628 return -ESHUTDOWN;
1629 spin_lock_irqsave(&dev->lock, iflags);
1630 ep->desc = desc;
1631 ep->halted = 0;
1632 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
29cc8897 1633 ep->ep.maxpacket = usb_endpoint_maxp(desc);
f646cf94
TO		 1634 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1635 spin_unlock_irqrestore(&dev->lock, iflags);
1636 return 0;
1637}
1638
1639/**
1640 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1641 * from gadget driver
1642 * @usbep Reference to the USB endpoint structure
1643 *
1644 * Return codes:
1645 * 0: Success
1646 * -EINVAL:
1647 */
1648static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1649{
1650 struct pch_udc_ep *ep;
1651 struct pch_udc_dev *dev;
1652 unsigned long iflags;
1653
1654 if (!usbep)
1655 return -EINVAL;
1656
1657 ep = container_of(usbep, struct pch_udc_ep, ep);
1658 dev = ep->dev;
1659 if ((usbep->name == ep0_string) || !ep->desc)
1660 return -EINVAL;
1661
1662 spin_lock_irqsave(&ep->dev->lock, iflags);
1663 empty_req_queue(ep);
1664 ep->halted = 1;
1665 pch_udc_ep_disable(ep);
1666 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1667 ep->desc = NULL;
1668 INIT_LIST_HEAD(&ep->queue);
1669 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1670 return 0;
1671}
1672
1673/**
1674 * pch_udc_alloc_request() - This function allocates request structure.
1675 * It is called by gadget driver
1676 * @usbep: Reference to the USB endpoint structure
1677 * @gfp: Flag to be used while allocating memory
1678 *
1679 * Return codes:
1680 * NULL: Failure
1681 * Allocated address: Success
1682 */
1683static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1684 gfp_t gfp)
1685{
1686 struct pch_udc_request *req;
1687 struct pch_udc_ep *ep;
1688 struct pch_udc_data_dma_desc *dma_desc;
1689 struct pch_udc_dev *dev;
1690
1691 if (!usbep)
1692 return NULL;
1693 ep = container_of(usbep, struct pch_udc_ep, ep);
1694 dev = ep->dev;
1695 req = kzalloc(sizeof *req, gfp);
1696 if (!req)
1697 return NULL;
1698 req->req.dma = DMA_ADDR_INVALID;
c17f459c 1699 req->dma = DMA_ADDR_INVALID;
f646cf94
TO		 1700 INIT_LIST_HEAD(&req->queue);
1701 if (!ep->dev->dma_addr)
1702 return &req->req;
1703 /* ep0 in requests are allocated from data pool here */
1704 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1705 &req->td_data_phys);
1706 if (NULL == dma_desc) {
1707 kfree(req);
1708 return NULL;
1709 }
1710 /* prevent from using desc. - set HOST BUSY */
1711 dma_desc->status |= PCH_UDC_BS_HST_BSY;
1712 dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID);
1713 req->td_data = dma_desc;
1714 req->td_data_last = dma_desc;
1715 req->chain_len = 1;
1716 return &req->req;
1717}
1718
1719/**
1720 * pch_udc_free_request() - This function frees request structure.
1721 * It is called by gadget driver
1722 * @usbep: Reference to the USB endpoint structure
1723 * @usbreq: Reference to the USB request
1724 */
1725static void pch_udc_free_request(struct usb_ep *usbep,
1726 struct usb_request *usbreq)
1727{
1728 struct pch_udc_ep *ep;
1729 struct pch_udc_request *req;
1730 struct pch_udc_dev *dev;
1731
1732 if (!usbep || !usbreq)
1733 return;
1734 ep = container_of(usbep, struct pch_udc_ep, ep);
1735 req = container_of(usbreq, struct pch_udc_request, req);
1736 dev = ep->dev;
1737 if (!list_empty(&req->queue))
1738 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1739 __func__, usbep->name, req);
1740 if (req->td_data != NULL) {
1741 if (req->chain_len > 1)
1742 pch_udc_free_dma_chain(ep->dev, req);
1743 pci_pool_free(ep->dev->data_requests, req->td_data,
1744 req->td_data_phys);
1745 }
1746 kfree(req);
1747}
1748
1749/**
1750 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1751 * by gadget driver
1752 * @usbep: Reference to the USB endpoint structure
1753 * @usbreq: Reference to the USB request
1754 * @gfp: Flag to be used while mapping the data buffer
1755 *
1756 * Return codes:
1757 * 0: Success
1758 * linux error number: Failure
1759 */
1760static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1761 gfp_t gfp)
1762{
1763 int retval = 0;
1764 struct pch_udc_ep *ep;
1765 struct pch_udc_dev *dev;
1766 struct pch_udc_request *req;
1767 unsigned long iflags;
1768
1769 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1770 return -EINVAL;
1771 ep = container_of(usbep, struct pch_udc_ep, ep);
1772 dev = ep->dev;
1773 if (!ep->desc && ep->num)
1774 return -EINVAL;
1775 req = container_of(usbreq, struct pch_udc_request, req);
1776 if (!list_empty(&req->queue))
1777 return -EINVAL;
1778 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1779 return -ESHUTDOWN;
48570711 1780 spin_lock_irqsave(&dev->lock, iflags);
f646cf94
TO		 1781 /* map the buffer for dma */
1782 if (usbreq->length &&
1783 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
c17f459c
TO		 1784 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1785 if (ep->in)
1786 usbreq->dma = dma_map_single(&dev->pdev->dev,
1787 usbreq->buf,
1788 usbreq->length,
1789 DMA_TO_DEVICE);
1790 else
1791 usbreq->dma = dma_map_single(&dev->pdev->dev,
1792 usbreq->buf,
1793 usbreq->length,
1794 DMA_FROM_DEVICE);
1795 } else {
1796 req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
48570711
DC		 1797 if (!req->buf) {
1798 retval = -ENOMEM;
1799 goto probe_end;
1800 }
c17f459c
TO		 1801 if (ep->in) {
1802 memcpy(req->buf, usbreq->buf, usbreq->length);
1803 req->dma = dma_map_single(&dev->pdev->dev,
1804 req->buf,
1805 usbreq->length,
1806 DMA_TO_DEVICE);
1807 } else
1808 req->dma = dma_map_single(&dev->pdev->dev,
1809 req->buf,
1810 usbreq->length,
1811 DMA_FROM_DEVICE);
1812 }
f646cf94
TO		 1813 req->dma_mapped = 1;
1814 }
1815 if (usbreq->length > 0) {
abab0c67 1816 retval = prepare_dma(ep, req, GFP_ATOMIC);
f646cf94
TO		 1817 if (retval)
1818 goto probe_end;
1819 }
1820 usbreq->actual = 0;
1821 usbreq->status = -EINPROGRESS;
1822 req->dma_done = 0;
1823 if (list_empty(&ep->queue) && !ep->halted) {
1824 /* no pending transfer, so start this req */
1825 if (!usbreq->length) {
1826 process_zlp(ep, req);
1827 retval = 0;
1828 goto probe_end;
1829 }
1830 if (!ep->in) {
1831 pch_udc_start_rxrequest(ep, req);
1832 } else {
1833 /*
1834 * For IN trfr the descriptors will be programmed and
1835 * P bit will be set when
1836 * we get an IN token
1837 */
1838 pch_udc_wait_ep_stall(ep);
1839 pch_udc_ep_clear_nak(ep);
1840 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
f646cf94
TO		 1841 }
1842 }
1843 /* Now add this request to the ep's pending requests */
1844 if (req != NULL)
1845 list_add_tail(&req->queue, &ep->queue);
1846
1847probe_end:
1848 spin_unlock_irqrestore(&dev->lock, iflags);
1849 return retval;
1850}
1851
1852/**
1853 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1854 * It is called by gadget driver
1855 * @usbep: Reference to the USB endpoint structure
1856 * @usbreq: Reference to the USB request
1857 *
1858 * Return codes:
1859 * 0: Success
1860 * linux error number: Failure
1861 */
1862static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1863 struct usb_request *usbreq)
1864{
1865 struct pch_udc_ep *ep;
1866 struct pch_udc_request *req;
1867 struct pch_udc_dev *dev;
1868 unsigned long flags;
1869 int ret = -EINVAL;
1870
1871 ep = container_of(usbep, struct pch_udc_ep, ep);
1872 dev = ep->dev;
1873 if (!usbep || !usbreq || (!ep->desc && ep->num))
1874 return ret;
1875 req = container_of(usbreq, struct pch_udc_request, req);
1876 spin_lock_irqsave(&ep->dev->lock, flags);
1877 /* make sure it's still queued on this endpoint */
1878 list_for_each_entry(req, &ep->queue, queue) {
1879 if (&req->req == usbreq) {
1880 pch_udc_ep_set_nak(ep);
1881 if (!list_empty(&req->queue))
1882 complete_req(ep, req, -ECONNRESET);
1883 ret = 0;
1884 break;
1885 }
1886 }
1887 spin_unlock_irqrestore(&ep->dev->lock, flags);
1888 return ret;
1889}
1890
1891/**
1892 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1893 * feature
1894 * @usbep: Reference to the USB endpoint structure
1895 * @halt: Specifies whether to set or clear the feature
1896 *
1897 * Return codes:
1898 * 0: Success
1899 * linux error number: Failure
1900 */
1901static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1902{
1903 struct pch_udc_ep *ep;
1904 struct pch_udc_dev *dev;
1905 unsigned long iflags;
1906 int ret;
1907
1908 if (!usbep)
1909 return -EINVAL;
1910 ep = container_of(usbep, struct pch_udc_ep, ep);
1911 dev = ep->dev;
1912 if (!ep->desc && !ep->num)
1913 return -EINVAL;
1914 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1915 return -ESHUTDOWN;
1916 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1917 if (list_empty(&ep->queue)) {
1918 if (halt) {
1919 if (ep->num == PCH_UDC_EP0)
1920 ep->dev->stall = 1;
1921 pch_udc_ep_set_stall(ep);
1922 pch_udc_enable_ep_interrupts(ep->dev,
1923 PCH_UDC_EPINT(ep->in,
1924 ep->num));
1925 } else {
1926 pch_udc_ep_clear_stall(ep);
1927 }
1928 ret = 0;
1929 } else {
1930 ret = -EAGAIN;
1931 }
1932 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1933 return ret;
1934}
1935
1936/**
1937 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
1938 * halt feature
1939 * @usbep: Reference to the USB endpoint structure
1940 * @halt: Specifies whether to set or clear the feature
1941 *
1942 * Return codes:
1943 * 0: Success
1944 * linux error number: Failure
1945 */
1946static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
1947{
1948 struct pch_udc_ep *ep;
1949 struct pch_udc_dev *dev;
1950 unsigned long iflags;
1951 int ret;
1952
1953 if (!usbep)
1954 return -EINVAL;
1955 ep = container_of(usbep, struct pch_udc_ep, ep);
1956 dev = ep->dev;
1957 if (!ep->desc && !ep->num)
1958 return -EINVAL;
1959 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1960 return -ESHUTDOWN;
1961 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1962 if (!list_empty(&ep->queue)) {
1963 ret = -EAGAIN;
1964 } else {
1965 if (ep->num == PCH_UDC_EP0)
1966 ep->dev->stall = 1;
1967 pch_udc_ep_set_stall(ep);
1968 pch_udc_enable_ep_interrupts(ep->dev,
1969 PCH_UDC_EPINT(ep->in, ep->num));
1970 ep->dev->prot_stall = 1;
1971 ret = 0;
1972 }
1973 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1974 return ret;
1975}
1976
1977/**
1978 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
1979 * @usbep: Reference to the USB endpoint structure
1980 */
1981static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
1982{
1983 struct pch_udc_ep *ep;
1984
1985 if (!usbep)
1986 return;
1987
1988 ep = container_of(usbep, struct pch_udc_ep, ep);
1989 if (ep->desc || !ep->num)
1990 pch_udc_ep_fifo_flush(ep, ep->in);
1991}
1992
1993static const struct usb_ep_ops pch_udc_ep_ops = {
1994 .enable = pch_udc_pcd_ep_enable,
1995 .disable = pch_udc_pcd_ep_disable,
1996 .alloc_request = pch_udc_alloc_request,
1997 .free_request = pch_udc_free_request,
1998 .queue = pch_udc_pcd_queue,
1999 .dequeue = pch_udc_pcd_dequeue,
2000 .set_halt = pch_udc_pcd_set_halt,
2001 .set_wedge = pch_udc_pcd_set_wedge,
2002 .fifo_status = NULL,
2003 .fifo_flush = pch_udc_pcd_fifo_flush,
2004};
2005
2006/**
2007 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
2008 * @td_stp: Reference to the SETP buffer structure
2009 */
2010static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
2011{
2012 static u32 pky_marker;
2013
2014 if (!td_stp)
2015 return;
2016 td_stp->reserved = ++pky_marker;
2017 memset(&td_stp->request, 0xFF, sizeof td_stp->request);
2018 td_stp->status = PCH_UDC_BS_HST_RDY;
2019}
2020
2021/**
2022 * pch_udc_start_next_txrequest() - This function starts
2023 * the next transmission requirement
2024 * @ep: Reference to the endpoint structure
2025 */
2026static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
2027{
2028 struct pch_udc_request *req;
2029 struct pch_udc_data_dma_desc *td_data;
2030
2031 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
2032 return;
2033
2034 if (list_empty(&ep->queue))
2035 return;
2036
2037 /* next request */
2038 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2039 if (req->dma_going)
2040 return;
2041 if (!req->td_data)
2042 return;
2043 pch_udc_wait_ep_stall(ep);
2044 req->dma_going = 1;
2045 pch_udc_ep_set_ddptr(ep, 0);
2046 td_data = req->td_data;
2047 while (1) {
2048 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
2049 PCH_UDC_BS_HST_RDY;
2050 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
2051 break;
2052 td_data = phys_to_virt(td_data->next);
2053 }
2054 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
2055 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
2056 pch_udc_ep_set_pd(ep);
2057 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2058 pch_udc_ep_clear_nak(ep);
2059}
2060
2061/**
2062 * pch_udc_complete_transfer() - This function completes a transfer
2063 * @ep: Reference to the endpoint structure
2064 */
2065static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
2066{
2067 struct pch_udc_request *req;
2068 struct pch_udc_dev *dev = ep->dev;
2069
2070 if (list_empty(&ep->queue))
2071 return;
2072 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2073 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2074 PCH_UDC_BS_DMA_DONE)
2075 return;
2076 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
2077 PCH_UDC_RTS_SUCC) {
2078 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
2079 "epstatus=0x%08x\n",
2080 (req->td_data_last->status & PCH_UDC_RXTX_STS),
2081 (int)(ep->epsts));
2082 return;
2083 }
2084
2085 req->req.actual = req->req.length;
2086 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2087 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2088 complete_req(ep, req, 0);
2089 req->dma_going = 0;
2090 if (!list_empty(&ep->queue)) {
2091 pch_udc_wait_ep_stall(ep);
2092 pch_udc_ep_clear_nak(ep);
2093 pch_udc_enable_ep_interrupts(ep->dev,
2094 PCH_UDC_EPINT(ep->in, ep->num));
2095 } else {
2096 pch_udc_disable_ep_interrupts(ep->dev,
2097 PCH_UDC_EPINT(ep->in, ep->num));
2098 }
2099}
2100
2101/**
2102 * pch_udc_complete_receiver() - This function completes a receiver
2103 * @ep: Reference to the endpoint structure
2104 */
2105static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
2106{
2107 struct pch_udc_request *req;
2108 struct pch_udc_dev *dev = ep->dev;
2109 unsigned int count;
c17f459c
TO		 2110 struct pch_udc_data_dma_desc *td;
2111 dma_addr_t addr;
f646cf94
TO		 2112
2113 if (list_empty(&ep->queue))
2114 return;
f646cf94
TO		 2115 /* next request */
2116 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
f646cf94 2117 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
abab0c67 2118 pch_udc_ep_set_ddptr(ep, 0);
c17f459c
TO		 2119 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
2120 PCH_UDC_BS_DMA_DONE)
2121 td = req->td_data_last;
2122 else
2123 td = req->td_data;
f646cf94 2124
c17f459c
TO		 2125 while (1) {
2126 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
2127 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
2128 "epstatus=0x%08x\n",
2129 (req->td_data->status & PCH_UDC_RXTX_STS),
2130 (int)(ep->epsts));
2131 return;
2132 }
2133 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2134 if (td->status | PCH_UDC_DMA_LAST) {
2135 count = td->status & PCH_UDC_RXTX_BYTES;
2136 break;
2137 }
2138 if (td == req->td_data_last) {
2139 dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2140 return;
2141 }
2142 addr = (dma_addr_t)td->next;
2143 td = phys_to_virt(addr);
2144 }
f646cf94
TO		 2145 /* on 64k packets the RXBYTES field is zero */
2146 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2147 count = UDC_DMA_MAXPACKET;
2148 req->td_data->status |= PCH_UDC_DMA_LAST;
c17f459c 2149 td->status |= PCH_UDC_BS_HST_BSY;
f646cf94
TO		 2150
2151 req->dma_going = 0;
2152 req->req.actual = count;
2153 complete_req(ep, req, 0);
2154 /* If there is a new/failed requests try that now */
2155 if (!list_empty(&ep->queue)) {
2156 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2157 pch_udc_start_rxrequest(ep, req);
2158 }
2159}
2160
2161/**
2162 * pch_udc_svc_data_in() - This function process endpoint interrupts
2163 * for IN endpoints
2164 * @dev: Reference to the device structure
2165 * @ep_num: Endpoint that generated the interrupt
2166 */
2167static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2168{
2169 u32 epsts;
2170 struct pch_udc_ep *ep;
2171
abab0c67 2172 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
f646cf94
TO		 2173 epsts = ep->epsts;
2174 ep->epsts = 0;
2175
2176 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2177 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2178 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2179 return;
2180 if ((epsts & UDC_EPSTS_BNA))
2181 return;
2182 if (epsts & UDC_EPSTS_HE)
2183 return;
2184 if (epsts & UDC_EPSTS_RSS) {
2185 pch_udc_ep_set_stall(ep);
2186 pch_udc_enable_ep_interrupts(ep->dev,
2187 PCH_UDC_EPINT(ep->in, ep->num));
2188 }
49e20834 2189 if (epsts & UDC_EPSTS_RCS) {
f646cf94
TO		 2190 if (!dev->prot_stall) {
2191 pch_udc_ep_clear_stall(ep);
2192 } else {
2193 pch_udc_ep_set_stall(ep);
2194 pch_udc_enable_ep_interrupts(ep->dev,
2195 PCH_UDC_EPINT(ep->in, ep->num));
2196 }
49e20834 2197 }
f646cf94
TO		 2198 if (epsts & UDC_EPSTS_TDC)
2199 pch_udc_complete_transfer(ep);
2200 /* On IN interrupt, provide data if we have any */
2201 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2202 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2203 pch_udc_start_next_txrequest(ep);
2204}
2205
2206/**
2207 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2208 * @dev: Reference to the device structure
2209 * @ep_num: Endpoint that generated the interrupt
2210 */
2211static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2212{
2213 u32 epsts;
2214 struct pch_udc_ep *ep;
2215 struct pch_udc_request *req = NULL;
2216
abab0c67 2217 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
f646cf94
TO		 2218 epsts = ep->epsts;
2219 ep->epsts = 0;
2220
2221 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2222 /* next request */
2223 req = list_entry(ep->queue.next, struct pch_udc_request,
2224 queue);
2225 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2226 PCH_UDC_BS_DMA_DONE) {
2227 if (!req->dma_going)
2228 pch_udc_start_rxrequest(ep, req);
2229 return;
2230 }
2231 }
2232 if (epsts & UDC_EPSTS_HE)
2233 return;
abab0c67 2234 if (epsts & UDC_EPSTS_RSS) {
f646cf94
TO		 2235 pch_udc_ep_set_stall(ep);
2236 pch_udc_enable_ep_interrupts(ep->dev,
2237 PCH_UDC_EPINT(ep->in, ep->num));
abab0c67 2238 }
49e20834 2239 if (epsts & UDC_EPSTS_RCS) {
f646cf94
TO		 2240 if (!dev->prot_stall) {
2241 pch_udc_ep_clear_stall(ep);
2242 } else {
2243 pch_udc_ep_set_stall(ep);
2244 pch_udc_enable_ep_interrupts(ep->dev,
2245 PCH_UDC_EPINT(ep->in, ep->num));
2246 }
49e20834 2247 }
f646cf94
TO		 2248 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2249 UDC_EPSTS_OUT_DATA) {
2250 if (ep->dev->prot_stall == 1) {
2251 pch_udc_ep_set_stall(ep);
2252 pch_udc_enable_ep_interrupts(ep->dev,
2253 PCH_UDC_EPINT(ep->in, ep->num));
2254 } else {
2255 pch_udc_complete_receiver(ep);
2256 }
2257 }
2258 if (list_empty(&ep->queue))
2259 pch_udc_set_dma(dev, DMA_DIR_RX);
2260}
2261
2262/**
2263 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2264 * @dev: Reference to the device structure
2265 */
2266static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2267{
2268 u32 epsts;
2269 struct pch_udc_ep *ep;
abab0c67 2270 struct pch_udc_ep *ep_out;
f646cf94
TO		 2271
2272 ep = &dev->ep[UDC_EP0IN_IDX];
abab0c67 2273 ep_out = &dev->ep[UDC_EP0OUT_IDX];
f646cf94
TO		 2274 epsts = ep->epsts;
2275 ep->epsts = 0;
2276
2277 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2278 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2279 UDC_EPSTS_XFERDONE)))
2280 return;
2281 if ((epsts & UDC_EPSTS_BNA))
2282 return;
2283 if (epsts & UDC_EPSTS_HE)
2284 return;
abab0c67 2285 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
f646cf94 2286 pch_udc_complete_transfer(ep);
abab0c67
TO		 2287 pch_udc_clear_dma(dev, DMA_DIR_RX);
2288 ep_out->td_data->status = (ep_out->td_data->status &
2289 ~PCH_UDC_BUFF_STS) |
2290 PCH_UDC_BS_HST_RDY;
2291 pch_udc_ep_clear_nak(ep_out);
2292 pch_udc_set_dma(dev, DMA_DIR_RX);
2293 pch_udc_ep_set_rrdy(ep_out);
2294 }
f646cf94
TO		 2295 /* On IN interrupt, provide data if we have any */
2296 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2297 !(epsts & UDC_EPSTS_TXEMPTY))
2298 pch_udc_start_next_txrequest(ep);
2299}
2300
2301/**
2302 * pch_udc_svc_control_out() - Routine that handle Control
2303 * OUT endpoint interrupts
2304 * @dev: Reference to the device structure
2305 */
2306static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2307{
2308 u32 stat;
2309 int setup_supported;
2310 struct pch_udc_ep *ep;
2311
2312 ep = &dev->ep[UDC_EP0OUT_IDX];
2313 stat = ep->epsts;
2314 ep->epsts = 0;
2315
2316 /* If setup data */
2317 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2318 UDC_EPSTS_OUT_SETUP) {
2319 dev->stall = 0;
2320 dev->ep[UDC_EP0IN_IDX].halted = 0;
2321 dev->ep[UDC_EP0OUT_IDX].halted = 0;
f646cf94
TO		 2322 dev->setup_data = ep->td_stp->request;
2323 pch_udc_init_setup_buff(ep->td_stp);
abab0c67 2324 pch_udc_clear_dma(dev, DMA_DIR_RX);
f646cf94
TO		 2325 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2326 dev->ep[UDC_EP0IN_IDX].in);
2327 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2328 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2329 else /* OUT */
2330 dev->gadget.ep0 = &ep->ep;
2331 spin_unlock(&dev->lock);
2332 /* If Mass storage Reset */
2333 if ((dev->setup_data.bRequestType == 0x21) &&
2334 (dev->setup_data.bRequest == 0xFF))
2335 dev->prot_stall = 0;
2336 /* call gadget with setup data received */
2337 setup_supported = dev->driver->setup(&dev->gadget,
2338 &dev->setup_data);
2339 spin_lock(&dev->lock);
abab0c67
TO		 2340
2341 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2342 ep->td_data->status = (ep->td_data->status &
2343 ~PCH_UDC_BUFF_STS) |
2344 PCH_UDC_BS_HST_RDY;
2345 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2346 }
f646cf94
TO		 2347 /* ep0 in returns data on IN phase */
2348 if (setup_supported >= 0 && setup_supported <
2349 UDC_EP0IN_MAX_PKT_SIZE) {
2350 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2351 /* Gadget would have queued a request when
2352 * we called the setup */
abab0c67
TO		 2353 if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2354 pch_udc_set_dma(dev, DMA_DIR_RX);
2355 pch_udc_ep_clear_nak(ep);
2356 }
f646cf94
TO		 2357 } else if (setup_supported < 0) {
2358 /* if unsupported request, then stall */
2359 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2360 pch_udc_enable_ep_interrupts(ep->dev,
2361 PCH_UDC_EPINT(ep->in, ep->num));
2362 dev->stall = 0;
2363 pch_udc_set_dma(dev, DMA_DIR_RX);
2364 } else {
2365 dev->waiting_zlp_ack = 1;
2366 }
2367 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2368 UDC_EPSTS_OUT_DATA) && !dev->stall) {
abab0c67
TO		 2369 pch_udc_clear_dma(dev, DMA_DIR_RX);
2370 pch_udc_ep_set_ddptr(ep, 0);
2371 if (!list_empty(&ep->queue)) {
ff176a4e 2372 ep->epsts = stat;
abab0c67 2373 pch_udc_svc_data_out(dev, PCH_UDC_EP0);
f646cf94 2374 }
abab0c67 2375 pch_udc_set_dma(dev, DMA_DIR_RX);
f646cf94
TO		 2376 }
2377 pch_udc_ep_set_rrdy(ep);
2378}
2379
2380
2381/**
2382 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2383 * and clears NAK status
2384 * @dev: Reference to the device structure
2385 * @ep_num: End point number
2386 */
2387static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2388{
2389 struct pch_udc_ep *ep;
2390 struct pch_udc_request *req;
2391
abab0c67 2392 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
f646cf94
TO		 2393 if (!list_empty(&ep->queue)) {
2394 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2395 pch_udc_enable_ep_interrupts(ep->dev,
2396 PCH_UDC_EPINT(ep->in, ep->num));
2397 pch_udc_ep_clear_nak(ep);
2398 }
2399}
2400
2401/**
2402 * pch_udc_read_all_epstatus() - This function read all endpoint status
2403 * @dev: Reference to the device structure
2404 * @ep_intr: Status of endpoint interrupt
2405 */
2406static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2407{
2408 int i;
2409 struct pch_udc_ep *ep;
2410
2411 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2412 /* IN */
2413 if (ep_intr & (0x1 << i)) {
abab0c67 2414 ep = &dev->ep[UDC_EPIN_IDX(i)];
f646cf94
TO		 2415 ep->epsts = pch_udc_read_ep_status(ep);
2416 pch_udc_clear_ep_status(ep, ep->epsts);
2417 }
2418 /* OUT */
2419 if (ep_intr & (0x10000 << i)) {
abab0c67 2420 ep = &dev->ep[UDC_EPOUT_IDX(i)];
f646cf94
TO		 2421 ep->epsts = pch_udc_read_ep_status(ep);
2422 pch_udc_clear_ep_status(ep, ep->epsts);
2423 }
2424 }
2425}
2426
2427/**
2428 * pch_udc_activate_control_ep() - This function enables the control endpoints
2429 * for traffic after a reset
2430 * @dev: Reference to the device structure
2431 */
2432static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2433{
2434 struct pch_udc_ep *ep;
2435 u32 val;
2436
2437 /* Setup the IN endpoint */
2438 ep = &dev->ep[UDC_EP0IN_IDX];
2439 pch_udc_clear_ep_control(ep);
2440 pch_udc_ep_fifo_flush(ep, ep->in);
2441 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2442 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2443 /* Initialize the IN EP Descriptor */
2444 ep->td_data = NULL;
2445 ep->td_stp = NULL;
2446 ep->td_data_phys = 0;
2447 ep->td_stp_phys = 0;
2448
2449 /* Setup the OUT endpoint */
2450 ep = &dev->ep[UDC_EP0OUT_IDX];
2451 pch_udc_clear_ep_control(ep);
2452 pch_udc_ep_fifo_flush(ep, ep->in);
2453 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2454 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2455 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2456 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2457
2458 /* Initialize the SETUP buffer */
2459 pch_udc_init_setup_buff(ep->td_stp);
2460 /* Write the pointer address of dma descriptor */
2461 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2462 /* Write the pointer address of Setup descriptor */
2463 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2464
2465 /* Initialize the dma descriptor */
2466 ep->td_data->status = PCH_UDC_DMA_LAST;
2467 ep->td_data->dataptr = dev->dma_addr;
2468 ep->td_data->next = ep->td_data_phys;
2469
2470 pch_udc_ep_clear_nak(ep);
2471}
2472
2473
2474/**
2475 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2476 * @dev: Reference to driver structure
2477 */
2478static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2479{
2480 struct pch_udc_ep *ep;
2481 int i;
2482
2483 pch_udc_clear_dma(dev, DMA_DIR_TX);
2484 pch_udc_clear_dma(dev, DMA_DIR_RX);
2485 /* Mask all endpoint interrupts */
2486 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2487 /* clear all endpoint interrupts */
2488 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2489
2490 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2491 ep = &dev->ep[i];
2492 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2493 pch_udc_clear_ep_control(ep);
2494 pch_udc_ep_set_ddptr(ep, 0);
2495 pch_udc_write_csr(ep->dev, 0x00, i);
2496 }
2497 dev->stall = 0;
2498 dev->prot_stall = 0;
2499 dev->waiting_zlp_ack = 0;
2500 dev->set_cfg_not_acked = 0;
2501
2502 /* disable ep to empty req queue. Skip the control EP's */
2503 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2504 ep = &dev->ep[i];
2505 pch_udc_ep_set_nak(ep);
2506 pch_udc_ep_fifo_flush(ep, ep->in);
2507 /* Complete request queue */
2508 empty_req_queue(ep);
2509 }
c50a3bff
TM		 2510 if (dev->driver && dev->driver->disconnect) {
2511 spin_unlock(&dev->lock);
f646cf94 2512 dev->driver->disconnect(&dev->gadget);
c50a3bff
TM		 2513 spin_lock(&dev->lock);
2514 }
f646cf94
TO		 2515}
2516
2517/**
2518 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2519 * done interrupt
2520 * @dev: Reference to driver structure
2521 */
2522static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2523{
2524 u32 dev_stat, dev_speed;
2525 u32 speed = USB_SPEED_FULL;
2526
2527 dev_stat = pch_udc_read_device_status(dev);
2528 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2529 UDC_DEVSTS_ENUM_SPEED_SHIFT;
2530 switch (dev_speed) {
2531 case UDC_DEVSTS_ENUM_SPEED_HIGH:
2532 speed = USB_SPEED_HIGH;
2533 break;
2534 case UDC_DEVSTS_ENUM_SPEED_FULL:
2535 speed = USB_SPEED_FULL;
2536 break;
2537 case UDC_DEVSTS_ENUM_SPEED_LOW:
2538 speed = USB_SPEED_LOW;
2539 break;
2540 default:
2541 BUG();
2542 }
2543 dev->gadget.speed = speed;
2544 pch_udc_activate_control_ep(dev);
2545 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2546 pch_udc_set_dma(dev, DMA_DIR_TX);
2547 pch_udc_set_dma(dev, DMA_DIR_RX);
2548 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
83331040
TM		 2549
2550 /* enable device interrupts */
2551 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2552 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2553 UDC_DEVINT_SI | UDC_DEVINT_SC);
f646cf94
TO		 2554}
2555
2556/**
2557 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2558 * interrupt
2559 * @dev: Reference to driver structure
2560 */
2561static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2562{
2563 u32 reg, dev_stat = 0;
2564 int i, ret;
2565
2566 dev_stat = pch_udc_read_device_status(dev);
2567 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2568 UDC_DEVSTS_INTF_SHIFT;
2569 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2570 UDC_DEVSTS_ALT_SHIFT;
2571 dev->set_cfg_not_acked = 1;
2572 /* Construct the usb request for gadget driver and inform it */
2573 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2574 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2575 dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2576 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2577 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2578 /* programm the Endpoint Cfg registers */
2579 /* Only one end point cfg register */
2580 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2581 reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2582 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2583 reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2584 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2585 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2586 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2587 /* clear stall bits */
2588 pch_udc_ep_clear_stall(&(dev->ep[i]));
2589 dev->ep[i].halted = 0;
2590 }
2591 dev->stall = 0;
2592 spin_unlock(&dev->lock);
2593 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2594 spin_lock(&dev->lock);
2595}
2596
2597/**
2598 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2599 * interrupt
2600 * @dev: Reference to driver structure
2601 */
2602static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2603{
2604 int i, ret;
2605 u32 reg, dev_stat = 0;
2606
2607 dev_stat = pch_udc_read_device_status(dev);
2608 dev->set_cfg_not_acked = 1;
2609 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2610 UDC_DEVSTS_CFG_SHIFT;
2611 /* make usb request for gadget driver */
2612 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2613 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2614 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2615 /* program the NE registers */
2616 /* Only one end point cfg register */
2617 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2618 reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2619 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2620 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2621 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2622 /* clear stall bits */
2623 pch_udc_ep_clear_stall(&(dev->ep[i]));
2624 dev->ep[i].halted = 0;
2625 }
2626 dev->stall = 0;
2627
2628 /* call gadget zero with setup data received */
2629 spin_unlock(&dev->lock);
2630 ret = dev->driver->setup(&dev->gadget, &dev->setup_data);
2631 spin_lock(&dev->lock);
2632}
2633
2634/**
2635 * pch_udc_dev_isr() - This function services device interrupts
2636 * by invoking appropriate routines.
2637 * @dev: Reference to the device structure
2638 * @dev_intr: The Device interrupt status.
2639 */
2640static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2641{
dd63180b
TM		 2642 int vbus;
2643
f646cf94 2644 /* USB Reset Interrupt */
9645f7d3 2645 if (dev_intr & UDC_DEVINT_UR) {
f646cf94 2646 pch_udc_svc_ur_interrupt(dev);
9645f7d3
TM		 2647 dev_dbg(&dev->pdev->dev, "USB_RESET\n");
2648 }
f646cf94 2649 /* Enumeration Done Interrupt */
9645f7d3 2650 if (dev_intr & UDC_DEVINT_ENUM) {
f646cf94 2651 pch_udc_svc_enum_interrupt(dev);
9645f7d3
TM		 2652 dev_dbg(&dev->pdev->dev, "USB_ENUM\n");
2653 }
f646cf94
TO		 2654 /* Set Interface Interrupt */
2655 if (dev_intr & UDC_DEVINT_SI)
2656 pch_udc_svc_intf_interrupt(dev);
2657 /* Set Config Interrupt */
2658 if (dev_intr & UDC_DEVINT_SC)
2659 pch_udc_svc_cfg_interrupt(dev);
2660 /* USB Suspend interrupt */
84566abb
TM		 2661 if (dev_intr & UDC_DEVINT_US) {
2662 if (dev->driver
2663 && dev->driver->suspend) {
2664 spin_unlock(&dev->lock);
2665 dev->driver->suspend(&dev->gadget);
2666 spin_lock(&dev->lock);
2667 }
1c575d2d 2668
dd63180b
TM		 2669 vbus = pch_vbus_gpio_get_value(dev);
2670 if ((dev->vbus_session == 0)
2671 && (vbus != 1)) {
1c575d2d
TM		 2672 if (dev->driver && dev->driver->disconnect) {
2673 spin_unlock(&dev->lock);
2674 dev->driver->disconnect(&dev->gadget);
2675 spin_lock(&dev->lock);
2676 }
2677 pch_udc_reconnect(dev);
dd63180b
TM		 2678 } else if ((dev->vbus_session == 0)
2679 && (vbus == 1))
2680 schedule_work(&dev->vbus_gpio.irq_work_fall);
2681
f646cf94 2682 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
84566abb 2683 }
f646cf94
TO		 2684 /* Clear the SOF interrupt, if enabled */
2685 if (dev_intr & UDC_DEVINT_SOF)
2686 dev_dbg(&dev->pdev->dev, "SOF\n");
2687 /* ES interrupt, IDLE > 3ms on the USB */
2688 if (dev_intr & UDC_DEVINT_ES)
2689 dev_dbg(&dev->pdev->dev, "ES\n");
2690 /* RWKP interrupt */
2691 if (dev_intr & UDC_DEVINT_RWKP)
2692 dev_dbg(&dev->pdev->dev, "RWKP\n");
2693}
2694
2695/**
2696 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2697 * @irq: Interrupt request number
2698 * @dev: Reference to the device structure
2699 */
2700static irqreturn_t pch_udc_isr(int irq, void *pdev)
2701{
2702 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2703 u32 dev_intr, ep_intr;
2704 int i;
2705
2706 dev_intr = pch_udc_read_device_interrupts(dev);
2707 ep_intr = pch_udc_read_ep_interrupts(dev);
2708
1c575d2d
TM		 2709 /* For a hot plug, this find that the controller is hung up. */
2710 if (dev_intr == ep_intr)
2711 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2712 dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2713 /* The controller is reset */
2714 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2715 return IRQ_HANDLED;
2716 }
f646cf94
TO		 2717 if (dev_intr)
2718 /* Clear device interrupts */
2719 pch_udc_write_device_interrupts(dev, dev_intr);
2720 if (ep_intr)
2721 /* Clear ep interrupts */
2722 pch_udc_write_ep_interrupts(dev, ep_intr);
2723 if (!dev_intr && !ep_intr)
2724 return IRQ_NONE;
2725 spin_lock(&dev->lock);
2726 if (dev_intr)
2727 pch_udc_dev_isr(dev, dev_intr);
2728 if (ep_intr) {
2729 pch_udc_read_all_epstatus(dev, ep_intr);
2730 /* Process Control In interrupts, if present */
2731 if (ep_intr & UDC_EPINT_IN_EP0) {
2732 pch_udc_svc_control_in(dev);
2733 pch_udc_postsvc_epinters(dev, 0);
2734 }
2735 /* Process Control Out interrupts, if present */
2736 if (ep_intr & UDC_EPINT_OUT_EP0)
2737 pch_udc_svc_control_out(dev);
2738 /* Process data in end point interrupts */
2739 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2740 if (ep_intr & (1 << i)) {
2741 pch_udc_svc_data_in(dev, i);
2742 pch_udc_postsvc_epinters(dev, i);
2743 }
2744 }
2745 /* Process data out end point interrupts */
2746 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2747 PCH_UDC_USED_EP_NUM); i++)
2748 if (ep_intr & (1 << i))
2749 pch_udc_svc_data_out(dev, i -
2750 UDC_EPINT_OUT_SHIFT);
2751 }
2752 spin_unlock(&dev->lock);
2753 return IRQ_HANDLED;
2754}
2755
2756/**
2757 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2758 * @dev: Reference to the device structure
2759 */
2760static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2761{
2762 /* enable ep0 interrupts */
2763 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2764 UDC_EPINT_OUT_EP0);
2765 /* enable device interrupts */
2766 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2767 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2768 UDC_DEVINT_SI | UDC_DEVINT_SC);
2769}
2770
2771/**
2772 * gadget_release() - Free the gadget driver private data
2773 * @pdev reference to struct pci_dev
2774 */
2775static void gadget_release(struct device *pdev)
2776{
2777 struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2778
2779 kfree(dev);
2780}
2781
2782/**
2783 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2784 * @dev: Reference to the driver structure
2785 */
2786static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2787{
2788 const char *const ep_string[] = {
2789 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2790 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2791 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2792 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2793 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2794 "ep15in", "ep15out",
2795 };
2796 int i;
2797
2798 dev->gadget.speed = USB_SPEED_UNKNOWN;
2799 INIT_LIST_HEAD(&dev->gadget.ep_list);
2800
2801 /* Initialize the endpoints structures */
2802 memset(dev->ep, 0, sizeof dev->ep);
2803 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2804 struct pch_udc_ep *ep = &dev->ep[i];
2805 ep->dev = dev;
2806 ep->halted = 1;
2807 ep->num = i / 2;
2808 ep->in = ~i & 1;
2809 ep->ep.name = ep_string[i];
2810 ep->ep.ops = &pch_udc_ep_ops;
2811 if (ep->in)
2812 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2813 else
2814 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2815 UDC_EP_REG_SHIFT;
2816 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2817 ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE;
2818 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2819 INIT_LIST_HEAD(&ep->queue);
2820 }
2821 dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
2822 dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
2823
f646cf94
TO		 2824 /* remove ep0 in and out from the list. They have own pointer */
2825 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2826 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2827
2828 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2829 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2830}
2831
2832/**
2833 * pch_udc_pcd_init() - This API initializes the driver structure
2834 * @dev: Reference to the driver structure
2835 *
2836 * Return codes:
2837 * 0: Success
2838 */
2839static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2840{
2841 pch_udc_init(dev);
2842 pch_udc_pcd_reinit(dev);
dd63180b 2843 pch_vbus_gpio_init(dev, vbus_gpio_port);
f646cf94
TO		 2844 return 0;
2845}
2846
2847/**
2848 * init_dma_pools() - create dma pools during initialization
2849 * @pdev: reference to struct pci_dev
2850 */
2851static int init_dma_pools(struct pch_udc_dev *dev)
2852{
2853 struct pch_udc_stp_dma_desc *td_stp;
2854 struct pch_udc_data_dma_desc *td_data;
2855
2856 /* DMA setup */
2857 dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2858 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2859 if (!dev->data_requests) {
2860 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2861 __func__);
2862 return -ENOMEM;
2863 }
2864
2865 /* dma desc for setup data */
2866 dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2867 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2868 if (!dev->stp_requests) {
2869 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2870 __func__);
2871 return -ENOMEM;
2872 }
2873 /* setup */
2874 td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2875 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2876 if (!td_stp) {
2877 dev_err(&dev->pdev->dev,
2878 "%s: can't allocate setup dma descriptor\n", __func__);
2879 return -ENOMEM;
2880 }
2881 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2882
2883 /* data: 0 packets !? */
2884 td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2885 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2886 if (!td_data) {
2887 dev_err(&dev->pdev->dev,
2888 "%s: can't allocate data dma descriptor\n", __func__);
2889 return -ENOMEM;
2890 }
2891 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2892 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2893 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2894 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2895 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
abab0c67
TO		 2896
2897 dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
2898 if (!dev->ep0out_buf)
2899 return -ENOMEM;
2900 dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
2901 UDC_EP0OUT_BUFF_SIZE * 4,
2902 DMA_FROM_DEVICE);
f646cf94
TO		 2903 return 0;
2904}
2905
0f91349b 2906static int pch_udc_start(struct usb_gadget_driver *driver,
49e20834 2907 int (*bind)(struct usb_gadget *))
f646cf94
TO		 2908{
2909 struct pch_udc_dev *dev = pch_udc;
2910 int retval;
2911
7177aed4 2912 if (!driver || (driver->max_speed == USB_SPEED_UNKNOWN) || !bind ||
f646cf94
TO		 2913 !driver->setup || !driver->unbind || !driver->disconnect) {
2914 dev_err(&dev->pdev->dev,
2915 "%s: invalid driver parameter\n", __func__);
2916 return -EINVAL;
2917 }
2918
2919 if (!dev)
2920 return -ENODEV;
2921
2922 if (dev->driver) {
2923 dev_err(&dev->pdev->dev, "%s: already bound\n", __func__);
2924 return -EBUSY;
2925 }
2926 driver->driver.bus = NULL;
2927 dev->driver = driver;
2928 dev->gadget.dev.driver = &driver->driver;
2929
2930 /* Invoke the bind routine of the gadget driver */
49e20834 2931 retval = bind(&dev->gadget);
f646cf94
TO		 2932
2933 if (retval) {
2934 dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n",
2935 __func__, driver->driver.name, retval);
2936 dev->driver = NULL;
2937 dev->gadget.dev.driver = NULL;
2938 return retval;
2939 }
2940 /* get ready for ep0 traffic */
2941 pch_udc_setup_ep0(dev);
2942
2943 /* clear SD */
2944 pch_udc_clear_disconnect(dev);
2945
2946 dev->connected = 1;
2947 return 0;
2948}
f646cf94 2949
0f91349b 2950static int pch_udc_stop(struct usb_gadget_driver *driver)
f646cf94
TO		 2951{
2952 struct pch_udc_dev *dev = pch_udc;
2953
2954 if (!dev)
2955 return -ENODEV;
2956
2957 if (!driver || (driver != dev->driver)) {
2958 dev_err(&dev->pdev->dev,
2959 "%s: invalid driver parameter\n", __func__);
2960 return -EINVAL;
2961 }
2962
2963 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2964
15680cdf
TO		 2965 /* Assures that there are no pending requests with this driver */
2966 driver->disconnect(&dev->gadget);
f646cf94
TO		 2967 driver->unbind(&dev->gadget);
2968 dev->gadget.dev.driver = NULL;
2969 dev->driver = NULL;
2970 dev->connected = 0;
2971
2972 /* set SD */
2973 pch_udc_set_disconnect(dev);
2974 return 0;
2975}
f646cf94
TO		 2976
2977static void pch_udc_shutdown(struct pci_dev *pdev)
2978{
2979 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2980
2981 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
2982 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2983
2984 /* disable the pullup so the host will think we're gone */
2985 pch_udc_set_disconnect(dev);
2986}
2987
2988static void pch_udc_remove(struct pci_dev *pdev)
2989{
2990 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
2991
0f91349b
SAS		 2992 usb_del_gadget_udc(&dev->gadget);
2993
f646cf94
TO		 2994 /* gadget driver must not be registered */
2995 if (dev->driver)
2996 dev_err(&pdev->dev,
2997 "%s: gadget driver still bound!!!\n", __func__);
2998 /* dma pool cleanup */
2999 if (dev->data_requests)
3000 pci_pool_destroy(dev->data_requests);
3001
3002 if (dev->stp_requests) {
3003 /* cleanup DMA desc's for ep0in */
3004 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
3005 pci_pool_free(dev->stp_requests,
3006 dev->ep[UDC_EP0OUT_IDX].td_stp,
3007 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
3008 }
3009 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
3010 pci_pool_free(dev->stp_requests,
3011 dev->ep[UDC_EP0OUT_IDX].td_data,
3012 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
3013 }
3014 pci_pool_destroy(dev->stp_requests);
3015 }
3016
abab0c67
TO		 3017 if (dev->dma_addr)
3018 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
3019 UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
3020 kfree(dev->ep0out_buf);
3021
dd63180b
TM		 3022 pch_vbus_gpio_free(dev);
3023
f646cf94
TO		 3024 pch_udc_exit(dev);
3025
3026 if (dev->irq_registered)
3027 free_irq(pdev->irq, dev);
3028 if (dev->base_addr)
3029 iounmap(dev->base_addr);
3030 if (dev->mem_region)
3031 release_mem_region(dev->phys_addr,
3032 pci_resource_len(pdev, PCH_UDC_PCI_BAR));
3033 if (dev->active)
3034 pci_disable_device(pdev);
3035 if (dev->registered)
3036 device_unregister(&dev->gadget.dev);
3037 kfree(dev);
3038 pci_set_drvdata(pdev, NULL);
3039}
3040
3041#ifdef CONFIG_PM
3042static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3043{
3044 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3045
3046 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3047 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3048
3049 pci_disable_device(pdev);
3050 pci_enable_wake(pdev, PCI_D3hot, 0);
3051
3052 if (pci_save_state(pdev)) {
3053 dev_err(&pdev->dev,
3054 "%s: could not save PCI config state\n", __func__);
3055 return -ENOMEM;
3056 }
3057 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3058 return 0;
3059}
3060
3061static int pch_udc_resume(struct pci_dev *pdev)
3062{
3063 int ret;
3064
3065 pci_set_power_state(pdev, PCI_D0);
abab0c67 3066 pci_restore_state(pdev);
f646cf94
TO		 3067 ret = pci_enable_device(pdev);
3068 if (ret) {
3069 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
3070 return ret;
3071 }
3072 pci_enable_wake(pdev, PCI_D3hot, 0);
3073 return 0;
3074}
3075#else
3076#define pch_udc_suspend NULL
3077#define pch_udc_resume NULL
3078#endif /* CONFIG_PM */
3079
3080static int pch_udc_probe(struct pci_dev *pdev,
3081 const struct pci_device_id *id)
3082{
3083 unsigned long resource;
3084 unsigned long len;
3085 int retval;
3086 struct pch_udc_dev *dev;
3087
3088 /* one udc only */
3089 if (pch_udc) {
3090 pr_err("%s: already probed\n", __func__);
3091 return -EBUSY;
3092 }
3093 /* init */
3094 dev = kzalloc(sizeof *dev, GFP_KERNEL);
3095 if (!dev) {
3096 pr_err("%s: no memory for device structure\n", __func__);
3097 return -ENOMEM;
3098 }
3099 /* pci setup */
3100 if (pci_enable_device(pdev) < 0) {
3101 kfree(dev);
3102 pr_err("%s: pci_enable_device failed\n", __func__);
3103 return -ENODEV;
3104 }
3105 dev->active = 1;
3106 pci_set_drvdata(pdev, dev);
3107
3108 /* PCI resource allocation */
3109 resource = pci_resource_start(pdev, 1);
3110 len = pci_resource_len(pdev, 1);
3111
3112 if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
3113 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
3114 retval = -EBUSY;
3115 goto finished;
3116 }
3117 dev->phys_addr = resource;
3118 dev->mem_region = 1;
3119
3120 dev->base_addr = ioremap_nocache(resource, len);
3121 if (!dev->base_addr) {
3122 pr_err("%s: device memory cannot be mapped\n", __func__);
3123 retval = -ENOMEM;
3124 goto finished;
3125 }
3126 if (!pdev->irq) {
3127 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
3128 retval = -ENODEV;
3129 goto finished;
3130 }
3131 pch_udc = dev;
3132 /* initialize the hardware */
c802672c
TM		 3133 if (pch_udc_pcd_init(dev)) {
3134 retval = -ENODEV;
f646cf94 3135 goto finished;
c802672c 3136 }
f646cf94
TO		 3137 if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
3138 dev)) {
3139 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
3140 pdev->irq);
3141 retval = -ENODEV;
3142 goto finished;
3143 }
3144 dev->irq = pdev->irq;
3145 dev->irq_registered = 1;
3146
3147 pci_set_master(pdev);
3148 pci_try_set_mwi(pdev);
3149
3150 /* device struct setup */
3151 spin_lock_init(&dev->lock);
3152 dev->pdev = pdev;
3153 dev->gadget.ops = &pch_udc_ops;
3154
3155 retval = init_dma_pools(dev);
3156 if (retval)
3157 goto finished;
3158
3159 dev_set_name(&dev->gadget.dev, "gadget");
3160 dev->gadget.dev.parent = &pdev->dev;
3161 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3162 dev->gadget.dev.release = gadget_release;
3163 dev->gadget.name = KBUILD_MODNAME;
d327ab5b 3164 dev->gadget.max_speed = USB_SPEED_HIGH;
f646cf94
TO		 3165
3166 retval = device_register(&dev->gadget.dev);
3167 if (retval)
3168 goto finished;
3169 dev->registered = 1;
3170
3171 /* Put the device in disconnected state till a driver is bound */
3172 pch_udc_set_disconnect(dev);
0f91349b
SAS		 3173 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3174 if (retval)
3175 goto finished;
f646cf94
TO		 3176 return 0;
3177
3178finished:
3179 pch_udc_remove(pdev);
3180 return retval;
3181}
3182
49e20834 3183static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = {
f646cf94
TO		 3184 {
3185 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3186 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3187 .class_mask = 0xffffffff,
3188 },
06f1b971
TM		 3189 {
3190 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3191 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3192 .class_mask = 0xffffffff,
3193 },
731ad81e
TM		 3194 {
3195 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3196 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3197 .class_mask = 0xffffffff,
3198 },
f646cf94
TO		 3199 { 0 },
3200};
3201
3202MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3203
3204
3205static struct pci_driver pch_udc_driver = {
3206 .name = KBUILD_MODNAME,
3207 .id_table = pch_udc_pcidev_id,
3208 .probe = pch_udc_probe,
3209 .remove = pch_udc_remove,
3210 .suspend = pch_udc_suspend,
3211 .resume = pch_udc_resume,
3212 .shutdown = pch_udc_shutdown,
3213};
3214
3215static int __init pch_udc_pci_init(void)
3216{
3217 return pci_register_driver(&pch_udc_driver);
3218}
3219module_init(pch_udc_pci_init);
3220
3221static void __exit pch_udc_pci_exit(void)
3222{
3223 pci_unregister_driver(&pch_udc_driver);
3224}
3225module_exit(pch_udc_pci_exit);
3226
3227MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
09b658dc 3228MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
f646cf94 3229MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.223081 seconds and 5 git commands to generate.