Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/usb/gadget/pxa2xx_udc.c | |
91987693 | 3 | * Intel PXA25x and IXP4xx on-chip full speed USB device controllers |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) | |
6 | * Copyright (C) 2003 Robert Schwebel, Pengutronix | |
7 | * Copyright (C) 2003 Benedikt Spranger, Pengutronix | |
8 | * Copyright (C) 2003 David Brownell | |
9 | * Copyright (C) 2003 Joshua Wise | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
24 | * | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | // #define VERBOSE DBG_VERBOSE |
28 | ||
9068a4c6 | 29 | #include <linux/device.h> |
1da177e4 LT |
30 | #include <linux/module.h> |
31 | #include <linux/kernel.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/types.h> | |
1da177e4 LT |
34 | #include <linux/errno.h> |
35 | #include <linux/delay.h> | |
1da177e4 LT |
36 | #include <linux/slab.h> |
37 | #include <linux/init.h> | |
38 | #include <linux/timer.h> | |
39 | #include <linux/list.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/proc_fs.h> | |
42 | #include <linux/mm.h> | |
d052d1be | 43 | #include <linux/platform_device.h> |
1da177e4 | 44 | #include <linux/dma-mapping.h> |
c7a3bd17 | 45 | #include <linux/irq.h> |
1da177e4 LT |
46 | |
47 | #include <asm/byteorder.h> | |
48 | #include <asm/dma.h> | |
9068a4c6 | 49 | #include <asm/gpio.h> |
1da177e4 | 50 | #include <asm/io.h> |
1da177e4 LT |
51 | #include <asm/system.h> |
52 | #include <asm/mach-types.h> | |
53 | #include <asm/unaligned.h> | |
54 | #include <asm/hardware.h> | |
1da177e4 | 55 | |
5f848137 | 56 | #include <linux/usb/ch9.h> |
9454a57a | 57 | #include <linux/usb/gadget.h> |
1da177e4 | 58 | |
9068a4c6 | 59 | #include <asm/mach/udc_pxa2xx.h> |
1da177e4 LT |
60 | |
61 | ||
62 | /* | |
91987693 | 63 | * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x |
1da177e4 LT |
64 | * series processors. The UDC for the IXP 4xx series is very similar. |
65 | * There are fifteen endpoints, in addition to ep0. | |
66 | * | |
67 | * Such controller drivers work with a gadget driver. The gadget driver | |
68 | * returns descriptors, implements configuration and data protocols used | |
69 | * by the host to interact with this device, and allocates endpoints to | |
70 | * the different protocol interfaces. The controller driver virtualizes | |
71 | * usb hardware so that the gadget drivers will be more portable. | |
34ebcd28 | 72 | * |
1da177e4 LT |
73 | * This UDC hardware wants to implement a bit too much USB protocol, so |
74 | * it constrains the sorts of USB configuration change events that work. | |
75 | * The errata for these chips are misleading; some "fixed" bugs from | |
76 | * pxa250 a0/a1 b0/b1/b2 sure act like they're still there. | |
ad8c623f DB |
77 | * |
78 | * Note that the UDC hardware supports DMA (except on IXP) but that's | |
79 | * not used here. IN-DMA (to host) is simple enough, when the data is | |
80 | * suitably aligned (16 bytes) ... the network stack doesn't do that, | |
81 | * other software can. OUT-DMA is buggy in most chip versions, as well | |
82 | * as poorly designed (data toggle not automatic). So this driver won't | |
83 | * bother using DMA. (Mostly-working IN-DMA support was available in | |
84 | * kernels before 2.6.23, but was never enabled or well tested.) | |
1da177e4 LT |
85 | */ |
86 | ||
ad8c623f | 87 | #define DRIVER_VERSION "30-June-2007" |
91987693 | 88 | #define DRIVER_DESC "PXA 25x USB Device Controller driver" |
1da177e4 LT |
89 | |
90 | ||
91 | static const char driver_name [] = "pxa2xx_udc"; | |
92 | ||
93 | static const char ep0name [] = "ep0"; | |
94 | ||
95 | ||
1da177e4 | 96 | #ifdef CONFIG_ARCH_IXP4XX |
1da177e4 LT |
97 | |
98 | /* cpu-specific register addresses are compiled in to this code */ | |
99 | #ifdef CONFIG_ARCH_PXA | |
100 | #error "Can't configure both IXP and PXA" | |
101 | #endif | |
102 | ||
103 | #endif | |
104 | ||
105 | #include "pxa2xx_udc.h" | |
106 | ||
107 | ||
1da177e4 LT |
108 | #ifdef CONFIG_USB_PXA2XX_SMALL |
109 | #define SIZE_STR " (small)" | |
110 | #else | |
111 | #define SIZE_STR "" | |
112 | #endif | |
113 | ||
1da177e4 | 114 | /* --------------------------------------------------------------------------- |
34ebcd28 | 115 | * endpoint related parts of the api to the usb controller hardware, |
1da177e4 LT |
116 | * used by gadget driver; and the inner talker-to-hardware core. |
117 | * --------------------------------------------------------------------------- | |
118 | */ | |
119 | ||
120 | static void pxa2xx_ep_fifo_flush (struct usb_ep *ep); | |
121 | static void nuke (struct pxa2xx_ep *, int status); | |
122 | ||
b2bbb20b DB |
123 | /* one GPIO should be used to detect VBUS from the host */ |
124 | static int is_vbus_present(void) | |
125 | { | |
126 | struct pxa2xx_udc_mach_info *mach = the_controller->mach; | |
127 | ||
128 | if (mach->gpio_vbus) | |
9068a4c6 | 129 | return gpio_get_value(mach->gpio_vbus); |
b2bbb20b DB |
130 | if (mach->udc_is_connected) |
131 | return mach->udc_is_connected(); | |
132 | return 1; | |
133 | } | |
134 | ||
135 | /* one GPIO should control a D+ pullup, so host sees this device (or not) */ | |
136 | static void pullup_off(void) | |
137 | { | |
138 | struct pxa2xx_udc_mach_info *mach = the_controller->mach; | |
139 | ||
140 | if (mach->gpio_pullup) | |
9068a4c6 | 141 | gpio_set_value(mach->gpio_pullup, 0); |
b2bbb20b DB |
142 | else if (mach->udc_command) |
143 | mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); | |
144 | } | |
145 | ||
146 | static void pullup_on(void) | |
147 | { | |
148 | struct pxa2xx_udc_mach_info *mach = the_controller->mach; | |
149 | ||
150 | if (mach->gpio_pullup) | |
9068a4c6 | 151 | gpio_set_value(mach->gpio_pullup, 1); |
b2bbb20b DB |
152 | else if (mach->udc_command) |
153 | mach->udc_command(PXA2XX_UDC_CMD_CONNECT); | |
154 | } | |
155 | ||
1da177e4 LT |
156 | static void pio_irq_enable(int bEndpointAddress) |
157 | { | |
158 | bEndpointAddress &= 0xf; | |
159 | if (bEndpointAddress < 8) | |
160 | UICR0 &= ~(1 << bEndpointAddress); | |
161 | else { | |
162 | bEndpointAddress -= 8; | |
163 | UICR1 &= ~(1 << bEndpointAddress); | |
164 | } | |
165 | } | |
166 | ||
167 | static void pio_irq_disable(int bEndpointAddress) | |
168 | { | |
169 | bEndpointAddress &= 0xf; | |
170 | if (bEndpointAddress < 8) | |
171 | UICR0 |= 1 << bEndpointAddress; | |
172 | else { | |
173 | bEndpointAddress -= 8; | |
174 | UICR1 |= 1 << bEndpointAddress; | |
175 | } | |
176 | } | |
177 | ||
178 | /* The UDCCR reg contains mask and interrupt status bits, | |
179 | * so using '|=' isn't safe as it may ack an interrupt. | |
180 | */ | |
181 | #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE) | |
182 | ||
183 | static inline void udc_set_mask_UDCCR(int mask) | |
184 | { | |
185 | UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS); | |
186 | } | |
187 | ||
188 | static inline void udc_clear_mask_UDCCR(int mask) | |
189 | { | |
190 | UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS); | |
191 | } | |
192 | ||
193 | static inline void udc_ack_int_UDCCR(int mask) | |
194 | { | |
195 | /* udccr contains the bits we dont want to change */ | |
196 | __u32 udccr = UDCCR & UDCCR_MASK_BITS; | |
197 | ||
198 | UDCCR = udccr | (mask & ~UDCCR_MASK_BITS); | |
199 | } | |
200 | ||
201 | /* | |
202 | * endpoint enable/disable | |
203 | * | |
204 | * we need to verify the descriptors used to enable endpoints. since pxa2xx | |
205 | * endpoint configurations are fixed, and are pretty much always enabled, | |
206 | * there's not a lot to manage here. | |
207 | * | |
208 | * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints, | |
209 | * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except | |
210 | * for a single interface (with only the default altsetting) and for gadget | |
211 | * drivers that don't halt endpoints (not reset by set_interface). that also | |
212 | * means that if you use ISO, you must violate the USB spec rule that all | |
213 | * iso endpoints must be in non-default altsettings. | |
214 | */ | |
215 | static int pxa2xx_ep_enable (struct usb_ep *_ep, | |
216 | const struct usb_endpoint_descriptor *desc) | |
217 | { | |
218 | struct pxa2xx_ep *ep; | |
219 | struct pxa2xx_udc *dev; | |
220 | ||
221 | ep = container_of (_ep, struct pxa2xx_ep, ep); | |
222 | if (!_ep || !desc || ep->desc || _ep->name == ep0name | |
223 | || desc->bDescriptorType != USB_DT_ENDPOINT | |
224 | || ep->bEndpointAddress != desc->bEndpointAddress | |
225 | || ep->fifo_size < le16_to_cpu | |
226 | (desc->wMaxPacketSize)) { | |
227 | DMSG("%s, bad ep or descriptor\n", __FUNCTION__); | |
228 | return -EINVAL; | |
229 | } | |
230 | ||
231 | /* xfer types must match, except that interrupt ~= bulk */ | |
232 | if (ep->bmAttributes != desc->bmAttributes | |
233 | && ep->bmAttributes != USB_ENDPOINT_XFER_BULK | |
234 | && desc->bmAttributes != USB_ENDPOINT_XFER_INT) { | |
235 | DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name); | |
236 | return -EINVAL; | |
237 | } | |
238 | ||
239 | /* hardware _could_ do smaller, but driver doesn't */ | |
240 | if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK | |
241 | && le16_to_cpu (desc->wMaxPacketSize) | |
242 | != BULK_FIFO_SIZE) | |
243 | || !desc->wMaxPacketSize) { | |
244 | DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name); | |
245 | return -ERANGE; | |
246 | } | |
247 | ||
248 | dev = ep->dev; | |
249 | if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) { | |
250 | DMSG("%s, bogus device state\n", __FUNCTION__); | |
251 | return -ESHUTDOWN; | |
252 | } | |
253 | ||
254 | ep->desc = desc; | |
1da177e4 | 255 | ep->stopped = 0; |
ad8c623f | 256 | ep->pio_irqs = 0; |
1da177e4 LT |
257 | ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize); |
258 | ||
259 | /* flush fifo (mostly for OUT buffers) */ | |
260 | pxa2xx_ep_fifo_flush (_ep); | |
261 | ||
262 | /* ... reset halt state too, if we could ... */ | |
263 | ||
1da177e4 LT |
264 | DBG(DBG_VERBOSE, "enabled %s\n", _ep->name); |
265 | return 0; | |
266 | } | |
267 | ||
268 | static int pxa2xx_ep_disable (struct usb_ep *_ep) | |
269 | { | |
270 | struct pxa2xx_ep *ep; | |
91987693 | 271 | unsigned long flags; |
1da177e4 LT |
272 | |
273 | ep = container_of (_ep, struct pxa2xx_ep, ep); | |
274 | if (!_ep || !ep->desc) { | |
275 | DMSG("%s, %s not enabled\n", __FUNCTION__, | |
276 | _ep ? ep->ep.name : NULL); | |
277 | return -EINVAL; | |
278 | } | |
91987693 DB |
279 | local_irq_save(flags); |
280 | ||
1da177e4 LT |
281 | nuke (ep, -ESHUTDOWN); |
282 | ||
1da177e4 LT |
283 | /* flush fifo (mostly for IN buffers) */ |
284 | pxa2xx_ep_fifo_flush (_ep); | |
285 | ||
286 | ep->desc = NULL; | |
287 | ep->stopped = 1; | |
288 | ||
91987693 | 289 | local_irq_restore(flags); |
1da177e4 LT |
290 | DBG(DBG_VERBOSE, "%s disabled\n", _ep->name); |
291 | return 0; | |
292 | } | |
293 | ||
294 | /*-------------------------------------------------------------------------*/ | |
295 | ||
296 | /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers | |
297 | * must still pass correctly initialized endpoints, since other controller | |
298 | * drivers may care about how it's currently set up (dma issues etc). | |
299 | */ | |
300 | ||
301 | /* | |
34ebcd28 | 302 | * pxa2xx_ep_alloc_request - allocate a request data structure |
1da177e4 LT |
303 | */ |
304 | static struct usb_request * | |
55016f10 | 305 | pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags) |
1da177e4 LT |
306 | { |
307 | struct pxa2xx_request *req; | |
308 | ||
7039f422 | 309 | req = kzalloc(sizeof(*req), gfp_flags); |
1da177e4 LT |
310 | if (!req) |
311 | return NULL; | |
312 | ||
1da177e4 LT |
313 | INIT_LIST_HEAD (&req->queue); |
314 | return &req->req; | |
315 | } | |
316 | ||
317 | ||
318 | /* | |
34ebcd28 | 319 | * pxa2xx_ep_free_request - deallocate a request data structure |
1da177e4 LT |
320 | */ |
321 | static void | |
322 | pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req) | |
323 | { | |
324 | struct pxa2xx_request *req; | |
325 | ||
326 | req = container_of (_req, struct pxa2xx_request, req); | |
327 | WARN_ON (!list_empty (&req->queue)); | |
328 | kfree(req); | |
329 | } | |
330 | ||
1da177e4 LT |
331 | /*-------------------------------------------------------------------------*/ |
332 | ||
333 | /* | |
334 | * done - retire a request; caller blocked irqs | |
335 | */ | |
336 | static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status) | |
337 | { | |
338 | unsigned stopped = ep->stopped; | |
339 | ||
340 | list_del_init(&req->queue); | |
341 | ||
342 | if (likely (req->req.status == -EINPROGRESS)) | |
343 | req->req.status = status; | |
344 | else | |
345 | status = req->req.status; | |
346 | ||
347 | if (status && status != -ESHUTDOWN) | |
348 | DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n", | |
349 | ep->ep.name, &req->req, status, | |
350 | req->req.actual, req->req.length); | |
351 | ||
352 | /* don't modify queue heads during completion callback */ | |
353 | ep->stopped = 1; | |
354 | req->req.complete(&ep->ep, &req->req); | |
355 | ep->stopped = stopped; | |
356 | } | |
357 | ||
358 | ||
359 | static inline void ep0_idle (struct pxa2xx_udc *dev) | |
360 | { | |
361 | dev->ep0state = EP0_IDLE; | |
362 | } | |
363 | ||
364 | static int | |
63a4b52c | 365 | write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max) |
1da177e4 LT |
366 | { |
367 | u8 *buf; | |
368 | unsigned length, count; | |
369 | ||
370 | buf = req->req.buf + req->req.actual; | |
371 | prefetch(buf); | |
372 | ||
373 | /* how big will this packet be? */ | |
374 | length = min(req->req.length - req->req.actual, max); | |
375 | req->req.actual += length; | |
376 | ||
377 | count = length; | |
378 | while (likely(count--)) | |
379 | *uddr = *buf++; | |
380 | ||
381 | return length; | |
382 | } | |
383 | ||
384 | /* | |
385 | * write to an IN endpoint fifo, as many packets as possible. | |
386 | * irqs will use this to write the rest later. | |
387 | * caller guarantees at least one packet buffer is ready (or a zlp). | |
388 | */ | |
389 | static int | |
390 | write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | |
391 | { | |
392 | unsigned max; | |
393 | ||
394 | max = le16_to_cpu(ep->desc->wMaxPacketSize); | |
395 | do { | |
396 | unsigned count; | |
397 | int is_last, is_short; | |
398 | ||
399 | count = write_packet(ep->reg_uddr, req, max); | |
400 | ||
401 | /* last packet is usually short (or a zlp) */ | |
402 | if (unlikely (count != max)) | |
403 | is_last = is_short = 1; | |
404 | else { | |
405 | if (likely(req->req.length != req->req.actual) | |
406 | || req->req.zero) | |
407 | is_last = 0; | |
408 | else | |
409 | is_last = 1; | |
410 | /* interrupt/iso maxpacket may not fill the fifo */ | |
411 | is_short = unlikely (max < ep->fifo_size); | |
412 | } | |
413 | ||
414 | DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n", | |
415 | ep->ep.name, count, | |
416 | is_last ? "/L" : "", is_short ? "/S" : "", | |
417 | req->req.length - req->req.actual, req); | |
418 | ||
419 | /* let loose that packet. maybe try writing another one, | |
420 | * double buffering might work. TSP, TPC, and TFS | |
421 | * bit values are the same for all normal IN endpoints. | |
422 | */ | |
423 | *ep->reg_udccs = UDCCS_BI_TPC; | |
424 | if (is_short) | |
425 | *ep->reg_udccs = UDCCS_BI_TSP; | |
426 | ||
427 | /* requests complete when all IN data is in the FIFO */ | |
428 | if (is_last) { | |
429 | done (ep, req, 0); | |
ad8c623f | 430 | if (list_empty(&ep->queue)) |
1da177e4 | 431 | pio_irq_disable (ep->bEndpointAddress); |
1da177e4 LT |
432 | return 1; |
433 | } | |
434 | ||
435 | // TODO experiment: how robust can fifo mode tweaking be? | |
436 | // double buffering is off in the default fifo mode, which | |
437 | // prevents TFS from being set here. | |
438 | ||
439 | } while (*ep->reg_udccs & UDCCS_BI_TFS); | |
440 | return 0; | |
441 | } | |
442 | ||
443 | /* caller asserts req->pending (ep0 irq status nyet cleared); starts | |
444 | * ep0 data stage. these chips want very simple state transitions. | |
445 | */ | |
446 | static inline | |
447 | void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag) | |
448 | { | |
449 | UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR; | |
450 | USIR0 = USIR0_IR0; | |
451 | dev->req_pending = 0; | |
452 | DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n", | |
453 | __FUNCTION__, tag, UDCCS0, flags); | |
454 | } | |
455 | ||
456 | static int | |
457 | write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | |
458 | { | |
459 | unsigned count; | |
460 | int is_short; | |
461 | ||
462 | count = write_packet(&UDDR0, req, EP0_FIFO_SIZE); | |
463 | ep->dev->stats.write.bytes += count; | |
464 | ||
465 | /* last packet "must be" short (or a zlp) */ | |
466 | is_short = (count != EP0_FIFO_SIZE); | |
467 | ||
468 | DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count, | |
469 | req->req.length - req->req.actual, req); | |
470 | ||
471 | if (unlikely (is_short)) { | |
472 | if (ep->dev->req_pending) | |
473 | ep0start(ep->dev, UDCCS0_IPR, "short IN"); | |
474 | else | |
475 | UDCCS0 = UDCCS0_IPR; | |
476 | ||
477 | count = req->req.length; | |
478 | done (ep, req, 0); | |
479 | ep0_idle(ep->dev); | |
043ea18b | 480 | #ifndef CONFIG_ARCH_IXP4XX |
1da177e4 LT |
481 | #if 1 |
482 | /* This seems to get rid of lost status irqs in some cases: | |
483 | * host responds quickly, or next request involves config | |
484 | * change automagic, or should have been hidden, or ... | |
485 | * | |
486 | * FIXME get rid of all udelays possible... | |
487 | */ | |
488 | if (count >= EP0_FIFO_SIZE) { | |
489 | count = 100; | |
490 | do { | |
491 | if ((UDCCS0 & UDCCS0_OPR) != 0) { | |
492 | /* clear OPR, generate ack */ | |
493 | UDCCS0 = UDCCS0_OPR; | |
494 | break; | |
495 | } | |
496 | count--; | |
497 | udelay(1); | |
498 | } while (count); | |
499 | } | |
043ea18b | 500 | #endif |
1da177e4 LT |
501 | #endif |
502 | } else if (ep->dev->req_pending) | |
503 | ep0start(ep->dev, 0, "IN"); | |
504 | return is_short; | |
505 | } | |
506 | ||
507 | ||
508 | /* | |
509 | * read_fifo - unload packet(s) from the fifo we use for usb OUT | |
510 | * transfers and put them into the request. caller should have made | |
511 | * sure there's at least one packet ready. | |
512 | * | |
513 | * returns true if the request completed because of short packet or the | |
514 | * request buffer having filled (and maybe overran till end-of-packet). | |
515 | */ | |
516 | static int | |
517 | read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | |
518 | { | |
519 | for (;;) { | |
520 | u32 udccs; | |
521 | u8 *buf; | |
522 | unsigned bufferspace, count, is_short; | |
523 | ||
524 | /* make sure there's a packet in the FIFO. | |
525 | * UDCCS_{BO,IO}_RPC are all the same bit value. | |
526 | * UDCCS_{BO,IO}_RNE are all the same bit value. | |
527 | */ | |
528 | udccs = *ep->reg_udccs; | |
529 | if (unlikely ((udccs & UDCCS_BO_RPC) == 0)) | |
530 | break; | |
531 | buf = req->req.buf + req->req.actual; | |
532 | prefetchw(buf); | |
533 | bufferspace = req->req.length - req->req.actual; | |
534 | ||
535 | /* read all bytes from this packet */ | |
536 | if (likely (udccs & UDCCS_BO_RNE)) { | |
537 | count = 1 + (0x0ff & *ep->reg_ubcr); | |
538 | req->req.actual += min (count, bufferspace); | |
539 | } else /* zlp */ | |
540 | count = 0; | |
541 | is_short = (count < ep->ep.maxpacket); | |
542 | DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n", | |
543 | ep->ep.name, udccs, count, | |
544 | is_short ? "/S" : "", | |
545 | req, req->req.actual, req->req.length); | |
546 | while (likely (count-- != 0)) { | |
547 | u8 byte = (u8) *ep->reg_uddr; | |
548 | ||
549 | if (unlikely (bufferspace == 0)) { | |
550 | /* this happens when the driver's buffer | |
551 | * is smaller than what the host sent. | |
552 | * discard the extra data. | |
553 | */ | |
554 | if (req->req.status != -EOVERFLOW) | |
555 | DMSG("%s overflow %d\n", | |
556 | ep->ep.name, count); | |
557 | req->req.status = -EOVERFLOW; | |
558 | } else { | |
559 | *buf++ = byte; | |
560 | bufferspace--; | |
561 | } | |
562 | } | |
563 | *ep->reg_udccs = UDCCS_BO_RPC; | |
564 | /* RPC/RSP/RNE could now reflect the other packet buffer */ | |
565 | ||
566 | /* iso is one request per packet */ | |
567 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
568 | if (udccs & UDCCS_IO_ROF) | |
569 | req->req.status = -EHOSTUNREACH; | |
570 | /* more like "is_done" */ | |
571 | is_short = 1; | |
572 | } | |
573 | ||
574 | /* completion */ | |
575 | if (is_short || req->req.actual == req->req.length) { | |
576 | done (ep, req, 0); | |
577 | if (list_empty(&ep->queue)) | |
578 | pio_irq_disable (ep->bEndpointAddress); | |
579 | return 1; | |
580 | } | |
581 | ||
582 | /* finished that packet. the next one may be waiting... */ | |
583 | } | |
584 | return 0; | |
585 | } | |
586 | ||
587 | /* | |
588 | * special ep0 version of the above. no UBCR0 or double buffering; status | |
589 | * handshaking is magic. most device protocols don't need control-OUT. | |
590 | * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other | |
591 | * protocols do use them. | |
592 | */ | |
593 | static int | |
594 | read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | |
595 | { | |
596 | u8 *buf, byte; | |
597 | unsigned bufferspace; | |
598 | ||
599 | buf = req->req.buf + req->req.actual; | |
600 | bufferspace = req->req.length - req->req.actual; | |
601 | ||
602 | while (UDCCS0 & UDCCS0_RNE) { | |
603 | byte = (u8) UDDR0; | |
604 | ||
605 | if (unlikely (bufferspace == 0)) { | |
606 | /* this happens when the driver's buffer | |
607 | * is smaller than what the host sent. | |
608 | * discard the extra data. | |
609 | */ | |
610 | if (req->req.status != -EOVERFLOW) | |
611 | DMSG("%s overflow\n", ep->ep.name); | |
612 | req->req.status = -EOVERFLOW; | |
613 | } else { | |
614 | *buf++ = byte; | |
615 | req->req.actual++; | |
616 | bufferspace--; | |
617 | } | |
618 | } | |
619 | ||
620 | UDCCS0 = UDCCS0_OPR | UDCCS0_IPR; | |
621 | ||
622 | /* completion */ | |
623 | if (req->req.actual >= req->req.length) | |
624 | return 1; | |
625 | ||
626 | /* finished that packet. the next one may be waiting... */ | |
627 | return 0; | |
628 | } | |
629 | ||
1da177e4 LT |
630 | /*-------------------------------------------------------------------------*/ |
631 | ||
632 | static int | |
55016f10 | 633 | pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) |
1da177e4 LT |
634 | { |
635 | struct pxa2xx_request *req; | |
636 | struct pxa2xx_ep *ep; | |
637 | struct pxa2xx_udc *dev; | |
638 | unsigned long flags; | |
639 | ||
640 | req = container_of(_req, struct pxa2xx_request, req); | |
641 | if (unlikely (!_req || !_req->complete || !_req->buf | |
642 | || !list_empty(&req->queue))) { | |
643 | DMSG("%s, bad params\n", __FUNCTION__); | |
644 | return -EINVAL; | |
645 | } | |
646 | ||
647 | ep = container_of(_ep, struct pxa2xx_ep, ep); | |
648 | if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) { | |
649 | DMSG("%s, bad ep\n", __FUNCTION__); | |
650 | return -EINVAL; | |
651 | } | |
652 | ||
653 | dev = ep->dev; | |
654 | if (unlikely (!dev->driver | |
655 | || dev->gadget.speed == USB_SPEED_UNKNOWN)) { | |
656 | DMSG("%s, bogus device state\n", __FUNCTION__); | |
657 | return -ESHUTDOWN; | |
658 | } | |
659 | ||
660 | /* iso is always one packet per request, that's the only way | |
661 | * we can report per-packet status. that also helps with dma. | |
662 | */ | |
663 | if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC | |
664 | && req->req.length > le16_to_cpu | |
665 | (ep->desc->wMaxPacketSize))) | |
666 | return -EMSGSIZE; | |
667 | ||
1da177e4 | 668 | DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n", |
ad8c623f | 669 | _ep->name, _req, _req->length, _req->buf); |
1da177e4 LT |
670 | |
671 | local_irq_save(flags); | |
672 | ||
673 | _req->status = -EINPROGRESS; | |
674 | _req->actual = 0; | |
675 | ||
676 | /* kickstart this i/o queue? */ | |
677 | if (list_empty(&ep->queue) && !ep->stopped) { | |
678 | if (ep->desc == 0 /* ep0 */) { | |
679 | unsigned length = _req->length; | |
680 | ||
681 | switch (dev->ep0state) { | |
682 | case EP0_IN_DATA_PHASE: | |
683 | dev->stats.write.ops++; | |
684 | if (write_ep0_fifo(ep, req)) | |
685 | req = NULL; | |
686 | break; | |
687 | ||
688 | case EP0_OUT_DATA_PHASE: | |
689 | dev->stats.read.ops++; | |
690 | /* messy ... */ | |
691 | if (dev->req_config) { | |
692 | DBG(DBG_VERBOSE, "ep0 config ack%s\n", | |
693 | dev->has_cfr ? "" : " raced"); | |
694 | if (dev->has_cfr) | |
695 | UDCCFR = UDCCFR_AREN|UDCCFR_ACM | |
696 | |UDCCFR_MB1; | |
697 | done(ep, req, 0); | |
698 | dev->ep0state = EP0_END_XFER; | |
699 | local_irq_restore (flags); | |
700 | return 0; | |
701 | } | |
702 | if (dev->req_pending) | |
703 | ep0start(dev, UDCCS0_IPR, "OUT"); | |
704 | if (length == 0 || ((UDCCS0 & UDCCS0_RNE) != 0 | |
705 | && read_ep0_fifo(ep, req))) { | |
706 | ep0_idle(dev); | |
707 | done(ep, req, 0); | |
708 | req = NULL; | |
709 | } | |
710 | break; | |
711 | ||
712 | default: | |
713 | DMSG("ep0 i/o, odd state %d\n", dev->ep0state); | |
714 | local_irq_restore (flags); | |
715 | return -EL2HLT; | |
716 | } | |
1da177e4 | 717 | /* can the FIFO can satisfy the request immediately? */ |
91987693 DB |
718 | } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) { |
719 | if ((*ep->reg_udccs & UDCCS_BI_TFS) != 0 | |
720 | && write_fifo(ep, req)) | |
721 | req = NULL; | |
1da177e4 LT |
722 | } else if ((*ep->reg_udccs & UDCCS_BO_RFS) != 0 |
723 | && read_fifo(ep, req)) { | |
724 | req = NULL; | |
725 | } | |
726 | ||
ad8c623f | 727 | if (likely (req && ep->desc)) |
1da177e4 LT |
728 | pio_irq_enable(ep->bEndpointAddress); |
729 | } | |
730 | ||
731 | /* pio or dma irq handler advances the queue. */ | |
732 | if (likely (req != 0)) | |
733 | list_add_tail(&req->queue, &ep->queue); | |
734 | local_irq_restore(flags); | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
739 | ||
740 | /* | |
34ebcd28 | 741 | * nuke - dequeue ALL requests |
1da177e4 LT |
742 | */ |
743 | static void nuke(struct pxa2xx_ep *ep, int status) | |
744 | { | |
745 | struct pxa2xx_request *req; | |
746 | ||
747 | /* called with irqs blocked */ | |
1da177e4 LT |
748 | while (!list_empty(&ep->queue)) { |
749 | req = list_entry(ep->queue.next, | |
750 | struct pxa2xx_request, | |
751 | queue); | |
752 | done(ep, req, status); | |
753 | } | |
754 | if (ep->desc) | |
755 | pio_irq_disable (ep->bEndpointAddress); | |
756 | } | |
757 | ||
758 | ||
759 | /* dequeue JUST ONE request */ | |
760 | static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
761 | { | |
762 | struct pxa2xx_ep *ep; | |
763 | struct pxa2xx_request *req; | |
764 | unsigned long flags; | |
765 | ||
766 | ep = container_of(_ep, struct pxa2xx_ep, ep); | |
767 | if (!_ep || ep->ep.name == ep0name) | |
768 | return -EINVAL; | |
769 | ||
770 | local_irq_save(flags); | |
771 | ||
772 | /* make sure it's actually queued on this endpoint */ | |
773 | list_for_each_entry (req, &ep->queue, queue) { | |
774 | if (&req->req == _req) | |
775 | break; | |
776 | } | |
777 | if (&req->req != _req) { | |
778 | local_irq_restore(flags); | |
779 | return -EINVAL; | |
780 | } | |
781 | ||
ad8c623f | 782 | done(ep, req, -ECONNRESET); |
1da177e4 LT |
783 | |
784 | local_irq_restore(flags); | |
785 | return 0; | |
786 | } | |
787 | ||
788 | /*-------------------------------------------------------------------------*/ | |
789 | ||
790 | static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value) | |
791 | { | |
792 | struct pxa2xx_ep *ep; | |
793 | unsigned long flags; | |
794 | ||
795 | ep = container_of(_ep, struct pxa2xx_ep, ep); | |
796 | if (unlikely (!_ep | |
797 | || (!ep->desc && ep->ep.name != ep0name)) | |
798 | || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
799 | DMSG("%s, bad ep\n", __FUNCTION__); | |
800 | return -EINVAL; | |
801 | } | |
802 | if (value == 0) { | |
803 | /* this path (reset toggle+halt) is needed to implement | |
804 | * SET_INTERFACE on normal hardware. but it can't be | |
805 | * done from software on the PXA UDC, and the hardware | |
806 | * forgets to do it as part of SET_INTERFACE automagic. | |
807 | */ | |
808 | DMSG("only host can clear %s halt\n", _ep->name); | |
809 | return -EROFS; | |
810 | } | |
811 | ||
812 | local_irq_save(flags); | |
813 | ||
814 | if ((ep->bEndpointAddress & USB_DIR_IN) != 0 | |
815 | && ((*ep->reg_udccs & UDCCS_BI_TFS) == 0 | |
816 | || !list_empty(&ep->queue))) { | |
817 | local_irq_restore(flags); | |
818 | return -EAGAIN; | |
819 | } | |
820 | ||
821 | /* FST bit is the same for control, bulk in, bulk out, interrupt in */ | |
822 | *ep->reg_udccs = UDCCS_BI_FST|UDCCS_BI_FTF; | |
823 | ||
824 | /* ep0 needs special care */ | |
825 | if (!ep->desc) { | |
826 | start_watchdog(ep->dev); | |
827 | ep->dev->req_pending = 0; | |
828 | ep->dev->ep0state = EP0_STALL; | |
829 | ||
34ebcd28 DB |
830 | /* and bulk/intr endpoints like dropping stalls too */ |
831 | } else { | |
832 | unsigned i; | |
833 | for (i = 0; i < 1000; i += 20) { | |
834 | if (*ep->reg_udccs & UDCCS_BI_SST) | |
835 | break; | |
836 | udelay(20); | |
837 | } | |
838 | } | |
839 | local_irq_restore(flags); | |
1da177e4 LT |
840 | |
841 | DBG(DBG_VERBOSE, "%s halt\n", _ep->name); | |
842 | return 0; | |
843 | } | |
844 | ||
845 | static int pxa2xx_ep_fifo_status(struct usb_ep *_ep) | |
846 | { | |
847 | struct pxa2xx_ep *ep; | |
848 | ||
849 | ep = container_of(_ep, struct pxa2xx_ep, ep); | |
850 | if (!_ep) { | |
851 | DMSG("%s, bad ep\n", __FUNCTION__); | |
852 | return -ENODEV; | |
853 | } | |
854 | /* pxa can't report unclaimed bytes from IN fifos */ | |
855 | if ((ep->bEndpointAddress & USB_DIR_IN) != 0) | |
856 | return -EOPNOTSUPP; | |
857 | if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN | |
858 | || (*ep->reg_udccs & UDCCS_BO_RFS) == 0) | |
859 | return 0; | |
860 | else | |
861 | return (*ep->reg_ubcr & 0xfff) + 1; | |
862 | } | |
863 | ||
864 | static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep) | |
865 | { | |
866 | struct pxa2xx_ep *ep; | |
867 | ||
868 | ep = container_of(_ep, struct pxa2xx_ep, ep); | |
869 | if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { | |
870 | DMSG("%s, bad ep\n", __FUNCTION__); | |
871 | return; | |
872 | } | |
873 | ||
874 | /* toggle and halt bits stay unchanged */ | |
875 | ||
876 | /* for OUT, just read and discard the FIFO contents. */ | |
877 | if ((ep->bEndpointAddress & USB_DIR_IN) == 0) { | |
878 | while (((*ep->reg_udccs) & UDCCS_BO_RNE) != 0) | |
879 | (void) *ep->reg_uddr; | |
880 | return; | |
881 | } | |
882 | ||
883 | /* most IN status is the same, but ISO can't stall */ | |
884 | *ep->reg_udccs = UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR | |
885 | | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | |
886 | ? 0 : UDCCS_BI_SST; | |
887 | } | |
888 | ||
889 | ||
890 | static struct usb_ep_ops pxa2xx_ep_ops = { | |
891 | .enable = pxa2xx_ep_enable, | |
892 | .disable = pxa2xx_ep_disable, | |
893 | ||
894 | .alloc_request = pxa2xx_ep_alloc_request, | |
895 | .free_request = pxa2xx_ep_free_request, | |
896 | ||
1da177e4 LT |
897 | .queue = pxa2xx_ep_queue, |
898 | .dequeue = pxa2xx_ep_dequeue, | |
899 | ||
900 | .set_halt = pxa2xx_ep_set_halt, | |
901 | .fifo_status = pxa2xx_ep_fifo_status, | |
902 | .fifo_flush = pxa2xx_ep_fifo_flush, | |
903 | }; | |
904 | ||
905 | ||
906 | /* --------------------------------------------------------------------------- | |
34ebcd28 | 907 | * device-scoped parts of the api to the usb controller hardware |
1da177e4 LT |
908 | * --------------------------------------------------------------------------- |
909 | */ | |
910 | ||
911 | static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget) | |
912 | { | |
913 | return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff); | |
914 | } | |
915 | ||
916 | static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget) | |
917 | { | |
918 | /* host may not have enabled remote wakeup */ | |
919 | if ((UDCCS0 & UDCCS0_DRWF) == 0) | |
920 | return -EHOSTUNREACH; | |
921 | udc_set_mask_UDCCR(UDCCR_RSM); | |
922 | return 0; | |
923 | } | |
924 | ||
925 | static void stop_activity(struct pxa2xx_udc *, struct usb_gadget_driver *); | |
926 | static void udc_enable (struct pxa2xx_udc *); | |
927 | static void udc_disable(struct pxa2xx_udc *); | |
928 | ||
929 | /* We disable the UDC -- and its 48 MHz clock -- whenever it's not | |
34ebcd28 | 930 | * in active use. |
1da177e4 LT |
931 | */ |
932 | static int pullup(struct pxa2xx_udc *udc, int is_active) | |
933 | { | |
934 | is_active = is_active && udc->vbus && udc->pullup; | |
935 | DMSG("%s\n", is_active ? "active" : "inactive"); | |
936 | if (is_active) | |
937 | udc_enable(udc); | |
938 | else { | |
939 | if (udc->gadget.speed != USB_SPEED_UNKNOWN) { | |
940 | DMSG("disconnect %s\n", udc->driver | |
941 | ? udc->driver->driver.name | |
942 | : "(no driver)"); | |
943 | stop_activity(udc, udc->driver); | |
944 | } | |
945 | udc_disable(udc); | |
946 | } | |
947 | return 0; | |
948 | } | |
949 | ||
950 | /* VBUS reporting logically comes from a transceiver */ | |
951 | static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active) | |
952 | { | |
953 | struct pxa2xx_udc *udc; | |
954 | ||
955 | udc = container_of(_gadget, struct pxa2xx_udc, gadget); | |
956 | udc->vbus = is_active = (is_active != 0); | |
957 | DMSG("vbus %s\n", is_active ? "supplied" : "inactive"); | |
958 | pullup(udc, is_active); | |
959 | return 0; | |
960 | } | |
961 | ||
962 | /* drivers may have software control over D+ pullup */ | |
963 | static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active) | |
964 | { | |
965 | struct pxa2xx_udc *udc; | |
966 | ||
967 | udc = container_of(_gadget, struct pxa2xx_udc, gadget); | |
968 | ||
969 | /* not all boards support pullup control */ | |
8c273033 | 970 | if (!udc->mach->gpio_pullup && !udc->mach->udc_command) |
1da177e4 LT |
971 | return -EOPNOTSUPP; |
972 | ||
973 | is_active = (is_active != 0); | |
974 | udc->pullup = is_active; | |
975 | pullup(udc, is_active); | |
976 | return 0; | |
977 | } | |
978 | ||
979 | static const struct usb_gadget_ops pxa2xx_udc_ops = { | |
980 | .get_frame = pxa2xx_udc_get_frame, | |
981 | .wakeup = pxa2xx_udc_wakeup, | |
982 | .vbus_session = pxa2xx_udc_vbus_session, | |
983 | .pullup = pxa2xx_udc_pullup, | |
984 | ||
985 | // .vbus_draw ... boards may consume current from VBUS, up to | |
986 | // 100-500mA based on config. the 500uA suspend ceiling means | |
987 | // that exclusively vbus-powered PXA designs violate USB specs. | |
988 | }; | |
989 | ||
990 | /*-------------------------------------------------------------------------*/ | |
991 | ||
992 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
993 | ||
994 | static const char proc_node_name [] = "driver/udc"; | |
995 | ||
996 | static int | |
997 | udc_proc_read(char *page, char **start, off_t off, int count, | |
998 | int *eof, void *_dev) | |
999 | { | |
1000 | char *buf = page; | |
1001 | struct pxa2xx_udc *dev = _dev; | |
1002 | char *next = buf; | |
1003 | unsigned size = count; | |
1004 | unsigned long flags; | |
1005 | int i, t; | |
1006 | u32 tmp; | |
1007 | ||
1008 | if (off != 0) | |
1009 | return 0; | |
1010 | ||
1011 | local_irq_save(flags); | |
1012 | ||
1013 | /* basic device status */ | |
1014 | t = scnprintf(next, size, DRIVER_DESC "\n" | |
1015 | "%s version: %s\nGadget driver: %s\nHost %s\n\n", | |
ad8c623f | 1016 | driver_name, DRIVER_VERSION SIZE_STR "(pio)", |
1da177e4 | 1017 | dev->driver ? dev->driver->driver.name : "(none)", |
91987693 | 1018 | is_vbus_present() ? "full speed" : "disconnected"); |
1da177e4 LT |
1019 | size -= t; |
1020 | next += t; | |
1021 | ||
1022 | /* registers for device and ep0 */ | |
1023 | t = scnprintf(next, size, | |
1024 | "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", | |
1025 | UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL); | |
1026 | size -= t; | |
1027 | next += t; | |
1028 | ||
1029 | tmp = UDCCR; | |
1030 | t = scnprintf(next, size, | |
1031 | "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp, | |
1032 | (tmp & UDCCR_REM) ? " rem" : "", | |
1033 | (tmp & UDCCR_RSTIR) ? " rstir" : "", | |
1034 | (tmp & UDCCR_SRM) ? " srm" : "", | |
1035 | (tmp & UDCCR_SUSIR) ? " susir" : "", | |
1036 | (tmp & UDCCR_RESIR) ? " resir" : "", | |
1037 | (tmp & UDCCR_RSM) ? " rsm" : "", | |
1038 | (tmp & UDCCR_UDA) ? " uda" : "", | |
1039 | (tmp & UDCCR_UDE) ? " ude" : ""); | |
1040 | size -= t; | |
1041 | next += t; | |
1042 | ||
1043 | tmp = UDCCS0; | |
1044 | t = scnprintf(next, size, | |
1045 | "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp, | |
1046 | (tmp & UDCCS0_SA) ? " sa" : "", | |
1047 | (tmp & UDCCS0_RNE) ? " rne" : "", | |
1048 | (tmp & UDCCS0_FST) ? " fst" : "", | |
1049 | (tmp & UDCCS0_SST) ? " sst" : "", | |
1050 | (tmp & UDCCS0_DRWF) ? " dwrf" : "", | |
1051 | (tmp & UDCCS0_FTF) ? " ftf" : "", | |
1052 | (tmp & UDCCS0_IPR) ? " ipr" : "", | |
1053 | (tmp & UDCCS0_OPR) ? " opr" : ""); | |
1054 | size -= t; | |
1055 | next += t; | |
1056 | ||
1057 | if (dev->has_cfr) { | |
1058 | tmp = UDCCFR; | |
1059 | t = scnprintf(next, size, | |
1060 | "udccfr %02X =%s%s\n", tmp, | |
1061 | (tmp & UDCCFR_AREN) ? " aren" : "", | |
1062 | (tmp & UDCCFR_ACM) ? " acm" : ""); | |
1063 | size -= t; | |
1064 | next += t; | |
1065 | } | |
1066 | ||
91987693 | 1067 | if (!is_vbus_present() || !dev->driver) |
1da177e4 LT |
1068 | goto done; |
1069 | ||
1070 | t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n", | |
1071 | dev->stats.write.bytes, dev->stats.write.ops, | |
1072 | dev->stats.read.bytes, dev->stats.read.ops, | |
1073 | dev->stats.irqs); | |
1074 | size -= t; | |
1075 | next += t; | |
1076 | ||
1077 | /* dump endpoint queues */ | |
1078 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | |
1079 | struct pxa2xx_ep *ep = &dev->ep [i]; | |
1080 | struct pxa2xx_request *req; | |
1da177e4 LT |
1081 | |
1082 | if (i != 0) { | |
1083 | const struct usb_endpoint_descriptor *d; | |
1084 | ||
1085 | d = ep->desc; | |
1086 | if (!d) | |
1087 | continue; | |
1088 | tmp = *dev->ep [i].reg_udccs; | |
1089 | t = scnprintf(next, size, | |
ad8c623f | 1090 | "%s max %d %s udccs %02x irqs %lu\n", |
1da177e4 | 1091 | ep->ep.name, le16_to_cpu (d->wMaxPacketSize), |
ad8c623f | 1092 | "pio", tmp, ep->pio_irqs); |
1da177e4 LT |
1093 | /* TODO translate all five groups of udccs bits! */ |
1094 | ||
1095 | } else /* ep0 should only have one transfer queued */ | |
1096 | t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n", | |
1097 | ep->pio_irqs); | |
1098 | if (t <= 0 || t > size) | |
1099 | goto done; | |
1100 | size -= t; | |
1101 | next += t; | |
1102 | ||
1103 | if (list_empty(&ep->queue)) { | |
1104 | t = scnprintf(next, size, "\t(nothing queued)\n"); | |
1105 | if (t <= 0 || t > size) | |
1106 | goto done; | |
1107 | size -= t; | |
1108 | next += t; | |
1109 | continue; | |
1110 | } | |
1111 | list_for_each_entry(req, &ep->queue, queue) { | |
ad8c623f | 1112 | t = scnprintf(next, size, |
1da177e4 LT |
1113 | "\treq %p len %d/%d buf %p\n", |
1114 | &req->req, req->req.actual, | |
1115 | req->req.length, req->req.buf); | |
1116 | if (t <= 0 || t > size) | |
1117 | goto done; | |
1118 | size -= t; | |
1119 | next += t; | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | done: | |
1124 | local_irq_restore(flags); | |
1125 | *eof = 1; | |
1126 | return count - size; | |
1127 | } | |
1128 | ||
1129 | #define create_proc_files() \ | |
1130 | create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev) | |
1131 | #define remove_proc_files() \ | |
1132 | remove_proc_entry(proc_node_name, NULL) | |
1133 | ||
1134 | #else /* !CONFIG_USB_GADGET_DEBUG_FILES */ | |
1135 | ||
1136 | #define create_proc_files() do {} while (0) | |
1137 | #define remove_proc_files() do {} while (0) | |
1138 | ||
1139 | #endif /* CONFIG_USB_GADGET_DEBUG_FILES */ | |
1140 | ||
1da177e4 LT |
1141 | /*-------------------------------------------------------------------------*/ |
1142 | ||
1143 | /* | |
34ebcd28 | 1144 | * udc_disable - disable USB device controller |
1da177e4 LT |
1145 | */ |
1146 | static void udc_disable(struct pxa2xx_udc *dev) | |
1147 | { | |
1148 | /* block all irqs */ | |
1149 | udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM); | |
1150 | UICR0 = UICR1 = 0xff; | |
1151 | UFNRH = UFNRH_SIM; | |
1152 | ||
1153 | /* if hardware supports it, disconnect from usb */ | |
91987693 | 1154 | pullup_off(); |
1da177e4 LT |
1155 | |
1156 | udc_clear_mask_UDCCR(UDCCR_UDE); | |
1157 | ||
1158 | #ifdef CONFIG_ARCH_PXA | |
1159 | /* Disable clock for USB device */ | |
7053acbd | 1160 | pxa_set_cken(CKEN_USB, 0); |
1da177e4 LT |
1161 | #endif |
1162 | ||
1163 | ep0_idle (dev); | |
1164 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
1da177e4 LT |
1165 | } |
1166 | ||
1167 | ||
1168 | /* | |
34ebcd28 | 1169 | * udc_reinit - initialize software state |
1da177e4 LT |
1170 | */ |
1171 | static void udc_reinit(struct pxa2xx_udc *dev) | |
1172 | { | |
1173 | u32 i; | |
1174 | ||
1175 | /* device/ep0 records init */ | |
1176 | INIT_LIST_HEAD (&dev->gadget.ep_list); | |
1177 | INIT_LIST_HEAD (&dev->gadget.ep0->ep_list); | |
1178 | dev->ep0state = EP0_IDLE; | |
1179 | ||
1180 | /* basic endpoint records init */ | |
1181 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | |
1182 | struct pxa2xx_ep *ep = &dev->ep[i]; | |
1183 | ||
1184 | if (i != 0) | |
1185 | list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list); | |
1186 | ||
1187 | ep->desc = NULL; | |
1188 | ep->stopped = 0; | |
1189 | INIT_LIST_HEAD (&ep->queue); | |
ad8c623f | 1190 | ep->pio_irqs = 0; |
1da177e4 LT |
1191 | } |
1192 | ||
1193 | /* the rest was statically initialized, and is read-only */ | |
1194 | } | |
1195 | ||
1196 | /* until it's enabled, this UDC should be completely invisible | |
1197 | * to any USB host. | |
1198 | */ | |
1199 | static void udc_enable (struct pxa2xx_udc *dev) | |
1200 | { | |
1201 | udc_clear_mask_UDCCR(UDCCR_UDE); | |
1202 | ||
1203 | #ifdef CONFIG_ARCH_PXA | |
1204 | /* Enable clock for USB device */ | |
7053acbd | 1205 | pxa_set_cken(CKEN_USB, 1); |
1da177e4 LT |
1206 | udelay(5); |
1207 | #endif | |
1208 | ||
1209 | /* try to clear these bits before we enable the udc */ | |
1210 | udc_ack_int_UDCCR(UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR); | |
1211 | ||
1212 | ep0_idle(dev); | |
1213 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
1214 | dev->stats.irqs = 0; | |
1215 | ||
1216 | /* | |
1217 | * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual: | |
1218 | * - enable UDC | |
1219 | * - if RESET is already in progress, ack interrupt | |
1220 | * - unmask reset interrupt | |
1221 | */ | |
1222 | udc_set_mask_UDCCR(UDCCR_UDE); | |
1223 | if (!(UDCCR & UDCCR_UDA)) | |
1224 | udc_ack_int_UDCCR(UDCCR_RSTIR); | |
1225 | ||
1226 | if (dev->has_cfr /* UDC_RES2 is defined */) { | |
1227 | /* pxa255 (a0+) can avoid a set_config race that could | |
1228 | * prevent gadget drivers from configuring correctly | |
1229 | */ | |
1230 | UDCCFR = UDCCFR_ACM | UDCCFR_MB1; | |
1231 | } else { | |
1232 | /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1) | |
1233 | * which could result in missing packets and interrupts. | |
1234 | * supposedly one bit per endpoint, controlling whether it | |
1235 | * double buffers or not; ACM/AREN bits fit into the holes. | |
1236 | * zero bits (like USIR0_IRx) disable double buffering. | |
1237 | */ | |
1238 | UDC_RES1 = 0x00; | |
1239 | UDC_RES2 = 0x00; | |
1240 | } | |
1241 | ||
1da177e4 LT |
1242 | /* enable suspend/resume and reset irqs */ |
1243 | udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM); | |
1244 | ||
1245 | /* enable ep0 irqs */ | |
1246 | UICR0 &= ~UICR0_IM0; | |
1247 | ||
1248 | /* if hardware supports it, pullup D+ and wait for reset */ | |
91987693 | 1249 | pullup_on(); |
1da177e4 LT |
1250 | } |
1251 | ||
1252 | ||
1253 | /* when a driver is successfully registered, it will receive | |
1254 | * control requests including set_configuration(), which enables | |
1255 | * non-control requests. then usb traffic follows until a | |
1256 | * disconnect is reported. then a host may connect again, or | |
1257 | * the driver might get unbound. | |
1258 | */ | |
1259 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) | |
1260 | { | |
1261 | struct pxa2xx_udc *dev = the_controller; | |
1262 | int retval; | |
1263 | ||
1264 | if (!driver | |
7c0642c1 | 1265 | || driver->speed < USB_SPEED_FULL |
1da177e4 | 1266 | || !driver->bind |
1da177e4 LT |
1267 | || !driver->disconnect |
1268 | || !driver->setup) | |
1269 | return -EINVAL; | |
1270 | if (!dev) | |
1271 | return -ENODEV; | |
1272 | if (dev->driver) | |
1273 | return -EBUSY; | |
1274 | ||
1275 | /* first hook up the driver ... */ | |
1276 | dev->driver = driver; | |
1277 | dev->gadget.dev.driver = &driver->driver; | |
1278 | dev->pullup = 1; | |
1279 | ||
34ebcd28 DB |
1280 | retval = device_add (&dev->gadget.dev); |
1281 | if (retval) { | |
1282 | fail: | |
1283 | dev->driver = NULL; | |
1284 | dev->gadget.dev.driver = NULL; | |
1285 | return retval; | |
1286 | } | |
1da177e4 LT |
1287 | retval = driver->bind(&dev->gadget); |
1288 | if (retval) { | |
1289 | DMSG("bind to driver %s --> error %d\n", | |
1290 | driver->driver.name, retval); | |
1291 | device_del (&dev->gadget.dev); | |
34ebcd28 | 1292 | goto fail; |
1da177e4 | 1293 | } |
1da177e4 LT |
1294 | |
1295 | /* ... then enable host detection and ep0; and we're ready | |
1296 | * for set_configuration as well as eventual disconnect. | |
1297 | */ | |
1298 | DMSG("registered gadget driver '%s'\n", driver->driver.name); | |
1299 | pullup(dev, 1); | |
1300 | dump_state(dev); | |
1301 | return 0; | |
1302 | } | |
1303 | EXPORT_SYMBOL(usb_gadget_register_driver); | |
1304 | ||
1305 | static void | |
1306 | stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver) | |
1307 | { | |
1308 | int i; | |
1309 | ||
1310 | /* don't disconnect drivers more than once */ | |
1311 | if (dev->gadget.speed == USB_SPEED_UNKNOWN) | |
1312 | driver = NULL; | |
1313 | dev->gadget.speed = USB_SPEED_UNKNOWN; | |
1314 | ||
1315 | /* prevent new request submissions, kill any outstanding requests */ | |
1316 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | |
1317 | struct pxa2xx_ep *ep = &dev->ep[i]; | |
1318 | ||
1319 | ep->stopped = 1; | |
1320 | nuke(ep, -ESHUTDOWN); | |
1321 | } | |
1322 | del_timer_sync(&dev->timer); | |
1323 | ||
1324 | /* report disconnect; the driver is already quiesced */ | |
1da177e4 LT |
1325 | if (driver) |
1326 | driver->disconnect(&dev->gadget); | |
1327 | ||
1328 | /* re-init driver-visible data structures */ | |
1329 | udc_reinit(dev); | |
1330 | } | |
1331 | ||
1332 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1333 | { | |
1334 | struct pxa2xx_udc *dev = the_controller; | |
1335 | ||
1336 | if (!dev) | |
1337 | return -ENODEV; | |
6bea476c | 1338 | if (!driver || driver != dev->driver || !driver->unbind) |
1da177e4 LT |
1339 | return -EINVAL; |
1340 | ||
1341 | local_irq_disable(); | |
1342 | pullup(dev, 0); | |
1343 | stop_activity(dev, driver); | |
1344 | local_irq_enable(); | |
1345 | ||
1346 | driver->unbind(&dev->gadget); | |
1347 | dev->driver = NULL; | |
1348 | ||
1349 | device_del (&dev->gadget.dev); | |
1da177e4 LT |
1350 | |
1351 | DMSG("unregistered gadget driver '%s'\n", driver->driver.name); | |
1352 | dump_state(dev); | |
1353 | return 0; | |
1354 | } | |
1355 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1356 | ||
1357 | ||
1358 | /*-------------------------------------------------------------------------*/ | |
1359 | ||
1360 | #ifdef CONFIG_ARCH_LUBBOCK | |
1361 | ||
1362 | /* Lubbock has separate connect and disconnect irqs. More typical designs | |
1363 | * use one GPIO as the VBUS IRQ, and another to control the D+ pullup. | |
1364 | */ | |
1365 | ||
1366 | static irqreturn_t | |
7d12e780 | 1367 | lubbock_vbus_irq(int irq, void *_dev) |
1da177e4 LT |
1368 | { |
1369 | struct pxa2xx_udc *dev = _dev; | |
1370 | int vbus; | |
1371 | ||
1372 | dev->stats.irqs++; | |
1da177e4 LT |
1373 | switch (irq) { |
1374 | case LUBBOCK_USB_IRQ: | |
1da177e4 LT |
1375 | vbus = 1; |
1376 | disable_irq(LUBBOCK_USB_IRQ); | |
1377 | enable_irq(LUBBOCK_USB_DISC_IRQ); | |
1378 | break; | |
1379 | case LUBBOCK_USB_DISC_IRQ: | |
1da177e4 LT |
1380 | vbus = 0; |
1381 | disable_irq(LUBBOCK_USB_DISC_IRQ); | |
1382 | enable_irq(LUBBOCK_USB_IRQ); | |
1383 | break; | |
1384 | default: | |
1385 | return IRQ_NONE; | |
1386 | } | |
1387 | ||
1388 | pxa2xx_udc_vbus_session(&dev->gadget, vbus); | |
1389 | return IRQ_HANDLED; | |
1390 | } | |
1391 | ||
1392 | #endif | |
1393 | ||
7d12e780 | 1394 | static irqreturn_t udc_vbus_irq(int irq, void *_dev) |
b2bbb20b DB |
1395 | { |
1396 | struct pxa2xx_udc *dev = _dev; | |
9068a4c6 | 1397 | int vbus = gpio_get_value(dev->mach->gpio_vbus); |
b2bbb20b DB |
1398 | |
1399 | pxa2xx_udc_vbus_session(&dev->gadget, vbus); | |
1400 | return IRQ_HANDLED; | |
1401 | } | |
1402 | ||
1da177e4 LT |
1403 | |
1404 | /*-------------------------------------------------------------------------*/ | |
1405 | ||
1406 | static inline void clear_ep_state (struct pxa2xx_udc *dev) | |
1407 | { | |
1408 | unsigned i; | |
1409 | ||
1410 | /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint | |
1411 | * fifos, and pending transactions mustn't be continued in any case. | |
1412 | */ | |
1413 | for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) | |
1414 | nuke(&dev->ep[i], -ECONNABORTED); | |
1415 | } | |
1416 | ||
1417 | static void udc_watchdog(unsigned long _dev) | |
1418 | { | |
1419 | struct pxa2xx_udc *dev = (void *)_dev; | |
1420 | ||
1421 | local_irq_disable(); | |
1422 | if (dev->ep0state == EP0_STALL | |
1423 | && (UDCCS0 & UDCCS0_FST) == 0 | |
1424 | && (UDCCS0 & UDCCS0_SST) == 0) { | |
1425 | UDCCS0 = UDCCS0_FST|UDCCS0_FTF; | |
1426 | DBG(DBG_VERBOSE, "ep0 re-stall\n"); | |
1427 | start_watchdog(dev); | |
1428 | } | |
1429 | local_irq_enable(); | |
1430 | } | |
1431 | ||
1432 | static void handle_ep0 (struct pxa2xx_udc *dev) | |
1433 | { | |
1434 | u32 udccs0 = UDCCS0; | |
1435 | struct pxa2xx_ep *ep = &dev->ep [0]; | |
1436 | struct pxa2xx_request *req; | |
1437 | union { | |
1438 | struct usb_ctrlrequest r; | |
1439 | u8 raw [8]; | |
1440 | u32 word [2]; | |
1441 | } u; | |
1442 | ||
1443 | if (list_empty(&ep->queue)) | |
1444 | req = NULL; | |
1445 | else | |
1446 | req = list_entry(ep->queue.next, struct pxa2xx_request, queue); | |
1447 | ||
1448 | /* clear stall status */ | |
1449 | if (udccs0 & UDCCS0_SST) { | |
1450 | nuke(ep, -EPIPE); | |
1451 | UDCCS0 = UDCCS0_SST; | |
1452 | del_timer(&dev->timer); | |
1453 | ep0_idle(dev); | |
1454 | } | |
1455 | ||
1456 | /* previous request unfinished? non-error iff back-to-back ... */ | |
1457 | if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { | |
1458 | nuke(ep, 0); | |
1459 | del_timer(&dev->timer); | |
1460 | ep0_idle(dev); | |
1461 | } | |
1462 | ||
1463 | switch (dev->ep0state) { | |
1464 | case EP0_IDLE: | |
1465 | /* late-breaking status? */ | |
1466 | udccs0 = UDCCS0; | |
1467 | ||
1468 | /* start control request? */ | |
1469 | if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE)) | |
1470 | == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) { | |
1471 | int i; | |
1472 | ||
1473 | nuke (ep, -EPROTO); | |
1474 | ||
1475 | /* read SETUP packet */ | |
1476 | for (i = 0; i < 8; i++) { | |
1477 | if (unlikely(!(UDCCS0 & UDCCS0_RNE))) { | |
1478 | bad_setup: | |
1479 | DMSG("SETUP %d!\n", i); | |
1480 | goto stall; | |
1481 | } | |
1482 | u.raw [i] = (u8) UDDR0; | |
1483 | } | |
1484 | if (unlikely((UDCCS0 & UDCCS0_RNE) != 0)) | |
1485 | goto bad_setup; | |
1486 | ||
1487 | got_setup: | |
1488 | DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1489 | u.r.bRequestType, u.r.bRequest, | |
1490 | le16_to_cpu(u.r.wValue), | |
1491 | le16_to_cpu(u.r.wIndex), | |
1492 | le16_to_cpu(u.r.wLength)); | |
1493 | ||
1494 | /* cope with automagic for some standard requests. */ | |
1495 | dev->req_std = (u.r.bRequestType & USB_TYPE_MASK) | |
1496 | == USB_TYPE_STANDARD; | |
1497 | dev->req_config = 0; | |
1498 | dev->req_pending = 1; | |
1499 | switch (u.r.bRequest) { | |
1500 | /* hardware restricts gadget drivers here! */ | |
1501 | case USB_REQ_SET_CONFIGURATION: | |
1502 | if (u.r.bRequestType == USB_RECIP_DEVICE) { | |
1503 | /* reflect hardware's automagic | |
1504 | * up to the gadget driver. | |
1505 | */ | |
1506 | config_change: | |
1507 | dev->req_config = 1; | |
1508 | clear_ep_state(dev); | |
1509 | /* if !has_cfr, there's no synch | |
1510 | * else use AREN (later) not SA|OPR | |
1511 | * USIR0_IR0 acts edge sensitive | |
1512 | */ | |
1513 | } | |
1514 | break; | |
1515 | /* ... and here, even more ... */ | |
1516 | case USB_REQ_SET_INTERFACE: | |
1517 | if (u.r.bRequestType == USB_RECIP_INTERFACE) { | |
1518 | /* udc hardware is broken by design: | |
1519 | * - altsetting may only be zero; | |
1520 | * - hw resets all interfaces' eps; | |
1521 | * - ep reset doesn't include halt(?). | |
1522 | */ | |
1523 | DMSG("broken set_interface (%d/%d)\n", | |
1524 | le16_to_cpu(u.r.wIndex), | |
1525 | le16_to_cpu(u.r.wValue)); | |
1526 | goto config_change; | |
1527 | } | |
1528 | break; | |
1529 | /* hardware was supposed to hide this */ | |
1530 | case USB_REQ_SET_ADDRESS: | |
1531 | if (u.r.bRequestType == USB_RECIP_DEVICE) { | |
1532 | ep0start(dev, 0, "address"); | |
1533 | return; | |
1534 | } | |
1535 | break; | |
1536 | } | |
1537 | ||
1538 | if (u.r.bRequestType & USB_DIR_IN) | |
1539 | dev->ep0state = EP0_IN_DATA_PHASE; | |
1540 | else | |
1541 | dev->ep0state = EP0_OUT_DATA_PHASE; | |
1542 | ||
1543 | i = dev->driver->setup(&dev->gadget, &u.r); | |
1544 | if (i < 0) { | |
1545 | /* hardware automagic preventing STALL... */ | |
1546 | if (dev->req_config) { | |
1547 | /* hardware sometimes neglects to tell | |
1548 | * tell us about config change events, | |
1549 | * so later ones may fail... | |
1550 | */ | |
1551 | WARN("config change %02x fail %d?\n", | |
1552 | u.r.bRequest, i); | |
1553 | return; | |
1554 | /* TODO experiment: if has_cfr, | |
1555 | * hardware didn't ACK; maybe we | |
1556 | * could actually STALL! | |
1557 | */ | |
1558 | } | |
1559 | DBG(DBG_VERBOSE, "protocol STALL, " | |
1560 | "%02x err %d\n", UDCCS0, i); | |
1561 | stall: | |
1562 | /* the watchdog timer helps deal with cases | |
1563 | * where udc seems to clear FST wrongly, and | |
1564 | * then NAKs instead of STALLing. | |
1565 | */ | |
1566 | ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall"); | |
1567 | start_watchdog(dev); | |
1568 | dev->ep0state = EP0_STALL; | |
1569 | ||
1570 | /* deferred i/o == no response yet */ | |
1571 | } else if (dev->req_pending) { | |
1572 | if (likely(dev->ep0state == EP0_IN_DATA_PHASE | |
1573 | || dev->req_std || u.r.wLength)) | |
1574 | ep0start(dev, 0, "defer"); | |
1575 | else | |
1576 | ep0start(dev, UDCCS0_IPR, "defer/IPR"); | |
1577 | } | |
1578 | ||
1579 | /* expect at least one data or status stage irq */ | |
1580 | return; | |
1581 | ||
1582 | } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA)) | |
1583 | == (UDCCS0_OPR|UDCCS0_SA))) { | |
1584 | unsigned i; | |
1585 | ||
1586 | /* pxa210/250 erratum 131 for B0/B1 says RNE lies. | |
1587 | * still observed on a pxa255 a0. | |
1588 | */ | |
1589 | DBG(DBG_VERBOSE, "e131\n"); | |
1590 | nuke(ep, -EPROTO); | |
1591 | ||
1592 | /* read SETUP data, but don't trust it too much */ | |
1593 | for (i = 0; i < 8; i++) | |
1594 | u.raw [i] = (u8) UDDR0; | |
1595 | if ((u.r.bRequestType & USB_RECIP_MASK) | |
1596 | > USB_RECIP_OTHER) | |
1597 | goto stall; | |
1598 | if (u.word [0] == 0 && u.word [1] == 0) | |
1599 | goto stall; | |
1600 | goto got_setup; | |
1601 | } else { | |
1602 | /* some random early IRQ: | |
1603 | * - we acked FST | |
1604 | * - IPR cleared | |
1605 | * - OPR got set, without SA (likely status stage) | |
1606 | */ | |
1607 | UDCCS0 = udccs0 & (UDCCS0_SA|UDCCS0_OPR); | |
1608 | } | |
1609 | break; | |
1610 | case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */ | |
1611 | if (udccs0 & UDCCS0_OPR) { | |
1612 | UDCCS0 = UDCCS0_OPR|UDCCS0_FTF; | |
1613 | DBG(DBG_VERBOSE, "ep0in premature status\n"); | |
1614 | if (req) | |
1615 | done(ep, req, 0); | |
1616 | ep0_idle(dev); | |
1617 | } else /* irq was IPR clearing */ { | |
1618 | if (req) { | |
1619 | /* this IN packet might finish the request */ | |
1620 | (void) write_ep0_fifo(ep, req); | |
1621 | } /* else IN token before response was written */ | |
1622 | } | |
1623 | break; | |
1624 | case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */ | |
1625 | if (udccs0 & UDCCS0_OPR) { | |
1626 | if (req) { | |
1627 | /* this OUT packet might finish the request */ | |
1628 | if (read_ep0_fifo(ep, req)) | |
1629 | done(ep, req, 0); | |
1630 | /* else more OUT packets expected */ | |
1631 | } /* else OUT token before read was issued */ | |
1632 | } else /* irq was IPR clearing */ { | |
1633 | DBG(DBG_VERBOSE, "ep0out premature status\n"); | |
1634 | if (req) | |
1635 | done(ep, req, 0); | |
1636 | ep0_idle(dev); | |
1637 | } | |
1638 | break; | |
1639 | case EP0_END_XFER: | |
1640 | if (req) | |
1641 | done(ep, req, 0); | |
1642 | /* ack control-IN status (maybe in-zlp was skipped) | |
1643 | * also appears after some config change events. | |
1644 | */ | |
1645 | if (udccs0 & UDCCS0_OPR) | |
1646 | UDCCS0 = UDCCS0_OPR; | |
1647 | ep0_idle(dev); | |
1648 | break; | |
1649 | case EP0_STALL: | |
1650 | UDCCS0 = UDCCS0_FST; | |
1651 | break; | |
1652 | } | |
1653 | USIR0 = USIR0_IR0; | |
1654 | } | |
1655 | ||
1656 | static void handle_ep(struct pxa2xx_ep *ep) | |
1657 | { | |
1658 | struct pxa2xx_request *req; | |
1659 | int is_in = ep->bEndpointAddress & USB_DIR_IN; | |
1660 | int completed; | |
1661 | u32 udccs, tmp; | |
1662 | ||
1663 | do { | |
1664 | completed = 0; | |
1665 | if (likely (!list_empty(&ep->queue))) | |
1666 | req = list_entry(ep->queue.next, | |
1667 | struct pxa2xx_request, queue); | |
1668 | else | |
1669 | req = NULL; | |
1670 | ||
1671 | // TODO check FST handling | |
1672 | ||
1673 | udccs = *ep->reg_udccs; | |
1674 | if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */ | |
1675 | tmp = UDCCS_BI_TUR; | |
1676 | if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) | |
1677 | tmp |= UDCCS_BI_SST; | |
1678 | tmp &= udccs; | |
1679 | if (likely (tmp)) | |
1680 | *ep->reg_udccs = tmp; | |
1681 | if (req && likely ((udccs & UDCCS_BI_TFS) != 0)) | |
1682 | completed = write_fifo(ep, req); | |
1683 | ||
1684 | } else { /* irq from RPC (or for ISO, ROF) */ | |
1685 | if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK)) | |
1686 | tmp = UDCCS_BO_SST | UDCCS_BO_DME; | |
1687 | else | |
1688 | tmp = UDCCS_IO_ROF | UDCCS_IO_DME; | |
1689 | tmp &= udccs; | |
1690 | if (likely(tmp)) | |
1691 | *ep->reg_udccs = tmp; | |
1692 | ||
1693 | /* fifos can hold packets, ready for reading... */ | |
1694 | if (likely(req)) { | |
1da177e4 LT |
1695 | completed = read_fifo(ep, req); |
1696 | } else | |
1697 | pio_irq_disable (ep->bEndpointAddress); | |
1698 | } | |
1699 | ep->pio_irqs++; | |
1700 | } while (completed); | |
1701 | } | |
1702 | ||
1703 | /* | |
1704 | * pxa2xx_udc_irq - interrupt handler | |
1705 | * | |
1706 | * avoid delays in ep0 processing. the control handshaking isn't always | |
1707 | * under software control (pxa250c0 and the pxa255 are better), and delays | |
1708 | * could cause usb protocol errors. | |
1709 | */ | |
1710 | static irqreturn_t | |
7d12e780 | 1711 | pxa2xx_udc_irq(int irq, void *_dev) |
1da177e4 LT |
1712 | { |
1713 | struct pxa2xx_udc *dev = _dev; | |
1714 | int handled; | |
1715 | ||
1716 | dev->stats.irqs++; | |
1da177e4 LT |
1717 | do { |
1718 | u32 udccr = UDCCR; | |
1719 | ||
1720 | handled = 0; | |
1721 | ||
1722 | /* SUSpend Interrupt Request */ | |
1723 | if (unlikely(udccr & UDCCR_SUSIR)) { | |
1724 | udc_ack_int_UDCCR(UDCCR_SUSIR); | |
1725 | handled = 1; | |
91987693 | 1726 | DBG(DBG_VERBOSE, "USB suspend%s\n", is_vbus_present() |
1da177e4 LT |
1727 | ? "" : "+disconnect"); |
1728 | ||
91987693 | 1729 | if (!is_vbus_present()) |
1da177e4 LT |
1730 | stop_activity(dev, dev->driver); |
1731 | else if (dev->gadget.speed != USB_SPEED_UNKNOWN | |
1732 | && dev->driver | |
1733 | && dev->driver->suspend) | |
1734 | dev->driver->suspend(&dev->gadget); | |
1735 | ep0_idle (dev); | |
1736 | } | |
1737 | ||
1738 | /* RESume Interrupt Request */ | |
1739 | if (unlikely(udccr & UDCCR_RESIR)) { | |
1740 | udc_ack_int_UDCCR(UDCCR_RESIR); | |
1741 | handled = 1; | |
1742 | DBG(DBG_VERBOSE, "USB resume\n"); | |
1743 | ||
1744 | if (dev->gadget.speed != USB_SPEED_UNKNOWN | |
1745 | && dev->driver | |
1746 | && dev->driver->resume | |
91987693 | 1747 | && is_vbus_present()) |
1da177e4 LT |
1748 | dev->driver->resume(&dev->gadget); |
1749 | } | |
1750 | ||
1751 | /* ReSeT Interrupt Request - USB reset */ | |
1752 | if (unlikely(udccr & UDCCR_RSTIR)) { | |
1753 | udc_ack_int_UDCCR(UDCCR_RSTIR); | |
1754 | handled = 1; | |
1755 | ||
1756 | if ((UDCCR & UDCCR_UDA) == 0) { | |
1757 | DBG(DBG_VERBOSE, "USB reset start\n"); | |
1758 | ||
1759 | /* reset driver and endpoints, | |
1760 | * in case that's not yet done | |
1761 | */ | |
1762 | stop_activity (dev, dev->driver); | |
1763 | ||
1764 | } else { | |
1765 | DBG(DBG_VERBOSE, "USB reset end\n"); | |
1766 | dev->gadget.speed = USB_SPEED_FULL; | |
1da177e4 LT |
1767 | memset(&dev->stats, 0, sizeof dev->stats); |
1768 | /* driver and endpoints are still reset */ | |
1769 | } | |
1770 | ||
1771 | } else { | |
1772 | u32 usir0 = USIR0 & ~UICR0; | |
1773 | u32 usir1 = USIR1 & ~UICR1; | |
1774 | int i; | |
1775 | ||
1776 | if (unlikely (!usir0 && !usir1)) | |
1777 | continue; | |
1778 | ||
1779 | DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0); | |
1780 | ||
1781 | /* control traffic */ | |
1782 | if (usir0 & USIR0_IR0) { | |
1783 | dev->ep[0].pio_irqs++; | |
1784 | handle_ep0(dev); | |
1785 | handled = 1; | |
1786 | } | |
1787 | ||
1788 | /* endpoint data transfers */ | |
1789 | for (i = 0; i < 8; i++) { | |
1790 | u32 tmp = 1 << i; | |
1791 | ||
1792 | if (i && (usir0 & tmp)) { | |
1793 | handle_ep(&dev->ep[i]); | |
1794 | USIR0 |= tmp; | |
1795 | handled = 1; | |
1796 | } | |
1797 | if (usir1 & tmp) { | |
1798 | handle_ep(&dev->ep[i+8]); | |
1799 | USIR1 |= tmp; | |
1800 | handled = 1; | |
1801 | } | |
1802 | } | |
1803 | } | |
1804 | ||
1805 | /* we could also ask for 1 msec SOF (SIR) interrupts */ | |
1806 | ||
1807 | } while (handled); | |
1808 | return IRQ_HANDLED; | |
1809 | } | |
1810 | ||
1811 | /*-------------------------------------------------------------------------*/ | |
1812 | ||
1813 | static void nop_release (struct device *dev) | |
1814 | { | |
1815 | DMSG("%s %s\n", __FUNCTION__, dev->bus_id); | |
1816 | } | |
1817 | ||
1818 | /* this uses load-time allocation and initialization (instead of | |
1819 | * doing it at run-time) to save code, eliminate fault paths, and | |
1820 | * be more obviously correct. | |
1821 | */ | |
1822 | static struct pxa2xx_udc memory = { | |
1823 | .gadget = { | |
1824 | .ops = &pxa2xx_udc_ops, | |
1825 | .ep0 = &memory.ep[0].ep, | |
1826 | .name = driver_name, | |
1827 | .dev = { | |
1828 | .bus_id = "gadget", | |
1829 | .release = nop_release, | |
1830 | }, | |
1831 | }, | |
1832 | ||
1833 | /* control endpoint */ | |
1834 | .ep[0] = { | |
1835 | .ep = { | |
1836 | .name = ep0name, | |
1837 | .ops = &pxa2xx_ep_ops, | |
1838 | .maxpacket = EP0_FIFO_SIZE, | |
1839 | }, | |
1840 | .dev = &memory, | |
1841 | .reg_udccs = &UDCCS0, | |
1842 | .reg_uddr = &UDDR0, | |
1843 | }, | |
1844 | ||
1845 | /* first group of endpoints */ | |
1846 | .ep[1] = { | |
1847 | .ep = { | |
1848 | .name = "ep1in-bulk", | |
1849 | .ops = &pxa2xx_ep_ops, | |
1850 | .maxpacket = BULK_FIFO_SIZE, | |
1851 | }, | |
1852 | .dev = &memory, | |
1853 | .fifo_size = BULK_FIFO_SIZE, | |
1854 | .bEndpointAddress = USB_DIR_IN | 1, | |
1855 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1856 | .reg_udccs = &UDCCS1, | |
1857 | .reg_uddr = &UDDR1, | |
1da177e4 LT |
1858 | }, |
1859 | .ep[2] = { | |
1860 | .ep = { | |
1861 | .name = "ep2out-bulk", | |
1862 | .ops = &pxa2xx_ep_ops, | |
1863 | .maxpacket = BULK_FIFO_SIZE, | |
1864 | }, | |
1865 | .dev = &memory, | |
1866 | .fifo_size = BULK_FIFO_SIZE, | |
1867 | .bEndpointAddress = 2, | |
1868 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1869 | .reg_udccs = &UDCCS2, | |
1870 | .reg_ubcr = &UBCR2, | |
1871 | .reg_uddr = &UDDR2, | |
1da177e4 LT |
1872 | }, |
1873 | #ifndef CONFIG_USB_PXA2XX_SMALL | |
1874 | .ep[3] = { | |
1875 | .ep = { | |
1876 | .name = "ep3in-iso", | |
1877 | .ops = &pxa2xx_ep_ops, | |
1878 | .maxpacket = ISO_FIFO_SIZE, | |
1879 | }, | |
1880 | .dev = &memory, | |
1881 | .fifo_size = ISO_FIFO_SIZE, | |
1882 | .bEndpointAddress = USB_DIR_IN | 3, | |
1883 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
1884 | .reg_udccs = &UDCCS3, | |
1885 | .reg_uddr = &UDDR3, | |
1da177e4 LT |
1886 | }, |
1887 | .ep[4] = { | |
1888 | .ep = { | |
1889 | .name = "ep4out-iso", | |
1890 | .ops = &pxa2xx_ep_ops, | |
1891 | .maxpacket = ISO_FIFO_SIZE, | |
1892 | }, | |
1893 | .dev = &memory, | |
1894 | .fifo_size = ISO_FIFO_SIZE, | |
1895 | .bEndpointAddress = 4, | |
1896 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
1897 | .reg_udccs = &UDCCS4, | |
1898 | .reg_ubcr = &UBCR4, | |
1899 | .reg_uddr = &UDDR4, | |
1da177e4 LT |
1900 | }, |
1901 | .ep[5] = { | |
1902 | .ep = { | |
1903 | .name = "ep5in-int", | |
1904 | .ops = &pxa2xx_ep_ops, | |
1905 | .maxpacket = INT_FIFO_SIZE, | |
1906 | }, | |
1907 | .dev = &memory, | |
1908 | .fifo_size = INT_FIFO_SIZE, | |
1909 | .bEndpointAddress = USB_DIR_IN | 5, | |
1910 | .bmAttributes = USB_ENDPOINT_XFER_INT, | |
1911 | .reg_udccs = &UDCCS5, | |
1912 | .reg_uddr = &UDDR5, | |
1913 | }, | |
1914 | ||
1915 | /* second group of endpoints */ | |
1916 | .ep[6] = { | |
1917 | .ep = { | |
1918 | .name = "ep6in-bulk", | |
1919 | .ops = &pxa2xx_ep_ops, | |
1920 | .maxpacket = BULK_FIFO_SIZE, | |
1921 | }, | |
1922 | .dev = &memory, | |
1923 | .fifo_size = BULK_FIFO_SIZE, | |
1924 | .bEndpointAddress = USB_DIR_IN | 6, | |
1925 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1926 | .reg_udccs = &UDCCS6, | |
1927 | .reg_uddr = &UDDR6, | |
1da177e4 LT |
1928 | }, |
1929 | .ep[7] = { | |
1930 | .ep = { | |
1931 | .name = "ep7out-bulk", | |
1932 | .ops = &pxa2xx_ep_ops, | |
1933 | .maxpacket = BULK_FIFO_SIZE, | |
1934 | }, | |
1935 | .dev = &memory, | |
1936 | .fifo_size = BULK_FIFO_SIZE, | |
1937 | .bEndpointAddress = 7, | |
1938 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1939 | .reg_udccs = &UDCCS7, | |
1940 | .reg_ubcr = &UBCR7, | |
1941 | .reg_uddr = &UDDR7, | |
1da177e4 LT |
1942 | }, |
1943 | .ep[8] = { | |
1944 | .ep = { | |
1945 | .name = "ep8in-iso", | |
1946 | .ops = &pxa2xx_ep_ops, | |
1947 | .maxpacket = ISO_FIFO_SIZE, | |
1948 | }, | |
1949 | .dev = &memory, | |
1950 | .fifo_size = ISO_FIFO_SIZE, | |
1951 | .bEndpointAddress = USB_DIR_IN | 8, | |
1952 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
1953 | .reg_udccs = &UDCCS8, | |
1954 | .reg_uddr = &UDDR8, | |
1da177e4 LT |
1955 | }, |
1956 | .ep[9] = { | |
1957 | .ep = { | |
1958 | .name = "ep9out-iso", | |
1959 | .ops = &pxa2xx_ep_ops, | |
1960 | .maxpacket = ISO_FIFO_SIZE, | |
1961 | }, | |
1962 | .dev = &memory, | |
1963 | .fifo_size = ISO_FIFO_SIZE, | |
1964 | .bEndpointAddress = 9, | |
1965 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
1966 | .reg_udccs = &UDCCS9, | |
1967 | .reg_ubcr = &UBCR9, | |
1968 | .reg_uddr = &UDDR9, | |
1da177e4 LT |
1969 | }, |
1970 | .ep[10] = { | |
1971 | .ep = { | |
1972 | .name = "ep10in-int", | |
1973 | .ops = &pxa2xx_ep_ops, | |
1974 | .maxpacket = INT_FIFO_SIZE, | |
1975 | }, | |
1976 | .dev = &memory, | |
1977 | .fifo_size = INT_FIFO_SIZE, | |
1978 | .bEndpointAddress = USB_DIR_IN | 10, | |
1979 | .bmAttributes = USB_ENDPOINT_XFER_INT, | |
1980 | .reg_udccs = &UDCCS10, | |
1981 | .reg_uddr = &UDDR10, | |
1982 | }, | |
1983 | ||
1984 | /* third group of endpoints */ | |
1985 | .ep[11] = { | |
1986 | .ep = { | |
1987 | .name = "ep11in-bulk", | |
1988 | .ops = &pxa2xx_ep_ops, | |
1989 | .maxpacket = BULK_FIFO_SIZE, | |
1990 | }, | |
1991 | .dev = &memory, | |
1992 | .fifo_size = BULK_FIFO_SIZE, | |
1993 | .bEndpointAddress = USB_DIR_IN | 11, | |
1994 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
1995 | .reg_udccs = &UDCCS11, | |
1996 | .reg_uddr = &UDDR11, | |
1da177e4 LT |
1997 | }, |
1998 | .ep[12] = { | |
1999 | .ep = { | |
2000 | .name = "ep12out-bulk", | |
2001 | .ops = &pxa2xx_ep_ops, | |
2002 | .maxpacket = BULK_FIFO_SIZE, | |
2003 | }, | |
2004 | .dev = &memory, | |
2005 | .fifo_size = BULK_FIFO_SIZE, | |
2006 | .bEndpointAddress = 12, | |
2007 | .bmAttributes = USB_ENDPOINT_XFER_BULK, | |
2008 | .reg_udccs = &UDCCS12, | |
2009 | .reg_ubcr = &UBCR12, | |
2010 | .reg_uddr = &UDDR12, | |
1da177e4 LT |
2011 | }, |
2012 | .ep[13] = { | |
2013 | .ep = { | |
2014 | .name = "ep13in-iso", | |
2015 | .ops = &pxa2xx_ep_ops, | |
2016 | .maxpacket = ISO_FIFO_SIZE, | |
2017 | }, | |
2018 | .dev = &memory, | |
2019 | .fifo_size = ISO_FIFO_SIZE, | |
2020 | .bEndpointAddress = USB_DIR_IN | 13, | |
2021 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
2022 | .reg_udccs = &UDCCS13, | |
2023 | .reg_uddr = &UDDR13, | |
1da177e4 LT |
2024 | }, |
2025 | .ep[14] = { | |
2026 | .ep = { | |
2027 | .name = "ep14out-iso", | |
2028 | .ops = &pxa2xx_ep_ops, | |
2029 | .maxpacket = ISO_FIFO_SIZE, | |
2030 | }, | |
2031 | .dev = &memory, | |
2032 | .fifo_size = ISO_FIFO_SIZE, | |
2033 | .bEndpointAddress = 14, | |
2034 | .bmAttributes = USB_ENDPOINT_XFER_ISOC, | |
2035 | .reg_udccs = &UDCCS14, | |
2036 | .reg_ubcr = &UBCR14, | |
2037 | .reg_uddr = &UDDR14, | |
1da177e4 LT |
2038 | }, |
2039 | .ep[15] = { | |
2040 | .ep = { | |
2041 | .name = "ep15in-int", | |
2042 | .ops = &pxa2xx_ep_ops, | |
2043 | .maxpacket = INT_FIFO_SIZE, | |
2044 | }, | |
2045 | .dev = &memory, | |
2046 | .fifo_size = INT_FIFO_SIZE, | |
2047 | .bEndpointAddress = USB_DIR_IN | 15, | |
2048 | .bmAttributes = USB_ENDPOINT_XFER_INT, | |
2049 | .reg_udccs = &UDCCS15, | |
2050 | .reg_uddr = &UDDR15, | |
2051 | }, | |
2052 | #endif /* !CONFIG_USB_PXA2XX_SMALL */ | |
2053 | }; | |
2054 | ||
2055 | #define CP15R0_VENDOR_MASK 0xffffe000 | |
2056 | ||
2057 | #if defined(CONFIG_ARCH_PXA) | |
2058 | #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */ | |
2059 | ||
2060 | #elif defined(CONFIG_ARCH_IXP4XX) | |
2061 | #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */ | |
2062 | ||
2063 | #endif | |
2064 | ||
2065 | #define CP15R0_PROD_MASK 0x000003f0 | |
2066 | #define PXA25x 0x00000100 /* and PXA26x */ | |
2067 | #define PXA210 0x00000120 | |
2068 | ||
2069 | #define CP15R0_REV_MASK 0x0000000f | |
2070 | ||
2071 | #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK) | |
2072 | ||
2073 | #define PXA255_A0 0x00000106 /* or PXA260_B1 */ | |
2074 | #define PXA250_C0 0x00000105 /* or PXA26x_B0 */ | |
2075 | #define PXA250_B2 0x00000104 | |
2076 | #define PXA250_B1 0x00000103 /* or PXA260_A0 */ | |
2077 | #define PXA250_B0 0x00000102 | |
2078 | #define PXA250_A1 0x00000101 | |
2079 | #define PXA250_A0 0x00000100 | |
2080 | ||
2081 | #define PXA210_C0 0x00000125 | |
2082 | #define PXA210_B2 0x00000124 | |
2083 | #define PXA210_B1 0x00000123 | |
2084 | #define PXA210_B0 0x00000122 | |
2085 | #define IXP425_A0 0x000001c1 | |
827982c5 | 2086 | #define IXP425_B0 0x000001f1 |
043ea18b | 2087 | #define IXP465_AD 0x00000200 |
1da177e4 LT |
2088 | |
2089 | /* | |
34ebcd28 | 2090 | * probe - binds to the platform device |
1da177e4 | 2091 | */ |
3ae5eaec | 2092 | static int __init pxa2xx_udc_probe(struct platform_device *pdev) |
1da177e4 LT |
2093 | { |
2094 | struct pxa2xx_udc *dev = &memory; | |
ad8c623f | 2095 | int retval, vbus_irq, irq; |
1da177e4 LT |
2096 | u32 chiprev; |
2097 | ||
2098 | /* insist on Intel/ARM/XScale */ | |
2099 | asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev)); | |
2100 | if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) { | |
2101 | printk(KERN_ERR "%s: not XScale!\n", driver_name); | |
2102 | return -ENODEV; | |
2103 | } | |
2104 | ||
2105 | /* trigger chiprev-specific logic */ | |
2106 | switch (chiprev & CP15R0_PRODREV_MASK) { | |
2107 | #if defined(CONFIG_ARCH_PXA) | |
2108 | case PXA255_A0: | |
2109 | dev->has_cfr = 1; | |
2110 | break; | |
2111 | case PXA250_A0: | |
2112 | case PXA250_A1: | |
2113 | /* A0/A1 "not released"; ep 13, 15 unusable */ | |
2114 | /* fall through */ | |
2115 | case PXA250_B2: case PXA210_B2: | |
2116 | case PXA250_B1: case PXA210_B1: | |
2117 | case PXA250_B0: case PXA210_B0: | |
ad8c623f | 2118 | /* OUT-DMA is broken ... */ |
1da177e4 LT |
2119 | /* fall through */ |
2120 | case PXA250_C0: case PXA210_C0: | |
2121 | break; | |
2122 | #elif defined(CONFIG_ARCH_IXP4XX) | |
2123 | case IXP425_A0: | |
827982c5 | 2124 | case IXP425_B0: |
043ea18b MS |
2125 | case IXP465_AD: |
2126 | dev->has_cfr = 1; | |
1da177e4 LT |
2127 | break; |
2128 | #endif | |
2129 | default: | |
1da177e4 LT |
2130 | printk(KERN_ERR "%s: unrecognized processor: %08x\n", |
2131 | driver_name, chiprev); | |
2132 | /* iop3xx, ixp4xx, ... */ | |
2133 | return -ENODEV; | |
2134 | } | |
2135 | ||
34ebcd28 DB |
2136 | irq = platform_get_irq(pdev, 0); |
2137 | if (irq < 0) | |
2138 | return -ENODEV; | |
2139 | ||
ad8c623f | 2140 | pr_debug("%s: IRQ %d%s%s\n", driver_name, irq, |
1da177e4 | 2141 | dev->has_cfr ? "" : " (!cfr)", |
ad8c623f | 2142 | SIZE_STR "(pio)" |
1da177e4 LT |
2143 | ); |
2144 | ||
1da177e4 | 2145 | /* other non-static parts of init */ |
3ae5eaec RK |
2146 | dev->dev = &pdev->dev; |
2147 | dev->mach = pdev->dev.platform_data; | |
9068a4c6 | 2148 | |
b2bbb20b | 2149 | if (dev->mach->gpio_vbus) { |
9068a4c6 MS |
2150 | if ((retval = gpio_request(dev->mach->gpio_vbus, |
2151 | "pxa2xx_udc GPIO VBUS"))) { | |
2152 | dev_dbg(&pdev->dev, | |
2153 | "can't get vbus gpio %d, err: %d\n", | |
2154 | dev->mach->gpio_vbus, retval); | |
2155 | return -EBUSY; | |
2156 | } | |
2157 | gpio_direction_input(dev->mach->gpio_vbus); | |
2158 | vbus_irq = gpio_to_irq(dev->mach->gpio_vbus); | |
b2bbb20b DB |
2159 | set_irq_type(vbus_irq, IRQT_BOTHEDGE); |
2160 | } else | |
2161 | vbus_irq = 0; | |
9068a4c6 MS |
2162 | |
2163 | if (dev->mach->gpio_pullup) { | |
2164 | if ((retval = gpio_request(dev->mach->gpio_pullup, | |
2165 | "pca2xx_udc GPIO PULLUP"))) { | |
2166 | dev_dbg(&pdev->dev, | |
2167 | "can't get pullup gpio %d, err: %d\n", | |
2168 | dev->mach->gpio_pullup, retval); | |
2169 | if (dev->mach->gpio_vbus) | |
2170 | gpio_free(dev->mach->gpio_vbus); | |
2171 | return -EBUSY; | |
2172 | } | |
2173 | gpio_direction_output(dev->mach->gpio_pullup, 0); | |
2174 | } | |
1da177e4 LT |
2175 | |
2176 | init_timer(&dev->timer); | |
2177 | dev->timer.function = udc_watchdog; | |
2178 | dev->timer.data = (unsigned long) dev; | |
2179 | ||
2180 | device_initialize(&dev->gadget.dev); | |
3ae5eaec RK |
2181 | dev->gadget.dev.parent = &pdev->dev; |
2182 | dev->gadget.dev.dma_mask = pdev->dev.dma_mask; | |
1da177e4 LT |
2183 | |
2184 | the_controller = dev; | |
3ae5eaec | 2185 | platform_set_drvdata(pdev, dev); |
1da177e4 LT |
2186 | |
2187 | udc_disable(dev); | |
2188 | udc_reinit(dev); | |
2189 | ||
91987693 | 2190 | dev->vbus = is_vbus_present(); |
1da177e4 LT |
2191 | |
2192 | /* irq setup after old hardware state is cleaned up */ | |
34ebcd28 | 2193 | retval = request_irq(irq, pxa2xx_udc_irq, |
d54b5caa | 2194 | IRQF_DISABLED, driver_name, dev); |
1da177e4 | 2195 | if (retval != 0) { |
34ebcd28 DB |
2196 | printk(KERN_ERR "%s: can't get irq %d, err %d\n", |
2197 | driver_name, irq, retval); | |
9068a4c6 MS |
2198 | if (dev->mach->gpio_pullup) |
2199 | gpio_free(dev->mach->gpio_pullup); | |
2200 | if (dev->mach->gpio_vbus) | |
2201 | gpio_free(dev->mach->gpio_vbus); | |
1da177e4 LT |
2202 | return -EBUSY; |
2203 | } | |
2204 | dev->got_irq = 1; | |
2205 | ||
2206 | #ifdef CONFIG_ARCH_LUBBOCK | |
2207 | if (machine_is_lubbock()) { | |
2208 | retval = request_irq(LUBBOCK_USB_DISC_IRQ, | |
2209 | lubbock_vbus_irq, | |
d54b5caa | 2210 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, |
1da177e4 LT |
2211 | driver_name, dev); |
2212 | if (retval != 0) { | |
2213 | printk(KERN_ERR "%s: can't get irq %i, err %d\n", | |
2214 | driver_name, LUBBOCK_USB_DISC_IRQ, retval); | |
2215 | lubbock_fail0: | |
34ebcd28 | 2216 | free_irq(irq, dev); |
9068a4c6 MS |
2217 | if (dev->mach->gpio_pullup) |
2218 | gpio_free(dev->mach->gpio_pullup); | |
2219 | if (dev->mach->gpio_vbus) | |
2220 | gpio_free(dev->mach->gpio_vbus); | |
1da177e4 LT |
2221 | return -EBUSY; |
2222 | } | |
2223 | retval = request_irq(LUBBOCK_USB_IRQ, | |
2224 | lubbock_vbus_irq, | |
d54b5caa | 2225 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, |
1da177e4 LT |
2226 | driver_name, dev); |
2227 | if (retval != 0) { | |
2228 | printk(KERN_ERR "%s: can't get irq %i, err %d\n", | |
2229 | driver_name, LUBBOCK_USB_IRQ, retval); | |
2230 | free_irq(LUBBOCK_USB_DISC_IRQ, dev); | |
2231 | goto lubbock_fail0; | |
2232 | } | |
b2bbb20b | 2233 | } else |
1da177e4 | 2234 | #endif |
b2bbb20b DB |
2235 | if (vbus_irq) { |
2236 | retval = request_irq(vbus_irq, udc_vbus_irq, | |
38515e90 | 2237 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, |
b2bbb20b DB |
2238 | driver_name, dev); |
2239 | if (retval != 0) { | |
2240 | printk(KERN_ERR "%s: can't get irq %i, err %d\n", | |
2241 | driver_name, vbus_irq, retval); | |
08a78cbb | 2242 | free_irq(irq, dev); |
9068a4c6 MS |
2243 | if (dev->mach->gpio_pullup) |
2244 | gpio_free(dev->mach->gpio_pullup); | |
2245 | if (dev->mach->gpio_vbus) | |
2246 | gpio_free(dev->mach->gpio_vbus); | |
b2bbb20b DB |
2247 | return -EBUSY; |
2248 | } | |
2249 | } | |
1da177e4 LT |
2250 | create_proc_files(); |
2251 | ||
2252 | return 0; | |
2253 | } | |
91987693 | 2254 | |
3ae5eaec | 2255 | static void pxa2xx_udc_shutdown(struct platform_device *_dev) |
91987693 DB |
2256 | { |
2257 | pullup_off(); | |
2258 | } | |
2259 | ||
3ae5eaec | 2260 | static int __exit pxa2xx_udc_remove(struct platform_device *pdev) |
1da177e4 | 2261 | { |
3ae5eaec | 2262 | struct pxa2xx_udc *dev = platform_get_drvdata(pdev); |
1da177e4 | 2263 | |
6bea476c DB |
2264 | if (dev->driver) |
2265 | return -EBUSY; | |
2266 | ||
1da177e4 LT |
2267 | udc_disable(dev); |
2268 | remove_proc_files(); | |
1da177e4 LT |
2269 | |
2270 | if (dev->got_irq) { | |
34ebcd28 | 2271 | free_irq(platform_get_irq(pdev, 0), dev); |
1da177e4 LT |
2272 | dev->got_irq = 0; |
2273 | } | |
44df45a0 | 2274 | #ifdef CONFIG_ARCH_LUBBOCK |
1da177e4 LT |
2275 | if (machine_is_lubbock()) { |
2276 | free_irq(LUBBOCK_USB_DISC_IRQ, dev); | |
2277 | free_irq(LUBBOCK_USB_IRQ, dev); | |
2278 | } | |
44df45a0 | 2279 | #endif |
9068a4c6 MS |
2280 | if (dev->mach->gpio_vbus) { |
2281 | free_irq(gpio_to_irq(dev->mach->gpio_vbus), dev); | |
2282 | gpio_free(dev->mach->gpio_vbus); | |
2283 | } | |
2284 | if (dev->mach->gpio_pullup) | |
2285 | gpio_free(dev->mach->gpio_pullup); | |
2286 | ||
3ae5eaec | 2287 | platform_set_drvdata(pdev, NULL); |
1da177e4 LT |
2288 | the_controller = NULL; |
2289 | return 0; | |
2290 | } | |
2291 | ||
2292 | /*-------------------------------------------------------------------------*/ | |
2293 | ||
2294 | #ifdef CONFIG_PM | |
2295 | ||
2296 | /* USB suspend (controlled by the host) and system suspend (controlled | |
2297 | * by the PXA) don't necessarily work well together. If USB is active, | |
2298 | * the 48 MHz clock is required; so the system can't enter 33 MHz idle | |
2299 | * mode, or any deeper PM saving state. | |
2300 | * | |
2301 | * For now, we punt and forcibly disconnect from the USB host when PXA | |
2302 | * enters any suspend state. While we're disconnected, we always disable | |
34ebcd28 | 2303 | * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states. |
1da177e4 LT |
2304 | * Boards without software pullup control shouldn't use those states. |
2305 | * VBUS IRQs should probably be ignored so that the PXA device just acts | |
2306 | * "dead" to USB hosts until system resume. | |
2307 | */ | |
3ae5eaec | 2308 | static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 2309 | { |
3ae5eaec | 2310 | struct pxa2xx_udc *udc = platform_get_drvdata(dev); |
1da177e4 | 2311 | |
8c273033 | 2312 | if (!udc->mach->gpio_pullup && !udc->mach->udc_command) |
9480e307 RK |
2313 | WARN("USB host won't detect disconnect!\n"); |
2314 | pullup(udc, 0); | |
2315 | ||
1da177e4 LT |
2316 | return 0; |
2317 | } | |
2318 | ||
3ae5eaec | 2319 | static int pxa2xx_udc_resume(struct platform_device *dev) |
1da177e4 | 2320 | { |
3ae5eaec | 2321 | struct pxa2xx_udc *udc = platform_get_drvdata(dev); |
1da177e4 | 2322 | |
9480e307 RK |
2323 | pullup(udc, 1); |
2324 | ||
1da177e4 LT |
2325 | return 0; |
2326 | } | |
2327 | ||
2328 | #else | |
2329 | #define pxa2xx_udc_suspend NULL | |
2330 | #define pxa2xx_udc_resume NULL | |
2331 | #endif | |
2332 | ||
2333 | /*-------------------------------------------------------------------------*/ | |
2334 | ||
3ae5eaec | 2335 | static struct platform_driver udc_driver = { |
91987693 | 2336 | .shutdown = pxa2xx_udc_shutdown, |
1da177e4 LT |
2337 | .remove = __exit_p(pxa2xx_udc_remove), |
2338 | .suspend = pxa2xx_udc_suspend, | |
2339 | .resume = pxa2xx_udc_resume, | |
3ae5eaec RK |
2340 | .driver = { |
2341 | .owner = THIS_MODULE, | |
2342 | .name = "pxa2xx-udc", | |
2343 | }, | |
1da177e4 LT |
2344 | }; |
2345 | ||
2346 | static int __init udc_init(void) | |
2347 | { | |
2348 | printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION); | |
34ebcd28 | 2349 | return platform_driver_probe(&udc_driver, pxa2xx_udc_probe); |
1da177e4 LT |
2350 | } |
2351 | module_init(udc_init); | |
2352 | ||
2353 | static void __exit udc_exit(void) | |
2354 | { | |
3ae5eaec | 2355 | platform_driver_unregister(&udc_driver); |
1da177e4 LT |
2356 | } |
2357 | module_exit(udc_exit); | |
2358 | ||
2359 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2360 | MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); | |
2361 | MODULE_LICENSE("GPL"); | |
2362 |