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bae4bd84 DB |
1 | /* |
2 | * at91_udc -- driver for at91-series USB peripheral controller | |
3 | * | |
4 | * Copyright (C) 2004 by Thomas Rathbone | |
5 | * Copyright (C) 2005 by HP Labs | |
6 | * Copyright (C) 2005 by David Brownell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
bae4bd84 DB |
12 | */ |
13 | ||
f3db6e82 | 14 | #undef VERBOSE_DEBUG |
bae4bd84 DB |
15 | #undef PACKET_TRACE |
16 | ||
bae4bd84 DB |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/ioport.h> | |
bae4bd84 | 22 | #include <linux/slab.h> |
bae4bd84 | 23 | #include <linux/errno.h> |
bae4bd84 DB |
24 | #include <linux/list.h> |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/proc_fs.h> | |
eed39366 | 27 | #include <linux/prefetch.h> |
bae4bd84 | 28 | #include <linux/clk.h> |
5f848137 | 29 | #include <linux/usb/ch9.h> |
9454a57a | 30 | #include <linux/usb/gadget.h> |
d1494a34 JCPV |
31 | #include <linux/of.h> |
32 | #include <linux/of_gpio.h> | |
bcd2360c | 33 | #include <linux/platform_data/atmel.h> |
f0bceab4 BB |
34 | #include <linux/regmap.h> |
35 | #include <linux/mfd/syscon.h> | |
36 | #include <linux/mfd/syscon/atmel-matrix.h> | |
bae4bd84 DB |
37 | |
38 | #include "at91_udc.h" | |
39 | ||
40 | ||
41 | /* | |
42 | * This controller is simple and PIO-only. It's used in many AT91-series | |
8b2e7668 DB |
43 | * full speed USB controllers, including the at91rm9200 (arm920T, with MMU), |
44 | * at91sam926x (arm926ejs, with MMU), and several no-mmu versions. | |
bae4bd84 | 45 | * |
d7558148 | 46 | * This driver expects the board has been wired with two GPIOs supporting |
bae4bd84 | 47 | * a VBUS sensing IRQ, and a D+ pullup. (They may be omitted, but the |
8b2e7668 DB |
48 | * testing hasn't covered such cases.) |
49 | * | |
50 | * The pullup is most important (so it's integrated on sam926x parts). It | |
bae4bd84 | 51 | * provides software control over whether the host enumerates the device. |
8b2e7668 | 52 | * |
bae4bd84 DB |
53 | * The VBUS sensing helps during enumeration, and allows both USB clocks |
54 | * (and the transceiver) to stay gated off until they're necessary, saving | |
8b2e7668 DB |
55 | * power. During USB suspend, the 48 MHz clock is gated off in hardware; |
56 | * it may also be gated off by software during some Linux sleep states. | |
bae4bd84 DB |
57 | */ |
58 | ||
8b2e7668 | 59 | #define DRIVER_VERSION "3 May 2006" |
bae4bd84 DB |
60 | |
61 | static const char driver_name [] = "at91_udc"; | |
b9ed96d7 RB |
62 | |
63 | static const struct { | |
64 | const char *name; | |
65 | const struct usb_ep_caps caps; | |
66 | } ep_info[] = { | |
67 | #define EP_INFO(_name, _caps) \ | |
68 | { \ | |
69 | .name = _name, \ | |
70 | .caps = _caps, \ | |
71 | } | |
72 | ||
73 | EP_INFO("ep0", | |
74 | USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)), | |
75 | EP_INFO("ep1", | |
76 | USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)), | |
77 | EP_INFO("ep2", | |
78 | USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)), | |
79 | EP_INFO("ep3-int", | |
80 | USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_ALL)), | |
81 | EP_INFO("ep4", | |
82 | USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)), | |
83 | EP_INFO("ep5", | |
84 | USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)), | |
85 | ||
86 | #undef EP_INFO | |
a5514d14 | 87 | }; |
b9ed96d7 RB |
88 | |
89 | #define ep0name ep_info[0].name | |
bae4bd84 | 90 | |
4037242c | 91 | #define VBUS_POLL_TIMEOUT msecs_to_jiffies(1000) |
bae4bd84 | 92 | |
4f4c5e36 HH |
93 | #define at91_udp_read(udc, reg) \ |
94 | __raw_readl((udc)->udp_baseaddr + (reg)) | |
95 | #define at91_udp_write(udc, reg, val) \ | |
96 | __raw_writel((val), (udc)->udp_baseaddr + (reg)) | |
bae4bd84 DB |
97 | |
98 | /*-------------------------------------------------------------------------*/ | |
99 | ||
100 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
101 | ||
102 | #include <linux/seq_file.h> | |
103 | ||
104 | static const char debug_filename[] = "driver/udc"; | |
105 | ||
106 | #define FOURBITS "%s%s%s%s" | |
107 | #define EIGHTBITS FOURBITS FOURBITS | |
108 | ||
109 | static void proc_ep_show(struct seq_file *s, struct at91_ep *ep) | |
110 | { | |
111 | static char *types[] = { | |
112 | "control", "out-iso", "out-bulk", "out-int", | |
113 | "BOGUS", "in-iso", "in-bulk", "in-int"}; | |
114 | ||
115 | u32 csr; | |
116 | struct at91_request *req; | |
117 | unsigned long flags; | |
4f4c5e36 | 118 | struct at91_udc *udc = ep->udc; |
bae4bd84 | 119 | |
4f4c5e36 | 120 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
121 | |
122 | csr = __raw_readl(ep->creg); | |
123 | ||
124 | /* NOTE: not collecting per-endpoint irq statistics... */ | |
125 | ||
126 | seq_printf(s, "\n"); | |
127 | seq_printf(s, "%s, maxpacket %d %s%s %s%s\n", | |
128 | ep->ep.name, ep->ep.maxpacket, | |
129 | ep->is_in ? "in" : "out", | |
130 | ep->is_iso ? " iso" : "", | |
131 | ep->is_pingpong | |
132 | ? (ep->fifo_bank ? "pong" : "ping") | |
133 | : "", | |
134 | ep->stopped ? " stopped" : ""); | |
135 | seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", | |
136 | csr, | |
137 | (csr & 0x07ff0000) >> 16, | |
138 | (csr & (1 << 15)) ? "enabled" : "disabled", | |
139 | (csr & (1 << 11)) ? "DATA1" : "DATA0", | |
140 | types[(csr & 0x700) >> 8], | |
141 | ||
142 | /* iff type is control then print current direction */ | |
143 | (!(csr & 0x700)) | |
144 | ? ((csr & (1 << 7)) ? " IN" : " OUT") | |
145 | : "", | |
146 | (csr & (1 << 6)) ? " rxdatabk1" : "", | |
147 | (csr & (1 << 5)) ? " forcestall" : "", | |
148 | (csr & (1 << 4)) ? " txpktrdy" : "", | |
149 | ||
150 | (csr & (1 << 3)) ? " stallsent" : "", | |
151 | (csr & (1 << 2)) ? " rxsetup" : "", | |
152 | (csr & (1 << 1)) ? " rxdatabk0" : "", | |
153 | (csr & (1 << 0)) ? " txcomp" : ""); | |
154 | if (list_empty (&ep->queue)) | |
155 | seq_printf(s, "\t(queue empty)\n"); | |
156 | ||
157 | else list_for_each_entry (req, &ep->queue, queue) { | |
158 | unsigned length = req->req.actual; | |
159 | ||
160 | seq_printf(s, "\treq %p len %d/%d buf %p\n", | |
161 | &req->req, length, | |
162 | req->req.length, req->req.buf); | |
163 | } | |
4f4c5e36 | 164 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
165 | } |
166 | ||
167 | static void proc_irq_show(struct seq_file *s, const char *label, u32 mask) | |
168 | { | |
169 | int i; | |
170 | ||
171 | seq_printf(s, "%s %04x:%s%s" FOURBITS, label, mask, | |
172 | (mask & (1 << 13)) ? " wakeup" : "", | |
173 | (mask & (1 << 12)) ? " endbusres" : "", | |
174 | ||
175 | (mask & (1 << 11)) ? " sofint" : "", | |
176 | (mask & (1 << 10)) ? " extrsm" : "", | |
177 | (mask & (1 << 9)) ? " rxrsm" : "", | |
178 | (mask & (1 << 8)) ? " rxsusp" : ""); | |
179 | for (i = 0; i < 8; i++) { | |
180 | if (mask & (1 << i)) | |
181 | seq_printf(s, " ep%d", i); | |
182 | } | |
183 | seq_printf(s, "\n"); | |
184 | } | |
185 | ||
186 | static int proc_udc_show(struct seq_file *s, void *unused) | |
187 | { | |
188 | struct at91_udc *udc = s->private; | |
189 | struct at91_ep *ep; | |
190 | u32 tmp; | |
191 | ||
192 | seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); | |
193 | ||
194 | seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", | |
195 | udc->vbus ? "present" : "off", | |
196 | udc->enabled | |
197 | ? (udc->vbus ? "active" : "enabled") | |
198 | : "disabled", | |
7301971f | 199 | udc->gadget.is_selfpowered ? "self" : "VBUS", |
bae4bd84 DB |
200 | udc->suspended ? ", suspended" : "", |
201 | udc->driver ? udc->driver->driver.name : "(none)"); | |
202 | ||
203 | /* don't access registers when interface isn't clocked */ | |
204 | if (!udc->clocked) { | |
205 | seq_printf(s, "(not clocked)\n"); | |
206 | return 0; | |
207 | } | |
208 | ||
ffd3326b | 209 | tmp = at91_udp_read(udc, AT91_UDP_FRM_NUM); |
bae4bd84 DB |
210 | seq_printf(s, "frame %05x:%s%s frame=%d\n", tmp, |
211 | (tmp & AT91_UDP_FRM_OK) ? " ok" : "", | |
212 | (tmp & AT91_UDP_FRM_ERR) ? " err" : "", | |
213 | (tmp & AT91_UDP_NUM)); | |
214 | ||
ffd3326b | 215 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
216 | seq_printf(s, "glbstate %02x:%s" FOURBITS "\n", tmp, |
217 | (tmp & AT91_UDP_RMWUPE) ? " rmwupe" : "", | |
218 | (tmp & AT91_UDP_RSMINPR) ? " rsminpr" : "", | |
219 | (tmp & AT91_UDP_ESR) ? " esr" : "", | |
220 | (tmp & AT91_UDP_CONFG) ? " confg" : "", | |
221 | (tmp & AT91_UDP_FADDEN) ? " fadden" : ""); | |
222 | ||
ffd3326b | 223 | tmp = at91_udp_read(udc, AT91_UDP_FADDR); |
bae4bd84 DB |
224 | seq_printf(s, "faddr %03x:%s fadd=%d\n", tmp, |
225 | (tmp & AT91_UDP_FEN) ? " fen" : "", | |
226 | (tmp & AT91_UDP_FADD)); | |
227 | ||
ffd3326b AV |
228 | proc_irq_show(s, "imr ", at91_udp_read(udc, AT91_UDP_IMR)); |
229 | proc_irq_show(s, "isr ", at91_udp_read(udc, AT91_UDP_ISR)); | |
bae4bd84 DB |
230 | |
231 | if (udc->enabled && udc->vbus) { | |
232 | proc_ep_show(s, &udc->ep[0]); | |
233 | list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) { | |
5a6506f0 | 234 | if (ep->ep.desc) |
bae4bd84 DB |
235 | proc_ep_show(s, ep); |
236 | } | |
237 | } | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static int proc_udc_open(struct inode *inode, struct file *file) | |
242 | { | |
d9dda78b | 243 | return single_open(file, proc_udc_show, PDE_DATA(inode)); |
bae4bd84 DB |
244 | } |
245 | ||
066202dd | 246 | static const struct file_operations proc_ops = { |
cdefa185 | 247 | .owner = THIS_MODULE, |
bae4bd84 DB |
248 | .open = proc_udc_open, |
249 | .read = seq_read, | |
250 | .llseek = seq_lseek, | |
251 | .release = single_release, | |
252 | }; | |
253 | ||
254 | static void create_debug_file(struct at91_udc *udc) | |
255 | { | |
cdefa185 | 256 | udc->pde = proc_create_data(debug_filename, 0, NULL, &proc_ops, udc); |
bae4bd84 DB |
257 | } |
258 | ||
259 | static void remove_debug_file(struct at91_udc *udc) | |
260 | { | |
261 | if (udc->pde) | |
262 | remove_proc_entry(debug_filename, NULL); | |
263 | } | |
264 | ||
265 | #else | |
266 | ||
267 | static inline void create_debug_file(struct at91_udc *udc) {} | |
268 | static inline void remove_debug_file(struct at91_udc *udc) {} | |
269 | ||
270 | #endif | |
271 | ||
272 | ||
273 | /*-------------------------------------------------------------------------*/ | |
274 | ||
275 | static void done(struct at91_ep *ep, struct at91_request *req, int status) | |
276 | { | |
277 | unsigned stopped = ep->stopped; | |
ffd3326b | 278 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
279 | |
280 | list_del_init(&req->queue); | |
281 | if (req->req.status == -EINPROGRESS) | |
282 | req->req.status = status; | |
283 | else | |
284 | status = req->req.status; | |
285 | if (status && status != -ESHUTDOWN) | |
286 | VDBG("%s done %p, status %d\n", ep->ep.name, req, status); | |
287 | ||
288 | ep->stopped = 1; | |
4f4c5e36 | 289 | spin_unlock(&udc->lock); |
304f7e5e | 290 | usb_gadget_giveback_request(&ep->ep, &req->req); |
4f4c5e36 | 291 | spin_lock(&udc->lock); |
bae4bd84 DB |
292 | ep->stopped = stopped; |
293 | ||
294 | /* ep0 is always ready; other endpoints need a non-empty queue */ | |
295 | if (list_empty(&ep->queue) && ep->int_mask != (1 << 0)) | |
ffd3326b | 296 | at91_udp_write(udc, AT91_UDP_IDR, ep->int_mask); |
bae4bd84 DB |
297 | } |
298 | ||
299 | /*-------------------------------------------------------------------------*/ | |
300 | ||
301 | /* bits indicating OUT fifo has data ready */ | |
302 | #define RX_DATA_READY (AT91_UDP_RX_DATA_BK0 | AT91_UDP_RX_DATA_BK1) | |
303 | ||
304 | /* | |
305 | * Endpoint FIFO CSR bits have a mix of bits, making it unsafe to just write | |
306 | * back most of the value you just read (because of side effects, including | |
307 | * bits that may change after reading and before writing). | |
308 | * | |
309 | * Except when changing a specific bit, always write values which: | |
310 | * - clear SET_FX bits (setting them could change something) | |
311 | * - set CLR_FX bits (clearing them could change something) | |
312 | * | |
313 | * There are also state bits like FORCESTALL, EPEDS, DIR, and EPTYPE | |
314 | * that shouldn't normally be changed. | |
8b2e7668 DB |
315 | * |
316 | * NOTE at91sam9260 docs mention synch between UDPCK and MCK clock domains, | |
317 | * implying a need to wait for one write to complete (test relevant bits) | |
318 | * before starting the next write. This shouldn't be an issue given how | |
319 | * infrequently we write, except maybe for write-then-read idioms. | |
bae4bd84 DB |
320 | */ |
321 | #define SET_FX (AT91_UDP_TXPKTRDY) | |
8b2e7668 DB |
322 | #define CLR_FX (RX_DATA_READY | AT91_UDP_RXSETUP \ |
323 | | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP) | |
bae4bd84 DB |
324 | |
325 | /* pull OUT packet data from the endpoint's fifo */ | |
326 | static int read_fifo (struct at91_ep *ep, struct at91_request *req) | |
327 | { | |
328 | u32 __iomem *creg = ep->creg; | |
329 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
330 | u32 csr; | |
331 | u8 *buf; | |
332 | unsigned int count, bufferspace, is_done; | |
333 | ||
334 | buf = req->req.buf + req->req.actual; | |
335 | bufferspace = req->req.length - req->req.actual; | |
336 | ||
337 | /* | |
338 | * there might be nothing to read if ep_queue() calls us, | |
339 | * or if we already emptied both pingpong buffers | |
340 | */ | |
341 | rescan: | |
342 | csr = __raw_readl(creg); | |
343 | if ((csr & RX_DATA_READY) == 0) | |
344 | return 0; | |
345 | ||
346 | count = (csr & AT91_UDP_RXBYTECNT) >> 16; | |
347 | if (count > ep->ep.maxpacket) | |
348 | count = ep->ep.maxpacket; | |
349 | if (count > bufferspace) { | |
350 | DBG("%s buffer overflow\n", ep->ep.name); | |
351 | req->req.status = -EOVERFLOW; | |
352 | count = bufferspace; | |
353 | } | |
354 | __raw_readsb(dreg, buf, count); | |
355 | ||
356 | /* release and swap pingpong mem bank */ | |
357 | csr |= CLR_FX; | |
358 | if (ep->is_pingpong) { | |
359 | if (ep->fifo_bank == 0) { | |
360 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
361 | ep->fifo_bank = 1; | |
362 | } else { | |
363 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1); | |
364 | ep->fifo_bank = 0; | |
365 | } | |
366 | } else | |
367 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
368 | __raw_writel(csr, creg); | |
369 | ||
370 | req->req.actual += count; | |
371 | is_done = (count < ep->ep.maxpacket); | |
372 | if (count == bufferspace) | |
373 | is_done = 1; | |
374 | ||
375 | PACKET("%s %p out/%d%s\n", ep->ep.name, &req->req, count, | |
376 | is_done ? " (done)" : ""); | |
377 | ||
378 | /* | |
379 | * avoid extra trips through IRQ logic for packets already in | |
380 | * the fifo ... maybe preventing an extra (expensive) OUT-NAK | |
381 | */ | |
382 | if (is_done) | |
383 | done(ep, req, 0); | |
384 | else if (ep->is_pingpong) { | |
76225374 HH |
385 | /* |
386 | * One dummy read to delay the code because of a HW glitch: | |
387 | * CSR returns bad RXCOUNT when read too soon after updating | |
388 | * RX_DATA_BK flags. | |
389 | */ | |
390 | csr = __raw_readl(creg); | |
391 | ||
bae4bd84 DB |
392 | bufferspace -= count; |
393 | buf += count; | |
394 | goto rescan; | |
395 | } | |
396 | ||
397 | return is_done; | |
398 | } | |
399 | ||
400 | /* load fifo for an IN packet */ | |
401 | static int write_fifo(struct at91_ep *ep, struct at91_request *req) | |
402 | { | |
403 | u32 __iomem *creg = ep->creg; | |
404 | u32 csr = __raw_readl(creg); | |
405 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
406 | unsigned total, count, is_last; | |
3cf27234 | 407 | u8 *buf; |
bae4bd84 DB |
408 | |
409 | /* | |
410 | * TODO: allow for writing two packets to the fifo ... that'll | |
411 | * reduce the amount of IN-NAKing, but probably won't affect | |
412 | * throughput much. (Unlike preventing OUT-NAKing!) | |
413 | */ | |
414 | ||
415 | /* | |
416 | * If ep_queue() calls us, the queue is empty and possibly in | |
417 | * odd states like TXCOMP not yet cleared (we do it, saving at | |
418 | * least one IRQ) or the fifo not yet being free. Those aren't | |
419 | * issues normally (IRQ handler fast path). | |
420 | */ | |
421 | if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) { | |
422 | if (csr & AT91_UDP_TXCOMP) { | |
423 | csr |= CLR_FX; | |
424 | csr &= ~(SET_FX | AT91_UDP_TXCOMP); | |
425 | __raw_writel(csr, creg); | |
426 | csr = __raw_readl(creg); | |
427 | } | |
428 | if (csr & AT91_UDP_TXPKTRDY) | |
429 | return 0; | |
430 | } | |
431 | ||
3cf27234 DB |
432 | buf = req->req.buf + req->req.actual; |
433 | prefetch(buf); | |
bae4bd84 DB |
434 | total = req->req.length - req->req.actual; |
435 | if (ep->ep.maxpacket < total) { | |
436 | count = ep->ep.maxpacket; | |
437 | is_last = 0; | |
438 | } else { | |
439 | count = total; | |
440 | is_last = (count < ep->ep.maxpacket) || !req->req.zero; | |
441 | } | |
442 | ||
443 | /* | |
444 | * Write the packet, maybe it's a ZLP. | |
445 | * | |
446 | * NOTE: incrementing req->actual before we receive the ACK means | |
447 | * gadget driver IN bytecounts can be wrong in fault cases. That's | |
448 | * fixable with PIO drivers like this one (save "count" here, and | |
449 | * do the increment later on TX irq), but not for most DMA hardware. | |
450 | * | |
451 | * So all gadget drivers must accept that potential error. Some | |
452 | * hardware supports precise fifo status reporting, letting them | |
453 | * recover when the actual bytecount matters (e.g. for USB Test | |
454 | * and Measurement Class devices). | |
455 | */ | |
3cf27234 | 456 | __raw_writesb(dreg, buf, count); |
bae4bd84 DB |
457 | csr &= ~SET_FX; |
458 | csr |= CLR_FX | AT91_UDP_TXPKTRDY; | |
459 | __raw_writel(csr, creg); | |
460 | req->req.actual += count; | |
461 | ||
462 | PACKET("%s %p in/%d%s\n", ep->ep.name, &req->req, count, | |
463 | is_last ? " (done)" : ""); | |
464 | if (is_last) | |
465 | done(ep, req, 0); | |
466 | return is_last; | |
467 | } | |
468 | ||
469 | static void nuke(struct at91_ep *ep, int status) | |
470 | { | |
471 | struct at91_request *req; | |
472 | ||
1a8060d9 | 473 | /* terminate any request in the queue */ |
bae4bd84 DB |
474 | ep->stopped = 1; |
475 | if (list_empty(&ep->queue)) | |
476 | return; | |
477 | ||
441b62c1 | 478 | VDBG("%s %s\n", __func__, ep->ep.name); |
bae4bd84 DB |
479 | while (!list_empty(&ep->queue)) { |
480 | req = list_entry(ep->queue.next, struct at91_request, queue); | |
481 | done(ep, req, status); | |
482 | } | |
483 | } | |
484 | ||
485 | /*-------------------------------------------------------------------------*/ | |
486 | ||
8b2e7668 DB |
487 | static int at91_ep_enable(struct usb_ep *_ep, |
488 | const struct usb_endpoint_descriptor *desc) | |
bae4bd84 DB |
489 | { |
490 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
162ca3ca | 491 | struct at91_udc *udc; |
bae4bd84 DB |
492 | u16 maxpacket; |
493 | u32 tmp; | |
494 | unsigned long flags; | |
495 | ||
496 | if (!_ep || !ep | |
f3bb8e63 | 497 | || !desc || _ep->name == ep0name |
bae4bd84 | 498 | || desc->bDescriptorType != USB_DT_ENDPOINT |
29cc8897 | 499 | || (maxpacket = usb_endpoint_maxp(desc)) == 0 |
bae4bd84 DB |
500 | || maxpacket > ep->maxpacket) { |
501 | DBG("bad ep or descriptor\n"); | |
502 | return -EINVAL; | |
503 | } | |
504 | ||
162ca3ca | 505 | udc = ep->udc; |
4f4c5e36 | 506 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { |
bae4bd84 DB |
507 | DBG("bogus device state\n"); |
508 | return -ESHUTDOWN; | |
509 | } | |
510 | ||
81c8d8d2 | 511 | tmp = usb_endpoint_type(desc); |
bae4bd84 DB |
512 | switch (tmp) { |
513 | case USB_ENDPOINT_XFER_CONTROL: | |
514 | DBG("only one control endpoint\n"); | |
515 | return -EINVAL; | |
516 | case USB_ENDPOINT_XFER_INT: | |
517 | if (maxpacket > 64) | |
518 | goto bogus_max; | |
519 | break; | |
520 | case USB_ENDPOINT_XFER_BULK: | |
521 | switch (maxpacket) { | |
522 | case 8: | |
523 | case 16: | |
524 | case 32: | |
525 | case 64: | |
526 | goto ok; | |
527 | } | |
528 | bogus_max: | |
529 | DBG("bogus maxpacket %d\n", maxpacket); | |
530 | return -EINVAL; | |
531 | case USB_ENDPOINT_XFER_ISOC: | |
532 | if (!ep->is_pingpong) { | |
533 | DBG("iso requires double buffering\n"); | |
534 | return -EINVAL; | |
535 | } | |
536 | break; | |
537 | } | |
538 | ||
539 | ok: | |
4f4c5e36 | 540 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
541 | |
542 | /* initialize endpoint to match this descriptor */ | |
81c8d8d2 | 543 | ep->is_in = usb_endpoint_dir_in(desc); |
bae4bd84 DB |
544 | ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC); |
545 | ep->stopped = 0; | |
546 | if (ep->is_in) | |
547 | tmp |= 0x04; | |
548 | tmp <<= 8; | |
549 | tmp |= AT91_UDP_EPEDS; | |
550 | __raw_writel(tmp, ep->creg); | |
551 | ||
bae4bd84 DB |
552 | ep->ep.maxpacket = maxpacket; |
553 | ||
554 | /* | |
555 | * reset/init endpoint fifo. NOTE: leaves fifo_bank alone, | |
556 | * since endpoint resets don't reset hw pingpong state. | |
557 | */ | |
4f4c5e36 HH |
558 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
559 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 | 560 | |
4f4c5e36 | 561 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
562 | return 0; |
563 | } | |
564 | ||
565 | static int at91_ep_disable (struct usb_ep * _ep) | |
566 | { | |
567 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
ffd3326b | 568 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
569 | unsigned long flags; |
570 | ||
571 | if (ep == &ep->udc->ep[0]) | |
572 | return -EINVAL; | |
573 | ||
4f4c5e36 | 574 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
575 | |
576 | nuke(ep, -ESHUTDOWN); | |
577 | ||
578 | /* restore the endpoint's pristine config */ | |
f9c56cdd | 579 | ep->ep.desc = NULL; |
bae4bd84 DB |
580 | ep->ep.maxpacket = ep->maxpacket; |
581 | ||
582 | /* reset fifos and endpoint */ | |
583 | if (ep->udc->clocked) { | |
ffd3326b AV |
584 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
585 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
586 | __raw_writel(0, ep->creg); |
587 | } | |
588 | ||
4f4c5e36 | 589 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
590 | return 0; |
591 | } | |
592 | ||
593 | /* | |
594 | * this is a PIO-only driver, so there's nothing | |
595 | * interesting for request or buffer allocation. | |
596 | */ | |
597 | ||
8b2e7668 | 598 | static struct usb_request * |
f3db6e82 | 599 | at91_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) |
bae4bd84 DB |
600 | { |
601 | struct at91_request *req; | |
602 | ||
cd861280 | 603 | req = kzalloc(sizeof (struct at91_request), gfp_flags); |
bae4bd84 DB |
604 | if (!req) |
605 | return NULL; | |
606 | ||
607 | INIT_LIST_HEAD(&req->queue); | |
608 | return &req->req; | |
609 | } | |
610 | ||
611 | static void at91_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
612 | { | |
613 | struct at91_request *req; | |
614 | ||
615 | req = container_of(_req, struct at91_request, req); | |
616 | BUG_ON(!list_empty(&req->queue)); | |
617 | kfree(req); | |
618 | } | |
619 | ||
bae4bd84 DB |
620 | static int at91_ep_queue(struct usb_ep *_ep, |
621 | struct usb_request *_req, gfp_t gfp_flags) | |
622 | { | |
623 | struct at91_request *req; | |
624 | struct at91_ep *ep; | |
4f4c5e36 | 625 | struct at91_udc *udc; |
bae4bd84 DB |
626 | int status; |
627 | unsigned long flags; | |
628 | ||
629 | req = container_of(_req, struct at91_request, req); | |
630 | ep = container_of(_ep, struct at91_ep, ep); | |
631 | ||
632 | if (!_req || !_req->complete | |
633 | || !_req->buf || !list_empty(&req->queue)) { | |
634 | DBG("invalid request\n"); | |
635 | return -EINVAL; | |
636 | } | |
637 | ||
5a6506f0 | 638 | if (!_ep || (!ep->ep.desc && ep->ep.name != ep0name)) { |
bae4bd84 DB |
639 | DBG("invalid ep\n"); |
640 | return -EINVAL; | |
641 | } | |
642 | ||
4f4c5e36 | 643 | udc = ep->udc; |
bae4bd84 | 644 | |
4f4c5e36 | 645 | if (!udc || !udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { |
bae4bd84 DB |
646 | DBG("invalid device\n"); |
647 | return -EINVAL; | |
648 | } | |
649 | ||
650 | _req->status = -EINPROGRESS; | |
651 | _req->actual = 0; | |
652 | ||
4f4c5e36 | 653 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
654 | |
655 | /* try to kickstart any empty and idle queue */ | |
656 | if (list_empty(&ep->queue) && !ep->stopped) { | |
657 | int is_ep0; | |
658 | ||
659 | /* | |
660 | * If this control request has a non-empty DATA stage, this | |
661 | * will start that stage. It works just like a non-control | |
662 | * request (until the status stage starts, maybe early). | |
663 | * | |
664 | * If the data stage is empty, then this starts a successful | |
665 | * IN/STATUS stage. (Unsuccessful ones use set_halt.) | |
666 | */ | |
667 | is_ep0 = (ep->ep.name == ep0name); | |
668 | if (is_ep0) { | |
669 | u32 tmp; | |
670 | ||
4f4c5e36 | 671 | if (!udc->req_pending) { |
bae4bd84 DB |
672 | status = -EINVAL; |
673 | goto done; | |
674 | } | |
675 | ||
676 | /* | |
677 | * defer changing CONFG until after the gadget driver | |
678 | * reconfigures the endpoints. | |
679 | */ | |
4f4c5e36 HH |
680 | if (udc->wait_for_config_ack) { |
681 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); | |
bae4bd84 DB |
682 | tmp ^= AT91_UDP_CONFG; |
683 | VDBG("toggle config\n"); | |
4f4c5e36 | 684 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
685 | } |
686 | if (req->req.length == 0) { | |
687 | ep0_in_status: | |
688 | PACKET("ep0 in/status\n"); | |
689 | status = 0; | |
690 | tmp = __raw_readl(ep->creg); | |
691 | tmp &= ~SET_FX; | |
692 | tmp |= CLR_FX | AT91_UDP_TXPKTRDY; | |
693 | __raw_writel(tmp, ep->creg); | |
4f4c5e36 | 694 | udc->req_pending = 0; |
bae4bd84 DB |
695 | goto done; |
696 | } | |
697 | } | |
698 | ||
699 | if (ep->is_in) | |
700 | status = write_fifo(ep, req); | |
701 | else { | |
702 | status = read_fifo(ep, req); | |
703 | ||
704 | /* IN/STATUS stage is otherwise triggered by irq */ | |
705 | if (status && is_ep0) | |
706 | goto ep0_in_status; | |
707 | } | |
708 | } else | |
709 | status = 0; | |
710 | ||
711 | if (req && !status) { | |
712 | list_add_tail (&req->queue, &ep->queue); | |
4f4c5e36 | 713 | at91_udp_write(udc, AT91_UDP_IER, ep->int_mask); |
bae4bd84 DB |
714 | } |
715 | done: | |
4f4c5e36 | 716 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
717 | return (status < 0) ? status : 0; |
718 | } | |
719 | ||
720 | static int at91_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
721 | { | |
4f4c5e36 | 722 | struct at91_ep *ep; |
bae4bd84 | 723 | struct at91_request *req; |
4f4c5e36 HH |
724 | unsigned long flags; |
725 | struct at91_udc *udc; | |
bae4bd84 DB |
726 | |
727 | ep = container_of(_ep, struct at91_ep, ep); | |
728 | if (!_ep || ep->ep.name == ep0name) | |
729 | return -EINVAL; | |
730 | ||
4f4c5e36 HH |
731 | udc = ep->udc; |
732 | ||
733 | spin_lock_irqsave(&udc->lock, flags); | |
734 | ||
bae4bd84 DB |
735 | /* make sure it's actually queued on this endpoint */ |
736 | list_for_each_entry (req, &ep->queue, queue) { | |
737 | if (&req->req == _req) | |
738 | break; | |
739 | } | |
4f4c5e36 HH |
740 | if (&req->req != _req) { |
741 | spin_unlock_irqrestore(&udc->lock, flags); | |
bae4bd84 | 742 | return -EINVAL; |
4f4c5e36 | 743 | } |
bae4bd84 DB |
744 | |
745 | done(ep, req, -ECONNRESET); | |
4f4c5e36 | 746 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
747 | return 0; |
748 | } | |
749 | ||
750 | static int at91_ep_set_halt(struct usb_ep *_ep, int value) | |
751 | { | |
752 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
ffd3326b | 753 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
754 | u32 __iomem *creg; |
755 | u32 csr; | |
756 | unsigned long flags; | |
757 | int status = 0; | |
758 | ||
759 | if (!_ep || ep->is_iso || !ep->udc->clocked) | |
760 | return -EINVAL; | |
761 | ||
762 | creg = ep->creg; | |
4f4c5e36 | 763 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
764 | |
765 | csr = __raw_readl(creg); | |
766 | ||
767 | /* | |
768 | * fail with still-busy IN endpoints, ensuring correct sequencing | |
769 | * of data tx then stall. note that the fifo rx bytecount isn't | |
770 | * completely accurate as a tx bytecount. | |
771 | */ | |
772 | if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0)) | |
773 | status = -EAGAIN; | |
774 | else { | |
775 | csr |= CLR_FX; | |
776 | csr &= ~SET_FX; | |
777 | if (value) { | |
778 | csr |= AT91_UDP_FORCESTALL; | |
779 | VDBG("halt %s\n", ep->ep.name); | |
780 | } else { | |
ffd3326b AV |
781 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
782 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
783 | csr &= ~AT91_UDP_FORCESTALL; |
784 | } | |
785 | __raw_writel(csr, creg); | |
786 | } | |
787 | ||
4f4c5e36 | 788 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
789 | return status; |
790 | } | |
791 | ||
398acce7 | 792 | static const struct usb_ep_ops at91_ep_ops = { |
bae4bd84 DB |
793 | .enable = at91_ep_enable, |
794 | .disable = at91_ep_disable, | |
795 | .alloc_request = at91_ep_alloc_request, | |
796 | .free_request = at91_ep_free_request, | |
bae4bd84 DB |
797 | .queue = at91_ep_queue, |
798 | .dequeue = at91_ep_dequeue, | |
799 | .set_halt = at91_ep_set_halt, | |
1a8060d9 | 800 | /* there's only imprecise fifo status reporting */ |
bae4bd84 DB |
801 | }; |
802 | ||
803 | /*-------------------------------------------------------------------------*/ | |
804 | ||
805 | static int at91_get_frame(struct usb_gadget *gadget) | |
806 | { | |
ffd3326b AV |
807 | struct at91_udc *udc = to_udc(gadget); |
808 | ||
bae4bd84 DB |
809 | if (!to_udc(gadget)->clocked) |
810 | return -EINVAL; | |
ffd3326b | 811 | return at91_udp_read(udc, AT91_UDP_FRM_NUM) & AT91_UDP_NUM; |
bae4bd84 DB |
812 | } |
813 | ||
814 | static int at91_wakeup(struct usb_gadget *gadget) | |
815 | { | |
816 | struct at91_udc *udc = to_udc(gadget); | |
817 | u32 glbstate; | |
818 | int status = -EINVAL; | |
819 | unsigned long flags; | |
820 | ||
441b62c1 | 821 | DBG("%s\n", __func__ ); |
4f4c5e36 | 822 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
823 | |
824 | if (!udc->clocked || !udc->suspended) | |
825 | goto done; | |
826 | ||
827 | /* NOTE: some "early versions" handle ESR differently ... */ | |
828 | ||
ffd3326b | 829 | glbstate = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
830 | if (!(glbstate & AT91_UDP_ESR)) |
831 | goto done; | |
832 | glbstate |= AT91_UDP_ESR; | |
ffd3326b | 833 | at91_udp_write(udc, AT91_UDP_GLB_STAT, glbstate); |
bae4bd84 DB |
834 | |
835 | done: | |
4f4c5e36 | 836 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
837 | return status; |
838 | } | |
839 | ||
25985edc | 840 | /* reinit == restore initial software state */ |
bae4bd84 DB |
841 | static void udc_reinit(struct at91_udc *udc) |
842 | { | |
843 | u32 i; | |
844 | ||
845 | INIT_LIST_HEAD(&udc->gadget.ep_list); | |
846 | INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); | |
02ded1b0 | 847 | udc->gadget.quirk_stall_not_supp = 1; |
bae4bd84 DB |
848 | |
849 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
850 | struct at91_ep *ep = &udc->ep[i]; | |
851 | ||
852 | if (i != 0) | |
853 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); | |
5a6506f0 | 854 | ep->ep.desc = NULL; |
bae4bd84 DB |
855 | ep->stopped = 0; |
856 | ep->fifo_bank = 0; | |
e117e742 | 857 | usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket); |
ffd3326b | 858 | ep->creg = (void __iomem *) udc->udp_baseaddr + AT91_UDP_CSR(i); |
1a8060d9 | 859 | /* initialize one queue per endpoint */ |
bae4bd84 DB |
860 | INIT_LIST_HEAD(&ep->queue); |
861 | } | |
862 | } | |
863 | ||
236e5064 PC |
864 | static void reset_gadget(struct at91_udc *udc) |
865 | { | |
866 | struct usb_gadget_driver *driver = udc->driver; | |
867 | int i; | |
868 | ||
869 | if (udc->gadget.speed == USB_SPEED_UNKNOWN) | |
870 | driver = NULL; | |
871 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
872 | udc->suspended = 0; | |
873 | ||
874 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
875 | struct at91_ep *ep = &udc->ep[i]; | |
876 | ||
877 | ep->stopped = 1; | |
878 | nuke(ep, -ESHUTDOWN); | |
879 | } | |
880 | if (driver) { | |
881 | spin_unlock(&udc->lock); | |
882 | usb_gadget_udc_reset(&udc->gadget, driver); | |
883 | spin_lock(&udc->lock); | |
884 | } | |
885 | ||
886 | udc_reinit(udc); | |
887 | } | |
888 | ||
bae4bd84 DB |
889 | static void stop_activity(struct at91_udc *udc) |
890 | { | |
891 | struct usb_gadget_driver *driver = udc->driver; | |
892 | int i; | |
893 | ||
894 | if (udc->gadget.speed == USB_SPEED_UNKNOWN) | |
895 | driver = NULL; | |
896 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
8b2e7668 | 897 | udc->suspended = 0; |
bae4bd84 DB |
898 | |
899 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
900 | struct at91_ep *ep = &udc->ep[i]; | |
901 | ep->stopped = 1; | |
902 | nuke(ep, -ESHUTDOWN); | |
903 | } | |
4f4c5e36 HH |
904 | if (driver) { |
905 | spin_unlock(&udc->lock); | |
bae4bd84 | 906 | driver->disconnect(&udc->gadget); |
4f4c5e36 HH |
907 | spin_lock(&udc->lock); |
908 | } | |
bae4bd84 DB |
909 | |
910 | udc_reinit(udc); | |
911 | } | |
912 | ||
913 | static void clk_on(struct at91_udc *udc) | |
914 | { | |
915 | if (udc->clocked) | |
916 | return; | |
917 | udc->clocked = 1; | |
c0aefc75 | 918 | |
b2ba27a5 RW |
919 | clk_enable(udc->iclk); |
920 | clk_enable(udc->fclk); | |
bae4bd84 DB |
921 | } |
922 | ||
923 | static void clk_off(struct at91_udc *udc) | |
924 | { | |
925 | if (!udc->clocked) | |
926 | return; | |
927 | udc->clocked = 0; | |
928 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
b2ba27a5 RW |
929 | clk_disable(udc->fclk); |
930 | clk_disable(udc->iclk); | |
bae4bd84 DB |
931 | } |
932 | ||
933 | /* | |
934 | * activate/deactivate link with host; minimize power usage for | |
935 | * inactive links by cutting clocks and transceiver power. | |
936 | */ | |
937 | static void pullup(struct at91_udc *udc, int is_on) | |
938 | { | |
939 | if (!udc->enabled || !udc->vbus) | |
940 | is_on = 0; | |
941 | DBG("%sactive\n", is_on ? "" : "in"); | |
ffd3326b | 942 | |
bae4bd84 DB |
943 | if (is_on) { |
944 | clk_on(udc); | |
08cbc706 | 945 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXRSM); |
ffd3326b | 946 | at91_udp_write(udc, AT91_UDP_TXVC, 0); |
ffd3326b | 947 | } else { |
bae4bd84 | 948 | stop_activity(udc); |
08cbc706 | 949 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXRSM); |
ffd3326b | 950 | at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); |
bae4bd84 | 951 | clk_off(udc); |
bae4bd84 | 952 | } |
f0bceab4 BB |
953 | |
954 | if (udc->caps && udc->caps->pullup) | |
955 | udc->caps->pullup(udc, is_on); | |
bae4bd84 DB |
956 | } |
957 | ||
958 | /* vbus is here! turn everything on that's ready */ | |
959 | static int at91_vbus_session(struct usb_gadget *gadget, int is_active) | |
960 | { | |
961 | struct at91_udc *udc = to_udc(gadget); | |
962 | unsigned long flags; | |
963 | ||
1a8060d9 | 964 | /* VDBG("vbus %s\n", is_active ? "on" : "off"); */ |
4f4c5e36 | 965 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 966 | udc->vbus = (is_active != 0); |
bfb7fb79 WK |
967 | if (udc->driver) |
968 | pullup(udc, is_active); | |
969 | else | |
970 | pullup(udc, 0); | |
4f4c5e36 | 971 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
972 | return 0; |
973 | } | |
974 | ||
975 | static int at91_pullup(struct usb_gadget *gadget, int is_on) | |
976 | { | |
977 | struct at91_udc *udc = to_udc(gadget); | |
978 | unsigned long flags; | |
979 | ||
4f4c5e36 | 980 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
981 | udc->enabled = is_on = !!is_on; |
982 | pullup(udc, is_on); | |
4f4c5e36 | 983 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
984 | return 0; |
985 | } | |
986 | ||
987 | static int at91_set_selfpowered(struct usb_gadget *gadget, int is_on) | |
988 | { | |
989 | struct at91_udc *udc = to_udc(gadget); | |
990 | unsigned long flags; | |
991 | ||
4f4c5e36 | 992 | spin_lock_irqsave(&udc->lock, flags); |
7301971f | 993 | gadget->is_selfpowered = (is_on != 0); |
4f4c5e36 | 994 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
995 | return 0; |
996 | } | |
997 | ||
f3d8bf34 SAS |
998 | static int at91_start(struct usb_gadget *gadget, |
999 | struct usb_gadget_driver *driver); | |
22835b80 FB |
1000 | static int at91_stop(struct usb_gadget *gadget); |
1001 | ||
bae4bd84 DB |
1002 | static const struct usb_gadget_ops at91_udc_ops = { |
1003 | .get_frame = at91_get_frame, | |
1004 | .wakeup = at91_wakeup, | |
1005 | .set_selfpowered = at91_set_selfpowered, | |
1006 | .vbus_session = at91_vbus_session, | |
1007 | .pullup = at91_pullup, | |
f3d8bf34 SAS |
1008 | .udc_start = at91_start, |
1009 | .udc_stop = at91_stop, | |
bae4bd84 DB |
1010 | |
1011 | /* | |
1012 | * VBUS-powered devices may also also want to support bigger | |
1013 | * power budgets after an appropriate SET_CONFIGURATION. | |
1014 | */ | |
1a8060d9 | 1015 | /* .vbus_power = at91_vbus_power, */ |
bae4bd84 DB |
1016 | }; |
1017 | ||
1018 | /*-------------------------------------------------------------------------*/ | |
1019 | ||
1020 | static int handle_ep(struct at91_ep *ep) | |
1021 | { | |
1022 | struct at91_request *req; | |
1023 | u32 __iomem *creg = ep->creg; | |
1024 | u32 csr = __raw_readl(creg); | |
1025 | ||
1026 | if (!list_empty(&ep->queue)) | |
1027 | req = list_entry(ep->queue.next, | |
1028 | struct at91_request, queue); | |
1029 | else | |
1030 | req = NULL; | |
1031 | ||
1032 | if (ep->is_in) { | |
1033 | if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) { | |
1034 | csr |= CLR_FX; | |
1035 | csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP); | |
1036 | __raw_writel(csr, creg); | |
1037 | } | |
1038 | if (req) | |
1039 | return write_fifo(ep, req); | |
1040 | ||
1041 | } else { | |
1042 | if (csr & AT91_UDP_STALLSENT) { | |
1043 | /* STALLSENT bit == ISOERR */ | |
1044 | if (ep->is_iso && req) | |
1045 | req->req.status = -EILSEQ; | |
1046 | csr |= CLR_FX; | |
1047 | csr &= ~(SET_FX | AT91_UDP_STALLSENT); | |
1048 | __raw_writel(csr, creg); | |
1049 | csr = __raw_readl(creg); | |
1050 | } | |
1051 | if (req && (csr & RX_DATA_READY)) | |
1052 | return read_fifo(ep, req); | |
1053 | } | |
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | union setup { | |
1058 | u8 raw[8]; | |
1059 | struct usb_ctrlrequest r; | |
1060 | }; | |
1061 | ||
1062 | static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) | |
1063 | { | |
1064 | u32 __iomem *creg = ep->creg; | |
1065 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
1066 | unsigned rxcount, i = 0; | |
1067 | u32 tmp; | |
1068 | union setup pkt; | |
1069 | int status = 0; | |
1070 | ||
1071 | /* read and ack SETUP; hard-fail for bogus packets */ | |
1072 | rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16; | |
1073 | if (likely(rxcount == 8)) { | |
1074 | while (rxcount--) | |
1075 | pkt.raw[i++] = __raw_readb(dreg); | |
1076 | if (pkt.r.bRequestType & USB_DIR_IN) { | |
1077 | csr |= AT91_UDP_DIR; | |
1078 | ep->is_in = 1; | |
1079 | } else { | |
1080 | csr &= ~AT91_UDP_DIR; | |
1081 | ep->is_in = 0; | |
1082 | } | |
1083 | } else { | |
1a8060d9 | 1084 | /* REVISIT this happens sometimes under load; why?? */ |
bae4bd84 DB |
1085 | ERR("SETUP len %d, csr %08x\n", rxcount, csr); |
1086 | status = -EINVAL; | |
1087 | } | |
1088 | csr |= CLR_FX; | |
1089 | csr &= ~(SET_FX | AT91_UDP_RXSETUP); | |
1090 | __raw_writel(csr, creg); | |
1091 | udc->wait_for_addr_ack = 0; | |
1092 | udc->wait_for_config_ack = 0; | |
1093 | ep->stopped = 0; | |
1094 | if (unlikely(status != 0)) | |
1095 | goto stall; | |
1096 | ||
1097 | #define w_index le16_to_cpu(pkt.r.wIndex) | |
1098 | #define w_value le16_to_cpu(pkt.r.wValue) | |
1099 | #define w_length le16_to_cpu(pkt.r.wLength) | |
1100 | ||
1101 | VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1102 | pkt.r.bRequestType, pkt.r.bRequest, | |
1103 | w_value, w_index, w_length); | |
1104 | ||
1105 | /* | |
1106 | * A few standard requests get handled here, ones that touch | |
1107 | * hardware ... notably for device and endpoint features. | |
1108 | */ | |
1109 | udc->req_pending = 1; | |
1110 | csr = __raw_readl(creg); | |
1111 | csr |= CLR_FX; | |
1112 | csr &= ~SET_FX; | |
1113 | switch ((pkt.r.bRequestType << 8) | pkt.r.bRequest) { | |
1114 | ||
1115 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1116 | | USB_REQ_SET_ADDRESS: | |
1117 | __raw_writel(csr | AT91_UDP_TXPKTRDY, creg); | |
1118 | udc->addr = w_value; | |
1119 | udc->wait_for_addr_ack = 1; | |
1120 | udc->req_pending = 0; | |
1121 | /* FADDR is set later, when we ack host STATUS */ | |
1122 | return; | |
1123 | ||
1124 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1125 | | USB_REQ_SET_CONFIGURATION: | |
ffd3326b | 1126 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_CONFG; |
bae4bd84 DB |
1127 | if (pkt.r.wValue) |
1128 | udc->wait_for_config_ack = (tmp == 0); | |
1129 | else | |
1130 | udc->wait_for_config_ack = (tmp != 0); | |
1131 | if (udc->wait_for_config_ack) | |
1132 | VDBG("wait for config\n"); | |
1133 | /* CONFG is toggled later, if gadget driver succeeds */ | |
1134 | break; | |
1135 | ||
1136 | /* | |
1137 | * Hosts may set or clear remote wakeup status, and | |
1138 | * devices may report they're VBUS powered. | |
1139 | */ | |
1140 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1141 | | USB_REQ_GET_STATUS: | |
7301971f | 1142 | tmp = (udc->gadget.is_selfpowered << USB_DEVICE_SELF_POWERED); |
ffd3326b | 1143 | if (at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_ESR) |
bae4bd84 DB |
1144 | tmp |= (1 << USB_DEVICE_REMOTE_WAKEUP); |
1145 | PACKET("get device status\n"); | |
1146 | __raw_writeb(tmp, dreg); | |
1147 | __raw_writeb(0, dreg); | |
1148 | goto write_in; | |
1149 | /* then STATUS starts later, automatically */ | |
1150 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1151 | | USB_REQ_SET_FEATURE: | |
1152 | if (w_value != USB_DEVICE_REMOTE_WAKEUP) | |
1153 | goto stall; | |
ffd3326b | 1154 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 | 1155 | tmp |= AT91_UDP_ESR; |
ffd3326b | 1156 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1157 | goto succeed; |
1158 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1159 | | USB_REQ_CLEAR_FEATURE: | |
1160 | if (w_value != USB_DEVICE_REMOTE_WAKEUP) | |
1161 | goto stall; | |
ffd3326b | 1162 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 | 1163 | tmp &= ~AT91_UDP_ESR; |
ffd3326b | 1164 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1165 | goto succeed; |
1166 | ||
1167 | /* | |
1168 | * Interfaces have no feature settings; this is pretty useless. | |
1169 | * we won't even insist the interface exists... | |
1170 | */ | |
1171 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1172 | | USB_REQ_GET_STATUS: | |
1173 | PACKET("get interface status\n"); | |
1174 | __raw_writeb(0, dreg); | |
1175 | __raw_writeb(0, dreg); | |
1176 | goto write_in; | |
1177 | /* then STATUS starts later, automatically */ | |
1178 | case ((USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1179 | | USB_REQ_SET_FEATURE: | |
1180 | case ((USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1181 | | USB_REQ_CLEAR_FEATURE: | |
1182 | goto stall; | |
1183 | ||
1184 | /* | |
1185 | * Hosts may clear bulk/intr endpoint halt after the gadget | |
1186 | * driver sets it (not widely used); or set it (for testing) | |
1187 | */ | |
1188 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1189 | | USB_REQ_GET_STATUS: | |
1190 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1191 | ep = &udc->ep[tmp]; | |
5a6506f0 | 1192 | if (tmp >= NUM_ENDPOINTS || (tmp && !ep->ep.desc)) |
bae4bd84 DB |
1193 | goto stall; |
1194 | ||
1195 | if (tmp) { | |
1196 | if ((w_index & USB_DIR_IN)) { | |
1197 | if (!ep->is_in) | |
1198 | goto stall; | |
1199 | } else if (ep->is_in) | |
1200 | goto stall; | |
1201 | } | |
1202 | PACKET("get %s status\n", ep->ep.name); | |
1203 | if (__raw_readl(ep->creg) & AT91_UDP_FORCESTALL) | |
1204 | tmp = (1 << USB_ENDPOINT_HALT); | |
1205 | else | |
1206 | tmp = 0; | |
1207 | __raw_writeb(tmp, dreg); | |
1208 | __raw_writeb(0, dreg); | |
1209 | goto write_in; | |
1210 | /* then STATUS starts later, automatically */ | |
1211 | case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1212 | | USB_REQ_SET_FEATURE: | |
1213 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1214 | ep = &udc->ep[tmp]; | |
1440e096 | 1215 | if (w_value != USB_ENDPOINT_HALT || tmp >= NUM_ENDPOINTS) |
bae4bd84 | 1216 | goto stall; |
5a6506f0 | 1217 | if (!ep->ep.desc || ep->is_iso) |
bae4bd84 DB |
1218 | goto stall; |
1219 | if ((w_index & USB_DIR_IN)) { | |
1220 | if (!ep->is_in) | |
1221 | goto stall; | |
1222 | } else if (ep->is_in) | |
1223 | goto stall; | |
1224 | ||
1225 | tmp = __raw_readl(ep->creg); | |
1226 | tmp &= ~SET_FX; | |
1227 | tmp |= CLR_FX | AT91_UDP_FORCESTALL; | |
1228 | __raw_writel(tmp, ep->creg); | |
1229 | goto succeed; | |
1230 | case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1231 | | USB_REQ_CLEAR_FEATURE: | |
1232 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1233 | ep = &udc->ep[tmp]; | |
1440e096 | 1234 | if (w_value != USB_ENDPOINT_HALT || tmp >= NUM_ENDPOINTS) |
bae4bd84 DB |
1235 | goto stall; |
1236 | if (tmp == 0) | |
1237 | goto succeed; | |
5a6506f0 | 1238 | if (!ep->ep.desc || ep->is_iso) |
bae4bd84 DB |
1239 | goto stall; |
1240 | if ((w_index & USB_DIR_IN)) { | |
1241 | if (!ep->is_in) | |
1242 | goto stall; | |
1243 | } else if (ep->is_in) | |
1244 | goto stall; | |
1245 | ||
ffd3326b AV |
1246 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
1247 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
1248 | tmp = __raw_readl(ep->creg); |
1249 | tmp |= CLR_FX; | |
1250 | tmp &= ~(SET_FX | AT91_UDP_FORCESTALL); | |
1251 | __raw_writel(tmp, ep->creg); | |
1252 | if (!list_empty(&ep->queue)) | |
1253 | handle_ep(ep); | |
1254 | goto succeed; | |
1255 | } | |
1256 | ||
1257 | #undef w_value | |
1258 | #undef w_index | |
1259 | #undef w_length | |
1260 | ||
1261 | /* pass request up to the gadget driver */ | |
4f4c5e36 HH |
1262 | if (udc->driver) { |
1263 | spin_unlock(&udc->lock); | |
bfb7fb79 | 1264 | status = udc->driver->setup(&udc->gadget, &pkt.r); |
4f4c5e36 HH |
1265 | spin_lock(&udc->lock); |
1266 | } | |
bfb7fb79 WK |
1267 | else |
1268 | status = -ENODEV; | |
bae4bd84 DB |
1269 | if (status < 0) { |
1270 | stall: | |
1271 | VDBG("req %02x.%02x protocol STALL; stat %d\n", | |
1272 | pkt.r.bRequestType, pkt.r.bRequest, status); | |
1273 | csr |= AT91_UDP_FORCESTALL; | |
1274 | __raw_writel(csr, creg); | |
1275 | udc->req_pending = 0; | |
1276 | } | |
1277 | return; | |
1278 | ||
1279 | succeed: | |
1280 | /* immediate successful (IN) STATUS after zero length DATA */ | |
1281 | PACKET("ep0 in/status\n"); | |
1282 | write_in: | |
1283 | csr |= AT91_UDP_TXPKTRDY; | |
1284 | __raw_writel(csr, creg); | |
1285 | udc->req_pending = 0; | |
bae4bd84 DB |
1286 | } |
1287 | ||
1288 | static void handle_ep0(struct at91_udc *udc) | |
1289 | { | |
1290 | struct at91_ep *ep0 = &udc->ep[0]; | |
1291 | u32 __iomem *creg = ep0->creg; | |
1292 | u32 csr = __raw_readl(creg); | |
1293 | struct at91_request *req; | |
1294 | ||
1295 | if (unlikely(csr & AT91_UDP_STALLSENT)) { | |
1296 | nuke(ep0, -EPROTO); | |
1297 | udc->req_pending = 0; | |
1298 | csr |= CLR_FX; | |
1299 | csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL); | |
1300 | __raw_writel(csr, creg); | |
1301 | VDBG("ep0 stalled\n"); | |
1302 | csr = __raw_readl(creg); | |
1303 | } | |
1304 | if (csr & AT91_UDP_RXSETUP) { | |
1305 | nuke(ep0, 0); | |
1306 | udc->req_pending = 0; | |
1307 | handle_setup(udc, ep0, csr); | |
1308 | return; | |
1309 | } | |
1310 | ||
1311 | if (list_empty(&ep0->queue)) | |
1312 | req = NULL; | |
1313 | else | |
1314 | req = list_entry(ep0->queue.next, struct at91_request, queue); | |
1315 | ||
1316 | /* host ACKed an IN packet that we sent */ | |
1317 | if (csr & AT91_UDP_TXCOMP) { | |
1318 | csr |= CLR_FX; | |
1319 | csr &= ~(SET_FX | AT91_UDP_TXCOMP); | |
1320 | ||
1321 | /* write more IN DATA? */ | |
1322 | if (req && ep0->is_in) { | |
1323 | if (handle_ep(ep0)) | |
1324 | udc->req_pending = 0; | |
1325 | ||
1326 | /* | |
1327 | * Ack after: | |
1328 | * - last IN DATA packet (including GET_STATUS) | |
1329 | * - IN/STATUS for OUT DATA | |
1330 | * - IN/STATUS for any zero-length DATA stage | |
1331 | * except for the IN DATA case, the host should send | |
1332 | * an OUT status later, which we'll ack. | |
1333 | */ | |
1334 | } else { | |
1335 | udc->req_pending = 0; | |
1336 | __raw_writel(csr, creg); | |
1337 | ||
1338 | /* | |
1339 | * SET_ADDRESS takes effect only after the STATUS | |
1340 | * (to the original address) gets acked. | |
1341 | */ | |
1342 | if (udc->wait_for_addr_ack) { | |
1343 | u32 tmp; | |
1344 | ||
ffd3326b | 1345 | at91_udp_write(udc, AT91_UDP_FADDR, |
8b2e7668 | 1346 | AT91_UDP_FEN | udc->addr); |
ffd3326b | 1347 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
1348 | tmp &= ~AT91_UDP_FADDEN; |
1349 | if (udc->addr) | |
1350 | tmp |= AT91_UDP_FADDEN; | |
ffd3326b | 1351 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1352 | |
1353 | udc->wait_for_addr_ack = 0; | |
1354 | VDBG("address %d\n", udc->addr); | |
1355 | } | |
1356 | } | |
1357 | } | |
1358 | ||
1359 | /* OUT packet arrived ... */ | |
1360 | else if (csr & AT91_UDP_RX_DATA_BK0) { | |
1361 | csr |= CLR_FX; | |
1362 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
1363 | ||
1364 | /* OUT DATA stage */ | |
1365 | if (!ep0->is_in) { | |
1366 | if (req) { | |
1367 | if (handle_ep(ep0)) { | |
1368 | /* send IN/STATUS */ | |
1369 | PACKET("ep0 in/status\n"); | |
1370 | csr = __raw_readl(creg); | |
1371 | csr &= ~SET_FX; | |
1372 | csr |= CLR_FX | AT91_UDP_TXPKTRDY; | |
1373 | __raw_writel(csr, creg); | |
1374 | udc->req_pending = 0; | |
1375 | } | |
1376 | } else if (udc->req_pending) { | |
1377 | /* | |
1378 | * AT91 hardware has a hard time with this | |
1379 | * "deferred response" mode for control-OUT | |
1380 | * transfers. (For control-IN it's fine.) | |
1381 | * | |
1382 | * The normal solution leaves OUT data in the | |
1383 | * fifo until the gadget driver is ready. | |
1384 | * We couldn't do that here without disabling | |
1385 | * the IRQ that tells about SETUP packets, | |
1386 | * e.g. when the host gets impatient... | |
1387 | * | |
1388 | * Working around it by copying into a buffer | |
1389 | * would almost be a non-deferred response, | |
1390 | * except that it wouldn't permit reliable | |
1391 | * stalling of the request. Instead, demand | |
1392 | * that gadget drivers not use this mode. | |
1393 | */ | |
1394 | DBG("no control-OUT deferred responses!\n"); | |
1395 | __raw_writel(csr | AT91_UDP_FORCESTALL, creg); | |
1396 | udc->req_pending = 0; | |
1397 | } | |
1398 | ||
1399 | /* STATUS stage for control-IN; ack. */ | |
1400 | } else { | |
1401 | PACKET("ep0 out/status ACK\n"); | |
1402 | __raw_writel(csr, creg); | |
1403 | ||
1404 | /* "early" status stage */ | |
1405 | if (req) | |
1406 | done(ep0, req, 0); | |
1407 | } | |
1408 | } | |
1409 | } | |
1410 | ||
7d12e780 | 1411 | static irqreturn_t at91_udc_irq (int irq, void *_udc) |
bae4bd84 DB |
1412 | { |
1413 | struct at91_udc *udc = _udc; | |
1414 | u32 rescans = 5; | |
c6c35237 | 1415 | int disable_clock = 0; |
4f4c5e36 HH |
1416 | unsigned long flags; |
1417 | ||
1418 | spin_lock_irqsave(&udc->lock, flags); | |
c6c35237 HH |
1419 | |
1420 | if (!udc->clocked) { | |
1421 | clk_on(udc); | |
1422 | disable_clock = 1; | |
1423 | } | |
bae4bd84 DB |
1424 | |
1425 | while (rescans--) { | |
8b2e7668 | 1426 | u32 status; |
bae4bd84 | 1427 | |
ffd3326b AV |
1428 | status = at91_udp_read(udc, AT91_UDP_ISR) |
1429 | & at91_udp_read(udc, AT91_UDP_IMR); | |
bae4bd84 DB |
1430 | if (!status) |
1431 | break; | |
1432 | ||
1433 | /* USB reset irq: not maskable */ | |
1434 | if (status & AT91_UDP_ENDBUSRES) { | |
ffd3326b AV |
1435 | at91_udp_write(udc, AT91_UDP_IDR, ~MINIMUS_INTERRUPTUS); |
1436 | at91_udp_write(udc, AT91_UDP_IER, MINIMUS_INTERRUPTUS); | |
bae4bd84 | 1437 | /* Atmel code clears this irq twice */ |
ffd3326b AV |
1438 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES); |
1439 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES); | |
bae4bd84 DB |
1440 | VDBG("end bus reset\n"); |
1441 | udc->addr = 0; | |
236e5064 | 1442 | reset_gadget(udc); |
bae4bd84 DB |
1443 | |
1444 | /* enable ep0 */ | |
ffd3326b | 1445 | at91_udp_write(udc, AT91_UDP_CSR(0), |
8b2e7668 | 1446 | AT91_UDP_EPEDS | AT91_UDP_EPTYPE_CTRL); |
bae4bd84 DB |
1447 | udc->gadget.speed = USB_SPEED_FULL; |
1448 | udc->suspended = 0; | |
ffd3326b | 1449 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_EP(0)); |
bae4bd84 DB |
1450 | |
1451 | /* | |
1452 | * NOTE: this driver keeps clocks off unless the | |
8b2e7668 DB |
1453 | * USB host is present. That saves power, but for |
1454 | * boards that don't support VBUS detection, both | |
1455 | * clocks need to be active most of the time. | |
bae4bd84 DB |
1456 | */ |
1457 | ||
1458 | /* host initiated suspend (3+ms bus idle) */ | |
1459 | } else if (status & AT91_UDP_RXSUSP) { | |
ffd3326b AV |
1460 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXSUSP); |
1461 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXRSM); | |
1462 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXSUSP); | |
1a8060d9 | 1463 | /* VDBG("bus suspend\n"); */ |
bae4bd84 DB |
1464 | if (udc->suspended) |
1465 | continue; | |
1466 | udc->suspended = 1; | |
1467 | ||
1468 | /* | |
1469 | * NOTE: when suspending a VBUS-powered device, the | |
1470 | * gadget driver should switch into slow clock mode | |
1471 | * and then into standby to avoid drawing more than | |
1472 | * 500uA power (2500uA for some high-power configs). | |
1473 | */ | |
4f4c5e36 HH |
1474 | if (udc->driver && udc->driver->suspend) { |
1475 | spin_unlock(&udc->lock); | |
bae4bd84 | 1476 | udc->driver->suspend(&udc->gadget); |
4f4c5e36 HH |
1477 | spin_lock(&udc->lock); |
1478 | } | |
bae4bd84 DB |
1479 | |
1480 | /* host initiated resume */ | |
1481 | } else if (status & AT91_UDP_RXRSM) { | |
ffd3326b AV |
1482 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXRSM); |
1483 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXSUSP); | |
1484 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXRSM); | |
1a8060d9 | 1485 | /* VDBG("bus resume\n"); */ |
bae4bd84 DB |
1486 | if (!udc->suspended) |
1487 | continue; | |
1488 | udc->suspended = 0; | |
1489 | ||
1490 | /* | |
1491 | * NOTE: for a VBUS-powered device, the gadget driver | |
1492 | * would normally want to switch out of slow clock | |
1493 | * mode into normal mode. | |
1494 | */ | |
4f4c5e36 HH |
1495 | if (udc->driver && udc->driver->resume) { |
1496 | spin_unlock(&udc->lock); | |
bae4bd84 | 1497 | udc->driver->resume(&udc->gadget); |
4f4c5e36 HH |
1498 | spin_lock(&udc->lock); |
1499 | } | |
bae4bd84 DB |
1500 | |
1501 | /* endpoint IRQs are cleared by handling them */ | |
1502 | } else { | |
1503 | int i; | |
1504 | unsigned mask = 1; | |
1505 | struct at91_ep *ep = &udc->ep[1]; | |
1506 | ||
1507 | if (status & mask) | |
1508 | handle_ep0(udc); | |
1509 | for (i = 1; i < NUM_ENDPOINTS; i++) { | |
1510 | mask <<= 1; | |
1511 | if (status & mask) | |
1512 | handle_ep(ep); | |
1513 | ep++; | |
1514 | } | |
1515 | } | |
1516 | } | |
1517 | ||
c6c35237 HH |
1518 | if (disable_clock) |
1519 | clk_off(udc); | |
1520 | ||
4f4c5e36 HH |
1521 | spin_unlock_irqrestore(&udc->lock, flags); |
1522 | ||
bae4bd84 DB |
1523 | return IRQ_HANDLED; |
1524 | } | |
1525 | ||
1526 | /*-------------------------------------------------------------------------*/ | |
1527 | ||
4037242c RM |
1528 | static void at91_vbus_update(struct at91_udc *udc, unsigned value) |
1529 | { | |
1530 | value ^= udc->board.vbus_active_low; | |
1531 | if (value != udc->vbus) | |
1532 | at91_vbus_session(&udc->gadget, value); | |
1533 | } | |
1534 | ||
7d12e780 | 1535 | static irqreturn_t at91_vbus_irq(int irq, void *_udc) |
bae4bd84 DB |
1536 | { |
1537 | struct at91_udc *udc = _udc; | |
bae4bd84 DB |
1538 | |
1539 | /* vbus needs at least brief debouncing */ | |
1540 | udelay(10); | |
4037242c | 1541 | at91_vbus_update(udc, gpio_get_value(udc->board.vbus_pin)); |
bae4bd84 DB |
1542 | |
1543 | return IRQ_HANDLED; | |
1544 | } | |
1545 | ||
4037242c RM |
1546 | static void at91_vbus_timer_work(struct work_struct *work) |
1547 | { | |
1548 | struct at91_udc *udc = container_of(work, struct at91_udc, | |
1549 | vbus_timer_work); | |
1550 | ||
1551 | at91_vbus_update(udc, gpio_get_value_cansleep(udc->board.vbus_pin)); | |
1552 | ||
1553 | if (!timer_pending(&udc->vbus_timer)) | |
1554 | mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT); | |
1555 | } | |
1556 | ||
1557 | static void at91_vbus_timer(unsigned long data) | |
1558 | { | |
1559 | struct at91_udc *udc = (struct at91_udc *)data; | |
1560 | ||
1561 | /* | |
1562 | * If we are polling vbus it is likely that the gpio is on an | |
1563 | * bus such as i2c or spi which may sleep, so schedule some work | |
1564 | * to read the vbus gpio | |
1565 | */ | |
348409a2 | 1566 | schedule_work(&udc->vbus_timer_work); |
4037242c RM |
1567 | } |
1568 | ||
f3d8bf34 SAS |
1569 | static int at91_start(struct usb_gadget *gadget, |
1570 | struct usb_gadget_driver *driver) | |
bae4bd84 | 1571 | { |
f3d8bf34 | 1572 | struct at91_udc *udc; |
bae4bd84 | 1573 | |
f3d8bf34 | 1574 | udc = container_of(gadget, struct at91_udc, gadget); |
bae4bd84 | 1575 | udc->driver = driver; |
65c84ea1 | 1576 | udc->gadget.dev.of_node = udc->pdev->dev.of_node; |
bae4bd84 | 1577 | udc->enabled = 1; |
7301971f | 1578 | udc->gadget.is_selfpowered = 1; |
bae4bd84 | 1579 | |
bae4bd84 DB |
1580 | return 0; |
1581 | } | |
bae4bd84 | 1582 | |
22835b80 | 1583 | static int at91_stop(struct usb_gadget *gadget) |
bae4bd84 | 1584 | { |
f3d8bf34 | 1585 | struct at91_udc *udc; |
4f4c5e36 | 1586 | unsigned long flags; |
bae4bd84 | 1587 | |
f3d8bf34 | 1588 | udc = container_of(gadget, struct at91_udc, gadget); |
4f4c5e36 | 1589 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1590 | udc->enabled = 0; |
ffd3326b | 1591 | at91_udp_write(udc, AT91_UDP_IDR, ~0); |
4f4c5e36 | 1592 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 | 1593 | |
bae4bd84 DB |
1594 | udc->driver = NULL; |
1595 | ||
bae4bd84 DB |
1596 | return 0; |
1597 | } | |
bae4bd84 DB |
1598 | |
1599 | /*-------------------------------------------------------------------------*/ | |
1600 | ||
1601 | static void at91udc_shutdown(struct platform_device *dev) | |
1602 | { | |
4f4c5e36 HH |
1603 | struct at91_udc *udc = platform_get_drvdata(dev); |
1604 | unsigned long flags; | |
1605 | ||
bae4bd84 | 1606 | /* force disconnect on reboot */ |
4f4c5e36 | 1607 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1608 | pullup(platform_get_drvdata(dev), 0); |
4f4c5e36 | 1609 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
1610 | } |
1611 | ||
f0bceab4 BB |
1612 | static int at91rm9200_udc_init(struct at91_udc *udc) |
1613 | { | |
1614 | struct at91_ep *ep; | |
1615 | int ret; | |
1616 | int i; | |
1617 | ||
1618 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
1619 | ep = &udc->ep[i]; | |
1620 | ||
1621 | switch (i) { | |
1622 | case 0: | |
1623 | case 3: | |
1624 | ep->maxpacket = 8; | |
1625 | break; | |
1626 | case 1 ... 2: | |
1627 | ep->maxpacket = 64; | |
1628 | break; | |
1629 | case 4 ... 5: | |
1630 | ep->maxpacket = 256; | |
1631 | break; | |
1632 | } | |
1633 | } | |
1634 | ||
1635 | if (!gpio_is_valid(udc->board.pullup_pin)) { | |
1636 | DBG("no D+ pullup?\n"); | |
1637 | return -ENODEV; | |
1638 | } | |
1639 | ||
1640 | ret = devm_gpio_request(&udc->pdev->dev, udc->board.pullup_pin, | |
1641 | "udc_pullup"); | |
1642 | if (ret) { | |
1643 | DBG("D+ pullup is busy\n"); | |
1644 | return ret; | |
1645 | } | |
1646 | ||
1647 | gpio_direction_output(udc->board.pullup_pin, | |
1648 | udc->board.pullup_active_low); | |
1649 | ||
1650 | return 0; | |
1651 | } | |
1652 | ||
1653 | static void at91rm9200_udc_pullup(struct at91_udc *udc, int is_on) | |
1654 | { | |
1655 | int active = !udc->board.pullup_active_low; | |
1656 | ||
1657 | if (is_on) | |
1658 | gpio_set_value(udc->board.pullup_pin, active); | |
1659 | else | |
1660 | gpio_set_value(udc->board.pullup_pin, !active); | |
1661 | } | |
1662 | ||
1663 | static const struct at91_udc_caps at91rm9200_udc_caps = { | |
1664 | .init = at91rm9200_udc_init, | |
1665 | .pullup = at91rm9200_udc_pullup, | |
1666 | }; | |
1667 | ||
1668 | static int at91sam9260_udc_init(struct at91_udc *udc) | |
1669 | { | |
1670 | struct at91_ep *ep; | |
1671 | int i; | |
1672 | ||
1673 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
1674 | ep = &udc->ep[i]; | |
1675 | ||
1676 | switch (i) { | |
1677 | case 0 ... 3: | |
1678 | ep->maxpacket = 64; | |
1679 | break; | |
1680 | case 4 ... 5: | |
1681 | ep->maxpacket = 512; | |
1682 | break; | |
1683 | } | |
1684 | } | |
1685 | ||
1686 | return 0; | |
1687 | } | |
1688 | ||
1689 | static void at91sam9260_udc_pullup(struct at91_udc *udc, int is_on) | |
1690 | { | |
1691 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); | |
1692 | ||
1693 | if (is_on) | |
1694 | txvc |= AT91_UDP_TXVC_PUON; | |
1695 | else | |
1696 | txvc &= ~AT91_UDP_TXVC_PUON; | |
1697 | ||
1698 | at91_udp_write(udc, AT91_UDP_TXVC, txvc); | |
1699 | } | |
1700 | ||
1701 | static const struct at91_udc_caps at91sam9260_udc_caps = { | |
1702 | .init = at91sam9260_udc_init, | |
1703 | .pullup = at91sam9260_udc_pullup, | |
1704 | }; | |
1705 | ||
1706 | static int at91sam9261_udc_init(struct at91_udc *udc) | |
1707 | { | |
1708 | struct at91_ep *ep; | |
1709 | int i; | |
1710 | ||
1711 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
1712 | ep = &udc->ep[i]; | |
1713 | ||
1714 | switch (i) { | |
1715 | case 0: | |
1716 | ep->maxpacket = 8; | |
1717 | break; | |
1718 | case 1 ... 3: | |
1719 | ep->maxpacket = 64; | |
1720 | break; | |
1721 | case 4 ... 5: | |
1722 | ep->maxpacket = 256; | |
1723 | break; | |
1724 | } | |
1725 | } | |
1726 | ||
1727 | udc->matrix = syscon_regmap_lookup_by_phandle(udc->pdev->dev.of_node, | |
1728 | "atmel,matrix"); | |
1729 | if (IS_ERR(udc->matrix)) | |
1730 | return PTR_ERR(udc->matrix); | |
1731 | ||
1732 | return 0; | |
1733 | } | |
1734 | ||
1735 | static void at91sam9261_udc_pullup(struct at91_udc *udc, int is_on) | |
1736 | { | |
1737 | u32 usbpucr = 0; | |
1738 | ||
1739 | if (is_on) | |
1740 | usbpucr = AT91_MATRIX_USBPUCR_PUON; | |
1741 | ||
1742 | regmap_update_bits(udc->matrix, AT91SAM9261_MATRIX_USBPUCR, | |
1743 | AT91_MATRIX_USBPUCR_PUON, usbpucr); | |
1744 | } | |
1745 | ||
1746 | static const struct at91_udc_caps at91sam9261_udc_caps = { | |
1747 | .init = at91sam9261_udc_init, | |
1748 | .pullup = at91sam9261_udc_pullup, | |
1749 | }; | |
1750 | ||
1751 | static int at91sam9263_udc_init(struct at91_udc *udc) | |
1752 | { | |
1753 | struct at91_ep *ep; | |
1754 | int i; | |
1755 | ||
1756 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
1757 | ep = &udc->ep[i]; | |
1758 | ||
1759 | switch (i) { | |
1760 | case 0: | |
1761 | case 1: | |
1762 | case 2: | |
1763 | case 3: | |
1764 | ep->maxpacket = 64; | |
1765 | break; | |
1766 | case 4: | |
1767 | case 5: | |
1768 | ep->maxpacket = 256; | |
1769 | break; | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | return 0; | |
1774 | } | |
1775 | ||
1776 | static const struct at91_udc_caps at91sam9263_udc_caps = { | |
1777 | .init = at91sam9263_udc_init, | |
1778 | .pullup = at91sam9260_udc_pullup, | |
1779 | }; | |
1780 | ||
1781 | static const struct of_device_id at91_udc_dt_ids[] = { | |
1782 | { | |
1783 | .compatible = "atmel,at91rm9200-udc", | |
1784 | .data = &at91rm9200_udc_caps, | |
1785 | }, | |
1786 | { | |
1787 | .compatible = "atmel,at91sam9260-udc", | |
1788 | .data = &at91sam9260_udc_caps, | |
1789 | }, | |
1790 | { | |
1791 | .compatible = "atmel,at91sam9261-udc", | |
1792 | .data = &at91sam9261_udc_caps, | |
1793 | }, | |
1794 | { | |
1795 | .compatible = "atmel,at91sam9263-udc", | |
1796 | .data = &at91sam9263_udc_caps, | |
1797 | }, | |
1798 | { /* sentinel */ } | |
1799 | }; | |
1800 | MODULE_DEVICE_TABLE(of, at91_udc_dt_ids); | |
1801 | ||
1802 | static void at91udc_of_init(struct at91_udc *udc, struct device_node *np) | |
d1494a34 JCPV |
1803 | { |
1804 | struct at91_udc_data *board = &udc->board; | |
f0bceab4 | 1805 | const struct of_device_id *match; |
d1494a34 | 1806 | enum of_gpio_flags flags; |
f0bceab4 | 1807 | u32 val; |
d1494a34 JCPV |
1808 | |
1809 | if (of_property_read_u32(np, "atmel,vbus-polled", &val) == 0) | |
1810 | board->vbus_polled = 1; | |
1811 | ||
1812 | board->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0, | |
1813 | &flags); | |
1814 | board->vbus_active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0; | |
1815 | ||
1816 | board->pullup_pin = of_get_named_gpio_flags(np, "atmel,pullup-gpio", 0, | |
1817 | &flags); | |
1818 | ||
1819 | board->pullup_active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0; | |
f0bceab4 BB |
1820 | |
1821 | match = of_match_node(at91_udc_dt_ids, np); | |
1822 | if (match) | |
1823 | udc->caps = match->data; | |
d1494a34 JCPV |
1824 | } |
1825 | ||
41ac7b3a | 1826 | static int at91udc_probe(struct platform_device *pdev) |
bae4bd84 DB |
1827 | { |
1828 | struct device *dev = &pdev->dev; | |
1829 | struct at91_udc *udc; | |
1830 | int retval; | |
ffd3326b | 1831 | struct resource *res; |
f0bceab4 BB |
1832 | struct at91_ep *ep; |
1833 | int i; | |
bae4bd84 | 1834 | |
a5514d14 BB |
1835 | udc = devm_kzalloc(dev, sizeof(*udc), GFP_KERNEL); |
1836 | if (!udc) | |
1837 | return -ENOMEM; | |
bae4bd84 DB |
1838 | |
1839 | /* init software state */ | |
bae4bd84 | 1840 | udc->gadget.dev.parent = dev; |
9f00fc1d | 1841 | at91udc_of_init(udc, pdev->dev.of_node); |
bae4bd84 | 1842 | udc->pdev = pdev; |
bae4bd84 | 1843 | udc->enabled = 0; |
4f4c5e36 | 1844 | spin_lock_init(&udc->lock); |
bae4bd84 | 1845 | |
a5514d14 BB |
1846 | udc->gadget.ops = &at91_udc_ops; |
1847 | udc->gadget.ep0 = &udc->ep[0].ep; | |
1848 | udc->gadget.name = driver_name; | |
1849 | udc->gadget.dev.init_name = "gadget"; | |
f3db6e82 | 1850 | |
a5514d14 BB |
1851 | for (i = 0; i < NUM_ENDPOINTS; i++) { |
1852 | ep = &udc->ep[i]; | |
b9ed96d7 RB |
1853 | ep->ep.name = ep_info[i].name; |
1854 | ep->ep.caps = ep_info[i].caps; | |
a5514d14 BB |
1855 | ep->ep.ops = &at91_ep_ops; |
1856 | ep->udc = udc; | |
1857 | ep->int_mask = BIT(i); | |
1858 | if (i != 0 && i != 3) | |
1859 | ep->is_pingpong = 1; | |
bb24280f DB |
1860 | } |
1861 | ||
422cde25 BB |
1862 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1863 | udc->udp_baseaddr = devm_ioremap_resource(dev, res); | |
1864 | if (IS_ERR(udc->udp_baseaddr)) | |
1865 | return PTR_ERR(udc->udp_baseaddr); | |
ffd3326b | 1866 | |
f0bceab4 BB |
1867 | if (udc->caps && udc->caps->init) { |
1868 | retval = udc->caps->init(udc); | |
1869 | if (retval) | |
1870 | return retval; | |
ffd3326b AV |
1871 | } |
1872 | ||
1873 | udc_reinit(udc); | |
1874 | ||
bae4bd84 | 1875 | /* get interface and function clocks */ |
422cde25 BB |
1876 | udc->iclk = devm_clk_get(dev, "pclk"); |
1877 | if (IS_ERR(udc->iclk)) | |
1878 | return PTR_ERR(udc->iclk); | |
1879 | ||
1880 | udc->fclk = devm_clk_get(dev, "hclk"); | |
1881 | if (IS_ERR(udc->fclk)) | |
1882 | return PTR_ERR(udc->fclk); | |
bae4bd84 | 1883 | |
8b2e7668 | 1884 | /* don't do anything until we have both gadget driver and VBUS */ |
9aa02165 | 1885 | clk_set_rate(udc->fclk, 48000000); |
b2ba27a5 RW |
1886 | retval = clk_prepare(udc->fclk); |
1887 | if (retval) | |
422cde25 | 1888 | return retval; |
b2ba27a5 | 1889 | |
76280832 BB |
1890 | retval = clk_prepare_enable(udc->iclk); |
1891 | if (retval) | |
422cde25 BB |
1892 | goto err_unprepare_fclk; |
1893 | ||
ffd3326b AV |
1894 | at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); |
1895 | at91_udp_write(udc, AT91_UDP_IDR, 0xffffffff); | |
29ba4b53 AV |
1896 | /* Clear all pending interrupts - UDP may be used by bootloader. */ |
1897 | at91_udp_write(udc, AT91_UDP_ICR, 0xffffffff); | |
b2ba27a5 | 1898 | clk_disable(udc->iclk); |
bae4bd84 DB |
1899 | |
1900 | /* request UDC and maybe VBUS irqs */ | |
8b2e7668 | 1901 | udc->udp_irq = platform_get_irq(pdev, 0); |
422cde25 BB |
1902 | retval = devm_request_irq(dev, udc->udp_irq, at91_udc_irq, 0, |
1903 | driver_name, udc); | |
1904 | if (retval) { | |
8b2e7668 | 1905 | DBG("request irq %d failed\n", udc->udp_irq); |
422cde25 | 1906 | goto err_unprepare_iclk; |
bae4bd84 | 1907 | } |
422cde25 | 1908 | |
3285e0ec | 1909 | if (gpio_is_valid(udc->board.vbus_pin)) { |
422cde25 BB |
1910 | retval = devm_gpio_request(dev, udc->board.vbus_pin, |
1911 | "udc_vbus"); | |
1912 | if (retval) { | |
f3db6e82 | 1913 | DBG("request vbus pin failed\n"); |
422cde25 | 1914 | goto err_unprepare_iclk; |
f3db6e82 | 1915 | } |
422cde25 | 1916 | |
f3db6e82 DB |
1917 | gpio_direction_input(udc->board.vbus_pin); |
1918 | ||
29ba4b53 AV |
1919 | /* |
1920 | * Get the initial state of VBUS - we cannot expect | |
1921 | * a pending interrupt. | |
1922 | */ | |
4037242c RM |
1923 | udc->vbus = gpio_get_value_cansleep(udc->board.vbus_pin) ^ |
1924 | udc->board.vbus_active_low; | |
1925 | ||
1926 | if (udc->board.vbus_polled) { | |
1927 | INIT_WORK(&udc->vbus_timer_work, at91_vbus_timer_work); | |
1928 | setup_timer(&udc->vbus_timer, at91_vbus_timer, | |
1929 | (unsigned long)udc); | |
1930 | mod_timer(&udc->vbus_timer, | |
1931 | jiffies + VBUS_POLL_TIMEOUT); | |
1932 | } else { | |
422cde25 BB |
1933 | retval = devm_request_irq(dev, |
1934 | gpio_to_irq(udc->board.vbus_pin), | |
1935 | at91_vbus_irq, 0, driver_name, udc); | |
1936 | if (retval) { | |
4037242c RM |
1937 | DBG("request vbus irq %d failed\n", |
1938 | udc->board.vbus_pin); | |
422cde25 | 1939 | goto err_unprepare_iclk; |
4037242c | 1940 | } |
bae4bd84 DB |
1941 | } |
1942 | } else { | |
1943 | DBG("no VBUS detection, assuming always-on\n"); | |
1944 | udc->vbus = 1; | |
1945 | } | |
0f91349b SAS |
1946 | retval = usb_add_gadget_udc(dev, &udc->gadget); |
1947 | if (retval) | |
422cde25 | 1948 | goto err_unprepare_iclk; |
bae4bd84 | 1949 | dev_set_drvdata(dev, udc); |
8b2e7668 | 1950 | device_init_wakeup(dev, 1); |
bae4bd84 DB |
1951 | create_debug_file(udc); |
1952 | ||
1953 | INFO("%s version %s\n", driver_name, DRIVER_VERSION); | |
1954 | return 0; | |
422cde25 BB |
1955 | |
1956 | err_unprepare_iclk: | |
b2ba27a5 | 1957 | clk_unprepare(udc->iclk); |
422cde25 | 1958 | err_unprepare_fclk: |
b2ba27a5 | 1959 | clk_unprepare(udc->fclk); |
422cde25 | 1960 | |
bae4bd84 | 1961 | DBG("%s probe failed, %d\n", driver_name, retval); |
422cde25 | 1962 | |
bae4bd84 DB |
1963 | return retval; |
1964 | } | |
1965 | ||
c94e289f | 1966 | static int at91udc_remove(struct platform_device *pdev) |
bae4bd84 | 1967 | { |
8b2e7668 | 1968 | struct at91_udc *udc = platform_get_drvdata(pdev); |
4f4c5e36 | 1969 | unsigned long flags; |
bae4bd84 DB |
1970 | |
1971 | DBG("remove\n"); | |
1972 | ||
0f91349b | 1973 | usb_del_gadget_udc(&udc->gadget); |
6bea476c DB |
1974 | if (udc->driver) |
1975 | return -EBUSY; | |
bae4bd84 | 1976 | |
4f4c5e36 | 1977 | spin_lock_irqsave(&udc->lock, flags); |
6bea476c | 1978 | pullup(udc, 0); |
4f4c5e36 | 1979 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 | 1980 | |
8b2e7668 | 1981 | device_init_wakeup(&pdev->dev, 0); |
bae4bd84 | 1982 | remove_debug_file(udc); |
b2ba27a5 RW |
1983 | clk_unprepare(udc->fclk); |
1984 | clk_unprepare(udc->iclk); | |
1985 | ||
bae4bd84 DB |
1986 | return 0; |
1987 | } | |
1988 | ||
1989 | #ifdef CONFIG_PM | |
8b2e7668 | 1990 | static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg) |
bae4bd84 | 1991 | { |
8b2e7668 DB |
1992 | struct at91_udc *udc = platform_get_drvdata(pdev); |
1993 | int wake = udc->driver && device_may_wakeup(&pdev->dev); | |
4f4c5e36 | 1994 | unsigned long flags; |
bae4bd84 | 1995 | |
8b2e7668 DB |
1996 | /* Unless we can act normally to the host (letting it wake us up |
1997 | * whenever it has work for us) force disconnect. Wakeup requires | |
1998 | * PLLB for USB events (signaling for reset, wakeup, or incoming | |
1999 | * tokens) and VBUS irqs (on systems which support them). | |
bae4bd84 | 2000 | */ |
8b2e7668 DB |
2001 | if ((!udc->suspended && udc->addr) |
2002 | || !wake | |
2003 | || at91_suspend_entering_slow_clock()) { | |
4f4c5e36 | 2004 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 2005 | pullup(udc, 0); |
66e56ce7 | 2006 | wake = 0; |
4f4c5e36 | 2007 | spin_unlock_irqrestore(&udc->lock, flags); |
8b2e7668 DB |
2008 | } else |
2009 | enable_irq_wake(udc->udp_irq); | |
2010 | ||
66e56ce7 | 2011 | udc->active_suspend = wake; |
3285e0ec | 2012 | if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled && wake) |
66e56ce7 | 2013 | enable_irq_wake(udc->board.vbus_pin); |
bae4bd84 DB |
2014 | return 0; |
2015 | } | |
2016 | ||
8b2e7668 | 2017 | static int at91udc_resume(struct platform_device *pdev) |
bae4bd84 | 2018 | { |
8b2e7668 | 2019 | struct at91_udc *udc = platform_get_drvdata(pdev); |
4f4c5e36 | 2020 | unsigned long flags; |
bae4bd84 | 2021 | |
3285e0ec | 2022 | if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled && |
4037242c | 2023 | udc->active_suspend) |
66e56ce7 DB |
2024 | disable_irq_wake(udc->board.vbus_pin); |
2025 | ||
bae4bd84 | 2026 | /* maybe reconnect to host; if so, clocks on */ |
66e56ce7 DB |
2027 | if (udc->active_suspend) |
2028 | disable_irq_wake(udc->udp_irq); | |
4f4c5e36 HH |
2029 | else { |
2030 | spin_lock_irqsave(&udc->lock, flags); | |
66e56ce7 | 2031 | pullup(udc, 1); |
4f4c5e36 HH |
2032 | spin_unlock_irqrestore(&udc->lock, flags); |
2033 | } | |
bae4bd84 DB |
2034 | return 0; |
2035 | } | |
2036 | #else | |
2037 | #define at91udc_suspend NULL | |
2038 | #define at91udc_resume NULL | |
2039 | #endif | |
2040 | ||
dee497df | 2041 | static struct platform_driver at91_udc_driver = { |
c94e289f | 2042 | .remove = at91udc_remove, |
bae4bd84 DB |
2043 | .shutdown = at91udc_shutdown, |
2044 | .suspend = at91udc_suspend, | |
8b2e7668 | 2045 | .resume = at91udc_resume, |
bae4bd84 DB |
2046 | .driver = { |
2047 | .name = (char *) driver_name, | |
9f00fc1d | 2048 | .of_match_table = at91_udc_dt_ids, |
bae4bd84 DB |
2049 | }, |
2050 | }; | |
2051 | ||
52f7a82b | 2052 | module_platform_driver_probe(at91_udc_driver, at91udc_probe); |
bae4bd84 | 2053 | |
8b2e7668 | 2054 | MODULE_DESCRIPTION("AT91 udc driver"); |
bae4bd84 DB |
2055 | MODULE_AUTHOR("Thomas Rathbone, David Brownell"); |
2056 | MODULE_LICENSE("GPL"); | |
f34c32f1 | 2057 | MODULE_ALIAS("platform:at91_udc"); |