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[deliverable/linux.git] / drivers / usb / gadget / udc / lpc32xx_udc.c
CommitLineData
24a28e42
RS		 1/*
2 * USB Gadget driver for LPC32xx
3 *
4 * Authors:
5 * Kevin Wells <kevin.wells@nxp.com>
6 * Mike James
7 * Roland Stigge <stigge@antcom.de>
8 *
9 * Copyright (C) 2006 Philips Semiconductors
10 * Copyright (C) 2009 NXP Semiconductors
11 * Copyright (C) 2012 Roland Stigge
12 *
13 * Note: This driver is based on original work done by Mike James for
14 * the LPC3180.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 */
30
2de59c09 31#include <linux/clk.h>
24a28e42 32#include <linux/delay.h>
2de59c09
VZ		 33#include <linux/dma-mapping.h>
34#include <linux/dmapool.h>
35#include <linux/i2c.h>
24a28e42 36#include <linux/interrupt.h>
2de59c09
VZ		 37#include <linux/module.h>
38#include <linux/of.h>
39#include <linux/platform_device.h>
24a28e42 40#include <linux/proc_fs.h>
2de59c09 41#include <linux/slab.h>
24a28e42
RS		 42#include <linux/usb/ch9.h>
43#include <linux/usb/gadget.h>
24a28e42
RS		 44#include <linux/usb/isp1301.h>
45
24a28e42 46#ifdef CONFIG_USB_GADGET_DEBUG_FILES
d7dbdb5e 47#include <linux/debugfs.h>
24a28e42
RS		 48#include <linux/seq_file.h>
49#endif
50
2de59c09 51#include <mach/hardware.h>
2de59c09 52
24a28e42
RS		 53/*
54 * USB device configuration structure
55 */
56typedef void (*usc_chg_event)(int);
57struct lpc32xx_usbd_cfg {
58 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
59 usc_chg_event conn_chgb; /* Connection change event (optional) */
60 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
61 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
62};
63
64/*
65 * controller driver data structures
66 */
67
68/* 16 endpoints (not to be confused with 32 hardware endpoints) */
69#define NUM_ENDPOINTS 16
70
71/*
72 * IRQ indices make reading the code a little easier
73 */
74#define IRQ_USB_LP 0
75#define IRQ_USB_HP 1
76#define IRQ_USB_DEVDMA 2
77#define IRQ_USB_ATX 3
78
79#define EP_OUT 0 /* RX (from host) */
80#define EP_IN 1 /* TX (to host) */
81
82/* Returns the interrupt mask for the selected hardware endpoint */
83#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
84
85#define EP_INT_TYPE 0
86#define EP_ISO_TYPE 1
87#define EP_BLK_TYPE 2
88#define EP_CTL_TYPE 3
89
90/* EP0 states */
91#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
92#define DATA_IN 1 /* Expect dev->host transfer */
93#define DATA_OUT 2 /* Expect host->dev transfer */
94
95/* DD (DMA Descriptor) structure, requires word alignment, this is already
96 * defined in the LPC32XX USB device header file, but this version is slightly
97 * modified to tag some work data with each DMA descriptor. */
98struct lpc32xx_usbd_dd_gad {
99 u32 dd_next_phy;
100 u32 dd_setup;
101 u32 dd_buffer_addr;
102 u32 dd_status;
103 u32 dd_iso_ps_mem_addr;
104 u32 this_dma;
105 u32 iso_status[6]; /* 5 spare */
106 u32 dd_next_v;
107};
108
109/*
110 * Logical endpoint structure
111 */
112struct lpc32xx_ep {
113 struct usb_ep ep;
114 struct list_head queue;
115 struct lpc32xx_udc *udc;
116
117 u32 hwep_num_base; /* Physical hardware EP */
118 u32 hwep_num; /* Maps to hardware endpoint */
119 u32 maxpacket;
120 u32 lep;
121
122 bool is_in;
123 bool req_pending;
124 u32 eptype;
125
126 u32 totalints;
127
128 bool wedge;
24a28e42
RS		 129};
130
131/*
132 * Common UDC structure
133 */
134struct lpc32xx_udc {
135 struct usb_gadget gadget;
136 struct usb_gadget_driver *driver;
137 struct platform_device *pdev;
138 struct device *dev;
139 struct dentry *pde;
140 spinlock_t lock;
141 struct i2c_client *isp1301_i2c_client;
142
143 /* Board and device specific */
144 struct lpc32xx_usbd_cfg *board;
145 u32 io_p_start;
146 u32 io_p_size;
147 void __iomem *udp_baseaddr;
148 int udp_irq[4];
24a28e42
RS		 149 struct clk *usb_slv_clk;
150
151 /* DMA support */
152 u32 *udca_v_base;
153 u32 udca_p_base;
154 struct dma_pool *dd_cache;
155
156 /* Common EP and control data */
157 u32 enabled_devints;
158 u32 enabled_hwepints;
159 u32 dev_status;
160 u32 realized_eps;
161
162 /* VBUS detection, pullup, and power flags */
163 u8 vbus;
164 u8 last_vbus;
165 int pullup;
166 int poweron;
167
168 /* Work queues related to I2C support */
169 struct work_struct pullup_job;
170 struct work_struct vbus_job;
171 struct work_struct power_job;
172
173 /* USB device peripheral - various */
174 struct lpc32xx_ep ep[NUM_ENDPOINTS];
175 bool enabled;
176 bool clocked;
177 bool suspended;
24a28e42
RS		 178 int ep0state;
179 atomic_t enabled_ep_cnt;
180 wait_queue_head_t ep_disable_wait_queue;
181};
182
183/*
184 * Endpoint request
185 */
186struct lpc32xx_request {
187 struct usb_request req;
188 struct list_head queue;
189 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
190 bool mapped;
191 bool send_zlp;
192};
193
194static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
195{
196 return container_of(g, struct lpc32xx_udc, gadget);
197}
198
199#define ep_dbg(epp, fmt, arg...) \
200 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
201#define ep_err(epp, fmt, arg...) \
202 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
203#define ep_info(epp, fmt, arg...) \
204 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
205#define ep_warn(epp, fmt, arg...) \
206 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
207
208#define UDCA_BUFF_SIZE (128)
209
24a28e42
RS		 210/**********************************************************************
211 * USB device controller register offsets
212 **********************************************************************/
213
214#define USBD_DEVINTST(x) ((x) + 0x200)
215#define USBD_DEVINTEN(x) ((x) + 0x204)
216#define USBD_DEVINTCLR(x) ((x) + 0x208)
217#define USBD_DEVINTSET(x) ((x) + 0x20C)
218#define USBD_CMDCODE(x) ((x) + 0x210)
219#define USBD_CMDDATA(x) ((x) + 0x214)
220#define USBD_RXDATA(x) ((x) + 0x218)
221#define USBD_TXDATA(x) ((x) + 0x21C)
222#define USBD_RXPLEN(x) ((x) + 0x220)
223#define USBD_TXPLEN(x) ((x) + 0x224)
224#define USBD_CTRL(x) ((x) + 0x228)
225#define USBD_DEVINTPRI(x) ((x) + 0x22C)
226#define USBD_EPINTST(x) ((x) + 0x230)
227#define USBD_EPINTEN(x) ((x) + 0x234)
228#define USBD_EPINTCLR(x) ((x) + 0x238)
229#define USBD_EPINTSET(x) ((x) + 0x23C)
230#define USBD_EPINTPRI(x) ((x) + 0x240)
231#define USBD_REEP(x) ((x) + 0x244)
232#define USBD_EPIND(x) ((x) + 0x248)
233#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
234/* DMA support registers only below */
235/* Set, clear, or get enabled state of the DMA request status. If
236 * enabled, an IN or OUT token will start a DMA transfer for the EP */
237#define USBD_DMARST(x) ((x) + 0x250)
238#define USBD_DMARCLR(x) ((x) + 0x254)
239#define USBD_DMARSET(x) ((x) + 0x258)
240/* DMA UDCA head pointer */
241#define USBD_UDCAH(x) ((x) + 0x280)
242/* EP DMA status, enable, and disable. This is used to specifically
243 * enabled or disable DMA for a specific EP */
244#define USBD_EPDMAST(x) ((x) + 0x284)
245#define USBD_EPDMAEN(x) ((x) + 0x288)
246#define USBD_EPDMADIS(x) ((x) + 0x28C)
247/* DMA master interrupts enable and pending interrupts */
248#define USBD_DMAINTST(x) ((x) + 0x290)
249#define USBD_DMAINTEN(x) ((x) + 0x294)
250/* DMA end of transfer interrupt enable, disable, status */
251#define USBD_EOTINTST(x) ((x) + 0x2A0)
252#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
253#define USBD_EOTINTSET(x) ((x) + 0x2A8)
254/* New DD request interrupt enable, disable, status */
255#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
256#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
257#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
258/* DMA error interrupt enable, disable, status */
259#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
260#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
261#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
262
263/**********************************************************************
264 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
265 * USBD_DEVINTPRI register definitions
266 **********************************************************************/
267#define USBD_ERR_INT (1 << 9)
268#define USBD_EP_RLZED (1 << 8)
269#define USBD_TXENDPKT (1 << 7)
270#define USBD_RXENDPKT (1 << 6)
271#define USBD_CDFULL (1 << 5)
272#define USBD_CCEMPTY (1 << 4)
273#define USBD_DEV_STAT (1 << 3)
274#define USBD_EP_SLOW (1 << 2)
275#define USBD_EP_FAST (1 << 1)
276#define USBD_FRAME (1 << 0)
277
278/**********************************************************************
279 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
280 * USBD_EPINTPRI register definitions
281 **********************************************************************/
282/* End point selection macro (RX) */
283#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
284
285/* End point selection macro (TX) */
286#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
287
288/**********************************************************************
289 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
290 * USBD_EPDMAEN/USBD_EPDMADIS/
291 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
292 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
293 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
294 * register definitions
295 **********************************************************************/
296/* Endpoint selection macro */
297#define USBD_EP_SEL(e) (1 << (e))
298
299/**********************************************************************
300 * SBD_DMAINTST/USBD_DMAINTEN
301 **********************************************************************/
302#define USBD_SYS_ERR_INT (1 << 2)
303#define USBD_NEW_DD_INT (1 << 1)
304#define USBD_EOT_INT (1 << 0)
305
306/**********************************************************************
307 * USBD_RXPLEN register definitions
308 **********************************************************************/
309#define USBD_PKT_RDY (1 << 11)
310#define USBD_DV (1 << 10)
311#define USBD_PK_LEN_MASK 0x3FF
312
313/**********************************************************************
314 * USBD_CTRL register definitions
315 **********************************************************************/
316#define USBD_LOG_ENDPOINT(e) ((e) << 2)
317#define USBD_WR_EN (1 << 1)
318#define USBD_RD_EN (1 << 0)
319
320/**********************************************************************
321 * USBD_CMDCODE register definitions
322 **********************************************************************/
323#define USBD_CMD_CODE(c) ((c) << 16)
324#define USBD_CMD_PHASE(p) ((p) << 8)
325
326/**********************************************************************
327 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
328 **********************************************************************/
329#define USBD_DMAEP(e) (1 << (e))
330
331/* DD (DMA Descriptor) structure, requires word alignment */
332struct lpc32xx_usbd_dd {
333 u32 *dd_next;
334 u32 dd_setup;
335 u32 dd_buffer_addr;
336 u32 dd_status;
337 u32 dd_iso_ps_mem_addr;
338};
339
340/* dd_setup bit defines */
341#define DD_SETUP_ATLE_DMA_MODE 0x01
342#define DD_SETUP_NEXT_DD_VALID 0x04
343#define DD_SETUP_ISO_EP 0x10
344#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
345#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
346
347/* dd_status bit defines */
348#define DD_STATUS_DD_RETIRED 0x01
349#define DD_STATUS_STS_MASK 0x1E
350#define DD_STATUS_STS_NS 0x00 /* Not serviced */
351#define DD_STATUS_STS_BS 0x02 /* Being serviced */
352#define DD_STATUS_STS_NC 0x04 /* Normal completion */
353#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
354#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
355#define DD_STATUS_STS_SE 0x12 /* System error */
356#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
357#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
358#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
359#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
360#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
361
362/*
363 *
364 * Protocol engine bits below
365 *
366 */
367/* Device Interrupt Bit Definitions */
368#define FRAME_INT 0x00000001
369#define EP_FAST_INT 0x00000002
370#define EP_SLOW_INT 0x00000004
371#define DEV_STAT_INT 0x00000008
372#define CCEMTY_INT 0x00000010
373#define CDFULL_INT 0x00000020
374#define RxENDPKT_INT 0x00000040
375#define TxENDPKT_INT 0x00000080
376#define EP_RLZED_INT 0x00000100
377#define ERR_INT 0x00000200
378
379/* Rx & Tx Packet Length Definitions */
380#define PKT_LNGTH_MASK 0x000003FF
381#define PKT_DV 0x00000400
382#define PKT_RDY 0x00000800
383
384/* USB Control Definitions */
385#define CTRL_RD_EN 0x00000001
386#define CTRL_WR_EN 0x00000002
387
388/* Command Codes */
389#define CMD_SET_ADDR 0x00D00500
390#define CMD_CFG_DEV 0x00D80500
391#define CMD_SET_MODE 0x00F30500
392#define CMD_RD_FRAME 0x00F50500
393#define DAT_RD_FRAME 0x00F50200
394#define CMD_RD_TEST 0x00FD0500
395#define DAT_RD_TEST 0x00FD0200
396#define CMD_SET_DEV_STAT 0x00FE0500
397#define CMD_GET_DEV_STAT 0x00FE0500
398#define DAT_GET_DEV_STAT 0x00FE0200
399#define CMD_GET_ERR_CODE 0x00FF0500
400#define DAT_GET_ERR_CODE 0x00FF0200
401#define CMD_RD_ERR_STAT 0x00FB0500
402#define DAT_RD_ERR_STAT 0x00FB0200
403#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
404#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
405#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
406#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
407#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
408#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
409#define CMD_CLR_BUF 0x00F20500
410#define DAT_CLR_BUF 0x00F20200
411#define CMD_VALID_BUF 0x00FA0500
412
413/* Device Address Register Definitions */
414#define DEV_ADDR_MASK 0x7F
415#define DEV_EN 0x80
416
417/* Device Configure Register Definitions */
418#define CONF_DVICE 0x01
419
420/* Device Mode Register Definitions */
421#define AP_CLK 0x01
422#define INAK_CI 0x02
423#define INAK_CO 0x04
424#define INAK_II 0x08
425#define INAK_IO 0x10
426#define INAK_BI 0x20
427#define INAK_BO 0x40
428
429/* Device Status Register Definitions */
430#define DEV_CON 0x01
431#define DEV_CON_CH 0x02
432#define DEV_SUS 0x04
433#define DEV_SUS_CH 0x08
434#define DEV_RST 0x10
435
436/* Error Code Register Definitions */
437#define ERR_EC_MASK 0x0F
438#define ERR_EA 0x10
439
440/* Error Status Register Definitions */
441#define ERR_PID 0x01
442#define ERR_UEPKT 0x02
443#define ERR_DCRC 0x04
444#define ERR_TIMOUT 0x08
445#define ERR_EOP 0x10
446#define ERR_B_OVRN 0x20
447#define ERR_BTSTF 0x40
448#define ERR_TGL 0x80
449
450/* Endpoint Select Register Definitions */
451#define EP_SEL_F 0x01
452#define EP_SEL_ST 0x02
453#define EP_SEL_STP 0x04
454#define EP_SEL_PO 0x08
455#define EP_SEL_EPN 0x10
456#define EP_SEL_B_1_FULL 0x20
457#define EP_SEL_B_2_FULL 0x40
458
459/* Endpoint Status Register Definitions */
460#define EP_STAT_ST 0x01
461#define EP_STAT_DA 0x20
462#define EP_STAT_RF_MO 0x40
463#define EP_STAT_CND_ST 0x80
464
465/* Clear Buffer Register Definitions */
466#define CLR_BUF_PO 0x01
467
468/* DMA Interrupt Bit Definitions */
469#define EOT_INT 0x01
470#define NDD_REQ_INT 0x02
471#define SYS_ERR_INT 0x04
472
473#define DRIVER_VERSION "1.03"
474static const char driver_name[] = "lpc32xx_udc";
475
476/*
477 *
478 * proc interface support
479 *
480 */
481#ifdef CONFIG_USB_GADGET_DEBUG_FILES
482static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
483static const char debug_filename[] = "driver/udc";
484
485static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
486{
487 struct lpc32xx_request *req;
488
489 seq_printf(s, "\n");
490 seq_printf(s, "%12s, maxpacket %4d %3s",
491 ep->ep.name, ep->ep.maxpacket,
492 ep->is_in ? "in" : "out");
493 seq_printf(s, " type %4s", epnames[ep->eptype]);
494 seq_printf(s, " ints: %12d", ep->totalints);
495
496 if (list_empty(&ep->queue))
497 seq_printf(s, "\t(queue empty)\n");
498 else {
499 list_for_each_entry(req, &ep->queue, queue) {
500 u32 length = req->req.actual;
501
502 seq_printf(s, "\treq %p len %d/%d buf %p\n",
503 &req->req, length,
504 req->req.length, req->req.buf);
505 }
506 }
507}
508
509static int proc_udc_show(struct seq_file *s, void *unused)
510{
511 struct lpc32xx_udc *udc = s->private;
512 struct lpc32xx_ep *ep;
513 unsigned long flags;
514
515 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
516
517 spin_lock_irqsave(&udc->lock, flags);
518
519 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
520 udc->vbus ? "present" : "off",
521 udc->enabled ? (udc->vbus ? "active" : "enabled") :
522 "disabled",
d60d9392 523 udc->gadget.is_selfpowered ? "self" : "VBUS",
24a28e42
RS		 524 udc->suspended ? ", suspended" : "",
525 udc->driver ? udc->driver->driver.name : "(none)");
526
527 if (udc->enabled && udc->vbus) {
528 proc_ep_show(s, &udc->ep[0]);
78ca9139
RS		 529 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
530 proc_ep_show(s, ep);
24a28e42
RS		 531 }
532
533 spin_unlock_irqrestore(&udc->lock, flags);
534
535 return 0;
536}
537
538static int proc_udc_open(struct inode *inode, struct file *file)
539{
d9dda78b 540 return single_open(file, proc_udc_show, PDE_DATA(inode));
24a28e42
RS		 541}
542
543static const struct file_operations proc_ops = {
544 .owner = THIS_MODULE,
545 .open = proc_udc_open,
546 .read = seq_read,
547 .llseek = seq_lseek,
548 .release = single_release,
549};
550
551static void create_debug_file(struct lpc32xx_udc *udc)
552{
553 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
554}
555
556static void remove_debug_file(struct lpc32xx_udc *udc)
557{
23fba80a 558 debugfs_remove(udc->pde);
24a28e42
RS		 559}
560
561#else
562static inline void create_debug_file(struct lpc32xx_udc *udc) {}
563static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
564#endif
565
566/* Primary initialization sequence for the ISP1301 transceiver */
567static void isp1301_udc_configure(struct lpc32xx_udc *udc)
568{
569 /* LPC32XX only supports DAT_SE0 USB mode */
570 /* This sequence is important */
571
572 /* Disable transparent UART mode first */
573 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
574 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
575 MC1_UART_EN);
576
577 /* Set full speed and SE0 mode */
578 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
579 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
580 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
581 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
582
583 /*
584 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
585 */
586 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
587 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
588 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
589 ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
590
591 /* Driver VBUS_DRV high or low depending on board setup */
592 if (udc->board->vbus_drv_pol != 0)
593 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
594 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
595 else
596 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
597 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
598 OTG1_VBUS_DRV);
599
600 /* Bi-directional mode with suspend control
601 * Enable both pulldowns for now - the pullup will be enable when VBUS
602 * is detected */
603 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
604 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
605 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
606 ISP1301_I2C_OTG_CONTROL_1,
607 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
608
609 /* Discharge VBUS (just in case) */
610 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
611 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
612 msleep(1);
613 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
614 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
615 OTG1_VBUS_DISCHRG);
616
617 /* Clear and enable VBUS high edge interrupt */
618 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
619 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
620 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
621 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
622 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
623 ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
624 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
625 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
626 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
627 ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
628
24a28e42
RS		 629 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
630 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
631 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
632 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
633 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
634 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
635}
636
637/* Enables or disables the USB device pullup via the ISP1301 transceiver */
638static void isp1301_pullup_set(struct lpc32xx_udc *udc)
639{
640 if (udc->pullup)
641 /* Enable pullup for bus signalling */
642 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
643 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
644 else
645 /* Enable pullup for bus signalling */
646 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
647 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
648 OTG1_DP_PULLUP);
649}
650
651static void pullup_work(struct work_struct *work)
652{
653 struct lpc32xx_udc *udc =
654 container_of(work, struct lpc32xx_udc, pullup_job);
655
656 isp1301_pullup_set(udc);
657}
658
659static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
660 int block)
661{
662 if (en_pullup == udc->pullup)
663 return;
664
665 udc->pullup = en_pullup;
666 if (block)
667 isp1301_pullup_set(udc);
668 else
669 /* defer slow i2c pull up setting */
670 schedule_work(&udc->pullup_job);
671}
672
673#ifdef CONFIG_PM
674/* Powers up or down the ISP1301 transceiver */
675static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
676{
677 if (enable != 0)
678 /* Power up ISP1301 - this ISP1301 will automatically wakeup
679 when VBUS is detected */
680 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
681 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
682 MC2_GLOBAL_PWR_DN);
683 else
684 /* Power down ISP1301 */
685 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
686 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
687}
688
689static void power_work(struct work_struct *work)
690{
691 struct lpc32xx_udc *udc =
692 container_of(work, struct lpc32xx_udc, power_job);
693
694 isp1301_set_powerstate(udc, udc->poweron);
695}
696#endif
697
698/*
699 *
700 * USB protocol engine command/data read/write helper functions
701 *
702 */
703/* Issues a single command to the USB device state machine */
704static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
705{
706 u32 pass = 0;
707 int to;
708
709 /* EP may lock on CLRI if this read isn't done */
710 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
711 (void) tmp;
712
713 while (pass == 0) {
714 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
715
716 /* Write command code */
717 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
718 to = 10000;
719 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
720 USBD_CCEMPTY) == 0) && (to > 0)) {
721 to--;
722 }
723
724 if (to > 0)
725 pass = 1;
726
727 cpu_relax();
728 }
729}
730
731/* Issues 2 commands (or command and data) to the USB device state machine */
732static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
733 u32 data)
734{
735 udc_protocol_cmd_w(udc, cmd);
736 udc_protocol_cmd_w(udc, data);
737}
738
739/* Issues a single command to the USB device state machine and reads
740 * response data */
741static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
742{
743 u32 tmp;
744 int to = 1000;
745
746 /* Write a command and read data from the protocol engine */
747 writel((USBD_CDFULL | USBD_CCEMPTY),
748 USBD_DEVINTCLR(udc->udp_baseaddr));
749
750 /* Write command code */
751 udc_protocol_cmd_w(udc, cmd);
752
753 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
754 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
755 && (to > 0))
756 to--;
757 if (!to)
758 dev_dbg(udc->dev,
759 "Protocol engine didn't receive response (CDFULL)\n");
760
761 return readl(USBD_CMDDATA(udc->udp_baseaddr));
762}
763
764/*
765 *
766 * USB device interrupt mask support functions
767 *
768 */
769/* Enable one or more USB device interrupts */
770static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
771{
772 udc->enabled_devints |= devmask;
773 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
774}
775
776/* Disable one or more USB device interrupts */
777static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
778{
779 udc->enabled_devints &= ~mask;
780 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
781}
782
783/* Clear one or more USB device interrupts */
784static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
785{
786 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
787}
788
789/*
790 *
791 * Endpoint interrupt disable/enable functions
792 *
793 */
794/* Enable one or more USB endpoint interrupts */
795static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
796{
797 udc->enabled_hwepints |= (1 << hwep);
798 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
799}
800
801/* Disable one or more USB endpoint interrupts */
802static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
803{
804 udc->enabled_hwepints &= ~(1 << hwep);
805 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
806}
807
808/* Clear one or more USB endpoint interrupts */
809static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
810{
811 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
812}
813
814/* Enable DMA for the HW channel */
815static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
816{
817 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
818}
819
820/* Disable DMA for the HW channel */
821static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
822{
823 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
824}
825
826/*
827 *
828 * Endpoint realize/unrealize functions
829 *
830 */
831/* Before an endpoint can be used, it needs to be realized
832 * in the USB protocol engine - this realizes the endpoint.
833 * The interrupt (FIFO or DMA) is not enabled with this function */
834static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
835 u32 maxpacket)
836{
837 int to = 1000;
838
839 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
840 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
841 udc->realized_eps |= (1 << hwep);
842 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
843 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
844
845 /* Wait until endpoint is realized in hardware */
846 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
847 USBD_EP_RLZED)) && (to > 0))
848 to--;
849 if (!to)
850 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
851
852 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
853}
854
855/* Unrealize an EP */
856static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
857{
858 udc->realized_eps &= ~(1 << hwep);
859 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
860}
861
862/*
863 *
864 * Endpoint support functions
865 *
866 */
867/* Select and clear endpoint interrupt */
868static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
869{
870 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
871 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
872}
873
874/* Disables the endpoint in the USB protocol engine */
875static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
876{
877 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
878 DAT_WR_BYTE(EP_STAT_DA));
879}
880
881/* Stalls the endpoint - endpoint will return STALL */
882static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
883{
884 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
885 DAT_WR_BYTE(EP_STAT_ST));
886}
887
888/* Clear stall or reset endpoint */
889static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
890{
891 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
892 DAT_WR_BYTE(0));
893}
894
895/* Select an endpoint for endpoint status, clear, validate */
896static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
897{
898 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
899}
900
901/*
902 *
903 * Endpoint buffer management functions
904 *
905 */
906/* Clear the current endpoint's buffer */
907static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
908{
909 udc_select_hwep(udc, hwep);
910 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
911}
912
913/* Validate the current endpoint's buffer */
914static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
915{
916 udc_select_hwep(udc, hwep);
917 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
918}
919
920static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
921{
922 /* Clear EP interrupt */
923 uda_clear_hwepint(udc, hwep);
924 return udc_selep_clrint(udc, hwep);
925}
926
927/*
928 *
929 * USB EP DMA support
930 *
931 */
932/* Allocate a DMA Descriptor */
933static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
934{
935 dma_addr_t dma;
936 struct lpc32xx_usbd_dd_gad *dd;
937
938 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
939 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
940 if (dd)
941 dd->this_dma = dma;
942
943 return dd;
944}
945
946/* Free a DMA Descriptor */
947static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
948{
949 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
950}
951
952/*
953 *
954 * USB setup and shutdown functions
955 *
956 */
957/* Enables or disables most of the USB system clocks when low power mode is
958 * needed. Clocks are typically started on a connection event, and disabled
959 * when a cable is disconnected */
24a28e42
RS		 960static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
961{
24a28e42
RS		 962 if (enable != 0) {
963 if (udc->clocked)
964 return;
965
966 udc->clocked = 1;
59e05272 967 clk_prepare_enable(udc->usb_slv_clk);
24a28e42
RS		 968 } else {
969 if (!udc->clocked)
970 return;
971
972 udc->clocked = 0;
59e05272 973 clk_disable_unprepare(udc->usb_slv_clk);
24a28e42
RS		 974 }
975}
976
977/* Set/reset USB device address */
978static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
979{
980 /* Address will be latched at the end of the status phase, or
981 latched immediately if function is called twice */
982 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
983 DAT_WR_BYTE(DEV_EN | addr));
984}
985
986/* Setup up a IN request for DMA transfer - this consists of determining the
987 * list of DMA addresses for the transfer, allocating DMA Descriptors,
988 * installing the DD into the UDCA, and then enabling the DMA for that EP */
989static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
990{
991 struct lpc32xx_request *req;
992 u32 hwep = ep->hwep_num;
993
994 ep->req_pending = 1;
995
996 /* There will always be a request waiting here */
997 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
998
999 /* Place the DD Descriptor into the UDCA */
1000 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1001
1002 /* Enable DMA and interrupt for the HW EP */
1003 udc_ep_dma_enable(udc, hwep);
1004
1005 /* Clear ZLP if last packet is not of MAXP size */
1006 if (req->req.length % ep->ep.maxpacket)
1007 req->send_zlp = 0;
1008
1009 return 0;
1010}
1011
1012/* Setup up a OUT request for DMA transfer - this consists of determining the
1013 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1014 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1015static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1016{
1017 struct lpc32xx_request *req;
1018 u32 hwep = ep->hwep_num;
1019
1020 ep->req_pending = 1;
1021
1022 /* There will always be a request waiting here */
1023 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1024
1025 /* Place the DD Descriptor into the UDCA */
1026 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1027
1028 /* Enable DMA and interrupt for the HW EP */
1029 udc_ep_dma_enable(udc, hwep);
1030 return 0;
1031}
1032
1033static void udc_disable(struct lpc32xx_udc *udc)
1034{
1035 u32 i;
1036
1037 /* Disable device */
1038 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1039 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1040
1041 /* Disable all device interrupts (including EP0) */
1042 uda_disable_devint(udc, 0x3FF);
1043
1044 /* Disable and reset all endpoint interrupts */
1045 for (i = 0; i < 32; i++) {
1046 uda_disable_hwepint(udc, i);
1047 uda_clear_hwepint(udc, i);
1048 udc_disable_hwep(udc, i);
1049 udc_unrealize_hwep(udc, i);
1050 udc->udca_v_base[i] = 0;
1051
1052 /* Disable and clear all interrupts and DMA */
1053 udc_ep_dma_disable(udc, i);
1054 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1055 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1056 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1057 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1058 }
1059
1060 /* Disable DMA interrupts */
1061 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1062
1063 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1064}
1065
1066static void udc_enable(struct lpc32xx_udc *udc)
1067{
1068 u32 i;
1069 struct lpc32xx_ep *ep = &udc->ep[0];
1070
1071 /* Start with known state */
1072 udc_disable(udc);
1073
1074 /* Enable device */
1075 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1076
1077 /* EP interrupts on high priority, FRAME interrupt on low priority */
1078 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1079 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1080
1081 /* Clear any pending device interrupts */
1082 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1083
1084 /* Setup UDCA - not yet used (DMA) */
1085 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1086
1087 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1088 for (i = 0; i <= 1; i++) {
1089 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1090 uda_enable_hwepint(udc, i);
1091 udc_select_hwep(udc, i);
1092 udc_clrstall_hwep(udc, i);
1093 udc_clr_buffer_hwep(udc, i);
1094 }
1095
1096 /* Device interrupt setup */
1097 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1098 USBD_EP_FAST));
1099 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1100 USBD_EP_FAST));
1101
1102 /* Set device address to 0 - called twice to force a latch in the USB
1103 engine without the need of a setup packet status closure */
1104 udc_set_address(udc, 0);
1105 udc_set_address(udc, 0);
1106
1107 /* Enable master DMA interrupts */
1108 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1109 USBD_DMAINTEN(udc->udp_baseaddr));
1110
1111 udc->dev_status = 0;
1112}
1113
1114/*
1115 *
1116 * USB device board specific events handled via callbacks
1117 *
1118 */
1119/* Connection change event - notify board function of change */
1120static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1121{
1122 /* Just notify of a connection change event (optional) */
1123 if (udc->board->conn_chgb != NULL)
1124 udc->board->conn_chgb(conn);
1125}
1126
1127/* Suspend/resume event - notify board function of change */
1128static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1129{
1130 /* Just notify of a Suspend/resume change event (optional) */
1131 if (udc->board->susp_chgb != NULL)
1132 udc->board->susp_chgb(conn);
1133
1134 if (conn)
1135 udc->suspended = 0;
1136 else
1137 udc->suspended = 1;
1138}
1139
1140/* Remote wakeup enable/disable - notify board function of change */
1141static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1142{
1143 if (udc->board->rmwk_chgb != NULL)
1144 udc->board->rmwk_chgb(udc->dev_status &
1145 (1 << USB_DEVICE_REMOTE_WAKEUP));
1146}
1147
1148/* Reads data from FIFO, adjusts for alignment and data size */
1149static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1150{
1151 int n, i, bl;
1152 u16 *p16;
1153 u32 *p32, tmp, cbytes;
1154
1155 /* Use optimal data transfer method based on source address and size */
1156 switch (((u32) data) & 0x3) {
1157 case 0: /* 32-bit aligned */
1158 p32 = (u32 *) data;
1159 cbytes = (bytes & ~0x3);
1160
1161 /* Copy 32-bit aligned data first */
1162 for (n = 0; n < cbytes; n += 4)
1163 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1164
1165 /* Handle any remaining bytes */
1166 bl = bytes - cbytes;
1167 if (bl) {
1168 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1169 for (n = 0; n < bl; n++)
1170 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1171
1172 }
1173 break;
1174
1175 case 1: /* 8-bit aligned */
1176 case 3:
1177 /* Each byte has to be handled independently */
1178 for (n = 0; n < bytes; n += 4) {
1179 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1180
1181 bl = bytes - n;
1182 if (bl > 3)
1183 bl = 3;
1184
1185 for (i = 0; i < bl; i++)
1186 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
1187 }
1188 break;
1189
1190 case 2: /* 16-bit aligned */
1191 p16 = (u16 *) data;
1192 cbytes = (bytes & ~0x3);
1193
1194 /* Copy 32-bit sized objects first with 16-bit alignment */
1195 for (n = 0; n < cbytes; n += 4) {
1196 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1197 *p16++ = (u16)(tmp & 0xFFFF);
1198 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1199 }
1200
1201 /* Handle any remaining bytes */
1202 bl = bytes - cbytes;
1203 if (bl) {
1204 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1205 for (n = 0; n < bl; n++)
1206 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1207 }
1208 break;
1209 }
1210}
1211
1212/* Read data from the FIFO for an endpoint. This function is for endpoints (such
1213 * as EP0) that don't use DMA. This function should only be called if a packet
1214 * is known to be ready to read for the endpoint. Note that the endpoint must
1215 * be selected in the protocol engine prior to this call. */
1216static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1217 u32 bytes)
1218{
1219 u32 tmpv;
1220 int to = 1000;
1221 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1222
1223 /* Setup read of endpoint */
1224 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1225
1226 /* Wait until packet is ready */
1227 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1228 PKT_RDY) == 0) && (to > 0))
1229 to--;
1230 if (!to)
1231 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1232
1233 /* Mask out count */
1234 tmp = tmpv & PKT_LNGTH_MASK;
1235 if (bytes < tmp)
1236 tmp = bytes;
1237
1238 if ((tmp > 0) && (data != NULL))
1239 udc_pop_fifo(udc, (u8 *) data, tmp);
1240
1241 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1242
1243 /* Clear the buffer */
1244 udc_clr_buffer_hwep(udc, hwep);
1245
1246 return tmp;
1247}
1248
1249/* Stuffs data into the FIFO, adjusts for alignment and data size */
1250static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1251{
1252 int n, i, bl;
1253 u16 *p16;
1254 u32 *p32, tmp, cbytes;
1255
1256 /* Use optimal data transfer method based on source address and size */
1257 switch (((u32) data) & 0x3) {
1258 case 0: /* 32-bit aligned */
1259 p32 = (u32 *) data;
1260 cbytes = (bytes & ~0x3);
1261
1262 /* Copy 32-bit aligned data first */
1263 for (n = 0; n < cbytes; n += 4)
1264 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1265
1266 /* Handle any remaining bytes */
1267 bl = bytes - cbytes;
1268 if (bl) {
1269 tmp = 0;
1270 for (n = 0; n < bl; n++)
1271 tmp |= data[cbytes + n] << (n * 8);
1272
1273 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1274 }
1275 break;
1276
1277 case 1: /* 8-bit aligned */
1278 case 3:
1279 /* Each byte has to be handled independently */
1280 for (n = 0; n < bytes; n += 4) {
1281 bl = bytes - n;
1282 if (bl > 4)
1283 bl = 4;
1284
1285 tmp = 0;
1286 for (i = 0; i < bl; i++)
1287 tmp |= data[n + i] << (i * 8);
1288
1289 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1290 }
1291 break;
1292
1293 case 2: /* 16-bit aligned */
1294 p16 = (u16 *) data;
1295 cbytes = (bytes & ~0x3);
1296
1297 /* Copy 32-bit aligned data first */
1298 for (n = 0; n < cbytes; n += 4) {
1299 tmp = *p16++ & 0xFFFF;
1300 tmp |= (*p16++ & 0xFFFF) << 16;
1301 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1302 }
1303
1304 /* Handle any remaining bytes */
1305 bl = bytes - cbytes;
1306 if (bl) {
1307 tmp = 0;
1308 for (n = 0; n < bl; n++)
1309 tmp |= data[cbytes + n] << (n * 8);
1310
1311 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1312 }
1313 break;
1314 }
1315}
1316
1317/* Write data to the FIFO for an endpoint. This function is for endpoints (such
1318 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1319 * protocol engine prior to this call. */
1320static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1321 u32 bytes)
1322{
1323 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1324
1325 if ((bytes > 0) && (data == NULL))
1326 return;
1327
1328 /* Setup write of endpoint */
1329 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1330
1331 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1332
1333 /* Need at least 1 byte to trigger TX */
1334 if (bytes == 0)
1335 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1336 else
1337 udc_stuff_fifo(udc, (u8 *) data, bytes);
1338
1339 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1340
1341 udc_val_buffer_hwep(udc, hwep);
1342}
1343
1344/* USB device reset - resets USB to a default state with just EP0
1345 enabled */
1346static void uda_usb_reset(struct lpc32xx_udc *udc)
1347{
1348 u32 i = 0;
1349 /* Re-init device controller and EP0 */
1350 udc_enable(udc);
1351 udc->gadget.speed = USB_SPEED_FULL;
1352
1353 for (i = 1; i < NUM_ENDPOINTS; i++) {
1354 struct lpc32xx_ep *ep = &udc->ep[i];
1355 ep->req_pending = 0;
1356 }
1357}
1358
1359/* Send a ZLP on EP0 */
1360static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1361{
1362 udc_write_hwep(udc, EP_IN, NULL, 0);
1363}
1364
1365/* Get current frame number */
1366static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1367{
1368 u16 flo, fhi;
1369
1370 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1371 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1372 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1373
1374 return (fhi << 8) | flo;
1375}
1376
1377/* Set the device as configured - enables all endpoints */
1378static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1379{
1380 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1381}
1382
1383/* Set the device as unconfigured - disables all endpoints */
1384static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1385{
1386 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1387}
1388
1389/* reinit == restore initial software state */
1390static void udc_reinit(struct lpc32xx_udc *udc)
1391{
1392 u32 i;
1393
1394 INIT_LIST_HEAD(&udc->gadget.ep_list);
1395 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1396
1397 for (i = 0; i < NUM_ENDPOINTS; i++) {
1398 struct lpc32xx_ep *ep = &udc->ep[i];
1399
1400 if (i != 0)
1401 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
e117e742 1402 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
24a28e42
RS		 1403 INIT_LIST_HEAD(&ep->queue);
1404 ep->req_pending = 0;
1405 }
1406
1407 udc->ep0state = WAIT_FOR_SETUP;
1408}
1409
1410/* Must be called with lock */
1411static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1412{
1413 struct lpc32xx_udc *udc = ep->udc;
1414
1415 list_del_init(&req->queue);
1416 if (req->req.status == -EINPROGRESS)
1417 req->req.status = status;
1418 else
1419 status = req->req.status;
1420
1421 if (ep->lep) {
369ac9cb 1422 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
24a28e42
RS		 1423
1424 /* Free DDs */
1425 udc_dd_free(udc, req->dd_desc_ptr);
1426 }
1427
1428 if (status && status != -ESHUTDOWN)
1429 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1430
1431 ep->req_pending = 0;
1432 spin_unlock(&udc->lock);
304f7e5e 1433 usb_gadget_giveback_request(&ep->ep, &req->req);
24a28e42
RS		 1434 spin_lock(&udc->lock);
1435}
1436
1437/* Must be called with lock */
1438static void nuke(struct lpc32xx_ep *ep, int status)
1439{
1440 struct lpc32xx_request *req;
1441
1442 while (!list_empty(&ep->queue)) {
1443 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1444 done(ep, req, status);
1445 }
1446
78ca9139 1447 if (status == -ESHUTDOWN) {
24a28e42
RS		 1448 uda_disable_hwepint(ep->udc, ep->hwep_num);
1449 udc_disable_hwep(ep->udc, ep->hwep_num);
1450 }
1451}
1452
1453/* IN endpoint 0 transfer */
1454static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1455{
1456 struct lpc32xx_request *req;
1457 struct lpc32xx_ep *ep0 = &udc->ep[0];
1458 u32 tsend, ts = 0;
1459
1460 if (list_empty(&ep0->queue))
1461 /* Nothing to send */
1462 return 0;
1463 else
1464 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1465 queue);
1466
1467 tsend = ts = req->req.length - req->req.actual;
1468 if (ts == 0) {
1469 /* Send a ZLP */
1470 udc_ep0_send_zlp(udc);
1471 done(ep0, req, 0);
1472 return 1;
1473 } else if (ts > ep0->ep.maxpacket)
1474 ts = ep0->ep.maxpacket; /* Just send what we can */
1475
1476 /* Write data to the EP0 FIFO and start transfer */
1477 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1478
1479 /* Increment data pointer */
1480 req->req.actual += ts;
1481
1482 if (tsend >= ep0->ep.maxpacket)
1483 return 0; /* Stay in data transfer state */
1484
1485 /* Transfer request is complete */
1486 udc->ep0state = WAIT_FOR_SETUP;
1487 done(ep0, req, 0);
1488 return 1;
1489}
1490
1491/* OUT endpoint 0 transfer */
1492static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1493{
1494 struct lpc32xx_request *req;
1495 struct lpc32xx_ep *ep0 = &udc->ep[0];
1496 u32 tr, bufferspace;
1497
1498 if (list_empty(&ep0->queue))
1499 return 0;
1500 else
1501 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1502 queue);
1503
1504 if (req) {
1505 if (req->req.length == 0) {
1506 /* Just dequeue request */
1507 done(ep0, req, 0);
1508 udc->ep0state = WAIT_FOR_SETUP;
1509 return 1;
1510 }
1511
1512 /* Get data from FIFO */
1513 bufferspace = req->req.length - req->req.actual;
1514 if (bufferspace > ep0->ep.maxpacket)
1515 bufferspace = ep0->ep.maxpacket;
1516
1517 /* Copy data to buffer */
1518 prefetchw(req->req.buf + req->req.actual);
1519 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1520 bufferspace);
1521 req->req.actual += bufferspace;
1522
1523 if (tr < ep0->ep.maxpacket) {
1524 /* This is the last packet */
1525 done(ep0, req, 0);
1526 udc->ep0state = WAIT_FOR_SETUP;
1527 return 1;
1528 }
1529 }
1530
1531 return 0;
1532}
1533
1534/* Must be called with lock */
1535static void stop_activity(struct lpc32xx_udc *udc)
1536{
1537 struct usb_gadget_driver *driver = udc->driver;
1538 int i;
1539
1540 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1541 driver = NULL;
1542
1543 udc->gadget.speed = USB_SPEED_UNKNOWN;
1544 udc->suspended = 0;
1545
1546 for (i = 0; i < NUM_ENDPOINTS; i++) {
1547 struct lpc32xx_ep *ep = &udc->ep[i];
1548 nuke(ep, -ESHUTDOWN);
1549 }
1550 if (driver) {
1551 spin_unlock(&udc->lock);
1552 driver->disconnect(&udc->gadget);
1553 spin_lock(&udc->lock);
1554 }
1555
1556 isp1301_pullup_enable(udc, 0, 0);
1557 udc_disable(udc);
1558 udc_reinit(udc);
1559}
1560
1561/*
1562 * Activate or kill host pullup
1563 * Can be called with or without lock
1564 */
1565static void pullup(struct lpc32xx_udc *udc, int is_on)
1566{
1567 if (!udc->clocked)
1568 return;
1569
1570 if (!udc->enabled || !udc->vbus)
1571 is_on = 0;
1572
1573 if (is_on != udc->pullup)
1574 isp1301_pullup_enable(udc, is_on, 0);
1575}
1576
1577/* Must be called without lock */
1578static int lpc32xx_ep_disable(struct usb_ep *_ep)
1579{
1580 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1581 struct lpc32xx_udc *udc = ep->udc;
1582 unsigned long flags;
1583
1584 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1585 return -EINVAL;
1586 spin_lock_irqsave(&udc->lock, flags);
1587
1588 nuke(ep, -ESHUTDOWN);
1589
24a28e42
RS		 1590 /* Clear all DMA statuses for this EP */
1591 udc_ep_dma_disable(udc, ep->hwep_num);
1592 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1593 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1594 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1595 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1596
1597 /* Remove the DD pointer in the UDCA */
1598 udc->udca_v_base[ep->hwep_num] = 0;
1599
1600 /* Disable and reset endpoint and interrupt */
1601 uda_clear_hwepint(udc, ep->hwep_num);
1602 udc_unrealize_hwep(udc, ep->hwep_num);
1603
1604 ep->hwep_num = 0;
1605
1606 spin_unlock_irqrestore(&udc->lock, flags);
1607
1608 atomic_dec(&udc->enabled_ep_cnt);
1609 wake_up(&udc->ep_disable_wait_queue);
1610
1611 return 0;
1612}
1613
1614/* Must be called without lock */
1615static int lpc32xx_ep_enable(struct usb_ep *_ep,
1616 const struct usb_endpoint_descriptor *desc)
1617{
1618 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1619 struct lpc32xx_udc *udc = ep->udc;
1620 u16 maxpacket;
1621 u32 tmp;
1622 unsigned long flags;
1623
1624 /* Verify EP data */
78ca9139 1625 if ((!_ep) || (!ep) || (!desc) ||
24a28e42
RS		 1626 (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1627 dev_dbg(udc->dev, "bad ep or descriptor\n");
1628 return -EINVAL;
1629 }
1630 maxpacket = usb_endpoint_maxp(desc);
1631 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1632 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1633 return -EINVAL;
1634 }
1635
1636 /* Don't touch EP0 */
1637 if (ep->hwep_num_base == 0) {
1638 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1639 return -EINVAL;
1640 }
1641
1642 /* Is driver ready? */
1643 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1644 dev_dbg(udc->dev, "bogus device state\n");
1645 return -ESHUTDOWN;
1646 }
1647
1648 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1649 switch (tmp) {
1650 case USB_ENDPOINT_XFER_CONTROL:
1651 return -EINVAL;
1652
1653 case USB_ENDPOINT_XFER_INT:
1654 if (maxpacket > ep->maxpacket) {
1655 dev_dbg(udc->dev,
1656 "Bad INT endpoint maxpacket %d\n", maxpacket);
1657 return -EINVAL;
1658 }
1659 break;
1660
1661 case USB_ENDPOINT_XFER_BULK:
1662 switch (maxpacket) {
1663 case 8:
1664 case 16:
1665 case 32:
1666 case 64:
1667 break;
1668
1669 default:
1670 dev_dbg(udc->dev,
1671 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1672 return -EINVAL;
1673 }
1674 break;
1675
1676 case USB_ENDPOINT_XFER_ISOC:
1677 break;
1678 }
1679 spin_lock_irqsave(&udc->lock, flags);
1680
1681 /* Initialize endpoint to match the selected descriptor */
1682 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
24a28e42
RS		 1683 ep->ep.maxpacket = maxpacket;
1684
1685 /* Map hardware endpoint from base and direction */
1686 if (ep->is_in)
1687 /* IN endpoints are offset 1 from the OUT endpoint */
1688 ep->hwep_num = ep->hwep_num_base + EP_IN;
1689 else
1690 ep->hwep_num = ep->hwep_num_base;
1691
1692 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1693 ep->hwep_num, maxpacket, (ep->is_in == 1));
1694
1695 /* Realize the endpoint, interrupt is enabled later when
1696 * buffers are queued, IN EPs will NAK until buffers are ready */
1697 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1698 udc_clr_buffer_hwep(udc, ep->hwep_num);
1699 uda_disable_hwepint(udc, ep->hwep_num);
1700 udc_clrstall_hwep(udc, ep->hwep_num);
1701
1702 /* Clear all DMA statuses for this EP */
1703 udc_ep_dma_disable(udc, ep->hwep_num);
1704 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1705 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1706 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1707 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1708
1709 spin_unlock_irqrestore(&udc->lock, flags);
1710
1711 atomic_inc(&udc->enabled_ep_cnt);
1712 return 0;
1713}
1714
1715/*
1716 * Allocate a USB request list
1717 * Can be called with or without lock
1718 */
1719static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1720 gfp_t gfp_flags)
1721{
1722 struct lpc32xx_request *req;
1723
1724 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1725 if (!req)
1726 return NULL;
1727
1728 INIT_LIST_HEAD(&req->queue);
1729 return &req->req;
1730}
1731
1732/*
1733 * De-allocate a USB request list
1734 * Can be called with or without lock
1735 */
1736static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1737 struct usb_request *_req)
1738{
1739 struct lpc32xx_request *req;
1740
1741 req = container_of(_req, struct lpc32xx_request, req);
1742 BUG_ON(!list_empty(&req->queue));
1743 kfree(req);
1744}
1745
1746/* Must be called without lock */
1747static int lpc32xx_ep_queue(struct usb_ep *_ep,
1748 struct usb_request *_req, gfp_t gfp_flags)
1749{
1750 struct lpc32xx_request *req;
1751 struct lpc32xx_ep *ep;
1752 struct lpc32xx_udc *udc;
1753 unsigned long flags;
1754 int status = 0;
1755
1756 req = container_of(_req, struct lpc32xx_request, req);
1757 ep = container_of(_ep, struct lpc32xx_ep, ep);
1758
005a6430 1759 if (!_ep || !_req || !_req->complete || !_req->buf ||
24a28e42
RS		 1760 !list_empty(&req->queue))
1761 return -EINVAL;
1762
1763 udc = ep->udc;
1764
005a6430
PC		 1765 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1766 return -EPIPE;
24a28e42
RS		 1767
1768 if (ep->lep) {
24a28e42
RS		 1769 struct lpc32xx_usbd_dd_gad *dd;
1770
369ac9cb
FB		 1771 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1772 if (status)
1773 return status;
24a28e42
RS		 1774
1775 /* For the request, build a list of DDs */
1776 dd = udc_dd_alloc(udc);
1777 if (!dd) {
1778 /* Error allocating DD */
1779 return -ENOMEM;
1780 }
1781 req->dd_desc_ptr = dd;
1782
1783 /* Setup the DMA descriptor */
1784 dd->dd_next_phy = dd->dd_next_v = 0;
1785 dd->dd_buffer_addr = req->req.dma;
1786 dd->dd_status = 0;
1787
1788 /* Special handling for ISO EPs */
1789 if (ep->eptype == EP_ISO_TYPE) {
1790 dd->dd_setup = DD_SETUP_ISO_EP |
1791 DD_SETUP_PACKETLEN(0) |
1792 DD_SETUP_DMALENBYTES(1);
1793 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1794 if (ep->is_in)
1795 dd->iso_status[0] = req->req.length;
1796 else
1797 dd->iso_status[0] = 0;
1798 } else
1799 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1800 DD_SETUP_DMALENBYTES(req->req.length);
1801 }
1802
1803 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1804 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1805
1806 spin_lock_irqsave(&udc->lock, flags);
1807
1808 _req->status = -EINPROGRESS;
1809 _req->actual = 0;
1810 req->send_zlp = _req->zero;
1811
1812 /* Kickstart empty queues */
1813 if (list_empty(&ep->queue)) {
1814 list_add_tail(&req->queue, &ep->queue);
1815
1816 if (ep->hwep_num_base == 0) {
1817 /* Handle expected data direction */
1818 if (ep->is_in) {
1819 /* IN packet to host */
1820 udc->ep0state = DATA_IN;
1821 status = udc_ep0_in_req(udc);
1822 } else {
1823 /* OUT packet from host */
1824 udc->ep0state = DATA_OUT;
1825 status = udc_ep0_out_req(udc);
1826 }
1827 } else if (ep->is_in) {
1828 /* IN packet to host and kick off transfer */
1829 if (!ep->req_pending)
1830 udc_ep_in_req_dma(udc, ep);
1831 } else
1832 /* OUT packet from host and kick off list */
1833 if (!ep->req_pending)
1834 udc_ep_out_req_dma(udc, ep);
1835 } else
1836 list_add_tail(&req->queue, &ep->queue);
1837
1838 spin_unlock_irqrestore(&udc->lock, flags);
1839
1840 return (status < 0) ? status : 0;
1841}
1842
1843/* Must be called without lock */
1844static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1845{
1846 struct lpc32xx_ep *ep;
1847 struct lpc32xx_request *req;
1848 unsigned long flags;
1849
1850 ep = container_of(_ep, struct lpc32xx_ep, ep);
1851 if (!_ep || ep->hwep_num_base == 0)
1852 return -EINVAL;
1853
1854 spin_lock_irqsave(&ep->udc->lock, flags);
1855
1856 /* make sure it's actually queued on this endpoint */
1857 list_for_each_entry(req, &ep->queue, queue) {
1858 if (&req->req == _req)
1859 break;
1860 }
1861 if (&req->req != _req) {
1862 spin_unlock_irqrestore(&ep->udc->lock, flags);
1863 return -EINVAL;
1864 }
1865
1866 done(ep, req, -ECONNRESET);
1867
1868 spin_unlock_irqrestore(&ep->udc->lock, flags);
1869
1870 return 0;
1871}
1872
1873/* Must be called without lock */
1874static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1875{
1876 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1877 struct lpc32xx_udc *udc = ep->udc;
1878 unsigned long flags;
1879
78ca9139 1880 if ((!ep) || (ep->hwep_num <= 1))
24a28e42
RS		 1881 return -EINVAL;
1882
1883 /* Don't halt an IN EP */
1884 if (ep->is_in)
1885 return -EAGAIN;
1886
1887 spin_lock_irqsave(&udc->lock, flags);
1888
1889 if (value == 1) {
1890 /* stall */
1891 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1892 DAT_WR_BYTE(EP_STAT_ST));
1893 } else {
1894 /* End stall */
1895 ep->wedge = 0;
1896 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1897 DAT_WR_BYTE(0));
1898 }
1899
1900 spin_unlock_irqrestore(&udc->lock, flags);
1901
1902 return 0;
1903}
1904
1905/* set the halt feature and ignores clear requests */
1906static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1907{
1908 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1909
1910 if (!_ep || !ep->udc)
1911 return -EINVAL;
1912
1913 ep->wedge = 1;
1914
1915 return usb_ep_set_halt(_ep);
1916}
1917
1918static const struct usb_ep_ops lpc32xx_ep_ops = {
1919 .enable = lpc32xx_ep_enable,
1920 .disable = lpc32xx_ep_disable,
1921 .alloc_request = lpc32xx_ep_alloc_request,
1922 .free_request = lpc32xx_ep_free_request,
1923 .queue = lpc32xx_ep_queue,
1924 .dequeue = lpc32xx_ep_dequeue,
1925 .set_halt = lpc32xx_ep_set_halt,
1926 .set_wedge = lpc32xx_ep_set_wedge,
1927};
1928
1929/* Send a ZLP on a non-0 IN EP */
1930void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1931{
1932 /* Clear EP status */
1933 udc_clearep_getsts(udc, ep->hwep_num);
1934
1935 /* Send ZLP via FIFO mechanism */
1936 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1937}
1938
1939/*
1940 * Handle EP completion for ZLP
1941 * This function will only be called when a delayed ZLP needs to be sent out
1942 * after a DMA transfer has filled both buffers.
1943 */
1944void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1945{
1946 u32 epstatus;
1947 struct lpc32xx_request *req;
1948
1949 if (ep->hwep_num <= 0)
1950 return;
1951
1952 uda_clear_hwepint(udc, ep->hwep_num);
1953
1954 /* If this interrupt isn't enabled, return now */
1955 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1956 return;
1957
1958 /* Get endpoint status */
1959 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1960
1961 /*
1962 * This should never happen, but protect against writing to the
1963 * buffer when full.
1964 */
1965 if (epstatus & EP_SEL_F)
1966 return;
1967
1968 if (ep->is_in) {
1969 udc_send_in_zlp(udc, ep);
1970 uda_disable_hwepint(udc, ep->hwep_num);
1971 } else
1972 return;
1973
1974 /* If there isn't a request waiting, something went wrong */
1975 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1976 if (req) {
1977 done(ep, req, 0);
1978
1979 /* Start another request if ready */
1980 if (!list_empty(&ep->queue)) {
1981 if (ep->is_in)
1982 udc_ep_in_req_dma(udc, ep);
1983 else
1984 udc_ep_out_req_dma(udc, ep);
1985 } else
1986 ep->req_pending = 0;
1987 }
1988}
1989
1990
1991/* DMA end of transfer completion */
1992static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1993{
1994 u32 status, epstatus;
1995 struct lpc32xx_request *req;
1996 struct lpc32xx_usbd_dd_gad *dd;
1997
1998#ifdef CONFIG_USB_GADGET_DEBUG_FILES
1999 ep->totalints++;
2000#endif
2001
2002 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2003 if (!req) {
2004 ep_err(ep, "DMA interrupt on no req!\n");
2005 return;
2006 }
2007 dd = req->dd_desc_ptr;
2008
2009 /* DMA descriptor should always be retired for this call */
2010 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2011 ep_warn(ep, "DMA descriptor did not retire\n");
2012
2013 /* Disable DMA */
2014 udc_ep_dma_disable(udc, ep->hwep_num);
2015 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2016 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2017
2018 /* System error? */
2019 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2020 (1 << ep->hwep_num)) {
2021 writel((1 << ep->hwep_num),
2022 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2023 ep_err(ep, "AHB critical error!\n");
2024 ep->req_pending = 0;
2025
2026 /* The error could have occurred on a packet of a multipacket
2027 * transfer, so recovering the transfer is not possible. Close
2028 * the request with an error */
2029 done(ep, req, -ECONNABORTED);
2030 return;
2031 }
2032
2033 /* Handle the current DD's status */
2034 status = dd->dd_status;
2035 switch (status & DD_STATUS_STS_MASK) {
2036 case DD_STATUS_STS_NS:
2037 /* DD not serviced? This shouldn't happen! */
2038 ep->req_pending = 0;
2039 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2040 status);
2041
2042 done(ep, req, -ECONNABORTED);
2043 return;
2044
2045 case DD_STATUS_STS_BS:
2046 /* Interrupt only fires on EOT - This shouldn't happen! */
2047 ep->req_pending = 0;
2048 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2049 status);
2050 done(ep, req, -ECONNABORTED);
2051 return;
2052
2053 case DD_STATUS_STS_NC:
2054 case DD_STATUS_STS_DUR:
2055 /* Really just a short packet, not an underrun */
2056 /* This is a good status and what we expect */
2057 break;
2058
2059 default:
2060 /* Data overrun, system error, or unknown */
2061 ep->req_pending = 0;
2062 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2063 status);
2064 done(ep, req, -ECONNABORTED);
2065 return;
2066 }
2067
2068 /* ISO endpoints are handled differently */
2069 if (ep->eptype == EP_ISO_TYPE) {
2070 if (ep->is_in)
2071 req->req.actual = req->req.length;
2072 else
2073 req->req.actual = dd->iso_status[0] & 0xFFFF;
2074 } else
2075 req->req.actual += DD_STATUS_CURDMACNT(status);
2076
2077 /* Send a ZLP if necessary. This will be done for non-int
2078 * packets which have a size that is a divisor of MAXP */
2079 if (req->send_zlp) {
2080 /*
2081 * If at least 1 buffer is available, send the ZLP now.
2082 * Otherwise, the ZLP send needs to be deferred until a
2083 * buffer is available.
2084 */
2085 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2086 udc_clearep_getsts(udc, ep->hwep_num);
2087 uda_enable_hwepint(udc, ep->hwep_num);
2088 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2089
2090 /* Let the EP interrupt handle the ZLP */
2091 return;
2092 } else
2093 udc_send_in_zlp(udc, ep);
2094 }
2095
2096 /* Transfer request is complete */
2097 done(ep, req, 0);
2098
2099 /* Start another request if ready */
2100 udc_clearep_getsts(udc, ep->hwep_num);
2101 if (!list_empty((&ep->queue))) {
2102 if (ep->is_in)
2103 udc_ep_in_req_dma(udc, ep);
2104 else
2105 udc_ep_out_req_dma(udc, ep);
2106 } else
2107 ep->req_pending = 0;
2108
2109}
2110
2111/*
2112 *
2113 * Endpoint 0 functions
2114 *
2115 */
2116static void udc_handle_dev(struct lpc32xx_udc *udc)
2117{
2118 u32 tmp;
2119
2120 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2121 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2122
2123 if (tmp & DEV_RST)
2124 uda_usb_reset(udc);
2125 else if (tmp & DEV_CON_CH)
2126 uda_power_event(udc, (tmp & DEV_CON));
2127 else if (tmp & DEV_SUS_CH) {
2128 if (tmp & DEV_SUS) {
2129 if (udc->vbus == 0)
2130 stop_activity(udc);
2131 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2132 udc->driver) {
2133 /* Power down transceiver */
2134 udc->poweron = 0;
2135 schedule_work(&udc->pullup_job);
2136 uda_resm_susp_event(udc, 1);
2137 }
2138 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2139 udc->driver && udc->vbus) {
2140 uda_resm_susp_event(udc, 0);
2141 /* Power up transceiver */
2142 udc->poweron = 1;
2143 schedule_work(&udc->pullup_job);
2144 }
2145 }
2146}
2147
2148static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2149{
2150 struct lpc32xx_ep *ep;
2151 u32 ep0buff = 0, tmp;
2152
2153 switch (reqtype & USB_RECIP_MASK) {
2154 case USB_RECIP_INTERFACE:
2155 break; /* Not supported */
2156
2157 case USB_RECIP_DEVICE:
d60d9392 2158 ep0buff = udc->gadget.is_selfpowered;
24a28e42
RS		 2159 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2160 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2161 break;
2162
2163 case USB_RECIP_ENDPOINT:
2164 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2165 ep = &udc->ep[tmp];
78ca9139 2166 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
24a28e42
RS		 2167 return -EOPNOTSUPP;
2168
2169 if (wIndex & USB_DIR_IN) {
2170 if (!ep->is_in)
2171 return -EOPNOTSUPP; /* Something's wrong */
2172 } else if (ep->is_in)
2173 return -EOPNOTSUPP; /* Not an IN endpoint */
2174
2175 /* Get status of the endpoint */
2176 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2177 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2178
2179 if (tmp & EP_SEL_ST)
2180 ep0buff = (1 << USB_ENDPOINT_HALT);
2181 else
2182 ep0buff = 0;
2183 break;
2184
2185 default:
2186 break;
2187 }
2188
2189 /* Return data */
2190 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2191
2192 return 0;
2193}
2194
2195static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2196{
2197 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2198 struct usb_ctrlrequest ctrlpkt;
2199 int i, bytes;
2200 u16 wIndex, wValue, wLength, reqtype, req, tmp;
2201
2202 /* Nuke previous transfers */
2203 nuke(ep0, -EPROTO);
2204
2205 /* Get setup packet */
2206 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2207 if (bytes != 8) {
2208 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2209 bytes);
2210 return;
2211 }
2212
2213 /* Native endianness */
2214 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2215 wValue = le16_to_cpu(ctrlpkt.wValue);
2216 wLength = le16_to_cpu(ctrlpkt.wLength);
2217 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2218
2219 /* Set direction of EP0 */
2220 if (likely(reqtype & USB_DIR_IN))
2221 ep0->is_in = 1;
2222 else
2223 ep0->is_in = 0;
2224
2225 /* Handle SETUP packet */
2226 req = le16_to_cpu(ctrlpkt.bRequest);
2227 switch (req) {
2228 case USB_REQ_CLEAR_FEATURE:
2229 case USB_REQ_SET_FEATURE:
2230 switch (reqtype) {
2231 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2232 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2233 goto stall; /* Nothing else handled */
2234
2235 /* Tell board about event */
2236 if (req == USB_REQ_CLEAR_FEATURE)
2237 udc->dev_status &=
2238 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2239 else
2240 udc->dev_status |=
2241 (1 << USB_DEVICE_REMOTE_WAKEUP);
2242 uda_remwkp_cgh(udc);
2243 goto zlp_send;
2244
2245 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2246 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2247 if ((wValue != USB_ENDPOINT_HALT) ||
2248 (tmp >= NUM_ENDPOINTS))
2249 break;
2250
2251 /* Find hardware endpoint from logical endpoint */
2252 ep = &udc->ep[tmp];
2253 tmp = ep->hwep_num;
2254 if (tmp == 0)
2255 break;
2256
2257 if (req == USB_REQ_SET_FEATURE)
2258 udc_stall_hwep(udc, tmp);
2259 else if (!ep->wedge)
2260 udc_clrstall_hwep(udc, tmp);
2261
2262 goto zlp_send;
2263
2264 default:
2265 break;
2266 }
2267
2268
2269 case USB_REQ_SET_ADDRESS:
2270 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2271 udc_set_address(udc, wValue);
2272 goto zlp_send;
2273 }
2274 break;
2275
2276 case USB_REQ_GET_STATUS:
2277 udc_get_status(udc, reqtype, wIndex);
2278 return;
2279
2280 default:
2281 break; /* Let GadgetFS handle the descriptor instead */
2282 }
2283
2284 if (likely(udc->driver)) {
2285 /* device-2-host (IN) or no data setup command, process
2286 * immediately */
2287 spin_unlock(&udc->lock);
2288 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2289
2290 spin_lock(&udc->lock);
2291 if (req == USB_REQ_SET_CONFIGURATION) {
2292 /* Configuration is set after endpoints are realized */
2293 if (wValue) {
2294 /* Set configuration */
2295 udc_set_device_configured(udc);
2296
2297 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2298 DAT_WR_BYTE(AP_CLK |
2299 INAK_BI | INAK_II));
2300 } else {
2301 /* Clear configuration */
2302 udc_set_device_unconfigured(udc);
2303
2304 /* Disable NAK interrupts */
2305 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2306 DAT_WR_BYTE(AP_CLK));
2307 }
2308 }
2309
2310 if (i < 0) {
2311 /* setup processing failed, force stall */
0696f929 2312 dev_dbg(udc->dev,
24a28e42
RS		 2313 "req %02x.%02x protocol STALL; stat %d\n",
2314 reqtype, req, i);
2315 udc->ep0state = WAIT_FOR_SETUP;
2316 goto stall;
2317 }
2318 }
2319
2320 if (!ep0->is_in)
2321 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2322
2323 return;
2324
2325stall:
2326 udc_stall_hwep(udc, EP_IN);
2327 return;
2328
2329zlp_send:
2330 udc_ep0_send_zlp(udc);
2331 return;
2332}
2333
2334/* IN endpoint 0 transfer */
2335static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2336{
2337 struct lpc32xx_ep *ep0 = &udc->ep[0];
2338 u32 epstatus;
2339
2340 /* Clear EP interrupt */
2341 epstatus = udc_clearep_getsts(udc, EP_IN);
2342
2343#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2344 ep0->totalints++;
2345#endif
2346
2347 /* Stalled? Clear stall and reset buffers */
2348 if (epstatus & EP_SEL_ST) {
2349 udc_clrstall_hwep(udc, EP_IN);
2350 nuke(ep0, -ECONNABORTED);
2351 udc->ep0state = WAIT_FOR_SETUP;
2352 return;
2353 }
2354
2355 /* Is a buffer available? */
2356 if (!(epstatus & EP_SEL_F)) {
2357 /* Handle based on current state */
2358 if (udc->ep0state == DATA_IN)
2359 udc_ep0_in_req(udc);
2360 else {
2361 /* Unknown state for EP0 oe end of DATA IN phase */
2362 nuke(ep0, -ECONNABORTED);
2363 udc->ep0state = WAIT_FOR_SETUP;
2364 }
2365 }
2366}
2367
2368/* OUT endpoint 0 transfer */
2369static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2370{
2371 struct lpc32xx_ep *ep0 = &udc->ep[0];
2372 u32 epstatus;
2373
2374 /* Clear EP interrupt */
2375 epstatus = udc_clearep_getsts(udc, EP_OUT);
2376
2377
2378#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2379 ep0->totalints++;
2380#endif
2381
2382 /* Stalled? */
2383 if (epstatus & EP_SEL_ST) {
2384 udc_clrstall_hwep(udc, EP_OUT);
2385 nuke(ep0, -ECONNABORTED);
2386 udc->ep0state = WAIT_FOR_SETUP;
2387 return;
2388 }
2389
2390 /* A NAK may occur if a packet couldn't be received yet */
2391 if (epstatus & EP_SEL_EPN)
2392 return;
2393 /* Setup packet incoming? */
2394 if (epstatus & EP_SEL_STP) {
2395 nuke(ep0, 0);
2396 udc->ep0state = WAIT_FOR_SETUP;
2397 }
2398
2399 /* Data available? */
2400 if (epstatus & EP_SEL_F)
2401 /* Handle based on current state */
2402 switch (udc->ep0state) {
2403 case WAIT_FOR_SETUP:
2404 udc_handle_ep0_setup(udc);
2405 break;
2406
2407 case DATA_OUT:
2408 udc_ep0_out_req(udc);
2409 break;
2410
2411 default:
2412 /* Unknown state for EP0 */
2413 nuke(ep0, -ECONNABORTED);
2414 udc->ep0state = WAIT_FOR_SETUP;
2415 }
2416}
2417
2418/* Must be called without lock */
2419static int lpc32xx_get_frame(struct usb_gadget *gadget)
2420{
2421 int frame;
2422 unsigned long flags;
2423 struct lpc32xx_udc *udc = to_udc(gadget);
2424
2425 if (!udc->clocked)
2426 return -EINVAL;
2427
2428 spin_lock_irqsave(&udc->lock, flags);
2429
2430 frame = (int) udc_get_current_frame(udc);
2431
2432 spin_unlock_irqrestore(&udc->lock, flags);
2433
2434 return frame;
2435}
2436
2437static int lpc32xx_wakeup(struct usb_gadget *gadget)
2438{
2439 return -ENOTSUPP;
2440}
2441
2442static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2443{
d60d9392 2444 gadget->is_selfpowered = (is_on != 0);
24a28e42
RS		 2445
2446 return 0;
2447}
2448
2449/*
2450 * vbus is here! turn everything on that's ready
2451 * Must be called without lock
2452 */
2453static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2454{
2455 unsigned long flags;
2456 struct lpc32xx_udc *udc = to_udc(gadget);
2457
2458 spin_lock_irqsave(&udc->lock, flags);
2459
2460 /* Doesn't need lock */
2461 if (udc->driver) {
2462 udc_clk_set(udc, 1);
2463 udc_enable(udc);
2464 pullup(udc, is_active);
2465 } else {
2466 stop_activity(udc);
2467 pullup(udc, 0);
2468
2469 spin_unlock_irqrestore(&udc->lock, flags);
2470 /*
2471 * Wait for all the endpoints to disable,
2472 * before disabling clocks. Don't wait if
2473 * endpoints are not enabled.
2474 */
2475 if (atomic_read(&udc->enabled_ep_cnt))
2476 wait_event_interruptible(udc->ep_disable_wait_queue,
2477 (atomic_read(&udc->enabled_ep_cnt) == 0));
2478
2479 spin_lock_irqsave(&udc->lock, flags);
2480
2481 udc_clk_set(udc, 0);
2482 }
2483
2484 spin_unlock_irqrestore(&udc->lock, flags);
2485
2486 return 0;
2487}
2488
2489/* Can be called with or without lock */
2490static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2491{
2492 struct lpc32xx_udc *udc = to_udc(gadget);
2493
2494 /* Doesn't need lock */
2495 pullup(udc, is_on);
2496
2497 return 0;
2498}
2499
252d8cec 2500static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
22835b80 2501static int lpc32xx_stop(struct usb_gadget *);
24a28e42
RS		 2502
2503static const struct usb_gadget_ops lpc32xx_udc_ops = {
2504 .get_frame = lpc32xx_get_frame,
2505 .wakeup = lpc32xx_wakeup,
2506 .set_selfpowered = lpc32xx_set_selfpowered,
2507 .vbus_session = lpc32xx_vbus_session,
2508 .pullup = lpc32xx_pullup,
252d8cec
RS		 2509 .udc_start = lpc32xx_start,
2510 .udc_stop = lpc32xx_stop,
24a28e42
RS		 2511};
2512
2513static void nop_release(struct device *dev)
2514{
2515 /* nothing to free */
2516}
2517
c4846a18 2518static const struct lpc32xx_udc controller_template = {
24a28e42
RS		 2519 .gadget = {
2520 .ops = &lpc32xx_udc_ops,
24a28e42
RS		 2521 .name = driver_name,
2522 .dev = {
2523 .init_name = "gadget",
2524 .release = nop_release,
2525 }
2526 },
2527 .ep[0] = {
2528 .ep = {
2529 .name = "ep0",
2530 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2531 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2532 USB_EP_CAPS_DIR_ALL),
24a28e42 2533 },
24a28e42
RS		 2534 .maxpacket = 64,
2535 .hwep_num_base = 0,
2536 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2537 .lep = 0,
2538 .eptype = EP_CTL_TYPE,
2539 },
2540 .ep[1] = {
2541 .ep = {
2542 .name = "ep1-int",
2543 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2544 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2545 USB_EP_CAPS_DIR_ALL),
24a28e42 2546 },
24a28e42
RS		 2547 .maxpacket = 64,
2548 .hwep_num_base = 2,
2549 .hwep_num = 0, /* 2 or 3, will be set later */
2550 .lep = 1,
2551 .eptype = EP_INT_TYPE,
2552 },
2553 .ep[2] = {
2554 .ep = {
2555 .name = "ep2-bulk",
2556 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2557 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2558 USB_EP_CAPS_DIR_ALL),
24a28e42 2559 },
24a28e42
RS		 2560 .maxpacket = 64,
2561 .hwep_num_base = 4,
2562 .hwep_num = 0, /* 4 or 5, will be set later */
2563 .lep = 2,
2564 .eptype = EP_BLK_TYPE,
2565 },
2566 .ep[3] = {
2567 .ep = {
2568 .name = "ep3-iso",
2569 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2570 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2571 USB_EP_CAPS_DIR_ALL),
24a28e42 2572 },
24a28e42
RS		 2573 .maxpacket = 1023,
2574 .hwep_num_base = 6,
2575 .hwep_num = 0, /* 6 or 7, will be set later */
2576 .lep = 3,
2577 .eptype = EP_ISO_TYPE,
2578 },
2579 .ep[4] = {
2580 .ep = {
2581 .name = "ep4-int",
2582 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2583 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2584 USB_EP_CAPS_DIR_ALL),
24a28e42 2585 },
24a28e42
RS		 2586 .maxpacket = 64,
2587 .hwep_num_base = 8,
2588 .hwep_num = 0, /* 8 or 9, will be set later */
2589 .lep = 4,
2590 .eptype = EP_INT_TYPE,
2591 },
2592 .ep[5] = {
2593 .ep = {
2594 .name = "ep5-bulk",
2595 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2596 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2597 USB_EP_CAPS_DIR_ALL),
24a28e42 2598 },
24a28e42
RS		 2599 .maxpacket = 64,
2600 .hwep_num_base = 10,
2601 .hwep_num = 0, /* 10 or 11, will be set later */
2602 .lep = 5,
2603 .eptype = EP_BLK_TYPE,
2604 },
2605 .ep[6] = {
2606 .ep = {
2607 .name = "ep6-iso",
2608 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2609 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2610 USB_EP_CAPS_DIR_ALL),
24a28e42 2611 },
24a28e42
RS		 2612 .maxpacket = 1023,
2613 .hwep_num_base = 12,
2614 .hwep_num = 0, /* 12 or 13, will be set later */
2615 .lep = 6,
2616 .eptype = EP_ISO_TYPE,
2617 },
2618 .ep[7] = {
2619 .ep = {
2620 .name = "ep7-int",
2621 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2622 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2623 USB_EP_CAPS_DIR_ALL),
24a28e42 2624 },
24a28e42
RS		 2625 .maxpacket = 64,
2626 .hwep_num_base = 14,
2627 .hwep_num = 0,
2628 .lep = 7,
2629 .eptype = EP_INT_TYPE,
2630 },
2631 .ep[8] = {
2632 .ep = {
2633 .name = "ep8-bulk",
2634 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2635 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2636 USB_EP_CAPS_DIR_ALL),
24a28e42 2637 },
24a28e42
RS		 2638 .maxpacket = 64,
2639 .hwep_num_base = 16,
2640 .hwep_num = 0,
2641 .lep = 8,
2642 .eptype = EP_BLK_TYPE,
2643 },
2644 .ep[9] = {
2645 .ep = {
2646 .name = "ep9-iso",
2647 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2648 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2649 USB_EP_CAPS_DIR_ALL),
24a28e42 2650 },
24a28e42
RS		 2651 .maxpacket = 1023,
2652 .hwep_num_base = 18,
2653 .hwep_num = 0,
2654 .lep = 9,
2655 .eptype = EP_ISO_TYPE,
2656 },
2657 .ep[10] = {
2658 .ep = {
2659 .name = "ep10-int",
2660 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2661 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2662 USB_EP_CAPS_DIR_ALL),
24a28e42 2663 },
24a28e42
RS		 2664 .maxpacket = 64,
2665 .hwep_num_base = 20,
2666 .hwep_num = 0,
2667 .lep = 10,
2668 .eptype = EP_INT_TYPE,
2669 },
2670 .ep[11] = {
2671 .ep = {
2672 .name = "ep11-bulk",
2673 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2674 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2675 USB_EP_CAPS_DIR_ALL),
24a28e42 2676 },
24a28e42
RS		 2677 .maxpacket = 64,
2678 .hwep_num_base = 22,
2679 .hwep_num = 0,
2680 .lep = 11,
2681 .eptype = EP_BLK_TYPE,
2682 },
2683 .ep[12] = {
2684 .ep = {
2685 .name = "ep12-iso",
2686 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2687 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2688 USB_EP_CAPS_DIR_ALL),
24a28e42 2689 },
24a28e42
RS		 2690 .maxpacket = 1023,
2691 .hwep_num_base = 24,
2692 .hwep_num = 0,
2693 .lep = 12,
2694 .eptype = EP_ISO_TYPE,
2695 },
2696 .ep[13] = {
2697 .ep = {
2698 .name = "ep13-int",
2699 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2700 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2701 USB_EP_CAPS_DIR_ALL),
24a28e42 2702 },
24a28e42
RS		 2703 .maxpacket = 64,
2704 .hwep_num_base = 26,
2705 .hwep_num = 0,
2706 .lep = 13,
2707 .eptype = EP_INT_TYPE,
2708 },
2709 .ep[14] = {
2710 .ep = {
2711 .name = "ep14-bulk",
2712 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2713 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2714 USB_EP_CAPS_DIR_ALL),
24a28e42 2715 },
24a28e42
RS		 2716 .maxpacket = 64,
2717 .hwep_num_base = 28,
2718 .hwep_num = 0,
2719 .lep = 14,
2720 .eptype = EP_BLK_TYPE,
2721 },
2722 .ep[15] = {
2723 .ep = {
2724 .name = "ep15-bulk",
2725 .ops = &lpc32xx_ep_ops,
4d75c8bd
RB		 2726 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2727 USB_EP_CAPS_DIR_ALL),
24a28e42 2728 },
24a28e42
RS		 2729 .maxpacket = 1023,
2730 .hwep_num_base = 30,
2731 .hwep_num = 0,
2732 .lep = 15,
2733 .eptype = EP_BLK_TYPE,
2734 },
2735};
2736
2737/* ISO and status interrupts */
2738static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2739{
2740 u32 tmp, devstat;
2741 struct lpc32xx_udc *udc = _udc;
2742
2743 spin_lock(&udc->lock);
2744
2745 /* Read the device status register */
2746 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2747
2748 devstat &= ~USBD_EP_FAST;
2749 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2750 devstat = devstat & udc->enabled_devints;
2751
2752 /* Device specific handling needed? */
2753 if (devstat & USBD_DEV_STAT)
2754 udc_handle_dev(udc);
2755
2756 /* Start of frame? (devstat & FRAME_INT):
2757 * The frame interrupt isn't really needed for ISO support,
2758 * as the driver will queue the necessary packets */
2759
2760 /* Error? */
2761 if (devstat & ERR_INT) {
2762 /* All types of errors, from cable removal during transfer to
2763 * misc protocol and bit errors. These are mostly for just info,
2764 * as the USB hardware will work around these. If these errors
2765 * happen alot, something is wrong. */
2766 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2767 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2768 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2769 }
2770
2771 spin_unlock(&udc->lock);
2772
2773 return IRQ_HANDLED;
2774}
2775
2776/* EP interrupts */
2777static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2778{
2779 u32 tmp;
2780 struct lpc32xx_udc *udc = _udc;
2781
2782 spin_lock(&udc->lock);
2783
2784 /* Read the device status register */
2785 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2786
2787 /* Endpoints */
2788 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2789
2790 /* Special handling for EP0 */
2791 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2792 /* Handle EP0 IN */
2793 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2794 udc_handle_ep0_in(udc);
2795
2796 /* Handle EP0 OUT */
2797 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2798 udc_handle_ep0_out(udc);
2799 }
2800
2801 /* All other EPs */
2802 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2803 int i;
2804
2805 /* Handle other EP interrupts */
2806 for (i = 1; i < NUM_ENDPOINTS; i++) {
2807 if (tmp & (1 << udc->ep[i].hwep_num))
2808 udc_handle_eps(udc, &udc->ep[i]);
2809 }
2810 }
2811
2812 spin_unlock(&udc->lock);
2813
2814 return IRQ_HANDLED;
2815}
2816
2817static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2818{
2819 struct lpc32xx_udc *udc = _udc;
2820
2821 int i;
2822 u32 tmp;
2823
2824 spin_lock(&udc->lock);
2825
2826 /* Handle EP DMA EOT interrupts */
2827 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2828 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2829 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2830 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2831 for (i = 1; i < NUM_ENDPOINTS; i++) {
2832 if (tmp & (1 << udc->ep[i].hwep_num))
2833 udc_handle_dma_ep(udc, &udc->ep[i]);
2834 }
2835
2836 spin_unlock(&udc->lock);
2837
2838 return IRQ_HANDLED;
2839}
2840
2841/*
2842 *
2843 * VBUS detection, pullup handler, and Gadget cable state notification
2844 *
2845 */
2846static void vbus_work(struct work_struct *work)
2847{
2848 u8 value;
2849 struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
2850 vbus_job);
2851
2852 if (udc->enabled != 0) {
2853 /* Discharge VBUS real quick */
2854 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2855 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2856
2857 /* Give VBUS some time (100mS) to discharge */
2858 msleep(100);
2859
2860 /* Disable VBUS discharge resistor */
2861 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2862 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2863 OTG1_VBUS_DISCHRG);
2864
2865 /* Clear interrupt */
2866 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2867 ISP1301_I2C_INTERRUPT_LATCH |
2868 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2869
2870 /* Get the VBUS status from the transceiver */
2871 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
69da85ed 2872 ISP1301_I2C_INTERRUPT_SOURCE);
24a28e42
RS		 2873
2874 /* VBUS on or off? */
69da85ed 2875 if (value & INT_SESS_VLD)
24a28e42
RS		 2876 udc->vbus = 1;
2877 else
2878 udc->vbus = 0;
2879
2880 /* VBUS changed? */
2881 if (udc->last_vbus != udc->vbus) {
2882 udc->last_vbus = udc->vbus;
2883 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2884 }
2885 }
2886
2887 /* Re-enable after completion */
2888 enable_irq(udc->udp_irq[IRQ_USB_ATX]);
2889}
2890
2891static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2892{
2893 struct lpc32xx_udc *udc = _udc;
2894
2895 /* Defer handling of VBUS IRQ to work queue */
2896 disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
2897 schedule_work(&udc->vbus_job);
2898
2899 return IRQ_HANDLED;
2900}
2901
252d8cec
RS		 2902static int lpc32xx_start(struct usb_gadget *gadget,
2903 struct usb_gadget_driver *driver)
24a28e42 2904{
252d8cec
RS		 2905 struct lpc32xx_udc *udc = to_udc(gadget);
2906 int i;
24a28e42 2907
252d8cec 2908 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
24a28e42
RS		 2909 dev_err(udc->dev, "bad parameter.\n");
2910 return -EINVAL;
2911 }
2912
2913 if (udc->driver) {
2914 dev_err(udc->dev, "UDC already has a gadget driver\n");
2915 return -EBUSY;
2916 }
2917
2918 udc->driver = driver;
eebc0d36 2919 udc->gadget.dev.of_node = udc->dev->of_node;
24a28e42 2920 udc->enabled = 1;
d60d9392 2921 udc->gadget.is_selfpowered = 1;
24a28e42
RS		 2922 udc->vbus = 0;
2923
24a28e42
RS		 2924 /* Force VBUS process once to check for cable insertion */
2925 udc->last_vbus = udc->vbus = 0;
2926 schedule_work(&udc->vbus_job);
2927
2928 /* Do not re-enable ATX IRQ (3) */
2929 for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
2930 enable_irq(udc->udp_irq[i]);
2931
2932 return 0;
2933}
2934
22835b80 2935static int lpc32xx_stop(struct usb_gadget *gadget)
24a28e42
RS		 2936{
2937 int i;
252d8cec 2938 struct lpc32xx_udc *udc = to_udc(gadget);
24a28e42 2939
24a28e42
RS		 2940 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
2941 disable_irq(udc->udp_irq[i]);
2942
2943 if (udc->clocked) {
24a28e42
RS		 2944 spin_lock(&udc->lock);
2945 stop_activity(udc);
2946 spin_unlock(&udc->lock);
2947
2948 /*
2949 * Wait for all the endpoints to disable,
2950 * before disabling clocks. Don't wait if
2951 * endpoints are not enabled.
2952 */
2953 if (atomic_read(&udc->enabled_ep_cnt))
2954 wait_event_interruptible(udc->ep_disable_wait_queue,
2955 (atomic_read(&udc->enabled_ep_cnt) == 0));
2956
2957 spin_lock(&udc->lock);
2958 udc_clk_set(udc, 0);
2959 spin_unlock(&udc->lock);
2960 }
2961
2962 udc->enabled = 0;
24a28e42
RS		 2963 udc->driver = NULL;
2964
24a28e42
RS		 2965 return 0;
2966}
2967
2968static void lpc32xx_udc_shutdown(struct platform_device *dev)
2969{
2970 /* Force disconnect on reboot */
252d8cec 2971 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
24a28e42
RS		 2972
2973 pullup(udc, 0);
2974}
2975
2976/*
2977 * Callbacks to be overridden by options passed via OF (TODO)
2978 */
2979
2980static void lpc32xx_usbd_conn_chg(int conn)
2981{
2982 /* Do nothing, it might be nice to enable an LED
2983 * based on conn state being !0 */
2984}
2985
2986static void lpc32xx_usbd_susp_chg(int susp)
2987{
2988 /* Device suspend if susp != 0 */
2989}
2990
2991static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2992{
2993 /* Enable or disable USB remote wakeup */
2994}
2995
2996struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2997 .vbus_drv_pol = 0,
2998 .conn_chgb = &lpc32xx_usbd_conn_chg,
2999 .susp_chgb = &lpc32xx_usbd_susp_chg,
3000 .rmwk_chgb = &lpc32xx_rmwkup_chg,
3001};
3002
3003
3004static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
3005
b1a7c4f2 3006static int lpc32xx_udc_probe(struct platform_device *pdev)
24a28e42
RS		 3007{
3008 struct device *dev = &pdev->dev;
c4846a18 3009 struct lpc32xx_udc *udc;
24a28e42
RS		 3010 int retval, i;
3011 struct resource *res;
3012 dma_addr_t dma_handle;
3013 struct device_node *isp1301_node;
3014
58b949e0 3015 udc = kmemdup(&controller_template, sizeof(*udc), GFP_KERNEL);
c4846a18
RS		 3016 if (!udc)
3017 return -ENOMEM;
3018
c4846a18
RS		 3019 for (i = 0; i <= 15; i++)
3020 udc->ep[i].udc = udc;
3021 udc->gadget.ep0 = &udc->ep[0].ep;
3022
24a28e42
RS		 3023 /* init software state */
3024 udc->gadget.dev.parent = dev;
3025 udc->pdev = pdev;
3026 udc->dev = &pdev->dev;
3027 udc->enabled = 0;
3028
3029 if (pdev->dev.of_node) {
3030 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3031 "transceiver", 0);
3032 } else {
3033 isp1301_node = NULL;
3034 }
3035
3036 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
c4846a18
RS		 3037 if (!udc->isp1301_i2c_client) {
3038 retval = -EPROBE_DEFER;
3039 goto phy_fail;
3040 }
24a28e42
RS		 3041
3042 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3043 udc->isp1301_i2c_client->addr);
3044
3045 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
22d9d8e8
RK		 3046 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3047 if (retval)
3048 goto resource_fail;
24a28e42
RS		 3049
3050 udc->board = &lpc32xx_usbddata;
3051
3052 /*
3053 * Resources are mapped as follows:
3054 * IORESOURCE_MEM, base address and size of USB space
3055 * IORESOURCE_IRQ, USB device low priority interrupt number
3056 * IORESOURCE_IRQ, USB device high priority interrupt number
3057 * IORESOURCE_IRQ, USB device interrupt number
3058 * IORESOURCE_IRQ, USB transceiver interrupt number
3059 */
3060 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c4846a18
RS		 3061 if (!res) {
3062 retval = -ENXIO;
3063 goto resource_fail;
3064 }
24a28e42
RS		 3065
3066 spin_lock_init(&udc->lock);
3067
3068 /* Get IRQs */
3069 for (i = 0; i < 4; i++) {
3070 udc->udp_irq[i] = platform_get_irq(pdev, i);
3071 if (udc->udp_irq[i] < 0) {
3072 dev_err(udc->dev,
3073 "irq resource %d not available!\n", i);
c4846a18
RS		 3074 retval = udc->udp_irq[i];
3075 goto irq_fail;
24a28e42
RS		 3076 }
3077 }
3078
3079 udc->io_p_start = res->start;
3080 udc->io_p_size = resource_size(res);
3081 if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
3082 dev_err(udc->dev, "someone's using UDC memory\n");
c4846a18
RS		 3083 retval = -EBUSY;
3084 goto request_mem_region_fail;
24a28e42
RS		 3085 }
3086
3087 udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
3088 if (!udc->udp_baseaddr) {
3089 retval = -ENOMEM;
3090 dev_err(udc->dev, "IO map failure\n");
3091 goto io_map_fail;
3092 }
3093
59e05272
VZ		 3094 /* Get USB device clock */
3095 udc->usb_slv_clk = clk_get(&pdev->dev, NULL);
24a28e42
RS		 3096 if (IS_ERR(udc->usb_slv_clk)) {
3097 dev_err(udc->dev, "failed to acquire USB device clock\n");
3098 retval = PTR_ERR(udc->usb_slv_clk);
3099 goto usb_clk_get_fail;
3100 }
24a28e42 3101
24a28e42 3102 /* Enable USB device clock */
68726e77 3103 retval = clk_prepare_enable(udc->usb_slv_clk);
24a28e42
RS		 3104 if (retval < 0) {
3105 dev_err(udc->dev, "failed to start USB device clock\n");
3106 goto usb_clk_enable_fail;
3107 }
3108
24a28e42
RS		 3109 /* Setup deferred workqueue data */
3110 udc->poweron = udc->pullup = 0;
3111 INIT_WORK(&udc->pullup_job, pullup_work);
3112 INIT_WORK(&udc->vbus_job, vbus_work);
3113#ifdef CONFIG_PM
3114 INIT_WORK(&udc->power_job, power_work);
3115#endif
3116
3117 /* All clocks are now on */
3118 udc->clocked = 1;
3119
3120 isp1301_udc_configure(udc);
3121 /* Allocate memory for the UDCA */
3122 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3123 &dma_handle,
3124 (GFP_KERNEL | GFP_DMA));
3125 if (!udc->udca_v_base) {
3126 dev_err(udc->dev, "error getting UDCA region\n");
3127 retval = -ENOMEM;
3128 goto i2c_fail;
3129 }
3130 udc->udca_p_base = dma_handle;
3131 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3132 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3133
3134 /* Setup the DD DMA memory pool */
3135 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3136 sizeof(struct lpc32xx_usbd_dd_gad),
3137 sizeof(u32), 0);
3138 if (!udc->dd_cache) {
3139 dev_err(udc->dev, "error getting DD DMA region\n");
3140 retval = -ENOMEM;
3141 goto dma_alloc_fail;
3142 }
3143
3144 /* Clear USB peripheral and initialize gadget endpoints */
3145 udc_disable(udc);
3146 udc_reinit(udc);
3147
24a28e42
RS		 3148 /* Request IRQs - low and high priority USB device IRQs are routed to
3149 * the same handler, while the DMA interrupt is routed elsewhere */
3150 retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
3151 0, "udc_lp", udc);
3152 if (retval < 0) {
3153 dev_err(udc->dev, "LP request irq %d failed\n",
3154 udc->udp_irq[IRQ_USB_LP]);
3155 goto irq_lp_fail;
3156 }
3157 retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
3158 0, "udc_hp", udc);
3159 if (retval < 0) {
3160 dev_err(udc->dev, "HP request irq %d failed\n",
3161 udc->udp_irq[IRQ_USB_HP]);
3162 goto irq_hp_fail;
3163 }
3164
3165 retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
3166 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3167 if (retval < 0) {
3168 dev_err(udc->dev, "DEV request irq %d failed\n",
3169 udc->udp_irq[IRQ_USB_DEVDMA]);
3170 goto irq_dev_fail;
3171 }
3172
3173 /* The transceiver interrupt is used for VBUS detection and will
3174 kick off the VBUS handler function */
3175 retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
3176 0, "udc_otg", udc);
3177 if (retval < 0) {
3178 dev_err(udc->dev, "VBUS request irq %d failed\n",
3179 udc->udp_irq[IRQ_USB_ATX]);
3180 goto irq_xcvr_fail;
3181 }
3182
3183 /* Initialize wait queue */
3184 init_waitqueue_head(&udc->ep_disable_wait_queue);
3185 atomic_set(&udc->enabled_ep_cnt, 0);
3186
3187 /* Keep all IRQs disabled until GadgetFS starts up */
3188 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3189 disable_irq(udc->udp_irq[i]);
3190
3191 retval = usb_add_gadget_udc(dev, &udc->gadget);
3192 if (retval < 0)
3193 goto add_gadget_fail;
3194
3195 dev_set_drvdata(dev, udc);
3196 device_init_wakeup(dev, 1);
3197 create_debug_file(udc);
3198
3199 /* Disable clocks for now */
3200 udc_clk_set(udc, 0);
3201
3202 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3203 return 0;
3204
3205add_gadget_fail:
3206 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3207irq_xcvr_fail:
3208 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3209irq_dev_fail:
3210 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3211irq_hp_fail:
3212 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3213irq_lp_fail:
24a28e42
RS		 3214 dma_pool_destroy(udc->dd_cache);
3215dma_alloc_fail:
3216 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3217 udc->udca_v_base, udc->udca_p_base);
3218i2c_fail:
68726e77 3219 clk_disable_unprepare(udc->usb_slv_clk);
24a28e42 3220usb_clk_enable_fail:
ade79d13 3221 clk_put(udc->usb_slv_clk);
24a28e42 3222usb_clk_get_fail:
24a28e42
RS		 3223 iounmap(udc->udp_baseaddr);
3224io_map_fail:
3225 release_mem_region(udc->io_p_start, udc->io_p_size);
3226 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
c4846a18
RS		 3227request_mem_region_fail:
3228irq_fail:
3229resource_fail:
3230phy_fail:
3231 kfree(udc);
24a28e42
RS		 3232 return retval;
3233}
3234
fb4e98ab 3235static int lpc32xx_udc_remove(struct platform_device *pdev)
24a28e42
RS		 3236{
3237 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3238
3239 usb_del_gadget_udc(&udc->gadget);
3240 if (udc->driver)
3241 return -EBUSY;
3242
3243 udc_clk_set(udc, 1);
3244 udc_disable(udc);
3245 pullup(udc, 0);
3246
3247 free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3248
3249 device_init_wakeup(&pdev->dev, 0);
3250 remove_debug_file(udc);
3251
3252 dma_pool_destroy(udc->dd_cache);
3253 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3254 udc->udca_v_base, udc->udca_p_base);
3255 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3256 free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3257 free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3258
68726e77 3259 clk_disable_unprepare(udc->usb_slv_clk);
24a28e42 3260 clk_put(udc->usb_slv_clk);
59e05272 3261
24a28e42
RS		 3262 iounmap(udc->udp_baseaddr);
3263 release_mem_region(udc->io_p_start, udc->io_p_size);
c4846a18 3264 kfree(udc);
24a28e42
RS		 3265
3266 return 0;
3267}
3268
3269#ifdef CONFIG_PM
3270static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3271{
24a28e42
RS		 3272 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3273
3274 if (udc->clocked) {
3275 /* Power down ISP */
3276 udc->poweron = 0;
3277 isp1301_set_powerstate(udc, 0);
3278
3279 /* Disable clocking */
3280 udc_clk_set(udc, 0);
3281
3282 /* Keep clock flag on, so we know to re-enable clocks
3283 on resume */
3284 udc->clocked = 1;
3285
24a28e42 3286 /* Kill global USB clock */
68726e77 3287 clk_disable_unprepare(udc->usb_slv_clk);
24a28e42
RS		 3288 }
3289
3290 return 0;
3291}
3292
3293static int lpc32xx_udc_resume(struct platform_device *pdev)
3294{
3295 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3296
3297 if (udc->clocked) {
3298 /* Enable global USB clock */
68726e77 3299 clk_prepare_enable(udc->usb_slv_clk);
24a28e42
RS		 3300
3301 /* Enable clocking */
3302 udc_clk_set(udc, 1);
3303
3304 /* ISP back to normal power mode */
3305 udc->poweron = 1;
3306 isp1301_set_powerstate(udc, 1);
3307 }
3308
3309 return 0;
3310}
3311#else
3312#define lpc32xx_udc_suspend NULL
3313#define lpc32xx_udc_resume NULL
3314#endif
3315
3316#ifdef CONFIG_OF
ca118b78 3317static const struct of_device_id lpc32xx_udc_of_match[] = {
24a28e42
RS		 3318 { .compatible = "nxp,lpc3220-udc", },
3319 { },
3320};
3321MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3322#endif
3323
3324static struct platform_driver lpc32xx_udc_driver = {
7690417d 3325 .remove = lpc32xx_udc_remove,
24a28e42
RS		 3326 .shutdown = lpc32xx_udc_shutdown,
3327 .suspend = lpc32xx_udc_suspend,
3328 .resume = lpc32xx_udc_resume,
3329 .driver = {
3330 .name = (char *) driver_name,
24a28e42
RS		 3331 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3332 },
3333};
3334
52f7a82b 3335module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
24a28e42
RS		 3336
3337MODULE_DESCRIPTION("LPC32XX udc driver");
3338MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3339MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3340MODULE_LICENSE("GPL");
3341MODULE_ALIAS("platform:lpc32xx_udc");
Linux kernel - Deliverables
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