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3d4eb9df YX |
1 | /* |
2 | * Copyright (C) 2011 Marvell International Ltd. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/dmapool.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/errno.h> | |
3d4eb9df YX |
18 | #include <linux/timer.h> |
19 | #include <linux/list.h> | |
20 | #include <linux/notifier.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/moduleparam.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/usb/ch9.h> | |
25 | #include <linux/usb/gadget.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/irq.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/platform_data/mv_usb.h> | |
31 | #include <linux/clk.h> | |
3d4eb9df YX |
32 | |
33 | #include "mv_u3d.h" | |
34 | ||
35 | #define DRIVER_DESC "Marvell PXA USB3.0 Device Controller driver" | |
36 | ||
37 | static const char driver_name[] = "mv_u3d"; | |
38 | static const char driver_desc[] = DRIVER_DESC; | |
39 | ||
40 | static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status); | |
41 | static void mv_u3d_stop_activity(struct mv_u3d *u3d, | |
42 | struct usb_gadget_driver *driver); | |
43 | ||
44 | /* for endpoint 0 operations */ | |
45 | static const struct usb_endpoint_descriptor mv_u3d_ep0_desc = { | |
46 | .bLength = USB_DT_ENDPOINT_SIZE, | |
47 | .bDescriptorType = USB_DT_ENDPOINT, | |
48 | .bEndpointAddress = 0, | |
49 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
50 | .wMaxPacketSize = MV_U3D_EP0_MAX_PKT_SIZE, | |
51 | }; | |
52 | ||
53 | static void mv_u3d_ep0_reset(struct mv_u3d *u3d) | |
54 | { | |
55 | struct mv_u3d_ep *ep; | |
56 | u32 epxcr; | |
57 | int i; | |
58 | ||
59 | for (i = 0; i < 2; i++) { | |
60 | ep = &u3d->eps[i]; | |
61 | ep->u3d = u3d; | |
62 | ||
63 | /* ep0 ep context, ep0 in and out share the same ep context */ | |
64 | ep->ep_context = &u3d->ep_context[1]; | |
65 | } | |
66 | ||
67 | /* reset ep state machine */ | |
68 | /* reset ep0 out */ | |
69 | epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0); | |
70 | epxcr |= MV_U3D_EPXCR_EP_INIT; | |
71 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
72 | udelay(5); | |
73 | epxcr &= ~MV_U3D_EPXCR_EP_INIT; | |
74 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
75 | ||
76 | epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE | |
77 | << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT) | |
78 | | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT) | |
79 | | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
80 | | MV_U3D_EPXCR_EP_TYPE_CONTROL); | |
81 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr1); | |
82 | ||
83 | /* reset ep0 in */ | |
84 | epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxincr0); | |
85 | epxcr |= MV_U3D_EPXCR_EP_INIT; | |
86 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0); | |
87 | udelay(5); | |
88 | epxcr &= ~MV_U3D_EPXCR_EP_INIT; | |
89 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0); | |
90 | ||
91 | epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE | |
92 | << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT) | |
93 | | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT) | |
94 | | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
95 | | MV_U3D_EPXCR_EP_TYPE_CONTROL); | |
96 | iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr1); | |
97 | } | |
98 | ||
99 | static void mv_u3d_ep0_stall(struct mv_u3d *u3d) | |
100 | { | |
101 | u32 tmp; | |
102 | dev_dbg(u3d->dev, "%s\n", __func__); | |
103 | ||
104 | /* set TX and RX to stall */ | |
105 | tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0); | |
106 | tmp |= MV_U3D_EPXCR_EP_HALT; | |
107 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
108 | ||
109 | tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0); | |
110 | tmp |= MV_U3D_EPXCR_EP_HALT; | |
111 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0); | |
112 | ||
113 | /* update ep0 state */ | |
114 | u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; | |
115 | u3d->ep0_dir = MV_U3D_EP_DIR_OUT; | |
116 | } | |
117 | ||
118 | static int mv_u3d_process_ep_req(struct mv_u3d *u3d, int index, | |
119 | struct mv_u3d_req *curr_req) | |
120 | { | |
121 | struct mv_u3d_trb *curr_trb; | |
bd8dc737 | 122 | int actual, remaining_length = 0; |
3d4eb9df YX |
123 | int direction, ep_num; |
124 | int retval = 0; | |
125 | u32 tmp, status, length; | |
126 | ||
3d4eb9df YX |
127 | direction = index % 2; |
128 | ep_num = index / 2; | |
129 | ||
3d4eb9df YX |
130 | actual = curr_req->req.length; |
131 | ||
132 | while (!list_empty(&curr_req->trb_list)) { | |
133 | curr_trb = list_entry(curr_req->trb_list.next, | |
134 | struct mv_u3d_trb, trb_list); | |
135 | if (!curr_trb->trb_hw->ctrl.own) { | |
136 | dev_err(u3d->dev, "%s, TRB own error!\n", | |
137 | u3d->eps[index].name); | |
138 | return 1; | |
139 | } | |
140 | ||
141 | curr_trb->trb_hw->ctrl.own = 0; | |
bd8dc737 | 142 | if (direction == MV_U3D_EP_DIR_OUT) |
3d4eb9df | 143 | tmp = ioread32(&u3d->vuc_regs->rxst[ep_num].statuslo); |
bd8dc737 | 144 | else |
3d4eb9df | 145 | tmp = ioread32(&u3d->vuc_regs->txst[ep_num].statuslo); |
3d4eb9df YX |
146 | |
147 | status = tmp >> MV_U3D_XFERSTATUS_COMPLETE_SHIFT; | |
148 | length = tmp & MV_U3D_XFERSTATUS_TRB_LENGTH_MASK; | |
149 | ||
150 | if (status == MV_U3D_COMPLETE_SUCCESS || | |
151 | (status == MV_U3D_COMPLETE_SHORT_PACKET && | |
152 | direction == MV_U3D_EP_DIR_OUT)) { | |
153 | remaining_length += length; | |
154 | actual -= remaining_length; | |
155 | } else { | |
156 | dev_err(u3d->dev, | |
157 | "complete_tr error: ep=%d %s: error = 0x%x\n", | |
158 | index >> 1, direction ? "SEND" : "RECV", | |
159 | status); | |
160 | retval = -EPROTO; | |
161 | } | |
162 | ||
163 | list_del_init(&curr_trb->trb_list); | |
164 | } | |
165 | if (retval) | |
166 | return retval; | |
167 | ||
168 | curr_req->req.actual = actual; | |
169 | return 0; | |
170 | } | |
171 | ||
172 | /* | |
173 | * mv_u3d_done() - retire a request; caller blocked irqs | |
174 | * @status : request status to be set, only works when | |
175 | * request is still in progress. | |
176 | */ | |
177 | static | |
178 | void mv_u3d_done(struct mv_u3d_ep *ep, struct mv_u3d_req *req, int status) | |
6fbb2f7d FB |
179 | __releases(&ep->udc->lock) |
180 | __acquires(&ep->udc->lock) | |
3d4eb9df YX |
181 | { |
182 | struct mv_u3d *u3d = (struct mv_u3d *)ep->u3d; | |
183 | ||
184 | dev_dbg(u3d->dev, "mv_u3d_done: remove req->queue\n"); | |
185 | /* Removed the req from ep queue */ | |
186 | list_del_init(&req->queue); | |
187 | ||
188 | /* req.status should be set as -EINPROGRESS in ep_queue() */ | |
189 | if (req->req.status == -EINPROGRESS) | |
190 | req->req.status = status; | |
191 | else | |
192 | status = req->req.status; | |
193 | ||
194 | /* Free trb for the request */ | |
195 | if (!req->chain) | |
196 | dma_pool_free(u3d->trb_pool, | |
197 | req->trb_head->trb_hw, req->trb_head->trb_dma); | |
198 | else { | |
199 | dma_unmap_single(ep->u3d->gadget.dev.parent, | |
200 | (dma_addr_t)req->trb_head->trb_dma, | |
201 | req->trb_count * sizeof(struct mv_u3d_trb_hw), | |
202 | DMA_BIDIRECTIONAL); | |
203 | kfree(req->trb_head->trb_hw); | |
204 | } | |
205 | kfree(req->trb_head); | |
206 | ||
207 | usb_gadget_unmap_request(&u3d->gadget, &req->req, mv_u3d_ep_dir(ep)); | |
208 | ||
209 | if (status && (status != -ESHUTDOWN)) { | |
210 | dev_dbg(u3d->dev, "complete %s req %p stat %d len %u/%u", | |
211 | ep->ep.name, &req->req, status, | |
212 | req->req.actual, req->req.length); | |
213 | } | |
214 | ||
215 | spin_unlock(&ep->u3d->lock); | |
304f7e5e MS |
216 | |
217 | usb_gadget_giveback_request(&ep->ep, &req->req); | |
3d4eb9df YX |
218 | |
219 | spin_lock(&ep->u3d->lock); | |
220 | } | |
221 | ||
222 | static int mv_u3d_queue_trb(struct mv_u3d_ep *ep, struct mv_u3d_req *req) | |
223 | { | |
224 | u32 tmp, direction; | |
225 | struct mv_u3d *u3d; | |
226 | struct mv_u3d_ep_context *ep_context; | |
227 | int retval = 0; | |
228 | ||
229 | u3d = ep->u3d; | |
230 | direction = mv_u3d_ep_dir(ep); | |
231 | ||
232 | /* ep0 in and out share the same ep context slot 1*/ | |
233 | if (ep->ep_num == 0) | |
234 | ep_context = &(u3d->ep_context[1]); | |
235 | else | |
236 | ep_context = &(u3d->ep_context[ep->ep_num * 2 + direction]); | |
237 | ||
238 | /* check if the pipe is empty or not */ | |
239 | if (!list_empty(&ep->queue)) { | |
240 | dev_err(u3d->dev, "add trb to non-empty queue!\n"); | |
241 | retval = -ENOMEM; | |
242 | WARN_ON(1); | |
243 | } else { | |
244 | ep_context->rsvd0 = cpu_to_le32(1); | |
245 | ep_context->rsvd1 = 0; | |
246 | ||
247 | /* Configure the trb address and set the DCS bit. | |
248 | * Both DCS bit and own bit in trb should be set. | |
249 | */ | |
250 | ep_context->trb_addr_lo = | |
251 | cpu_to_le32(req->trb_head->trb_dma | DCS_ENABLE); | |
252 | ep_context->trb_addr_hi = 0; | |
253 | ||
254 | /* Ensure that updates to the EP Context will | |
255 | * occure before Ring Bell. | |
256 | */ | |
257 | wmb(); | |
258 | ||
259 | /* ring bell the ep */ | |
260 | if (ep->ep_num == 0) | |
261 | tmp = 0x1; | |
262 | else | |
263 | tmp = ep->ep_num * 2 | |
264 | + ((direction == MV_U3D_EP_DIR_OUT) ? 0 : 1); | |
265 | ||
266 | iowrite32(tmp, &u3d->op_regs->doorbell); | |
267 | } | |
268 | return retval; | |
269 | } | |
270 | ||
271 | static struct mv_u3d_trb *mv_u3d_build_trb_one(struct mv_u3d_req *req, | |
272 | unsigned *length, dma_addr_t *dma) | |
273 | { | |
274 | u32 temp; | |
275 | unsigned int direction; | |
276 | struct mv_u3d_trb *trb; | |
277 | struct mv_u3d_trb_hw *trb_hw; | |
278 | struct mv_u3d *u3d; | |
279 | ||
280 | /* how big will this transfer be? */ | |
281 | *length = req->req.length - req->req.actual; | |
282 | BUG_ON(*length > (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER); | |
283 | ||
284 | u3d = req->ep->u3d; | |
285 | ||
286 | trb = kzalloc(sizeof(*trb), GFP_ATOMIC); | |
f3772c2b | 287 | if (!trb) |
3d4eb9df | 288 | return NULL; |
3d4eb9df YX |
289 | |
290 | /* | |
291 | * Be careful that no _GFP_HIGHMEM is set, | |
292 | * or we can not use dma_to_virt | |
293 | * cannot use GFP_KERNEL in spin lock | |
294 | */ | |
295 | trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma); | |
296 | if (!trb_hw) { | |
f51a08da | 297 | kfree(trb); |
3d4eb9df YX |
298 | dev_err(u3d->dev, |
299 | "%s, dma_pool_alloc fail\n", __func__); | |
300 | return NULL; | |
301 | } | |
302 | trb->trb_dma = *dma; | |
303 | trb->trb_hw = trb_hw; | |
304 | ||
305 | /* initialize buffer page pointers */ | |
306 | temp = (u32)(req->req.dma + req->req.actual); | |
307 | ||
308 | trb_hw->buf_addr_lo = cpu_to_le32(temp); | |
309 | trb_hw->buf_addr_hi = 0; | |
310 | trb_hw->trb_len = cpu_to_le32(*length); | |
311 | trb_hw->ctrl.own = 1; | |
312 | ||
313 | if (req->ep->ep_num == 0) | |
314 | trb_hw->ctrl.type = TYPE_DATA; | |
315 | else | |
316 | trb_hw->ctrl.type = TYPE_NORMAL; | |
317 | ||
318 | req->req.actual += *length; | |
319 | ||
320 | direction = mv_u3d_ep_dir(req->ep); | |
321 | if (direction == MV_U3D_EP_DIR_IN) | |
322 | trb_hw->ctrl.dir = 1; | |
323 | else | |
324 | trb_hw->ctrl.dir = 0; | |
325 | ||
326 | /* Enable interrupt for the last trb of a request */ | |
327 | if (!req->req.no_interrupt) | |
328 | trb_hw->ctrl.ioc = 1; | |
329 | ||
330 | trb_hw->ctrl.chain = 0; | |
331 | ||
332 | wmb(); | |
333 | return trb; | |
334 | } | |
335 | ||
336 | static int mv_u3d_build_trb_chain(struct mv_u3d_req *req, unsigned *length, | |
337 | struct mv_u3d_trb *trb, int *is_last) | |
338 | { | |
339 | u32 temp; | |
340 | unsigned int direction; | |
341 | struct mv_u3d *u3d; | |
342 | ||
343 | /* how big will this transfer be? */ | |
344 | *length = min(req->req.length - req->req.actual, | |
345 | (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER); | |
346 | ||
347 | u3d = req->ep->u3d; | |
348 | ||
349 | trb->trb_dma = 0; | |
350 | ||
351 | /* initialize buffer page pointers */ | |
352 | temp = (u32)(req->req.dma + req->req.actual); | |
353 | ||
354 | trb->trb_hw->buf_addr_lo = cpu_to_le32(temp); | |
355 | trb->trb_hw->buf_addr_hi = 0; | |
356 | trb->trb_hw->trb_len = cpu_to_le32(*length); | |
357 | trb->trb_hw->ctrl.own = 1; | |
358 | ||
359 | if (req->ep->ep_num == 0) | |
360 | trb->trb_hw->ctrl.type = TYPE_DATA; | |
361 | else | |
362 | trb->trb_hw->ctrl.type = TYPE_NORMAL; | |
363 | ||
364 | req->req.actual += *length; | |
365 | ||
366 | direction = mv_u3d_ep_dir(req->ep); | |
367 | if (direction == MV_U3D_EP_DIR_IN) | |
368 | trb->trb_hw->ctrl.dir = 1; | |
369 | else | |
370 | trb->trb_hw->ctrl.dir = 0; | |
371 | ||
372 | /* zlp is needed if req->req.zero is set */ | |
373 | if (req->req.zero) { | |
374 | if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0) | |
375 | *is_last = 1; | |
376 | else | |
377 | *is_last = 0; | |
378 | } else if (req->req.length == req->req.actual) | |
379 | *is_last = 1; | |
380 | else | |
381 | *is_last = 0; | |
382 | ||
383 | /* Enable interrupt for the last trb of a request */ | |
384 | if (*is_last && !req->req.no_interrupt) | |
385 | trb->trb_hw->ctrl.ioc = 1; | |
386 | ||
387 | if (*is_last) | |
388 | trb->trb_hw->ctrl.chain = 0; | |
389 | else { | |
390 | trb->trb_hw->ctrl.chain = 1; | |
391 | dev_dbg(u3d->dev, "chain trb\n"); | |
392 | } | |
393 | ||
394 | wmb(); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | /* generate TRB linked list for a request | |
400 | * usb controller only supports continous trb chain, | |
401 | * that trb structure physical address should be continous. | |
402 | */ | |
403 | static int mv_u3d_req_to_trb(struct mv_u3d_req *req) | |
404 | { | |
405 | unsigned count; | |
406 | int is_last; | |
407 | struct mv_u3d_trb *trb; | |
408 | struct mv_u3d_trb_hw *trb_hw; | |
409 | struct mv_u3d *u3d; | |
410 | dma_addr_t dma; | |
411 | unsigned length; | |
412 | unsigned trb_num; | |
413 | ||
414 | u3d = req->ep->u3d; | |
415 | ||
416 | INIT_LIST_HEAD(&req->trb_list); | |
417 | ||
418 | length = req->req.length - req->req.actual; | |
419 | /* normally the request transfer length is less than 16KB. | |
420 | * we use buil_trb_one() to optimize it. | |
421 | */ | |
422 | if (length <= (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER) { | |
423 | trb = mv_u3d_build_trb_one(req, &count, &dma); | |
424 | list_add_tail(&trb->trb_list, &req->trb_list); | |
425 | req->trb_head = trb; | |
426 | req->trb_count = 1; | |
427 | req->chain = 0; | |
428 | } else { | |
429 | trb_num = length / MV_U3D_EP_MAX_LENGTH_TRANSFER; | |
430 | if (length % MV_U3D_EP_MAX_LENGTH_TRANSFER) | |
431 | trb_num++; | |
432 | ||
433 | trb = kcalloc(trb_num, sizeof(*trb), GFP_ATOMIC); | |
f3772c2b | 434 | if (!trb) |
3d4eb9df | 435 | return -ENOMEM; |
3d4eb9df YX |
436 | |
437 | trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC); | |
438 | if (!trb_hw) { | |
f51a08da | 439 | kfree(trb); |
3d4eb9df YX |
440 | return -ENOMEM; |
441 | } | |
442 | ||
443 | do { | |
444 | trb->trb_hw = trb_hw; | |
445 | if (mv_u3d_build_trb_chain(req, &count, | |
446 | trb, &is_last)) { | |
447 | dev_err(u3d->dev, | |
448 | "%s, mv_u3d_build_trb_chain fail\n", | |
449 | __func__); | |
450 | return -EIO; | |
451 | } | |
452 | ||
453 | list_add_tail(&trb->trb_list, &req->trb_list); | |
454 | req->trb_count++; | |
455 | trb++; | |
456 | trb_hw++; | |
457 | } while (!is_last); | |
458 | ||
459 | req->trb_head = list_entry(req->trb_list.next, | |
460 | struct mv_u3d_trb, trb_list); | |
461 | req->trb_head->trb_dma = dma_map_single(u3d->gadget.dev.parent, | |
462 | req->trb_head->trb_hw, | |
463 | trb_num * sizeof(*trb_hw), | |
464 | DMA_BIDIRECTIONAL); | |
465 | ||
466 | req->chain = 1; | |
467 | } | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
472 | static int | |
473 | mv_u3d_start_queue(struct mv_u3d_ep *ep) | |
474 | { | |
475 | struct mv_u3d *u3d = ep->u3d; | |
476 | struct mv_u3d_req *req; | |
477 | int ret; | |
478 | ||
479 | if (!list_empty(&ep->req_list) && !ep->processing) | |
480 | req = list_entry(ep->req_list.next, struct mv_u3d_req, list); | |
481 | else | |
482 | return 0; | |
483 | ||
484 | ep->processing = 1; | |
485 | ||
486 | /* set up dma mapping */ | |
487 | ret = usb_gadget_map_request(&u3d->gadget, &req->req, | |
488 | mv_u3d_ep_dir(ep)); | |
489 | if (ret) | |
490 | return ret; | |
491 | ||
492 | req->req.status = -EINPROGRESS; | |
493 | req->req.actual = 0; | |
494 | req->trb_count = 0; | |
495 | ||
496 | /* build trbs and push them to device queue */ | |
497 | if (!mv_u3d_req_to_trb(req)) { | |
498 | ret = mv_u3d_queue_trb(ep, req); | |
499 | if (ret) { | |
500 | ep->processing = 0; | |
501 | return ret; | |
502 | } | |
503 | } else { | |
504 | ep->processing = 0; | |
505 | dev_err(u3d->dev, "%s, mv_u3d_req_to_trb fail\n", __func__); | |
506 | return -ENOMEM; | |
507 | } | |
508 | ||
509 | /* irq handler advances the queue */ | |
510 | if (req) | |
511 | list_add_tail(&req->queue, &ep->queue); | |
512 | ||
513 | return 0; | |
514 | } | |
515 | ||
516 | static int mv_u3d_ep_enable(struct usb_ep *_ep, | |
517 | const struct usb_endpoint_descriptor *desc) | |
518 | { | |
519 | struct mv_u3d *u3d; | |
520 | struct mv_u3d_ep *ep; | |
3d4eb9df YX |
521 | u16 max = 0; |
522 | unsigned maxburst = 0; | |
523 | u32 epxcr, direction; | |
524 | ||
525 | if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) | |
526 | return -EINVAL; | |
527 | ||
528 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
529 | u3d = ep->u3d; | |
530 | ||
531 | if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) | |
532 | return -ESHUTDOWN; | |
533 | ||
534 | direction = mv_u3d_ep_dir(ep); | |
535 | max = le16_to_cpu(desc->wMaxPacketSize); | |
536 | ||
537 | if (!_ep->maxburst) | |
538 | _ep->maxburst = 1; | |
539 | maxburst = _ep->maxburst; | |
540 | ||
3d4eb9df YX |
541 | /* Set the max burst size */ |
542 | switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { | |
543 | case USB_ENDPOINT_XFER_BULK: | |
544 | if (maxburst > 16) { | |
545 | dev_dbg(u3d->dev, | |
546 | "max burst should not be greater " | |
547 | "than 16 on bulk ep\n"); | |
548 | maxburst = 1; | |
549 | _ep->maxburst = maxburst; | |
550 | } | |
551 | dev_dbg(u3d->dev, | |
552 | "maxburst: %d on bulk %s\n", maxburst, ep->name); | |
553 | break; | |
554 | case USB_ENDPOINT_XFER_CONTROL: | |
555 | /* control transfer only supports maxburst as one */ | |
556 | maxburst = 1; | |
557 | _ep->maxburst = maxburst; | |
558 | break; | |
559 | case USB_ENDPOINT_XFER_INT: | |
560 | if (maxburst != 1) { | |
561 | dev_dbg(u3d->dev, | |
562 | "max burst should be 1 on int ep " | |
563 | "if transfer size is not 1024\n"); | |
564 | maxburst = 1; | |
565 | _ep->maxburst = maxburst; | |
566 | } | |
567 | break; | |
568 | case USB_ENDPOINT_XFER_ISOC: | |
569 | if (maxburst != 1) { | |
570 | dev_dbg(u3d->dev, | |
571 | "max burst should be 1 on isoc ep " | |
572 | "if transfer size is not 1024\n"); | |
573 | maxburst = 1; | |
574 | _ep->maxburst = maxburst; | |
575 | } | |
576 | break; | |
577 | default: | |
578 | goto en_done; | |
579 | } | |
580 | ||
581 | ep->ep.maxpacket = max; | |
582 | ep->ep.desc = desc; | |
583 | ep->enabled = 1; | |
584 | ||
585 | /* Enable the endpoint for Rx or Tx and set the endpoint type */ | |
586 | if (direction == MV_U3D_EP_DIR_OUT) { | |
587 | epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
588 | epxcr |= MV_U3D_EPXCR_EP_INIT; | |
589 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
590 | udelay(5); | |
591 | epxcr &= ~MV_U3D_EPXCR_EP_INIT; | |
592 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
593 | ||
594 | epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT) | |
595 | | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT) | |
596 | | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
597 | | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)); | |
598 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1); | |
599 | } else { | |
600 | epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
601 | epxcr |= MV_U3D_EPXCR_EP_INIT; | |
602 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
603 | udelay(5); | |
604 | epxcr &= ~MV_U3D_EPXCR_EP_INIT; | |
605 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
606 | ||
607 | epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT) | |
608 | | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT) | |
609 | | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
610 | | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)); | |
611 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1); | |
612 | } | |
613 | ||
614 | return 0; | |
615 | en_done: | |
616 | return -EINVAL; | |
617 | } | |
618 | ||
619 | static int mv_u3d_ep_disable(struct usb_ep *_ep) | |
620 | { | |
621 | struct mv_u3d *u3d; | |
622 | struct mv_u3d_ep *ep; | |
3d4eb9df | 623 | u32 epxcr, direction; |
2389df45 | 624 | unsigned long flags; |
3d4eb9df YX |
625 | |
626 | if (!_ep) | |
627 | return -EINVAL; | |
628 | ||
629 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
630 | if (!ep->ep.desc) | |
631 | return -EINVAL; | |
632 | ||
633 | u3d = ep->u3d; | |
634 | ||
3d4eb9df YX |
635 | direction = mv_u3d_ep_dir(ep); |
636 | ||
637 | /* nuke all pending requests (does flush) */ | |
2389df45 | 638 | spin_lock_irqsave(&u3d->lock, flags); |
3d4eb9df | 639 | mv_u3d_nuke(ep, -ESHUTDOWN); |
2389df45 | 640 | spin_unlock_irqrestore(&u3d->lock, flags); |
3d4eb9df YX |
641 | |
642 | /* Disable the endpoint for Rx or Tx and reset the endpoint type */ | |
643 | if (direction == MV_U3D_EP_DIR_OUT) { | |
644 | epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1); | |
645 | epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
646 | | USB_ENDPOINT_XFERTYPE_MASK); | |
647 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1); | |
648 | } else { | |
649 | epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr1); | |
650 | epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT) | |
651 | | USB_ENDPOINT_XFERTYPE_MASK); | |
652 | iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1); | |
653 | } | |
654 | ||
655 | ep->enabled = 0; | |
656 | ||
657 | ep->ep.desc = NULL; | |
658 | return 0; | |
659 | } | |
660 | ||
661 | static struct usb_request * | |
662 | mv_u3d_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) | |
663 | { | |
664 | struct mv_u3d_req *req = NULL; | |
665 | ||
666 | req = kzalloc(sizeof *req, gfp_flags); | |
667 | if (!req) | |
668 | return NULL; | |
669 | ||
670 | INIT_LIST_HEAD(&req->queue); | |
671 | ||
672 | return &req->req; | |
673 | } | |
674 | ||
675 | static void mv_u3d_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
676 | { | |
677 | struct mv_u3d_req *req = container_of(_req, struct mv_u3d_req, req); | |
678 | ||
679 | kfree(req); | |
680 | } | |
681 | ||
682 | static void mv_u3d_ep_fifo_flush(struct usb_ep *_ep) | |
683 | { | |
684 | struct mv_u3d *u3d; | |
685 | u32 direction; | |
686 | struct mv_u3d_ep *ep = container_of(_ep, struct mv_u3d_ep, ep); | |
687 | unsigned int loops; | |
688 | u32 tmp; | |
689 | ||
690 | /* if endpoint is not enabled, cannot flush endpoint */ | |
691 | if (!ep->enabled) | |
692 | return; | |
693 | ||
694 | u3d = ep->u3d; | |
695 | direction = mv_u3d_ep_dir(ep); | |
696 | ||
697 | /* ep0 need clear bit after flushing fifo. */ | |
698 | if (!ep->ep_num) { | |
699 | if (direction == MV_U3D_EP_DIR_OUT) { | |
700 | tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0); | |
701 | tmp |= MV_U3D_EPXCR_EP_FLUSH; | |
702 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
703 | udelay(10); | |
704 | tmp &= ~MV_U3D_EPXCR_EP_FLUSH; | |
705 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0); | |
706 | } else { | |
707 | tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0); | |
708 | tmp |= MV_U3D_EPXCR_EP_FLUSH; | |
709 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0); | |
710 | udelay(10); | |
711 | tmp &= ~MV_U3D_EPXCR_EP_FLUSH; | |
712 | iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0); | |
713 | } | |
714 | return; | |
715 | } | |
716 | ||
717 | if (direction == MV_U3D_EP_DIR_OUT) { | |
718 | tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
719 | tmp |= MV_U3D_EPXCR_EP_FLUSH; | |
720 | iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
721 | ||
722 | /* Wait until flushing completed */ | |
723 | loops = LOOPS(MV_U3D_FLUSH_TIMEOUT); | |
724 | while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0) & | |
725 | MV_U3D_EPXCR_EP_FLUSH) { | |
726 | /* | |
727 | * EP_FLUSH bit should be cleared to indicate this | |
728 | * operation is complete | |
729 | */ | |
730 | if (loops == 0) { | |
731 | dev_dbg(u3d->dev, | |
732 | "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num, | |
733 | direction ? "in" : "out"); | |
734 | return; | |
735 | } | |
736 | loops--; | |
737 | udelay(LOOPS_USEC); | |
738 | } | |
739 | } else { /* EP_DIR_IN */ | |
740 | tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
741 | tmp |= MV_U3D_EPXCR_EP_FLUSH; | |
742 | iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
743 | ||
744 | /* Wait until flushing completed */ | |
745 | loops = LOOPS(MV_U3D_FLUSH_TIMEOUT); | |
746 | while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0) & | |
747 | MV_U3D_EPXCR_EP_FLUSH) { | |
748 | /* | |
749 | * EP_FLUSH bit should be cleared to indicate this | |
750 | * operation is complete | |
751 | */ | |
752 | if (loops == 0) { | |
753 | dev_dbg(u3d->dev, | |
754 | "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num, | |
755 | direction ? "in" : "out"); | |
756 | return; | |
757 | } | |
758 | loops--; | |
759 | udelay(LOOPS_USEC); | |
760 | } | |
761 | } | |
762 | } | |
763 | ||
764 | /* queues (submits) an I/O request to an endpoint */ | |
765 | static int | |
766 | mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |
767 | { | |
768 | struct mv_u3d_ep *ep; | |
769 | struct mv_u3d_req *req; | |
770 | struct mv_u3d *u3d; | |
771 | unsigned long flags; | |
772 | int is_first_req = 0; | |
773 | ||
774 | if (unlikely(!_ep || !_req)) | |
775 | return -EINVAL; | |
776 | ||
777 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
778 | u3d = ep->u3d; | |
779 | ||
780 | req = container_of(_req, struct mv_u3d_req, req); | |
781 | ||
782 | if (!ep->ep_num | |
783 | && u3d->ep0_state == MV_U3D_STATUS_STAGE | |
784 | && !_req->length) { | |
785 | dev_dbg(u3d->dev, "ep0 status stage\n"); | |
786 | u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; | |
787 | return 0; | |
788 | } | |
789 | ||
e6667ef7 FB |
790 | dev_dbg(u3d->dev, "%s: %s, req: 0x%p\n", |
791 | __func__, _ep->name, req); | |
3d4eb9df YX |
792 | |
793 | /* catch various bogus parameters */ | |
794 | if (!req->req.complete || !req->req.buf | |
795 | || !list_empty(&req->queue)) { | |
796 | dev_err(u3d->dev, | |
e6667ef7 FB |
797 | "%s, bad params, _req: 0x%p," |
798 | "req->req.complete: 0x%p, req->req.buf: 0x%p," | |
3d4eb9df | 799 | "list_empty: 0x%x\n", |
e6667ef7 FB |
800 | __func__, _req, |
801 | req->req.complete, req->req.buf, | |
802 | list_empty(&req->queue)); | |
3d4eb9df YX |
803 | return -EINVAL; |
804 | } | |
805 | if (unlikely(!ep->ep.desc)) { | |
806 | dev_err(u3d->dev, "%s, bad ep\n", __func__); | |
807 | return -EINVAL; | |
808 | } | |
809 | if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
810 | if (req->req.length > ep->ep.maxpacket) | |
811 | return -EMSGSIZE; | |
812 | } | |
813 | ||
814 | if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) { | |
815 | dev_err(u3d->dev, | |
816 | "bad params of driver/speed\n"); | |
817 | return -ESHUTDOWN; | |
818 | } | |
819 | ||
820 | req->ep = ep; | |
821 | ||
822 | /* Software list handles usb request. */ | |
823 | spin_lock_irqsave(&ep->req_lock, flags); | |
824 | is_first_req = list_empty(&ep->req_list); | |
825 | list_add_tail(&req->list, &ep->req_list); | |
826 | spin_unlock_irqrestore(&ep->req_lock, flags); | |
827 | if (!is_first_req) { | |
828 | dev_dbg(u3d->dev, "list is not empty\n"); | |
829 | return 0; | |
830 | } | |
831 | ||
832 | dev_dbg(u3d->dev, "call mv_u3d_start_queue from usb_ep_queue\n"); | |
833 | spin_lock_irqsave(&u3d->lock, flags); | |
834 | mv_u3d_start_queue(ep); | |
835 | spin_unlock_irqrestore(&u3d->lock, flags); | |
836 | return 0; | |
837 | } | |
838 | ||
839 | /* dequeues (cancels, unlinks) an I/O request from an endpoint */ | |
840 | static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
841 | { | |
842 | struct mv_u3d_ep *ep; | |
843 | struct mv_u3d_req *req; | |
844 | struct mv_u3d *u3d; | |
845 | struct mv_u3d_ep_context *ep_context; | |
846 | struct mv_u3d_req *next_req; | |
847 | ||
848 | unsigned long flags; | |
849 | int ret = 0; | |
850 | ||
851 | if (!_ep || !_req) | |
852 | return -EINVAL; | |
853 | ||
854 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
855 | u3d = ep->u3d; | |
856 | ||
857 | spin_lock_irqsave(&ep->u3d->lock, flags); | |
858 | ||
859 | /* make sure it's actually queued on this endpoint */ | |
860 | list_for_each_entry(req, &ep->queue, queue) { | |
861 | if (&req->req == _req) | |
862 | break; | |
863 | } | |
864 | if (&req->req != _req) { | |
865 | ret = -EINVAL; | |
866 | goto out; | |
867 | } | |
868 | ||
869 | /* The request is in progress, or completed but not dequeued */ | |
870 | if (ep->queue.next == &req->queue) { | |
871 | _req->status = -ECONNRESET; | |
872 | mv_u3d_ep_fifo_flush(_ep); | |
873 | ||
874 | /* The request isn't the last request in this ep queue */ | |
875 | if (req->queue.next != &ep->queue) { | |
876 | dev_dbg(u3d->dev, | |
877 | "it is the last request in this ep queue\n"); | |
878 | ep_context = ep->ep_context; | |
879 | next_req = list_entry(req->queue.next, | |
880 | struct mv_u3d_req, queue); | |
881 | ||
882 | /* Point first TRB of next request to the EP context. */ | |
e6667ef7 | 883 | iowrite32((unsigned long) next_req->trb_head, |
3d4eb9df YX |
884 | &ep_context->trb_addr_lo); |
885 | } else { | |
886 | struct mv_u3d_ep_context *ep_context; | |
887 | ep_context = ep->ep_context; | |
888 | ep_context->trb_addr_lo = 0; | |
889 | ep_context->trb_addr_hi = 0; | |
890 | } | |
891 | ||
892 | } else | |
893 | WARN_ON(1); | |
894 | ||
895 | mv_u3d_done(ep, req, -ECONNRESET); | |
896 | ||
897 | /* remove the req from the ep req list */ | |
898 | if (!list_empty(&ep->req_list)) { | |
899 | struct mv_u3d_req *curr_req; | |
900 | curr_req = list_entry(ep->req_list.next, | |
901 | struct mv_u3d_req, list); | |
902 | if (curr_req == req) { | |
903 | list_del_init(&req->list); | |
904 | ep->processing = 0; | |
905 | } | |
906 | } | |
907 | ||
908 | out: | |
909 | spin_unlock_irqrestore(&ep->u3d->lock, flags); | |
910 | return ret; | |
911 | } | |
912 | ||
913 | static void | |
914 | mv_u3d_ep_set_stall(struct mv_u3d *u3d, u8 ep_num, u8 direction, int stall) | |
915 | { | |
916 | u32 tmp; | |
917 | struct mv_u3d_ep *ep = u3d->eps; | |
918 | ||
919 | dev_dbg(u3d->dev, "%s\n", __func__); | |
920 | if (direction == MV_U3D_EP_DIR_OUT) { | |
921 | tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
922 | if (stall) | |
923 | tmp |= MV_U3D_EPXCR_EP_HALT; | |
924 | else | |
925 | tmp &= ~MV_U3D_EPXCR_EP_HALT; | |
926 | iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0); | |
927 | } else { | |
928 | tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
929 | if (stall) | |
930 | tmp |= MV_U3D_EPXCR_EP_HALT; | |
931 | else | |
932 | tmp &= ~MV_U3D_EPXCR_EP_HALT; | |
933 | iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0); | |
934 | } | |
935 | } | |
936 | ||
937 | static int mv_u3d_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge) | |
938 | { | |
939 | struct mv_u3d_ep *ep; | |
940 | unsigned long flags = 0; | |
941 | int status = 0; | |
942 | struct mv_u3d *u3d; | |
943 | ||
944 | ep = container_of(_ep, struct mv_u3d_ep, ep); | |
945 | u3d = ep->u3d; | |
946 | if (!ep->ep.desc) { | |
947 | status = -EINVAL; | |
948 | goto out; | |
949 | } | |
950 | ||
951 | if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | |
952 | status = -EOPNOTSUPP; | |
953 | goto out; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Attempt to halt IN ep will fail if any transfer requests | |
958 | * are still queue | |
959 | */ | |
960 | if (halt && (mv_u3d_ep_dir(ep) == MV_U3D_EP_DIR_IN) | |
961 | && !list_empty(&ep->queue)) { | |
962 | status = -EAGAIN; | |
963 | goto out; | |
964 | } | |
965 | ||
966 | spin_lock_irqsave(&ep->u3d->lock, flags); | |
967 | mv_u3d_ep_set_stall(u3d, ep->ep_num, mv_u3d_ep_dir(ep), halt); | |
968 | if (halt && wedge) | |
969 | ep->wedge = 1; | |
970 | else if (!halt) | |
971 | ep->wedge = 0; | |
972 | spin_unlock_irqrestore(&ep->u3d->lock, flags); | |
973 | ||
974 | if (ep->ep_num == 0) | |
975 | u3d->ep0_dir = MV_U3D_EP_DIR_OUT; | |
976 | out: | |
977 | return status; | |
978 | } | |
979 | ||
980 | static int mv_u3d_ep_set_halt(struct usb_ep *_ep, int halt) | |
981 | { | |
982 | return mv_u3d_ep_set_halt_wedge(_ep, halt, 0); | |
983 | } | |
984 | ||
985 | static int mv_u3d_ep_set_wedge(struct usb_ep *_ep) | |
986 | { | |
987 | return mv_u3d_ep_set_halt_wedge(_ep, 1, 1); | |
988 | } | |
989 | ||
990 | static struct usb_ep_ops mv_u3d_ep_ops = { | |
991 | .enable = mv_u3d_ep_enable, | |
992 | .disable = mv_u3d_ep_disable, | |
993 | ||
994 | .alloc_request = mv_u3d_alloc_request, | |
995 | .free_request = mv_u3d_free_request, | |
996 | ||
997 | .queue = mv_u3d_ep_queue, | |
998 | .dequeue = mv_u3d_ep_dequeue, | |
999 | ||
1000 | .set_wedge = mv_u3d_ep_set_wedge, | |
1001 | .set_halt = mv_u3d_ep_set_halt, | |
1002 | .fifo_flush = mv_u3d_ep_fifo_flush, | |
1003 | }; | |
1004 | ||
1005 | static void mv_u3d_controller_stop(struct mv_u3d *u3d) | |
1006 | { | |
1007 | u32 tmp; | |
1008 | ||
1009 | if (!u3d->clock_gating && u3d->vbus_valid_detect) | |
1010 | iowrite32(MV_U3D_INTR_ENABLE_VBUS_VALID, | |
1011 | &u3d->vuc_regs->intrenable); | |
1012 | else | |
1013 | iowrite32(0, &u3d->vuc_regs->intrenable); | |
1014 | iowrite32(~0x0, &u3d->vuc_regs->endcomplete); | |
1015 | iowrite32(~0x0, &u3d->vuc_regs->trbunderrun); | |
1016 | iowrite32(~0x0, &u3d->vuc_regs->trbcomplete); | |
1017 | iowrite32(~0x0, &u3d->vuc_regs->linkchange); | |
1018 | iowrite32(0x1, &u3d->vuc_regs->setuplock); | |
1019 | ||
1020 | /* Reset the RUN bit in the command register to stop USB */ | |
1021 | tmp = ioread32(&u3d->op_regs->usbcmd); | |
1022 | tmp &= ~MV_U3D_CMD_RUN_STOP; | |
1023 | iowrite32(tmp, &u3d->op_regs->usbcmd); | |
1024 | dev_dbg(u3d->dev, "after u3d_stop, USBCMD 0x%x\n", | |
1025 | ioread32(&u3d->op_regs->usbcmd)); | |
1026 | } | |
1027 | ||
1028 | static void mv_u3d_controller_start(struct mv_u3d *u3d) | |
1029 | { | |
1030 | u32 usbintr; | |
1031 | u32 temp; | |
1032 | ||
1033 | /* enable link LTSSM state machine */ | |
1034 | temp = ioread32(&u3d->vuc_regs->ltssm); | |
1035 | temp |= MV_U3D_LTSSM_PHY_INIT_DONE; | |
1036 | iowrite32(temp, &u3d->vuc_regs->ltssm); | |
1037 | ||
1038 | /* Enable interrupts */ | |
1039 | usbintr = MV_U3D_INTR_ENABLE_LINK_CHG | MV_U3D_INTR_ENABLE_TXDESC_ERR | | |
1040 | MV_U3D_INTR_ENABLE_RXDESC_ERR | MV_U3D_INTR_ENABLE_TX_COMPLETE | | |
1041 | MV_U3D_INTR_ENABLE_RX_COMPLETE | MV_U3D_INTR_ENABLE_SETUP | | |
1042 | (u3d->vbus_valid_detect ? MV_U3D_INTR_ENABLE_VBUS_VALID : 0); | |
1043 | iowrite32(usbintr, &u3d->vuc_regs->intrenable); | |
1044 | ||
1045 | /* Enable ctrl ep */ | |
1046 | iowrite32(0x1, &u3d->vuc_regs->ctrlepenable); | |
1047 | ||
1048 | /* Set the Run bit in the command register */ | |
1049 | iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd); | |
1050 | dev_dbg(u3d->dev, "after u3d_start, USBCMD 0x%x\n", | |
1051 | ioread32(&u3d->op_regs->usbcmd)); | |
1052 | } | |
1053 | ||
1054 | static int mv_u3d_controller_reset(struct mv_u3d *u3d) | |
1055 | { | |
1056 | unsigned int loops; | |
1057 | u32 tmp; | |
1058 | ||
1059 | /* Stop the controller */ | |
1060 | tmp = ioread32(&u3d->op_regs->usbcmd); | |
1061 | tmp &= ~MV_U3D_CMD_RUN_STOP; | |
1062 | iowrite32(tmp, &u3d->op_regs->usbcmd); | |
1063 | ||
1064 | /* Reset the controller to get default values */ | |
1065 | iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd); | |
1066 | ||
1067 | /* wait for reset to complete */ | |
1068 | loops = LOOPS(MV_U3D_RESET_TIMEOUT); | |
1069 | while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) { | |
1070 | if (loops == 0) { | |
1071 | dev_err(u3d->dev, | |
1072 | "Wait for RESET completed TIMEOUT\n"); | |
1073 | return -ETIMEDOUT; | |
1074 | } | |
1075 | loops--; | |
1076 | udelay(LOOPS_USEC); | |
1077 | } | |
1078 | ||
1079 | /* Configure the Endpoint Context Address */ | |
1080 | iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl); | |
1081 | iowrite32(0, &u3d->op_regs->dcbaaph); | |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | static int mv_u3d_enable(struct mv_u3d *u3d) | |
1087 | { | |
e01ee9f5 | 1088 | struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev); |
3d4eb9df YX |
1089 | int retval; |
1090 | ||
1091 | if (u3d->active) | |
1092 | return 0; | |
1093 | ||
1094 | if (!u3d->clock_gating) { | |
1095 | u3d->active = 1; | |
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | dev_dbg(u3d->dev, "enable u3d\n"); | |
1100 | clk_enable(u3d->clk); | |
1101 | if (pdata->phy_init) { | |
1102 | retval = pdata->phy_init(u3d->phy_regs); | |
1103 | if (retval) { | |
1104 | dev_err(u3d->dev, | |
1105 | "init phy error %d\n", retval); | |
1106 | clk_disable(u3d->clk); | |
1107 | return retval; | |
1108 | } | |
1109 | } | |
1110 | u3d->active = 1; | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static void mv_u3d_disable(struct mv_u3d *u3d) | |
1116 | { | |
e01ee9f5 | 1117 | struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev); |
3d4eb9df YX |
1118 | if (u3d->clock_gating && u3d->active) { |
1119 | dev_dbg(u3d->dev, "disable u3d\n"); | |
1120 | if (pdata->phy_deinit) | |
1121 | pdata->phy_deinit(u3d->phy_regs); | |
1122 | clk_disable(u3d->clk); | |
1123 | u3d->active = 0; | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | static int mv_u3d_vbus_session(struct usb_gadget *gadget, int is_active) | |
1128 | { | |
1129 | struct mv_u3d *u3d; | |
1130 | unsigned long flags; | |
1131 | int retval = 0; | |
1132 | ||
1133 | u3d = container_of(gadget, struct mv_u3d, gadget); | |
1134 | ||
1135 | spin_lock_irqsave(&u3d->lock, flags); | |
1136 | ||
1137 | u3d->vbus_active = (is_active != 0); | |
1138 | dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n", | |
1139 | __func__, u3d->softconnect, u3d->vbus_active); | |
1140 | /* | |
1141 | * 1. external VBUS detect: we can disable/enable clock on demand. | |
1142 | * 2. UDC VBUS detect: we have to enable clock all the time. | |
1143 | * 3. No VBUS detect: we have to enable clock all the time. | |
1144 | */ | |
1145 | if (u3d->driver && u3d->softconnect && u3d->vbus_active) { | |
1146 | retval = mv_u3d_enable(u3d); | |
1147 | if (retval == 0) { | |
1148 | /* | |
1149 | * after clock is disabled, we lost all the register | |
1150 | * context. We have to re-init registers | |
1151 | */ | |
1152 | mv_u3d_controller_reset(u3d); | |
1153 | mv_u3d_ep0_reset(u3d); | |
1154 | mv_u3d_controller_start(u3d); | |
1155 | } | |
1156 | } else if (u3d->driver && u3d->softconnect) { | |
1157 | if (!u3d->active) | |
1158 | goto out; | |
1159 | ||
1160 | /* stop all the transfer in queue*/ | |
1161 | mv_u3d_stop_activity(u3d, u3d->driver); | |
1162 | mv_u3d_controller_stop(u3d); | |
1163 | mv_u3d_disable(u3d); | |
1164 | } | |
1165 | ||
1166 | out: | |
1167 | spin_unlock_irqrestore(&u3d->lock, flags); | |
1168 | return retval; | |
1169 | } | |
1170 | ||
1171 | /* constrain controller's VBUS power usage | |
1172 | * This call is used by gadget drivers during SET_CONFIGURATION calls, | |
1173 | * reporting how much power the device may consume. For example, this | |
1174 | * could affect how quickly batteries are recharged. | |
1175 | * | |
1176 | * Returns zero on success, else negative errno. | |
1177 | */ | |
1178 | static int mv_u3d_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1179 | { | |
1180 | struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget); | |
1181 | ||
1182 | u3d->power = mA; | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | static int mv_u3d_pullup(struct usb_gadget *gadget, int is_on) | |
1188 | { | |
1189 | struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget); | |
1190 | unsigned long flags; | |
1191 | int retval = 0; | |
1192 | ||
1193 | spin_lock_irqsave(&u3d->lock, flags); | |
1194 | ||
1195 | dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n", | |
1196 | __func__, u3d->softconnect, u3d->vbus_active); | |
1197 | u3d->softconnect = (is_on != 0); | |
1198 | if (u3d->driver && u3d->softconnect && u3d->vbus_active) { | |
1199 | retval = mv_u3d_enable(u3d); | |
1200 | if (retval == 0) { | |
1201 | /* | |
1202 | * after clock is disabled, we lost all the register | |
1203 | * context. We have to re-init registers | |
1204 | */ | |
1205 | mv_u3d_controller_reset(u3d); | |
1206 | mv_u3d_ep0_reset(u3d); | |
1207 | mv_u3d_controller_start(u3d); | |
1208 | } | |
1209 | } else if (u3d->driver && u3d->vbus_active) { | |
1210 | /* stop all the transfer in queue*/ | |
1211 | mv_u3d_stop_activity(u3d, u3d->driver); | |
1212 | mv_u3d_controller_stop(u3d); | |
1213 | mv_u3d_disable(u3d); | |
1214 | } | |
1215 | ||
1216 | spin_unlock_irqrestore(&u3d->lock, flags); | |
1217 | ||
1218 | return retval; | |
1219 | } | |
1220 | ||
1221 | static int mv_u3d_start(struct usb_gadget *g, | |
1222 | struct usb_gadget_driver *driver) | |
1223 | { | |
1224 | struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget); | |
e01ee9f5 | 1225 | struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev); |
3d4eb9df YX |
1226 | unsigned long flags; |
1227 | ||
1228 | if (u3d->driver) | |
1229 | return -EBUSY; | |
1230 | ||
1231 | spin_lock_irqsave(&u3d->lock, flags); | |
1232 | ||
1233 | if (!u3d->clock_gating) { | |
1234 | clk_enable(u3d->clk); | |
1235 | if (pdata->phy_init) | |
1236 | pdata->phy_init(u3d->phy_regs); | |
1237 | } | |
1238 | ||
1239 | /* hook up the driver ... */ | |
1240 | driver->driver.bus = NULL; | |
1241 | u3d->driver = driver; | |
3d4eb9df YX |
1242 | |
1243 | u3d->ep0_dir = USB_DIR_OUT; | |
1244 | ||
1245 | spin_unlock_irqrestore(&u3d->lock, flags); | |
1246 | ||
1247 | u3d->vbus_valid_detect = 1; | |
1248 | ||
1249 | return 0; | |
1250 | } | |
1251 | ||
22835b80 | 1252 | static int mv_u3d_stop(struct usb_gadget *g) |
3d4eb9df YX |
1253 | { |
1254 | struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget); | |
e01ee9f5 | 1255 | struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev); |
3d4eb9df YX |
1256 | unsigned long flags; |
1257 | ||
1258 | u3d->vbus_valid_detect = 0; | |
1259 | spin_lock_irqsave(&u3d->lock, flags); | |
1260 | ||
1261 | /* enable clock to access controller register */ | |
1262 | clk_enable(u3d->clk); | |
1263 | if (pdata->phy_init) | |
1264 | pdata->phy_init(u3d->phy_regs); | |
1265 | ||
1266 | mv_u3d_controller_stop(u3d); | |
1267 | /* stop all usb activities */ | |
1268 | u3d->gadget.speed = USB_SPEED_UNKNOWN; | |
a19f3787 | 1269 | mv_u3d_stop_activity(u3d, NULL); |
3d4eb9df YX |
1270 | mv_u3d_disable(u3d); |
1271 | ||
1272 | if (pdata->phy_deinit) | |
1273 | pdata->phy_deinit(u3d->phy_regs); | |
1274 | clk_disable(u3d->clk); | |
1275 | ||
1276 | spin_unlock_irqrestore(&u3d->lock, flags); | |
1277 | ||
3d4eb9df YX |
1278 | u3d->driver = NULL; |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | /* device controller usb_gadget_ops structure */ | |
1284 | static const struct usb_gadget_ops mv_u3d_ops = { | |
1285 | /* notify controller that VBUS is powered or not */ | |
1286 | .vbus_session = mv_u3d_vbus_session, | |
1287 | ||
1288 | /* constrain controller's VBUS power usage */ | |
1289 | .vbus_draw = mv_u3d_vbus_draw, | |
1290 | ||
1291 | .pullup = mv_u3d_pullup, | |
1292 | .udc_start = mv_u3d_start, | |
1293 | .udc_stop = mv_u3d_stop, | |
1294 | }; | |
1295 | ||
1296 | static int mv_u3d_eps_init(struct mv_u3d *u3d) | |
1297 | { | |
1298 | struct mv_u3d_ep *ep; | |
1299 | char name[14]; | |
1300 | int i; | |
1301 | ||
1302 | /* initialize ep0, ep0 in/out use eps[1] */ | |
1303 | ep = &u3d->eps[1]; | |
1304 | ep->u3d = u3d; | |
1305 | strncpy(ep->name, "ep0", sizeof(ep->name)); | |
1306 | ep->ep.name = ep->name; | |
1307 | ep->ep.ops = &mv_u3d_ep_ops; | |
1308 | ep->wedge = 0; | |
e117e742 | 1309 | usb_ep_set_maxpacket_limit(&ep->ep, MV_U3D_EP0_MAX_PKT_SIZE); |
c12a3062 RB |
1310 | ep->ep.caps.type_control = true; |
1311 | ep->ep.caps.dir_in = true; | |
1312 | ep->ep.caps.dir_out = true; | |
3d4eb9df YX |
1313 | ep->ep_num = 0; |
1314 | ep->ep.desc = &mv_u3d_ep0_desc; | |
1315 | INIT_LIST_HEAD(&ep->queue); | |
1316 | INIT_LIST_HEAD(&ep->req_list); | |
1317 | ep->ep_type = USB_ENDPOINT_XFER_CONTROL; | |
1318 | ||
1319 | /* add ep0 ep_context */ | |
1320 | ep->ep_context = &u3d->ep_context[1]; | |
1321 | ||
1322 | /* initialize other endpoints */ | |
1323 | for (i = 2; i < u3d->max_eps * 2; i++) { | |
1324 | ep = &u3d->eps[i]; | |
1325 | if (i & 1) { | |
1326 | snprintf(name, sizeof(name), "ep%din", i >> 1); | |
1327 | ep->direction = MV_U3D_EP_DIR_IN; | |
c12a3062 | 1328 | ep->ep.caps.dir_in = true; |
3d4eb9df YX |
1329 | } else { |
1330 | snprintf(name, sizeof(name), "ep%dout", i >> 1); | |
1331 | ep->direction = MV_U3D_EP_DIR_OUT; | |
c12a3062 | 1332 | ep->ep.caps.dir_out = true; |
3d4eb9df YX |
1333 | } |
1334 | ep->u3d = u3d; | |
1335 | strncpy(ep->name, name, sizeof(ep->name)); | |
1336 | ep->ep.name = ep->name; | |
1337 | ||
c12a3062 RB |
1338 | ep->ep.caps.type_iso = true; |
1339 | ep->ep.caps.type_bulk = true; | |
1340 | ep->ep.caps.type_int = true; | |
1341 | ||
3d4eb9df | 1342 | ep->ep.ops = &mv_u3d_ep_ops; |
e117e742 | 1343 | usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0); |
3d4eb9df YX |
1344 | ep->ep_num = i / 2; |
1345 | ||
1346 | INIT_LIST_HEAD(&ep->queue); | |
1347 | list_add_tail(&ep->ep.ep_list, &u3d->gadget.ep_list); | |
1348 | ||
1349 | INIT_LIST_HEAD(&ep->req_list); | |
1350 | spin_lock_init(&ep->req_lock); | |
1351 | ep->ep_context = &u3d->ep_context[i]; | |
1352 | } | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | ||
1357 | /* delete all endpoint requests, called with spinlock held */ | |
1358 | static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status) | |
1359 | { | |
1360 | /* endpoint fifo flush */ | |
1361 | mv_u3d_ep_fifo_flush(&ep->ep); | |
1362 | ||
1363 | while (!list_empty(&ep->queue)) { | |
1364 | struct mv_u3d_req *req = NULL; | |
1365 | req = list_entry(ep->queue.next, struct mv_u3d_req, queue); | |
1366 | mv_u3d_done(ep, req, status); | |
1367 | } | |
1368 | } | |
1369 | ||
1370 | /* stop all USB activities */ | |
1371 | static | |
1372 | void mv_u3d_stop_activity(struct mv_u3d *u3d, struct usb_gadget_driver *driver) | |
1373 | { | |
1374 | struct mv_u3d_ep *ep; | |
1375 | ||
1376 | mv_u3d_nuke(&u3d->eps[1], -ESHUTDOWN); | |
1377 | ||
1378 | list_for_each_entry(ep, &u3d->gadget.ep_list, ep.ep_list) { | |
1379 | mv_u3d_nuke(ep, -ESHUTDOWN); | |
1380 | } | |
1381 | ||
1382 | /* report disconnect; the driver is already quiesced */ | |
1383 | if (driver) { | |
1384 | spin_unlock(&u3d->lock); | |
1385 | driver->disconnect(&u3d->gadget); | |
1386 | spin_lock(&u3d->lock); | |
1387 | } | |
1388 | } | |
1389 | ||
1390 | static void mv_u3d_irq_process_error(struct mv_u3d *u3d) | |
1391 | { | |
1392 | /* Increment the error count */ | |
1393 | u3d->errors++; | |
1394 | dev_err(u3d->dev, "%s\n", __func__); | |
1395 | } | |
1396 | ||
1397 | static void mv_u3d_irq_process_link_change(struct mv_u3d *u3d) | |
1398 | { | |
1399 | u32 linkchange; | |
1400 | ||
1401 | linkchange = ioread32(&u3d->vuc_regs->linkchange); | |
1402 | iowrite32(linkchange, &u3d->vuc_regs->linkchange); | |
1403 | ||
1404 | dev_dbg(u3d->dev, "linkchange: 0x%x\n", linkchange); | |
1405 | ||
1406 | if (linkchange & MV_U3D_LINK_CHANGE_LINK_UP) { | |
1407 | dev_dbg(u3d->dev, "link up: ltssm state: 0x%x\n", | |
1408 | ioread32(&u3d->vuc_regs->ltssmstate)); | |
1409 | ||
1410 | u3d->usb_state = USB_STATE_DEFAULT; | |
1411 | u3d->ep0_dir = MV_U3D_EP_DIR_OUT; | |
1412 | u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP; | |
1413 | ||
1414 | /* set speed */ | |
1415 | u3d->gadget.speed = USB_SPEED_SUPER; | |
1416 | } | |
1417 | ||
1418 | if (linkchange & MV_U3D_LINK_CHANGE_SUSPEND) { | |
1419 | dev_dbg(u3d->dev, "link suspend\n"); | |
1420 | u3d->resume_state = u3d->usb_state; | |
1421 | u3d->usb_state = USB_STATE_SUSPENDED; | |
1422 | } | |
1423 | ||
1424 | if (linkchange & MV_U3D_LINK_CHANGE_RESUME) { | |
1425 | dev_dbg(u3d->dev, "link resume\n"); | |
1426 | u3d->usb_state = u3d->resume_state; | |
1427 | u3d->resume_state = 0; | |
1428 | } | |
1429 | ||
1430 | if (linkchange & MV_U3D_LINK_CHANGE_WRESET) { | |
1431 | dev_dbg(u3d->dev, "warm reset\n"); | |
1432 | u3d->usb_state = USB_STATE_POWERED; | |
1433 | } | |
1434 | ||
1435 | if (linkchange & MV_U3D_LINK_CHANGE_HRESET) { | |
1436 | dev_dbg(u3d->dev, "hot reset\n"); | |
1437 | u3d->usb_state = USB_STATE_DEFAULT; | |
1438 | } | |
1439 | ||
1440 | if (linkchange & MV_U3D_LINK_CHANGE_INACT) | |
1441 | dev_dbg(u3d->dev, "inactive\n"); | |
1442 | ||
1443 | if (linkchange & MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0) | |
1444 | dev_dbg(u3d->dev, "ss.disabled\n"); | |
1445 | ||
1446 | if (linkchange & MV_U3D_LINK_CHANGE_VBUS_INVALID) { | |
1447 | dev_dbg(u3d->dev, "vbus invalid\n"); | |
1448 | u3d->usb_state = USB_STATE_ATTACHED; | |
1449 | u3d->vbus_valid_detect = 1; | |
1450 | /* if external vbus detect is not supported, | |
1451 | * we handle it here. | |
1452 | */ | |
1453 | if (!u3d->vbus) { | |
1454 | spin_unlock(&u3d->lock); | |
1455 | mv_u3d_vbus_session(&u3d->gadget, 0); | |
1456 | spin_lock(&u3d->lock); | |
1457 | } | |
1458 | } | |
1459 | } | |
1460 | ||
1461 | static void mv_u3d_ch9setaddress(struct mv_u3d *u3d, | |
1462 | struct usb_ctrlrequest *setup) | |
1463 | { | |
1464 | u32 tmp; | |
1465 | ||
1466 | if (u3d->usb_state != USB_STATE_DEFAULT) { | |
1467 | dev_err(u3d->dev, | |
1468 | "%s, cannot setaddr in this state (%d)\n", | |
1469 | __func__, u3d->usb_state); | |
1470 | goto err; | |
1471 | } | |
1472 | ||
1473 | u3d->dev_addr = (u8)setup->wValue; | |
1474 | ||
1475 | dev_dbg(u3d->dev, "%s: 0x%x\n", __func__, u3d->dev_addr); | |
1476 | ||
1477 | if (u3d->dev_addr > 127) { | |
1478 | dev_err(u3d->dev, | |
1479 | "%s, u3d address is wrong (out of range)\n", __func__); | |
1480 | u3d->dev_addr = 0; | |
1481 | goto err; | |
1482 | } | |
1483 | ||
1484 | /* update usb state */ | |
1485 | u3d->usb_state = USB_STATE_ADDRESS; | |
1486 | ||
1487 | /* set the new address */ | |
1488 | tmp = ioread32(&u3d->vuc_regs->devaddrtiebrkr); | |
1489 | tmp &= ~0x7F; | |
1490 | tmp |= (u32)u3d->dev_addr; | |
1491 | iowrite32(tmp, &u3d->vuc_regs->devaddrtiebrkr); | |
1492 | ||
1493 | return; | |
1494 | err: | |
1495 | mv_u3d_ep0_stall(u3d); | |
1496 | } | |
1497 | ||
1498 | static int mv_u3d_is_set_configuration(struct usb_ctrlrequest *setup) | |
1499 | { | |
1500 | if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
1501 | if (setup->bRequest == USB_REQ_SET_CONFIGURATION) | |
1502 | return 1; | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | static void mv_u3d_handle_setup_packet(struct mv_u3d *u3d, u8 ep_num, | |
1508 | struct usb_ctrlrequest *setup) | |
6fbb2f7d FB |
1509 | __releases(&u3c->lock) |
1510 | __acquires(&u3c->lock) | |
3d4eb9df YX |
1511 | { |
1512 | bool delegate = false; | |
1513 | ||
1514 | mv_u3d_nuke(&u3d->eps[ep_num * 2 + MV_U3D_EP_DIR_IN], -ESHUTDOWN); | |
1515 | ||
1516 | dev_dbg(u3d->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1517 | setup->bRequestType, setup->bRequest, | |
1518 | setup->wValue, setup->wIndex, setup->wLength); | |
1519 | ||
1520 | /* We process some stardard setup requests here */ | |
1521 | if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1522 | switch (setup->bRequest) { | |
1523 | case USB_REQ_GET_STATUS: | |
1524 | delegate = true; | |
1525 | break; | |
1526 | ||
1527 | case USB_REQ_SET_ADDRESS: | |
1528 | mv_u3d_ch9setaddress(u3d, setup); | |
1529 | break; | |
1530 | ||
1531 | case USB_REQ_CLEAR_FEATURE: | |
1532 | delegate = true; | |
1533 | break; | |
1534 | ||
1535 | case USB_REQ_SET_FEATURE: | |
1536 | delegate = true; | |
1537 | break; | |
1538 | ||
1539 | default: | |
1540 | delegate = true; | |
1541 | } | |
1542 | } else | |
1543 | delegate = true; | |
1544 | ||
1545 | /* delegate USB standard requests to the gadget driver */ | |
1546 | if (delegate == true) { | |
1547 | /* USB requests handled by gadget */ | |
1548 | if (setup->wLength) { | |
1549 | /* DATA phase from gadget, STATUS phase from u3d */ | |
1550 | u3d->ep0_dir = (setup->bRequestType & USB_DIR_IN) | |
1551 | ? MV_U3D_EP_DIR_IN : MV_U3D_EP_DIR_OUT; | |
1552 | spin_unlock(&u3d->lock); | |
1553 | if (u3d->driver->setup(&u3d->gadget, | |
1554 | &u3d->local_setup_buff) < 0) { | |
1555 | dev_err(u3d->dev, "setup error!\n"); | |
1556 | mv_u3d_ep0_stall(u3d); | |
1557 | } | |
1558 | spin_lock(&u3d->lock); | |
1559 | } else { | |
1560 | /* no DATA phase, STATUS phase from gadget */ | |
1561 | u3d->ep0_dir = MV_U3D_EP_DIR_IN; | |
1562 | u3d->ep0_state = MV_U3D_STATUS_STAGE; | |
1563 | spin_unlock(&u3d->lock); | |
1564 | if (u3d->driver->setup(&u3d->gadget, | |
1565 | &u3d->local_setup_buff) < 0) | |
1566 | mv_u3d_ep0_stall(u3d); | |
1567 | spin_lock(&u3d->lock); | |
1568 | } | |
1569 | ||
1570 | if (mv_u3d_is_set_configuration(setup)) { | |
1571 | dev_dbg(u3d->dev, "u3d configured\n"); | |
1572 | u3d->usb_state = USB_STATE_CONFIGURED; | |
1573 | } | |
1574 | } | |
1575 | } | |
1576 | ||
1577 | static void mv_u3d_get_setup_data(struct mv_u3d *u3d, u8 ep_num, u8 *buffer_ptr) | |
1578 | { | |
1579 | struct mv_u3d_ep_context *epcontext; | |
1580 | ||
1581 | epcontext = &u3d->ep_context[ep_num * 2 + MV_U3D_EP_DIR_IN]; | |
1582 | ||
1583 | /* Copy the setup packet to local buffer */ | |
1584 | memcpy(buffer_ptr, (u8 *) &epcontext->setup_buffer, 8); | |
1585 | } | |
1586 | ||
1587 | static void mv_u3d_irq_process_setup(struct mv_u3d *u3d) | |
1588 | { | |
1589 | u32 tmp, i; | |
1590 | /* Process all Setup packet received interrupts */ | |
1591 | tmp = ioread32(&u3d->vuc_regs->setuplock); | |
1592 | if (tmp) { | |
1593 | for (i = 0; i < u3d->max_eps; i++) { | |
1594 | if (tmp & (1 << i)) { | |
1595 | mv_u3d_get_setup_data(u3d, i, | |
1596 | (u8 *)(&u3d->local_setup_buff)); | |
1597 | mv_u3d_handle_setup_packet(u3d, i, | |
1598 | &u3d->local_setup_buff); | |
1599 | } | |
1600 | } | |
1601 | } | |
1602 | ||
1603 | iowrite32(tmp, &u3d->vuc_regs->setuplock); | |
1604 | } | |
1605 | ||
1606 | static void mv_u3d_irq_process_tr_complete(struct mv_u3d *u3d) | |
1607 | { | |
1608 | u32 tmp, bit_pos; | |
1609 | int i, ep_num = 0, direction = 0; | |
1610 | struct mv_u3d_ep *curr_ep; | |
1611 | struct mv_u3d_req *curr_req, *temp_req; | |
1612 | int status; | |
1613 | ||
1614 | tmp = ioread32(&u3d->vuc_regs->endcomplete); | |
1615 | ||
1616 | dev_dbg(u3d->dev, "tr_complete: ep: 0x%x\n", tmp); | |
1617 | if (!tmp) | |
1618 | return; | |
1619 | iowrite32(tmp, &u3d->vuc_regs->endcomplete); | |
1620 | ||
1621 | for (i = 0; i < u3d->max_eps * 2; i++) { | |
1622 | ep_num = i >> 1; | |
1623 | direction = i % 2; | |
1624 | ||
1625 | bit_pos = 1 << (ep_num + 16 * direction); | |
1626 | ||
1627 | if (!(bit_pos & tmp)) | |
1628 | continue; | |
1629 | ||
1630 | if (i == 0) | |
1631 | curr_ep = &u3d->eps[1]; | |
1632 | else | |
1633 | curr_ep = &u3d->eps[i]; | |
1634 | ||
1635 | /* remove req out of ep request list after completion */ | |
1636 | dev_dbg(u3d->dev, "tr comp: check req_list\n"); | |
1637 | spin_lock(&curr_ep->req_lock); | |
1638 | if (!list_empty(&curr_ep->req_list)) { | |
1639 | struct mv_u3d_req *req; | |
1640 | req = list_entry(curr_ep->req_list.next, | |
1641 | struct mv_u3d_req, list); | |
1642 | list_del_init(&req->list); | |
1643 | curr_ep->processing = 0; | |
1644 | } | |
1645 | spin_unlock(&curr_ep->req_lock); | |
1646 | ||
1647 | /* process the req queue until an uncomplete request */ | |
1648 | list_for_each_entry_safe(curr_req, temp_req, | |
1649 | &curr_ep->queue, queue) { | |
1650 | status = mv_u3d_process_ep_req(u3d, i, curr_req); | |
1651 | if (status) | |
1652 | break; | |
1653 | /* write back status to req */ | |
1654 | curr_req->req.status = status; | |
1655 | ||
1656 | /* ep0 request completion */ | |
1657 | if (ep_num == 0) { | |
1658 | mv_u3d_done(curr_ep, curr_req, 0); | |
1659 | break; | |
1660 | } else { | |
1661 | mv_u3d_done(curr_ep, curr_req, status); | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | dev_dbg(u3d->dev, "call mv_u3d_start_queue from ep complete\n"); | |
1666 | mv_u3d_start_queue(curr_ep); | |
1667 | } | |
1668 | } | |
1669 | ||
1670 | static irqreturn_t mv_u3d_irq(int irq, void *dev) | |
1671 | { | |
1672 | struct mv_u3d *u3d = (struct mv_u3d *)dev; | |
1673 | u32 status, intr; | |
1674 | u32 bridgesetting; | |
1675 | u32 trbunderrun; | |
1676 | ||
1677 | spin_lock(&u3d->lock); | |
1678 | ||
1679 | status = ioread32(&u3d->vuc_regs->intrcause); | |
1680 | intr = ioread32(&u3d->vuc_regs->intrenable); | |
1681 | status &= intr; | |
1682 | ||
1683 | if (status == 0) { | |
1684 | spin_unlock(&u3d->lock); | |
1685 | dev_err(u3d->dev, "irq error!\n"); | |
1686 | return IRQ_NONE; | |
1687 | } | |
1688 | ||
1689 | if (status & MV_U3D_USBINT_VBUS_VALID) { | |
1690 | bridgesetting = ioread32(&u3d->vuc_regs->bridgesetting); | |
1691 | if (bridgesetting & MV_U3D_BRIDGE_SETTING_VBUS_VALID) { | |
1692 | /* write vbus valid bit of bridge setting to clear */ | |
1693 | bridgesetting = MV_U3D_BRIDGE_SETTING_VBUS_VALID; | |
1694 | iowrite32(bridgesetting, &u3d->vuc_regs->bridgesetting); | |
1695 | dev_dbg(u3d->dev, "vbus valid\n"); | |
1696 | ||
1697 | u3d->usb_state = USB_STATE_POWERED; | |
1698 | u3d->vbus_valid_detect = 0; | |
1699 | /* if external vbus detect is not supported, | |
1700 | * we handle it here. | |
1701 | */ | |
1702 | if (!u3d->vbus) { | |
1703 | spin_unlock(&u3d->lock); | |
1704 | mv_u3d_vbus_session(&u3d->gadget, 1); | |
1705 | spin_lock(&u3d->lock); | |
1706 | } | |
1707 | } else | |
1708 | dev_err(u3d->dev, "vbus bit is not set\n"); | |
1709 | } | |
1710 | ||
1711 | /* RX data is already in the 16KB FIFO.*/ | |
1712 | if (status & MV_U3D_USBINT_UNDER_RUN) { | |
1713 | trbunderrun = ioread32(&u3d->vuc_regs->trbunderrun); | |
1714 | dev_err(u3d->dev, "under run, ep%d\n", trbunderrun); | |
1715 | iowrite32(trbunderrun, &u3d->vuc_regs->trbunderrun); | |
1716 | mv_u3d_irq_process_error(u3d); | |
1717 | } | |
1718 | ||
1719 | if (status & (MV_U3D_USBINT_RXDESC_ERR | MV_U3D_USBINT_TXDESC_ERR)) { | |
1720 | /* write one to clear */ | |
1721 | iowrite32(status & (MV_U3D_USBINT_RXDESC_ERR | |
1722 | | MV_U3D_USBINT_TXDESC_ERR), | |
1723 | &u3d->vuc_regs->intrcause); | |
1724 | dev_err(u3d->dev, "desc err 0x%x\n", status); | |
1725 | mv_u3d_irq_process_error(u3d); | |
1726 | } | |
1727 | ||
1728 | if (status & MV_U3D_USBINT_LINK_CHG) | |
1729 | mv_u3d_irq_process_link_change(u3d); | |
1730 | ||
1731 | if (status & MV_U3D_USBINT_TX_COMPLETE) | |
1732 | mv_u3d_irq_process_tr_complete(u3d); | |
1733 | ||
1734 | if (status & MV_U3D_USBINT_RX_COMPLETE) | |
1735 | mv_u3d_irq_process_tr_complete(u3d); | |
1736 | ||
1737 | if (status & MV_U3D_USBINT_SETUP) | |
1738 | mv_u3d_irq_process_setup(u3d); | |
1739 | ||
1740 | spin_unlock(&u3d->lock); | |
1741 | return IRQ_HANDLED; | |
1742 | } | |
1743 | ||
fb4e98ab | 1744 | static int mv_u3d_remove(struct platform_device *dev) |
3d4eb9df YX |
1745 | { |
1746 | struct mv_u3d *u3d = platform_get_drvdata(dev); | |
1747 | ||
1748 | BUG_ON(u3d == NULL); | |
1749 | ||
1750 | usb_del_gadget_udc(&u3d->gadget); | |
1751 | ||
1752 | /* free memory allocated in probe */ | |
51b91b7e | 1753 | dma_pool_destroy(u3d->trb_pool); |
3d4eb9df YX |
1754 | |
1755 | if (u3d->ep_context) | |
1756 | dma_free_coherent(&dev->dev, u3d->ep_context_size, | |
1757 | u3d->ep_context, u3d->ep_context_dma); | |
1758 | ||
1759 | kfree(u3d->eps); | |
1760 | ||
1761 | if (u3d->irq) | |
5257a633 | 1762 | free_irq(u3d->irq, u3d); |
3d4eb9df YX |
1763 | |
1764 | if (u3d->cap_regs) | |
1765 | iounmap(u3d->cap_regs); | |
1766 | u3d->cap_regs = NULL; | |
1767 | ||
1768 | kfree(u3d->status_req); | |
1769 | ||
1770 | clk_put(u3d->clk); | |
1771 | ||
3d4eb9df YX |
1772 | kfree(u3d); |
1773 | ||
1774 | return 0; | |
1775 | } | |
1776 | ||
1777 | static int mv_u3d_probe(struct platform_device *dev) | |
1778 | { | |
1779 | struct mv_u3d *u3d = NULL; | |
e01ee9f5 | 1780 | struct mv_usb_platform_data *pdata = dev_get_platdata(&dev->dev); |
3d4eb9df YX |
1781 | int retval = 0; |
1782 | struct resource *r; | |
1783 | size_t size; | |
1784 | ||
e01ee9f5 | 1785 | if (!dev_get_platdata(&dev->dev)) { |
3d4eb9df YX |
1786 | dev_err(&dev->dev, "missing platform_data\n"); |
1787 | retval = -ENODEV; | |
1788 | goto err_pdata; | |
1789 | } | |
1790 | ||
1791 | u3d = kzalloc(sizeof(*u3d), GFP_KERNEL); | |
1792 | if (!u3d) { | |
3d4eb9df YX |
1793 | retval = -ENOMEM; |
1794 | goto err_alloc_private; | |
1795 | } | |
1796 | ||
1797 | spin_lock_init(&u3d->lock); | |
1798 | ||
1799 | platform_set_drvdata(dev, u3d); | |
1800 | ||
1801 | u3d->dev = &dev->dev; | |
1802 | u3d->vbus = pdata->vbus; | |
1803 | ||
65cd3f2b | 1804 | u3d->clk = clk_get(&dev->dev, NULL); |
3d4eb9df YX |
1805 | if (IS_ERR(u3d->clk)) { |
1806 | retval = PTR_ERR(u3d->clk); | |
1807 | goto err_get_clk; | |
1808 | } | |
1809 | ||
1810 | r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs"); | |
1811 | if (!r) { | |
1812 | dev_err(&dev->dev, "no I/O memory resource defined\n"); | |
1813 | retval = -ENODEV; | |
1814 | goto err_get_cap_regs; | |
1815 | } | |
1816 | ||
1817 | u3d->cap_regs = (struct mv_u3d_cap_regs __iomem *) | |
1818 | ioremap(r->start, resource_size(r)); | |
1819 | if (!u3d->cap_regs) { | |
1820 | dev_err(&dev->dev, "failed to map I/O memory\n"); | |
1821 | retval = -EBUSY; | |
1822 | goto err_map_cap_regs; | |
1823 | } else { | |
e6667ef7 FB |
1824 | dev_dbg(&dev->dev, "cap_regs address: 0x%lx/0x%lx\n", |
1825 | (unsigned long) r->start, | |
1826 | (unsigned long) u3d->cap_regs); | |
3d4eb9df YX |
1827 | } |
1828 | ||
1829 | /* we will access controller register, so enable the u3d controller */ | |
1830 | clk_enable(u3d->clk); | |
1831 | ||
1832 | if (pdata->phy_init) { | |
1833 | retval = pdata->phy_init(u3d->phy_regs); | |
1834 | if (retval) { | |
1835 | dev_err(&dev->dev, "init phy error %d\n", retval); | |
1836 | goto err_u3d_enable; | |
1837 | } | |
1838 | } | |
1839 | ||
e6667ef7 | 1840 | u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs |
3d4eb9df YX |
1841 | + MV_U3D_USB3_OP_REGS_OFFSET); |
1842 | ||
e6667ef7 | 1843 | u3d->vuc_regs = (struct mv_u3d_vuc_regs __iomem *)(u3d->cap_regs |
3d4eb9df YX |
1844 | + ioread32(&u3d->cap_regs->vuoff)); |
1845 | ||
1846 | u3d->max_eps = 16; | |
1847 | ||
1848 | /* | |
1849 | * some platform will use usb to download image, it may not disconnect | |
1850 | * usb gadget before loading kernel. So first stop u3d here. | |
1851 | */ | |
1852 | mv_u3d_controller_stop(u3d); | |
1853 | iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause); | |
1854 | ||
1855 | if (pdata->phy_deinit) | |
1856 | pdata->phy_deinit(u3d->phy_regs); | |
1857 | clk_disable(u3d->clk); | |
1858 | ||
1859 | size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2; | |
1860 | size = (size + MV_U3D_EP_CONTEXT_ALIGNMENT - 1) | |
1861 | & ~(MV_U3D_EP_CONTEXT_ALIGNMENT - 1); | |
1862 | u3d->ep_context = dma_alloc_coherent(&dev->dev, size, | |
1863 | &u3d->ep_context_dma, GFP_KERNEL); | |
1864 | if (!u3d->ep_context) { | |
1865 | dev_err(&dev->dev, "allocate ep context memory failed\n"); | |
1866 | retval = -ENOMEM; | |
1867 | goto err_alloc_ep_context; | |
1868 | } | |
1869 | u3d->ep_context_size = size; | |
1870 | ||
1871 | /* create TRB dma_pool resource */ | |
1872 | u3d->trb_pool = dma_pool_create("u3d_trb", | |
1873 | &dev->dev, | |
1874 | sizeof(struct mv_u3d_trb_hw), | |
1875 | MV_U3D_TRB_ALIGNMENT, | |
1876 | MV_U3D_DMA_BOUNDARY); | |
1877 | ||
1878 | if (!u3d->trb_pool) { | |
1879 | retval = -ENOMEM; | |
1880 | goto err_alloc_trb_pool; | |
1881 | } | |
1882 | ||
1883 | size = u3d->max_eps * sizeof(struct mv_u3d_ep) * 2; | |
1884 | u3d->eps = kzalloc(size, GFP_KERNEL); | |
1885 | if (!u3d->eps) { | |
3d4eb9df YX |
1886 | retval = -ENOMEM; |
1887 | goto err_alloc_eps; | |
1888 | } | |
1889 | ||
1890 | /* initialize ep0 status request structure */ | |
1891 | u3d->status_req = kzalloc(sizeof(struct mv_u3d_req) + 8, GFP_KERNEL); | |
1892 | if (!u3d->status_req) { | |
3d4eb9df YX |
1893 | retval = -ENOMEM; |
1894 | goto err_alloc_status_req; | |
1895 | } | |
1896 | INIT_LIST_HEAD(&u3d->status_req->queue); | |
1897 | ||
1898 | /* allocate a small amount of memory to get valid address */ | |
1899 | u3d->status_req->req.buf = (char *)u3d->status_req | |
1900 | + sizeof(struct mv_u3d_req); | |
1901 | u3d->status_req->req.dma = virt_to_phys(u3d->status_req->req.buf); | |
1902 | ||
1903 | u3d->resume_state = USB_STATE_NOTATTACHED; | |
1904 | u3d->usb_state = USB_STATE_ATTACHED; | |
1905 | u3d->ep0_dir = MV_U3D_EP_DIR_OUT; | |
1906 | u3d->remote_wakeup = 0; | |
1907 | ||
1908 | r = platform_get_resource(dev, IORESOURCE_IRQ, 0); | |
1909 | if (!r) { | |
1910 | dev_err(&dev->dev, "no IRQ resource defined\n"); | |
1911 | retval = -ENODEV; | |
1912 | goto err_get_irq; | |
1913 | } | |
1914 | u3d->irq = r->start; | |
1915 | if (request_irq(u3d->irq, mv_u3d_irq, | |
dc807576 | 1916 | IRQF_SHARED, driver_name, u3d)) { |
3d4eb9df YX |
1917 | u3d->irq = 0; |
1918 | dev_err(&dev->dev, "Request irq %d for u3d failed\n", | |
1919 | u3d->irq); | |
1920 | retval = -ENODEV; | |
1921 | goto err_request_irq; | |
1922 | } | |
1923 | ||
1924 | /* initialize gadget structure */ | |
1925 | u3d->gadget.ops = &mv_u3d_ops; /* usb_gadget_ops */ | |
1926 | u3d->gadget.ep0 = &u3d->eps[1].ep; /* gadget ep0 */ | |
1927 | INIT_LIST_HEAD(&u3d->gadget.ep_list); /* ep_list */ | |
1928 | u3d->gadget.speed = USB_SPEED_UNKNOWN; /* speed */ | |
1929 | ||
1930 | /* the "gadget" abstracts/virtualizes the controller */ | |
3d4eb9df | 1931 | u3d->gadget.name = driver_name; /* gadget name */ |
3d4eb9df YX |
1932 | |
1933 | mv_u3d_eps_init(u3d); | |
1934 | ||
1935 | /* external vbus detection */ | |
1936 | if (u3d->vbus) { | |
1937 | u3d->clock_gating = 1; | |
1938 | dev_err(&dev->dev, "external vbus detection\n"); | |
1939 | } | |
1940 | ||
1941 | if (!u3d->clock_gating) | |
1942 | u3d->vbus_active = 1; | |
1943 | ||
1944 | /* enable usb3 controller vbus detection */ | |
1945 | u3d->vbus_valid_detect = 1; | |
1946 | ||
1947 | retval = usb_add_gadget_udc(&dev->dev, &u3d->gadget); | |
1948 | if (retval) | |
1949 | goto err_unregister; | |
1950 | ||
1951 | dev_dbg(&dev->dev, "successful probe usb3 device %s clock gating.\n", | |
1952 | u3d->clock_gating ? "with" : "without"); | |
1953 | ||
1954 | return 0; | |
1955 | ||
1956 | err_unregister: | |
5257a633 | 1957 | free_irq(u3d->irq, u3d); |
3d4eb9df YX |
1958 | err_request_irq: |
1959 | err_get_irq: | |
1960 | kfree(u3d->status_req); | |
1961 | err_alloc_status_req: | |
1962 | kfree(u3d->eps); | |
1963 | err_alloc_eps: | |
1964 | dma_pool_destroy(u3d->trb_pool); | |
1965 | err_alloc_trb_pool: | |
1966 | dma_free_coherent(&dev->dev, u3d->ep_context_size, | |
1967 | u3d->ep_context, u3d->ep_context_dma); | |
1968 | err_alloc_ep_context: | |
1969 | if (pdata->phy_deinit) | |
1970 | pdata->phy_deinit(u3d->phy_regs); | |
1971 | clk_disable(u3d->clk); | |
1972 | err_u3d_enable: | |
1973 | iounmap(u3d->cap_regs); | |
1974 | err_map_cap_regs: | |
1975 | err_get_cap_regs: | |
1976 | err_get_clk: | |
1977 | clk_put(u3d->clk); | |
3d4eb9df YX |
1978 | kfree(u3d); |
1979 | err_alloc_private: | |
1980 | err_pdata: | |
1981 | return retval; | |
1982 | } | |
1983 | ||
4895a2ee | 1984 | #ifdef CONFIG_PM_SLEEP |
3d4eb9df YX |
1985 | static int mv_u3d_suspend(struct device *dev) |
1986 | { | |
1987 | struct mv_u3d *u3d = dev_get_drvdata(dev); | |
1988 | ||
1989 | /* | |
1990 | * only cable is unplugged, usb can suspend. | |
1991 | * So do not care about clock_gating == 1, it is handled by | |
1992 | * vbus session. | |
1993 | */ | |
1994 | if (!u3d->clock_gating) { | |
1995 | mv_u3d_controller_stop(u3d); | |
1996 | ||
1997 | spin_lock_irq(&u3d->lock); | |
1998 | /* stop all usb activities */ | |
1999 | mv_u3d_stop_activity(u3d, u3d->driver); | |
2000 | spin_unlock_irq(&u3d->lock); | |
2001 | ||
2002 | mv_u3d_disable(u3d); | |
2003 | } | |
2004 | ||
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | static int mv_u3d_resume(struct device *dev) | |
2009 | { | |
2010 | struct mv_u3d *u3d = dev_get_drvdata(dev); | |
2011 | int retval; | |
2012 | ||
2013 | if (!u3d->clock_gating) { | |
2014 | retval = mv_u3d_enable(u3d); | |
2015 | if (retval) | |
2016 | return retval; | |
2017 | ||
2018 | if (u3d->driver && u3d->softconnect) { | |
2019 | mv_u3d_controller_reset(u3d); | |
2020 | mv_u3d_ep0_reset(u3d); | |
2021 | mv_u3d_controller_start(u3d); | |
2022 | } | |
2023 | } | |
2024 | ||
2025 | return 0; | |
2026 | } | |
3d4eb9df YX |
2027 | #endif |
2028 | ||
4895a2ee JH |
2029 | static SIMPLE_DEV_PM_OPS(mv_u3d_pm_ops, mv_u3d_suspend, mv_u3d_resume); |
2030 | ||
3d4eb9df YX |
2031 | static void mv_u3d_shutdown(struct platform_device *dev) |
2032 | { | |
dae8eadf | 2033 | struct mv_u3d *u3d = platform_get_drvdata(dev); |
3d4eb9df YX |
2034 | u32 tmp; |
2035 | ||
2036 | tmp = ioread32(&u3d->op_regs->usbcmd); | |
2037 | tmp &= ~MV_U3D_CMD_RUN_STOP; | |
2038 | iowrite32(tmp, &u3d->op_regs->usbcmd); | |
2039 | } | |
2040 | ||
2041 | static struct platform_driver mv_u3d_driver = { | |
2042 | .probe = mv_u3d_probe, | |
2cd807e7 | 2043 | .remove = mv_u3d_remove, |
3d4eb9df YX |
2044 | .shutdown = mv_u3d_shutdown, |
2045 | .driver = { | |
3d4eb9df | 2046 | .name = "mv-u3d", |
3d4eb9df | 2047 | .pm = &mv_u3d_pm_ops, |
3d4eb9df YX |
2048 | }, |
2049 | }; | |
2050 | ||
2051 | module_platform_driver(mv_u3d_driver); | |
2052 | MODULE_ALIAS("platform:mv-u3d"); | |
2053 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2054 | MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>"); | |
2055 | MODULE_LICENSE("GPL"); |