Commit | Line | Data |
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80cb9aee | 1 | /* |
1af10774 | 2 | * Copyright 2005-2009 MontaVista Software, Inc. |
ca07e1c1 | 3 | * Copyright 2008,2012,2015 Freescale Semiconductor, Inc. |
80cb9aee RV |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software Foundation, | |
17 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided | |
20 | * by Hunter Wu. | |
1af10774 AV |
21 | * Power Management support by Dave Liu <daveliu@freescale.com>, |
22 | * Jerry Huang <Chang-Ming.Huang@freescale.com> and | |
23 | * Anton Vorontsov <avorontsov@ru.mvista.com>. | |
80cb9aee RV |
24 | */ |
25 | ||
1af10774 | 26 | #include <linux/kernel.h> |
ca07e1c1 | 27 | #include <linux/module.h> |
1af10774 AV |
28 | #include <linux/types.h> |
29 | #include <linux/delay.h> | |
30 | #include <linux/pm.h> | |
ded017ee | 31 | #include <linux/err.h> |
ca07e1c1 RM |
32 | #include <linux/usb.h> |
33 | #include <linux/usb/ehci_def.h> | |
34 | #include <linux/usb/hcd.h> | |
35 | #include <linux/usb/otg.h> | |
80cb9aee RV |
36 | #include <linux/platform_device.h> |
37 | #include <linux/fsl_devices.h> | |
38 | ||
ca07e1c1 | 39 | #include "ehci.h" |
80cb9aee RV |
40 | #include "ehci-fsl.h" |
41 | ||
ca07e1c1 RM |
42 | #define DRIVER_DESC "Freescale EHCI Host controller driver" |
43 | #define DRV_NAME "ehci-fsl" | |
44 | ||
45 | static struct hc_driver __read_mostly fsl_ehci_hc_driver; | |
46 | ||
80cb9aee RV |
47 | /* configure so an HC device and id are always provided */ |
48 | /* always called with process context; sleeping is OK */ | |
49 | ||
ca07e1c1 RM |
50 | /* |
51 | * fsl_ehci_drv_probe - initialize FSL-based HCDs | |
80cb9aee RV |
52 | * @pdev: USB Host Controller being probed |
53 | * Context: !in_interrupt() | |
54 | * | |
55 | * Allocates basic resources for this USB host controller. | |
56 | * | |
57 | */ | |
ca07e1c1 | 58 | static int fsl_ehci_drv_probe(struct platform_device *pdev) |
80cb9aee RV |
59 | { |
60 | struct fsl_usb2_platform_data *pdata; | |
61 | struct usb_hcd *hcd; | |
62 | struct resource *res; | |
63 | int irq; | |
64 | int retval; | |
80cb9aee RV |
65 | |
66 | pr_debug("initializing FSL-SOC USB Controller\n"); | |
67 | ||
68 | /* Need platform data for setup */ | |
37c3a3c4 | 69 | pdata = dev_get_platdata(&pdev->dev); |
80cb9aee RV |
70 | if (!pdata) { |
71 | dev_err(&pdev->dev, | |
7071a3ce | 72 | "No platform data for %s.\n", dev_name(&pdev->dev)); |
80cb9aee RV |
73 | return -ENODEV; |
74 | } | |
75 | ||
76 | /* | |
77 | * This is a host mode driver, verify that we're supposed to be | |
78 | * in host mode. | |
79 | */ | |
80 | if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || | |
ba02978a LY |
81 | (pdata->operating_mode == FSL_USB2_MPH_HOST) || |
82 | (pdata->operating_mode == FSL_USB2_DR_OTG))) { | |
80cb9aee RV |
83 | dev_err(&pdev->dev, |
84 | "Non Host Mode configured for %s. Wrong driver linked.\n", | |
7071a3ce | 85 | dev_name(&pdev->dev)); |
80cb9aee RV |
86 | return -ENODEV; |
87 | } | |
88 | ||
89 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
90 | if (!res) { | |
91 | dev_err(&pdev->dev, | |
92 | "Found HC with no IRQ. Check %s setup!\n", | |
7071a3ce | 93 | dev_name(&pdev->dev)); |
80cb9aee RV |
94 | return -ENODEV; |
95 | } | |
96 | irq = res->start; | |
97 | ||
ca07e1c1 RM |
98 | hcd = usb_create_hcd(&fsl_ehci_hc_driver, &pdev->dev, |
99 | dev_name(&pdev->dev)); | |
80cb9aee RV |
100 | if (!hcd) { |
101 | retval = -ENOMEM; | |
102 | goto err1; | |
103 | } | |
104 | ||
105 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
7667fe69 JH |
106 | hcd->regs = devm_ioremap_resource(&pdev->dev, res); |
107 | if (IS_ERR(hcd->regs)) { | |
108 | retval = PTR_ERR(hcd->regs); | |
80cb9aee RV |
109 | goto err2; |
110 | } | |
80cb9aee | 111 | |
ce98f548 VB |
112 | hcd->rsrc_start = res->start; |
113 | hcd->rsrc_len = resource_size(res); | |
114 | ||
230f7ede | 115 | pdata->regs = hcd->regs; |
80cb9aee | 116 | |
83722bc9 AG |
117 | if (pdata->power_budget) |
118 | hcd->power_budget = pdata->power_budget; | |
119 | ||
230f7ede AG |
120 | /* |
121 | * do platform specific init: check the clock, grab/config pins, etc. | |
122 | */ | |
123 | if (pdata->init && pdata->init(pdev)) { | |
124 | retval = -ENODEV; | |
7667fe69 | 125 | goto err2; |
230f7ede AG |
126 | } |
127 | ||
230f7ede | 128 | /* Enable USB controller, 83xx or 8536 */ |
ad1260e9 | 129 | if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) |
4e02bea8 NB |
130 | clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, |
131 | CONTROL_REGISTER_W1C_MASK, 0x4); | |
230f7ede | 132 | |
523f1dec NB |
133 | /* |
134 | * Enable UTMI phy and program PTS field in UTMI mode before asserting | |
135 | * controller reset for USB Controller version 2.5 | |
136 | */ | |
137 | if (pdata->has_fsl_erratum_a007792) { | |
4e02bea8 NB |
138 | clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL, |
139 | CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN); | |
523f1dec NB |
140 | writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); |
141 | } | |
142 | ||
230f7ede | 143 | /* Don't need to set host mode here. It will be done by tdi_reset() */ |
80cb9aee | 144 | |
b5dd18d8 | 145 | retval = usb_add_hcd(hcd, irq, IRQF_SHARED); |
80cb9aee | 146 | if (retval != 0) |
7667fe69 | 147 | goto err2; |
3c9740a1 | 148 | device_wakeup_enable(hcd->self.controller); |
83722bc9 AG |
149 | |
150 | #ifdef CONFIG_USB_OTG | |
151 | if (pdata->operating_mode == FSL_USB2_DR_OTG) { | |
152 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
153 | ||
3d46e73d | 154 | hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2); |
c2e935a7 | 155 | dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n", |
3d46e73d | 156 | hcd, ehci, hcd->usb_phy); |
83722bc9 | 157 | |
3d46e73d AT |
158 | if (!IS_ERR_OR_NULL(hcd->usb_phy)) { |
159 | retval = otg_set_host(hcd->usb_phy->otg, | |
83722bc9 AG |
160 | &ehci_to_hcd(ehci)->self); |
161 | if (retval) { | |
3d46e73d | 162 | usb_put_phy(hcd->usb_phy); |
7667fe69 | 163 | goto err2; |
83722bc9 AG |
164 | } |
165 | } else { | |
c2e935a7 | 166 | dev_err(&pdev->dev, "can't find phy\n"); |
83722bc9 | 167 | retval = -ENODEV; |
7667fe69 | 168 | goto err2; |
83722bc9 AG |
169 | } |
170 | } | |
171 | #endif | |
80cb9aee RV |
172 | return retval; |
173 | ||
80cb9aee RV |
174 | err2: |
175 | usb_put_hcd(hcd); | |
176 | err1: | |
7071a3ce | 177 | dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); |
230f7ede AG |
178 | if (pdata->exit) |
179 | pdata->exit(pdev); | |
80cb9aee RV |
180 | return retval; |
181 | } | |
182 | ||
3735ba8d | 183 | static int ehci_fsl_setup_phy(struct usb_hcd *hcd, |
230f7ede AG |
184 | enum fsl_usb2_phy_modes phy_mode, |
185 | unsigned int port_offset) | |
80cb9aee | 186 | { |
3735ba8d | 187 | u32 portsc; |
58c559e6 | 188 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
28c56ea1 | 189 | void __iomem *non_ehci = hcd->regs; |
58c559e6 | 190 | struct device *dev = hcd->self.controller; |
d4f09e28 | 191 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
f941f692 | 192 | |
58c559e6 RM |
193 | if (pdata->controller_ver < 0) { |
194 | dev_warn(hcd->self.controller, "Could not get controller version\n"); | |
d479c911 | 195 | return -ENODEV; |
58c559e6 | 196 | } |
230f7ede AG |
197 | |
198 | portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); | |
199 | portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); | |
200 | ||
80cb9aee RV |
201 | switch (phy_mode) { |
202 | case FSL_USB2_PHY_ULPI: | |
f66dea70 | 203 | if (pdata->have_sysif_regs && pdata->controller_ver) { |
58c559e6 | 204 | /* controller version 1.6 or above */ |
4e02bea8 NB |
205 | clrbits32(non_ehci + FSL_SOC_USB_CTRL, |
206 | CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); | |
207 | clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, | |
208 | CONTROL_REGISTER_W1C_MASK, | |
209 | ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN); | |
58c559e6 | 210 | } |
80cb9aee RV |
211 | portsc |= PORT_PTS_ULPI; |
212 | break; | |
213 | case FSL_USB2_PHY_SERIAL: | |
214 | portsc |= PORT_PTS_SERIAL; | |
215 | break; | |
216 | case FSL_USB2_PHY_UTMI_WIDE: | |
217 | portsc |= PORT_PTS_PTW; | |
218 | /* fall through */ | |
219 | case FSL_USB2_PHY_UTMI: | |
6009d95e | 220 | case FSL_USB2_PHY_UTMI_DUAL: |
f66dea70 | 221 | if (pdata->have_sysif_regs && pdata->controller_ver) { |
58c559e6 | 222 | /* controller version 1.6 or above */ |
4e02bea8 NB |
223 | clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, |
224 | CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN); | |
58c559e6 RM |
225 | mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to |
226 | become stable - 10ms*/ | |
227 | } | |
28c56ea1 | 228 | /* enable UTMI PHY */ |
f941f692 | 229 | if (pdata->have_sysif_regs) |
4e02bea8 NB |
230 | clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, |
231 | CONTROL_REGISTER_W1C_MASK, | |
232 | CTRL_UTMI_PHY_EN); | |
80cb9aee RV |
233 | portsc |= PORT_PTS_UTMI; |
234 | break; | |
235 | case FSL_USB2_PHY_NONE: | |
236 | break; | |
237 | } | |
3735ba8d | 238 | |
f4fdfaa2 NB |
239 | /* |
240 | * check PHY_CLK_VALID to determine phy clock presence before writing | |
241 | * to portsc | |
242 | */ | |
243 | if (pdata->check_phy_clk_valid) { | |
244 | if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) { | |
245 | dev_warn(hcd->self.controller, | |
246 | "USB PHY clock invalid\n"); | |
3735ba8d SL |
247 | return -EINVAL; |
248 | } | |
249 | } | |
250 | ||
083522d7 | 251 | ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); |
3735ba8d | 252 | |
f66dea70 | 253 | if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) |
4e02bea8 NB |
254 | clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL, |
255 | CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN); | |
3735ba8d SL |
256 | |
257 | return 0; | |
80cb9aee RV |
258 | } |
259 | ||
3735ba8d | 260 | static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) |
80cb9aee | 261 | { |
230f7ede | 262 | struct usb_hcd *hcd = ehci_to_hcd(ehci); |
80cb9aee RV |
263 | struct fsl_usb2_platform_data *pdata; |
264 | void __iomem *non_ehci = hcd->regs; | |
265 | ||
d4f09e28 | 266 | pdata = dev_get_platdata(hcd->self.controller); |
230f7ede | 267 | |
230f7ede | 268 | if (pdata->have_sysif_regs) { |
4c954326 PJ |
269 | /* |
270 | * Turn on cache snooping hardware, since some PowerPC platforms | |
271 | * wholly rely on hardware to deal with cache coherent | |
272 | */ | |
40acc095 | 273 | |
4c954326 PJ |
274 | /* Setup Snooping for all the 4GB space */ |
275 | /* SNOOP1 starts from 0x0, size 2G */ | |
276 | out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB); | |
277 | /* SNOOP2 starts from 0x80000000, size 2G */ | |
278 | out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB); | |
279 | } | |
40acc095 | 280 | |
f8786a91 NB |
281 | /* Deal with USB erratum A-005275 */ |
282 | if (pdata->has_fsl_erratum_a005275 == 1) | |
283 | ehci->has_fsl_hs_errata = 1; | |
284 | ||
ba02978a LY |
285 | if ((pdata->operating_mode == FSL_USB2_DR_HOST) || |
286 | (pdata->operating_mode == FSL_USB2_DR_OTG)) | |
3735ba8d SL |
287 | if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) |
288 | return -EINVAL; | |
80cb9aee RV |
289 | |
290 | if (pdata->operating_mode == FSL_USB2_MPH_HOST) { | |
8cd42e97 KG |
291 | unsigned int chip, rev, svr; |
292 | ||
293 | svr = mfspr(SPRN_SVR); | |
294 | chip = svr >> 16; | |
295 | rev = (svr >> 4) & 0xf; | |
296 | ||
297 | /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ | |
298 | if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055)) | |
299 | ehci->has_fsl_port_bug = 1; | |
300 | ||
80cb9aee | 301 | if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) |
3735ba8d SL |
302 | if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) |
303 | return -EINVAL; | |
304 | ||
80cb9aee | 305 | if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) |
3735ba8d SL |
306 | if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1)) |
307 | return -EINVAL; | |
80cb9aee RV |
308 | } |
309 | ||
230f7ede | 310 | if (pdata->have_sysif_regs) { |
08d7660d | 311 | #ifdef CONFIG_FSL_SOC_BOOKE |
230f7ede AG |
312 | out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008); |
313 | out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080); | |
4f534258 | 314 | #else |
230f7ede AG |
315 | out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c); |
316 | out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040); | |
4f534258 | 317 | #endif |
230f7ede AG |
318 | out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001); |
319 | } | |
3735ba8d SL |
320 | |
321 | return 0; | |
80cb9aee RV |
322 | } |
323 | ||
324 | /* called after powerup, by probe or system-pm "wakeup" */ | |
325 | static int ehci_fsl_reinit(struct ehci_hcd *ehci) | |
326 | { | |
3735ba8d SL |
327 | if (ehci_fsl_usb_setup(ehci)) |
328 | return -EINVAL; | |
80cb9aee RV |
329 | |
330 | return 0; | |
331 | } | |
332 | ||
333 | /* called during probe() after chip reset completes */ | |
334 | static int ehci_fsl_setup(struct usb_hcd *hcd) | |
335 | { | |
336 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
337 | int retval; | |
230f7ede | 338 | struct fsl_usb2_platform_data *pdata; |
761bbcb7 | 339 | struct device *dev; |
230f7ede | 340 | |
761bbcb7 | 341 | dev = hcd->self.controller; |
d4f09e28 | 342 | pdata = dev_get_platdata(hcd->self.controller); |
230f7ede AG |
343 | ehci->big_endian_desc = pdata->big_endian_desc; |
344 | ehci->big_endian_mmio = pdata->big_endian_mmio; | |
80cb9aee RV |
345 | |
346 | /* EHCI registers start at offset 0x100 */ | |
347 | ehci->caps = hcd->regs + 0x100; | |
80cb9aee | 348 | |
e6604a7f CE |
349 | #ifdef CONFIG_PPC_83xx |
350 | /* | |
351 | * Deal with MPC834X that need port power to be cycled after the power | |
352 | * fault condition is removed. Otherwise the state machine does not | |
353 | * reflect PORTSC[CSC] correctly. | |
354 | */ | |
355 | ehci->need_oc_pp_cycle = 1; | |
356 | #endif | |
357 | ||
65fd4272 MC |
358 | hcd->has_tt = 1; |
359 | ||
1a49e2ac | 360 | retval = ehci_setup(hcd); |
80cb9aee RV |
361 | if (retval) |
362 | return retval; | |
363 | ||
761bbcb7 AG |
364 | if (of_device_is_compatible(dev->parent->of_node, |
365 | "fsl,mpc5121-usb2-dr")) { | |
366 | /* | |
367 | * set SBUSCFG:AHBBRST so that control msgs don't | |
368 | * fail when doing heavy PATA writes. | |
369 | */ | |
370 | ehci_writel(ehci, SBUSCFG_INCR8, | |
371 | hcd->regs + FSL_SOC_USB_SBUSCFG); | |
372 | } | |
373 | ||
80cb9aee RV |
374 | retval = ehci_fsl_reinit(ehci); |
375 | return retval; | |
376 | } | |
377 | ||
1af10774 AV |
378 | struct ehci_fsl { |
379 | struct ehci_hcd ehci; | |
380 | ||
381 | #ifdef CONFIG_PM | |
382 | /* Saved USB PHY settings, need to restore after deep sleep. */ | |
383 | u32 usb_ctrl; | |
384 | #endif | |
385 | }; | |
386 | ||
387 | #ifdef CONFIG_PM | |
388 | ||
13b7ee2a AG |
389 | #ifdef CONFIG_PPC_MPC512x |
390 | static int ehci_fsl_mpc512x_drv_suspend(struct device *dev) | |
391 | { | |
392 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
393 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
d4f09e28 | 394 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
13b7ee2a AG |
395 | u32 tmp; |
396 | ||
1c20163d | 397 | #ifdef CONFIG_DYNAMIC_DEBUG |
13b7ee2a AG |
398 | u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); |
399 | mode &= USBMODE_CM_MASK; | |
400 | tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ | |
401 | ||
402 | dev_dbg(dev, "suspend=%d already_suspended=%d " | |
403 | "mode=%d usbcmd %08x\n", pdata->suspended, | |
404 | pdata->already_suspended, mode, tmp); | |
405 | #endif | |
406 | ||
407 | /* | |
408 | * If the controller is already suspended, then this must be a | |
409 | * PM suspend. Remember this fact, so that we will leave the | |
410 | * controller suspended at PM resume time. | |
411 | */ | |
412 | if (pdata->suspended) { | |
413 | dev_dbg(dev, "already suspended, leaving early\n"); | |
414 | pdata->already_suspended = 1; | |
415 | return 0; | |
416 | } | |
417 | ||
418 | dev_dbg(dev, "suspending...\n"); | |
419 | ||
e8799906 | 420 | ehci->rh_state = EHCI_RH_SUSPENDED; |
13b7ee2a AG |
421 | dev->power.power_state = PMSG_SUSPEND; |
422 | ||
423 | /* ignore non-host interrupts */ | |
424 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
425 | ||
426 | /* stop the controller */ | |
427 | tmp = ehci_readl(ehci, &ehci->regs->command); | |
428 | tmp &= ~CMD_RUN; | |
429 | ehci_writel(ehci, tmp, &ehci->regs->command); | |
430 | ||
431 | /* save EHCI registers */ | |
432 | pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); | |
433 | pdata->pm_command &= ~CMD_RUN; | |
434 | pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); | |
435 | pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); | |
436 | pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); | |
437 | pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); | |
438 | pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); | |
439 | pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); | |
440 | pdata->pm_configured_flag = | |
441 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
442 | pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); | |
443 | pdata->pm_usbgenctrl = ehci_readl(ehci, | |
444 | hcd->regs + FSL_SOC_USB_USBGENCTRL); | |
445 | ||
446 | /* clear the W1C bits */ | |
447 | pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); | |
448 | ||
449 | pdata->suspended = 1; | |
450 | ||
451 | /* clear PP to cut power to the port */ | |
452 | tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); | |
453 | tmp &= ~PORT_POWER; | |
454 | ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | static int ehci_fsl_mpc512x_drv_resume(struct device *dev) | |
460 | { | |
461 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
462 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
d4f09e28 | 463 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); |
13b7ee2a AG |
464 | u32 tmp; |
465 | ||
466 | dev_dbg(dev, "suspend=%d already_suspended=%d\n", | |
467 | pdata->suspended, pdata->already_suspended); | |
468 | ||
469 | /* | |
470 | * If the controller was already suspended at suspend time, | |
471 | * then don't resume it now. | |
472 | */ | |
473 | if (pdata->already_suspended) { | |
474 | dev_dbg(dev, "already suspended, leaving early\n"); | |
475 | pdata->already_suspended = 0; | |
476 | return 0; | |
477 | } | |
478 | ||
479 | if (!pdata->suspended) { | |
480 | dev_dbg(dev, "not suspended, leaving early\n"); | |
481 | return 0; | |
482 | } | |
483 | ||
484 | pdata->suspended = 0; | |
485 | ||
486 | dev_dbg(dev, "resuming...\n"); | |
487 | ||
488 | /* set host mode */ | |
489 | tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); | |
490 | ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE); | |
491 | ||
492 | ehci_writel(ehci, pdata->pm_usbgenctrl, | |
493 | hcd->regs + FSL_SOC_USB_USBGENCTRL); | |
494 | ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, | |
495 | hcd->regs + FSL_SOC_USB_ISIPHYCTRL); | |
496 | ||
761bbcb7 AG |
497 | ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); |
498 | ||
13b7ee2a AG |
499 | /* restore EHCI registers */ |
500 | ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); | |
501 | ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); | |
502 | ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); | |
503 | ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); | |
504 | ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); | |
505 | ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); | |
506 | ehci_writel(ehci, pdata->pm_configured_flag, | |
507 | &ehci->regs->configured_flag); | |
508 | ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); | |
509 | ||
510 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
e8799906 | 511 | ehci->rh_state = EHCI_RH_RUNNING; |
13b7ee2a AG |
512 | dev->power.power_state = PMSG_ON; |
513 | ||
514 | tmp = ehci_readl(ehci, &ehci->regs->command); | |
515 | tmp |= CMD_RUN; | |
516 | ehci_writel(ehci, tmp, &ehci->regs->command); | |
517 | ||
518 | usb_hcd_resume_root_hub(hcd); | |
519 | ||
520 | return 0; | |
521 | } | |
522 | #else | |
523 | static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev) | |
524 | { | |
525 | return 0; | |
526 | } | |
527 | ||
528 | static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev) | |
529 | { | |
530 | return 0; | |
531 | } | |
532 | #endif /* CONFIG_PPC_MPC512x */ | |
533 | ||
1af10774 AV |
534 | static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) |
535 | { | |
536 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
537 | ||
538 | return container_of(ehci, struct ehci_fsl, ehci); | |
539 | } | |
540 | ||
541 | static int ehci_fsl_drv_suspend(struct device *dev) | |
542 | { | |
543 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
544 | struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); | |
545 | void __iomem *non_ehci = hcd->regs; | |
546 | ||
13b7ee2a AG |
547 | if (of_device_is_compatible(dev->parent->of_node, |
548 | "fsl,mpc5121-usb2-dr")) { | |
549 | return ehci_fsl_mpc512x_drv_suspend(dev); | |
550 | } | |
551 | ||
4147200d AS |
552 | ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), |
553 | device_may_wakeup(dev)); | |
1af10774 AV |
554 | if (!fsl_deep_sleep()) |
555 | return 0; | |
556 | ||
557 | ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL); | |
558 | return 0; | |
559 | } | |
560 | ||
561 | static int ehci_fsl_drv_resume(struct device *dev) | |
562 | { | |
563 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
564 | struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); | |
565 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
566 | void __iomem *non_ehci = hcd->regs; | |
567 | ||
13b7ee2a AG |
568 | if (of_device_is_compatible(dev->parent->of_node, |
569 | "fsl,mpc5121-usb2-dr")) { | |
570 | return ehci_fsl_mpc512x_drv_resume(dev); | |
571 | } | |
572 | ||
16032c4f | 573 | ehci_prepare_ports_for_controller_resume(ehci); |
1af10774 AV |
574 | if (!fsl_deep_sleep()) |
575 | return 0; | |
576 | ||
577 | usb_root_hub_lost_power(hcd->self.root_hub); | |
578 | ||
579 | /* Restore USB PHY settings and enable the controller. */ | |
580 | out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl); | |
581 | ||
582 | ehci_reset(ehci); | |
583 | ehci_fsl_reinit(ehci); | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | static int ehci_fsl_drv_restore(struct device *dev) | |
589 | { | |
590 | struct usb_hcd *hcd = dev_get_drvdata(dev); | |
591 | ||
592 | usb_root_hub_lost_power(hcd->self.root_hub); | |
593 | return 0; | |
594 | } | |
595 | ||
596 | static struct dev_pm_ops ehci_fsl_pm_ops = { | |
597 | .suspend = ehci_fsl_drv_suspend, | |
598 | .resume = ehci_fsl_drv_resume, | |
599 | .restore = ehci_fsl_drv_restore, | |
600 | }; | |
601 | ||
602 | #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops) | |
603 | #else | |
604 | #define EHCI_FSL_PM_OPS NULL | |
605 | #endif /* CONFIG_PM */ | |
606 | ||
83722bc9 AG |
607 | #ifdef CONFIG_USB_OTG |
608 | static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) | |
609 | { | |
610 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
611 | u32 status; | |
612 | ||
613 | if (!port) | |
614 | return -EINVAL; | |
615 | ||
616 | port--; | |
617 | ||
618 | /* start port reset before HNP protocol time out */ | |
619 | status = readl(&ehci->regs->port_status[port]); | |
620 | if (!(status & PORT_CONNECT)) | |
621 | return -ENODEV; | |
622 | ||
37ebb549 | 623 | /* hub_wq will finish the reset later */ |
83722bc9 AG |
624 | if (ehci_is_TDI(ehci)) { |
625 | writel(PORT_RESET | | |
626 | (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)), | |
627 | &ehci->regs->port_status[port]); | |
628 | } else { | |
629 | writel(PORT_RESET, &ehci->regs->port_status[port]); | |
630 | } | |
631 | ||
632 | return 0; | |
633 | } | |
634 | #else | |
635 | #define ehci_start_port_reset NULL | |
636 | #endif /* CONFIG_USB_OTG */ | |
637 | ||
ca07e1c1 RM |
638 | static struct ehci_driver_overrides ehci_fsl_overrides __initdata = { |
639 | .extra_priv_size = sizeof(struct ehci_fsl), | |
640 | .reset = ehci_fsl_setup, | |
641 | }; | |
83722bc9 | 642 | |
ca07e1c1 RM |
643 | /** |
644 | * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs | |
645 | * @dev: USB Host Controller being removed | |
646 | * Context: !in_interrupt() | |
647 | * | |
648 | * Reverses the effect of usb_hcd_fsl_probe(). | |
649 | * | |
650 | */ | |
80cb9aee | 651 | |
ca07e1c1 RM |
652 | static int fsl_ehci_drv_remove(struct platform_device *pdev) |
653 | { | |
654 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
655 | struct usb_hcd *hcd = platform_get_drvdata(pdev); | |
80cb9aee | 656 | |
ca07e1c1 RM |
657 | if (!IS_ERR_OR_NULL(hcd->usb_phy)) { |
658 | otg_set_host(hcd->usb_phy->otg, NULL); | |
659 | usb_put_phy(hcd->usb_phy); | |
660 | } | |
80cb9aee | 661 | |
ca07e1c1 | 662 | usb_remove_hcd(hcd); |
80cb9aee RV |
663 | |
664 | /* | |
ca07e1c1 RM |
665 | * do platform specific un-initialization: |
666 | * release iomux pins, disable clock, etc. | |
80cb9aee | 667 | */ |
ca07e1c1 RM |
668 | if (pdata->exit) |
669 | pdata->exit(pdev); | |
670 | usb_put_hcd(hcd); | |
80cb9aee | 671 | |
ca07e1c1 RM |
672 | return 0; |
673 | } | |
674 | ||
675 | static struct platform_driver ehci_fsl_driver = { | |
676 | .probe = fsl_ehci_drv_probe, | |
677 | .remove = fsl_ehci_drv_remove, | |
678 | .shutdown = usb_hcd_platform_shutdown, | |
679 | .driver = { | |
680 | .name = "fsl-ehci", | |
681 | .pm = EHCI_FSL_PM_OPS, | |
682 | }, | |
80cb9aee RV |
683 | }; |
684 | ||
ca07e1c1 | 685 | static int __init ehci_fsl_init(void) |
80cb9aee RV |
686 | { |
687 | if (usb_disabled()) | |
688 | return -ENODEV; | |
689 | ||
ca07e1c1 | 690 | pr_info(DRV_NAME ": " DRIVER_DESC "\n"); |
80cb9aee | 691 | |
ca07e1c1 | 692 | ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides); |
80cb9aee | 693 | |
ca07e1c1 RM |
694 | fsl_ehci_hc_driver.product_desc = |
695 | "Freescale On-Chip EHCI Host Controller"; | |
696 | fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset; | |
697 | ||
698 | ||
699 | return platform_driver_register(&ehci_fsl_driver); | |
80cb9aee | 700 | } |
ca07e1c1 | 701 | module_init(ehci_fsl_init); |
80cb9aee | 702 | |
ca07e1c1 RM |
703 | static void __exit ehci_fsl_cleanup(void) |
704 | { | |
705 | platform_driver_unregister(&ehci_fsl_driver); | |
706 | } | |
707 | module_exit(ehci_fsl_cleanup); | |
80cb9aee | 708 | |
ca07e1c1 RM |
709 | MODULE_DESCRIPTION(DRIVER_DESC); |
710 | MODULE_LICENSE("GPL"); | |
711 | MODULE_ALIAS("platform:" DRV_NAME); |