usb: chipidea: Allow disabling streaming not only in udc mode
[deliverable/linux.git] / drivers / usb / host / ehci-fsl.c
CommitLineData
80cb9aee 1/*
1af10774 2 * Copyright 2005-2009 MontaVista Software, Inc.
58c559e6 3 * Copyright 2008,2012 Freescale Semiconductor, Inc.
80cb9aee
RV
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
20 * by Hunter Wu.
1af10774
AV
21 * Power Management support by Dave Liu <daveliu@freescale.com>,
22 * Jerry Huang <Chang-Ming.Huang@freescale.com> and
23 * Anton Vorontsov <avorontsov@ru.mvista.com>.
80cb9aee
RV
24 */
25
1af10774
AV
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/delay.h>
29#include <linux/pm.h>
ded017ee 30#include <linux/err.h>
80cb9aee
RV
31#include <linux/platform_device.h>
32#include <linux/fsl_devices.h>
33
34#include "ehci-fsl.h"
35
80cb9aee
RV
36/* configure so an HC device and id are always provided */
37/* always called with process context; sleeping is OK */
38
39/**
40 * usb_hcd_fsl_probe - initialize FSL-based HCDs
41 * @drvier: Driver to be used for this HCD
42 * @pdev: USB Host Controller being probed
43 * Context: !in_interrupt()
44 *
45 * Allocates basic resources for this USB host controller.
46 *
47 */
dad3843f
AV
48static int usb_hcd_fsl_probe(const struct hc_driver *driver,
49 struct platform_device *pdev)
80cb9aee
RV
50{
51 struct fsl_usb2_platform_data *pdata;
52 struct usb_hcd *hcd;
53 struct resource *res;
54 int irq;
55 int retval;
80cb9aee
RV
56
57 pr_debug("initializing FSL-SOC USB Controller\n");
58
59 /* Need platform data for setup */
60 pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
61 if (!pdata) {
62 dev_err(&pdev->dev,
7071a3ce 63 "No platform data for %s.\n", dev_name(&pdev->dev));
80cb9aee
RV
64 return -ENODEV;
65 }
66
67 /*
68 * This is a host mode driver, verify that we're supposed to be
69 * in host mode.
70 */
71 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
ba02978a
LY
72 (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
73 (pdata->operating_mode == FSL_USB2_DR_OTG))) {
80cb9aee
RV
74 dev_err(&pdev->dev,
75 "Non Host Mode configured for %s. Wrong driver linked.\n",
7071a3ce 76 dev_name(&pdev->dev));
80cb9aee
RV
77 return -ENODEV;
78 }
79
80 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
81 if (!res) {
82 dev_err(&pdev->dev,
83 "Found HC with no IRQ. Check %s setup!\n",
7071a3ce 84 dev_name(&pdev->dev));
80cb9aee
RV
85 return -ENODEV;
86 }
87 irq = res->start;
88
7071a3ce 89 hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
80cb9aee
RV
90 if (!hcd) {
91 retval = -ENOMEM;
92 goto err1;
93 }
94
95 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
96 if (!res) {
97 dev_err(&pdev->dev,
98 "Found HC with no register addr. Check %s setup!\n",
7071a3ce 99 dev_name(&pdev->dev));
80cb9aee
RV
100 retval = -ENODEV;
101 goto err2;
102 }
103 hcd->rsrc_start = res->start;
28f65c11 104 hcd->rsrc_len = resource_size(res);
80cb9aee
RV
105 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
106 driver->description)) {
107 dev_dbg(&pdev->dev, "controller already in use\n");
108 retval = -EBUSY;
109 goto err2;
110 }
111 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
112
113 if (hcd->regs == NULL) {
114 dev_dbg(&pdev->dev, "error mapping memory\n");
115 retval = -EFAULT;
116 goto err3;
117 }
118
230f7ede 119 pdata->regs = hcd->regs;
80cb9aee 120
83722bc9
AG
121 if (pdata->power_budget)
122 hcd->power_budget = pdata->power_budget;
123
230f7ede
AG
124 /*
125 * do platform specific init: check the clock, grab/config pins, etc.
126 */
127 if (pdata->init && pdata->init(pdev)) {
128 retval = -ENODEV;
2492c6e6 129 goto err4;
230f7ede
AG
130 }
131
230f7ede
AG
132 /* Enable USB controller, 83xx or 8536 */
133 if (pdata->have_sysif_regs)
134 setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
135
136 /* Don't need to set host mode here. It will be done by tdi_reset() */
80cb9aee 137
b5dd18d8 138 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
80cb9aee
RV
139 if (retval != 0)
140 goto err4;
83722bc9
AG
141
142#ifdef CONFIG_USB_OTG
143 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
144 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
145
ff9cce82 146 hcd->phy = usb_get_phy(USB_PHY_TYPE_USB2);
c2e935a7
RZ
147 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
148 hcd, ehci, hcd->phy);
83722bc9 149
ff9cce82 150 if (!IS_ERR_OR_NULL(hcd->phy)) {
c2e935a7 151 retval = otg_set_host(hcd->phy->otg,
83722bc9
AG
152 &ehci_to_hcd(ehci)->self);
153 if (retval) {
ff9cce82 154 usb_put_phy(hcd->phy);
83722bc9
AG
155 goto err4;
156 }
157 } else {
c2e935a7 158 dev_err(&pdev->dev, "can't find phy\n");
83722bc9
AG
159 retval = -ENODEV;
160 goto err4;
161 }
162 }
163#endif
80cb9aee
RV
164 return retval;
165
166 err4:
167 iounmap(hcd->regs);
168 err3:
169 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
170 err2:
171 usb_put_hcd(hcd);
172 err1:
7071a3ce 173 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
230f7ede
AG
174 if (pdata->exit)
175 pdata->exit(pdev);
80cb9aee
RV
176 return retval;
177}
178
179/* may be called without controller electrically present */
180/* may be called with controller, bus, and devices active */
181
182/**
183 * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
184 * @dev: USB Host Controller being removed
185 * Context: !in_interrupt()
186 *
187 * Reverses the effect of usb_hcd_fsl_probe().
188 *
189 */
dad3843f
AV
190static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
191 struct platform_device *pdev)
80cb9aee 192{
230f7ede 193 struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
83722bc9 194
ff9cce82 195 if (!IS_ERR_OR_NULL(hcd->phy)) {
c2e935a7 196 otg_set_host(hcd->phy->otg, NULL);
ff9cce82 197 usb_put_phy(hcd->phy);
83722bc9 198 }
230f7ede 199
80cb9aee 200 usb_remove_hcd(hcd);
230f7ede
AG
201
202 /*
203 * do platform specific un-initialization:
204 * release iomux pins, disable clock, etc.
205 */
206 if (pdata->exit)
207 pdata->exit(pdev);
80cb9aee
RV
208 iounmap(hcd->regs);
209 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
210 usb_put_hcd(hcd);
211}
212
3735ba8d 213static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
230f7ede
AG
214 enum fsl_usb2_phy_modes phy_mode,
215 unsigned int port_offset)
80cb9aee 216{
3735ba8d 217 u32 portsc;
58c559e6 218 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
28c56ea1 219 void __iomem *non_ehci = hcd->regs;
58c559e6
RM
220 struct device *dev = hcd->self.controller;
221 struct fsl_usb2_platform_data *pdata = dev->platform_data;
f941f692 222
58c559e6
RM
223 if (pdata->controller_ver < 0) {
224 dev_warn(hcd->self.controller, "Could not get controller version\n");
d479c911 225 return -ENODEV;
58c559e6 226 }
230f7ede
AG
227
228 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
229 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
230
80cb9aee
RV
231 switch (phy_mode) {
232 case FSL_USB2_PHY_ULPI:
58c559e6
RM
233 if (pdata->controller_ver) {
234 /* controller version 1.6 or above */
3735ba8d
SL
235 setbits32(non_ehci + FSL_SOC_USB_CTRL,
236 ULPI_PHY_CLK_SEL);
237 /*
238 * Due to controller issue of PHY_CLK_VALID in ULPI
239 * mode, we set USB_CTRL_USB_EN before checking
240 * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
241 */
242 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
243 UTMI_PHY_EN, USB_CTRL_USB_EN);
58c559e6 244 }
80cb9aee
RV
245 portsc |= PORT_PTS_ULPI;
246 break;
247 case FSL_USB2_PHY_SERIAL:
248 portsc |= PORT_PTS_SERIAL;
249 break;
250 case FSL_USB2_PHY_UTMI_WIDE:
251 portsc |= PORT_PTS_PTW;
252 /* fall through */
253 case FSL_USB2_PHY_UTMI:
58c559e6
RM
254 if (pdata->controller_ver) {
255 /* controller version 1.6 or above */
3735ba8d 256 setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
58c559e6
RM
257 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
258 become stable - 10ms*/
259 }
28c56ea1 260 /* enable UTMI PHY */
f941f692
AG
261 if (pdata->have_sysif_regs)
262 setbits32(non_ehci + FSL_SOC_USB_CTRL,
263 CTRL_UTMI_PHY_EN);
80cb9aee
RV
264 portsc |= PORT_PTS_UTMI;
265 break;
266 case FSL_USB2_PHY_NONE:
267 break;
268 }
3735ba8d 269
5ed33877 270 if (pdata->controller_ver && (phy_mode == FSL_USB2_PHY_ULPI)) {
3735ba8d
SL
271 /* check PHY_CLK_VALID to get phy clk valid */
272 if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
273 PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
274 printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
275 return -EINVAL;
276 }
277 }
278
083522d7 279 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
3735ba8d
SL
280
281 if (phy_mode != FSL_USB2_PHY_ULPI)
282 setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
283
284 return 0;
80cb9aee
RV
285}
286
3735ba8d 287static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
80cb9aee 288{
230f7ede 289 struct usb_hcd *hcd = ehci_to_hcd(ehci);
80cb9aee
RV
290 struct fsl_usb2_platform_data *pdata;
291 void __iomem *non_ehci = hcd->regs;
292
230f7ede
AG
293 pdata = hcd->self.controller->platform_data;
294
230f7ede 295 if (pdata->have_sysif_regs) {
4c954326
PJ
296 /*
297 * Turn on cache snooping hardware, since some PowerPC platforms
298 * wholly rely on hardware to deal with cache coherent
299 */
40acc095 300
4c954326
PJ
301 /* Setup Snooping for all the 4GB space */
302 /* SNOOP1 starts from 0x0, size 2G */
303 out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
304 /* SNOOP2 starts from 0x80000000, size 2G */
305 out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
306 }
40acc095 307
ba02978a
LY
308 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
309 (pdata->operating_mode == FSL_USB2_DR_OTG))
3735ba8d
SL
310 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
311 return -EINVAL;
80cb9aee
RV
312
313 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
8cd42e97
KG
314 unsigned int chip, rev, svr;
315
316 svr = mfspr(SPRN_SVR);
317 chip = svr >> 16;
318 rev = (svr >> 4) & 0xf;
319
320 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
321 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
322 ehci->has_fsl_port_bug = 1;
323
80cb9aee 324 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
3735ba8d
SL
325 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
326 return -EINVAL;
327
80cb9aee 328 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
3735ba8d
SL
329 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
330 return -EINVAL;
80cb9aee
RV
331 }
332
230f7ede 333 if (pdata->have_sysif_regs) {
08d7660d 334#ifdef CONFIG_FSL_SOC_BOOKE
230f7ede
AG
335 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
336 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
4f534258 337#else
230f7ede
AG
338 out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
339 out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
4f534258 340#endif
230f7ede
AG
341 out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
342 }
3735ba8d
SL
343
344 return 0;
80cb9aee
RV
345}
346
347/* called after powerup, by probe or system-pm "wakeup" */
348static int ehci_fsl_reinit(struct ehci_hcd *ehci)
349{
3735ba8d
SL
350 if (ehci_fsl_usb_setup(ehci))
351 return -EINVAL;
80cb9aee
RV
352
353 return 0;
354}
355
356/* called during probe() after chip reset completes */
357static int ehci_fsl_setup(struct usb_hcd *hcd)
358{
359 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
360 int retval;
230f7ede 361 struct fsl_usb2_platform_data *pdata;
761bbcb7 362 struct device *dev;
230f7ede 363
761bbcb7 364 dev = hcd->self.controller;
230f7ede
AG
365 pdata = hcd->self.controller->platform_data;
366 ehci->big_endian_desc = pdata->big_endian_desc;
367 ehci->big_endian_mmio = pdata->big_endian_mmio;
80cb9aee
RV
368
369 /* EHCI registers start at offset 0x100 */
370 ehci->caps = hcd->regs + 0x100;
80cb9aee 371
65fd4272
MC
372 hcd->has_tt = 1;
373
1a49e2ac 374 retval = ehci_setup(hcd);
80cb9aee
RV
375 if (retval)
376 return retval;
377
761bbcb7
AG
378 if (of_device_is_compatible(dev->parent->of_node,
379 "fsl,mpc5121-usb2-dr")) {
380 /*
381 * set SBUSCFG:AHBBRST so that control msgs don't
382 * fail when doing heavy PATA writes.
383 */
384 ehci_writel(ehci, SBUSCFG_INCR8,
385 hcd->regs + FSL_SOC_USB_SBUSCFG);
386 }
387
80cb9aee
RV
388 retval = ehci_fsl_reinit(ehci);
389 return retval;
390}
391
1af10774
AV
392struct ehci_fsl {
393 struct ehci_hcd ehci;
394
395#ifdef CONFIG_PM
396 /* Saved USB PHY settings, need to restore after deep sleep. */
397 u32 usb_ctrl;
398#endif
399};
400
401#ifdef CONFIG_PM
402
13b7ee2a
AG
403#ifdef CONFIG_PPC_MPC512x
404static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
405{
406 struct usb_hcd *hcd = dev_get_drvdata(dev);
407 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
408 struct fsl_usb2_platform_data *pdata = dev->platform_data;
409 u32 tmp;
410
411#ifdef DEBUG
412 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
413 mode &= USBMODE_CM_MASK;
414 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
415
416 dev_dbg(dev, "suspend=%d already_suspended=%d "
417 "mode=%d usbcmd %08x\n", pdata->suspended,
418 pdata->already_suspended, mode, tmp);
419#endif
420
421 /*
422 * If the controller is already suspended, then this must be a
423 * PM suspend. Remember this fact, so that we will leave the
424 * controller suspended at PM resume time.
425 */
426 if (pdata->suspended) {
427 dev_dbg(dev, "already suspended, leaving early\n");
428 pdata->already_suspended = 1;
429 return 0;
430 }
431
432 dev_dbg(dev, "suspending...\n");
433
e8799906 434 ehci->rh_state = EHCI_RH_SUSPENDED;
13b7ee2a
AG
435 dev->power.power_state = PMSG_SUSPEND;
436
437 /* ignore non-host interrupts */
438 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
439
440 /* stop the controller */
441 tmp = ehci_readl(ehci, &ehci->regs->command);
442 tmp &= ~CMD_RUN;
443 ehci_writel(ehci, tmp, &ehci->regs->command);
444
445 /* save EHCI registers */
446 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
447 pdata->pm_command &= ~CMD_RUN;
448 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
449 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
450 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
451 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
452 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
453 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
454 pdata->pm_configured_flag =
455 ehci_readl(ehci, &ehci->regs->configured_flag);
456 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
457 pdata->pm_usbgenctrl = ehci_readl(ehci,
458 hcd->regs + FSL_SOC_USB_USBGENCTRL);
459
460 /* clear the W1C bits */
461 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
462
463 pdata->suspended = 1;
464
465 /* clear PP to cut power to the port */
466 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
467 tmp &= ~PORT_POWER;
468 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
469
470 return 0;
471}
472
473static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
474{
475 struct usb_hcd *hcd = dev_get_drvdata(dev);
476 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
477 struct fsl_usb2_platform_data *pdata = dev->platform_data;
478 u32 tmp;
479
480 dev_dbg(dev, "suspend=%d already_suspended=%d\n",
481 pdata->suspended, pdata->already_suspended);
482
483 /*
484 * If the controller was already suspended at suspend time,
485 * then don't resume it now.
486 */
487 if (pdata->already_suspended) {
488 dev_dbg(dev, "already suspended, leaving early\n");
489 pdata->already_suspended = 0;
490 return 0;
491 }
492
493 if (!pdata->suspended) {
494 dev_dbg(dev, "not suspended, leaving early\n");
495 return 0;
496 }
497
498 pdata->suspended = 0;
499
500 dev_dbg(dev, "resuming...\n");
501
502 /* set host mode */
503 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
504 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
505
506 ehci_writel(ehci, pdata->pm_usbgenctrl,
507 hcd->regs + FSL_SOC_USB_USBGENCTRL);
508 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
509 hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
510
761bbcb7
AG
511 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
512
13b7ee2a
AG
513 /* restore EHCI registers */
514 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
515 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
516 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
517 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
518 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
519 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
520 ehci_writel(ehci, pdata->pm_configured_flag,
521 &ehci->regs->configured_flag);
522 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
523
524 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
e8799906 525 ehci->rh_state = EHCI_RH_RUNNING;
13b7ee2a
AG
526 dev->power.power_state = PMSG_ON;
527
528 tmp = ehci_readl(ehci, &ehci->regs->command);
529 tmp |= CMD_RUN;
530 ehci_writel(ehci, tmp, &ehci->regs->command);
531
532 usb_hcd_resume_root_hub(hcd);
533
534 return 0;
535}
536#else
537static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
538{
539 return 0;
540}
541
542static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
543{
544 return 0;
545}
546#endif /* CONFIG_PPC_MPC512x */
547
1af10774
AV
548static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
549{
550 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
551
552 return container_of(ehci, struct ehci_fsl, ehci);
553}
554
555static int ehci_fsl_drv_suspend(struct device *dev)
556{
557 struct usb_hcd *hcd = dev_get_drvdata(dev);
558 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
559 void __iomem *non_ehci = hcd->regs;
560
13b7ee2a
AG
561 if (of_device_is_compatible(dev->parent->of_node,
562 "fsl,mpc5121-usb2-dr")) {
563 return ehci_fsl_mpc512x_drv_suspend(dev);
564 }
565
4147200d
AS
566 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
567 device_may_wakeup(dev));
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AV
568 if (!fsl_deep_sleep())
569 return 0;
570
571 ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
572 return 0;
573}
574
575static int ehci_fsl_drv_resume(struct device *dev)
576{
577 struct usb_hcd *hcd = dev_get_drvdata(dev);
578 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
579 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
580 void __iomem *non_ehci = hcd->regs;
581
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AG
582 if (of_device_is_compatible(dev->parent->of_node,
583 "fsl,mpc5121-usb2-dr")) {
584 return ehci_fsl_mpc512x_drv_resume(dev);
585 }
586
16032c4f 587 ehci_prepare_ports_for_controller_resume(ehci);
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AV
588 if (!fsl_deep_sleep())
589 return 0;
590
591 usb_root_hub_lost_power(hcd->self.root_hub);
592
593 /* Restore USB PHY settings and enable the controller. */
594 out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
595
596 ehci_reset(ehci);
597 ehci_fsl_reinit(ehci);
598
599 return 0;
600}
601
602static int ehci_fsl_drv_restore(struct device *dev)
603{
604 struct usb_hcd *hcd = dev_get_drvdata(dev);
605
606 usb_root_hub_lost_power(hcd->self.root_hub);
607 return 0;
608}
609
610static struct dev_pm_ops ehci_fsl_pm_ops = {
611 .suspend = ehci_fsl_drv_suspend,
612 .resume = ehci_fsl_drv_resume,
613 .restore = ehci_fsl_drv_restore,
614};
615
616#define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
617#else
618#define EHCI_FSL_PM_OPS NULL
619#endif /* CONFIG_PM */
620
83722bc9
AG
621#ifdef CONFIG_USB_OTG
622static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
623{
624 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
625 u32 status;
626
627 if (!port)
628 return -EINVAL;
629
630 port--;
631
632 /* start port reset before HNP protocol time out */
633 status = readl(&ehci->regs->port_status[port]);
634 if (!(status & PORT_CONNECT))
635 return -ENODEV;
636
637 /* khubd will finish the reset later */
638 if (ehci_is_TDI(ehci)) {
639 writel(PORT_RESET |
640 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
641 &ehci->regs->port_status[port]);
642 } else {
643 writel(PORT_RESET, &ehci->regs->port_status[port]);
644 }
645
646 return 0;
647}
648#else
649#define ehci_start_port_reset NULL
650#endif /* CONFIG_USB_OTG */
651
652
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RV
653static const struct hc_driver ehci_fsl_hc_driver = {
654 .description = hcd_name,
655 .product_desc = "Freescale On-Chip EHCI Host Controller",
1af10774 656 .hcd_priv_size = sizeof(struct ehci_fsl),
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RV
657
658 /*
659 * generic hardware linkage
660 */
661 .irq = ehci_irq,
230f7ede 662 .flags = HCD_USB2 | HCD_MEMORY,
80cb9aee
RV
663
664 /*
665 * basic lifecycle operations
666 */
667 .reset = ehci_fsl_setup,
668 .start = ehci_run,
80cb9aee 669 .stop = ehci_stop,
64a21d02 670 .shutdown = ehci_shutdown,
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RV
671
672 /*
673 * managing i/o requests and associated device resources
674 */
675 .urb_enqueue = ehci_urb_enqueue,
676 .urb_dequeue = ehci_urb_dequeue,
677 .endpoint_disable = ehci_endpoint_disable,
b18ffd49 678 .endpoint_reset = ehci_endpoint_reset,
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RV
679
680 /*
681 * scheduling support
682 */
683 .get_frame_number = ehci_get_frame,
684
685 /*
686 * root hub support
687 */
688 .hub_status_data = ehci_hub_status_data,
689 .hub_control = ehci_hub_control,
690 .bus_suspend = ehci_bus_suspend,
691 .bus_resume = ehci_bus_resume,
83722bc9 692 .start_port_reset = ehci_start_port_reset,
90da096e 693 .relinquish_port = ehci_relinquish_port,
3a31155c 694 .port_handed_over = ehci_port_handed_over,
914b7012
AS
695
696 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
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RV
697};
698
699static int ehci_fsl_drv_probe(struct platform_device *pdev)
700{
701 if (usb_disabled())
702 return -ENODEV;
703
135db048 704 /* FIXME we only want one one probe() not two */
80cb9aee
RV
705 return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
706}
707
708static int ehci_fsl_drv_remove(struct platform_device *pdev)
709{
710 struct usb_hcd *hcd = platform_get_drvdata(pdev);
711
135db048 712 /* FIXME we only want one one remove() not two */
80cb9aee 713 usb_hcd_fsl_remove(hcd, pdev);
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RV
714 return 0;
715}
716
135db048 717MODULE_ALIAS("platform:fsl-ehci");
80cb9aee 718
01cced25 719static struct platform_driver ehci_fsl_driver = {
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RV
720 .probe = ehci_fsl_drv_probe,
721 .remove = ehci_fsl_drv_remove,
64a21d02 722 .shutdown = usb_hcd_platform_shutdown,
80cb9aee 723 .driver = {
1af10774
AV
724 .name = "fsl-ehci",
725 .pm = EHCI_FSL_PM_OPS,
135db048 726 },
80cb9aee 727};
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