gpu: host1x: Remove second host1x driver
[deliverable/linux.git] / drivers / usb / host / ehci-hcd.c
CommitLineData
1da177e4 1/*
578333ab
AS
2 * Enhanced Host Controller Interface (EHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
1da177e4 6 * Copyright (c) 2000-2004 by David Brownell
53bd6a60 7 *
1da177e4
LT
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
1da177e4
LT
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/dmapool.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
3c04e20e 30#include <linux/vmalloc.h>
1da177e4
LT
31#include <linux/errno.h>
32#include <linux/init.h>
d58b4bcc 33#include <linux/hrtimer.h>
1da177e4
LT
34#include <linux/list.h>
35#include <linux/interrupt.h>
1da177e4 36#include <linux/usb.h>
27729aad 37#include <linux/usb/hcd.h>
1da177e4
LT
38#include <linux/moduleparam.h>
39#include <linux/dma-mapping.h>
694cc208 40#include <linux/debugfs.h>
5a0e3ad6 41#include <linux/slab.h>
1da177e4 42
1da177e4
LT
43#include <asm/byteorder.h>
44#include <asm/io.h>
45#include <asm/irq.h>
1da177e4 46#include <asm/unaligned.h>
1da177e4 47
df7c1ca2
GL
48#if defined(CONFIG_PPC_PS3)
49#include <asm/firmware.h>
50#endif
51
1da177e4
LT
52/*-------------------------------------------------------------------------*/
53
54/*
55 * EHCI hc_driver implementation ... experimental, incomplete.
56 * Based on the final 1.0 register interface specification.
57 *
58 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
59 * First was PCMCIA, like ISA; then CardBus, which is PCI.
60 * Next comes "CardBay", using USB 2.0 signals.
61 *
62 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
63 * Special thanks to Intel and VIA for providing host controllers to
64 * test this driver on, and Cypress (including In-System Design) for
65 * providing early devices for those host controllers to talk to!
1da177e4
LT
66 */
67
1da177e4
LT
68#define DRIVER_AUTHOR "David Brownell"
69#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
70
71static const char hcd_name [] = "ehci_hcd";
72
73
9776afc8 74#undef VERBOSE_DEBUG
1da177e4
LT
75#undef EHCI_URB_TRACE
76
1da177e4
LT
77/* magic numbers that can affect system performance */
78#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
79#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
80#define EHCI_TUNE_RL_TT 0
81#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
82#define EHCI_TUNE_MULT_TT 1
ffda0803
AS
83/*
84 * Some drivers think it's safe to schedule isochronous transfers more than
85 * 256 ms into the future (partly as a result of an old bug in the scheduling
86 * code). In an attempt to avoid trouble, we will use a minimum scheduling
87 * length of 512 frames instead of 256.
88 */
89#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
1da177e4 90
1da177e4
LT
91/* Initial IRQ latency: faster than hw default */
92static int log2_irq_thresh = 0; // 0 to 6
93module_param (log2_irq_thresh, int, S_IRUGO);
94MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
95
96/* initial park setting: slower than hw default */
97static unsigned park = 0;
98module_param (park, uint, S_IRUGO);
99MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
100
93f1a47c 101/* for flakey hardware, ignore overcurrent indicators */
90ab5ee9 102static bool ignore_oc = 0;
93f1a47c
DB
103module_param (ignore_oc, bool, S_IRUGO);
104MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
105
1da177e4
LT
106#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
107
108/*-------------------------------------------------------------------------*/
109
110#include "ehci.h"
ad93562b 111#include "pci-quirks.h"
1da177e4 112
acc08503
AS
113/*
114 * The MosChip MCS9990 controller updates its microframe counter
115 * a little before the frame counter, and occasionally we will read
116 * the invalid intermediate value. Avoid problems by checking the
117 * microframe number (the low-order 3 bits); if they are 0 then
118 * re-read the register to get the correct value.
119 */
120static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci)
121{
122 unsigned uf;
123
124 uf = ehci_readl(ehci, &ehci->regs->frame_index);
125 if (unlikely((uf & 7) == 0))
126 uf = ehci_readl(ehci, &ehci->regs->frame_index);
127 return uf;
128}
129
130static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
131{
132 if (ehci->frame_index_bug)
133 return ehci_moschip_read_frame_index(ehci);
134 return ehci_readl(ehci, &ehci->regs->frame_index);
135}
136
137#include "ehci-dbg.c"
138
1da177e4
LT
139/*-------------------------------------------------------------------------*/
140
141/*
142 * handshake - spin reading hc until handshake completes or fails
143 * @ptr: address of hc register to be read
144 * @mask: bits to look at in result of read
145 * @done: value of those bits when handshake succeeds
146 * @usec: timeout in microseconds
147 *
148 * Returns negative errno, or zero on success
149 *
150 * Success happens when the "mask" bits have the specified value (hardware
151 * handshake done). There are two failure modes: "usec" have passed (major
152 * hardware flakeout), or the register reads as all-ones (hardware removed).
153 *
154 * That last failure should_only happen in cases like physical cardbus eject
155 * before driver shutdown. But it also seems to be caused by bugs in cardbus
156 * bridge shutdown: shutting down the bridge before the devices using it.
157 */
083522d7
BH
158static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
159 u32 mask, u32 done, int usec)
1da177e4
LT
160{
161 u32 result;
162
163 do {
083522d7 164 result = ehci_readl(ehci, ptr);
1da177e4
LT
165 if (result == ~(u32)0) /* card removed */
166 return -ENODEV;
167 result &= mask;
168 if (result == done)
169 return 0;
170 udelay (1);
171 usec--;
172 } while (usec > 0);
173 return -ETIMEDOUT;
174}
175
65fd4272
MC
176/* check TDI/ARC silicon is in host mode */
177static int tdi_in_host_mode (struct ehci_hcd *ehci)
178{
65fd4272
MC
179 u32 tmp;
180
a46af4eb 181 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
65fd4272
MC
182 return (tmp & 3) == USBMODE_CM_HC;
183}
184
c4f34764
AS
185/*
186 * Force HC to halt state from unknown (EHCI spec section 2.3).
187 * Must be called with interrupts enabled and the lock not held.
188 */
1da177e4
LT
189static int ehci_halt (struct ehci_hcd *ehci)
190{
c4f34764
AS
191 u32 temp;
192
193 spin_lock_irq(&ehci->lock);
1da177e4 194
72f30b6f 195 /* disable any irqs left enabled by previous code */
083522d7 196 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
72f30b6f 197
c4f34764
AS
198 if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) {
199 spin_unlock_irq(&ehci->lock);
65fd4272
MC
200 return 0;
201 }
202
3d9545cc
AS
203 /*
204 * This routine gets called during probe before ehci->command
205 * has been initialized, so we can't rely on its value.
206 */
207 ehci->command &= ~CMD_RUN;
083522d7 208 temp = ehci_readl(ehci, &ehci->regs->command);
3d9545cc 209 temp &= ~(CMD_RUN | CMD_IAAD);
083522d7 210 ehci_writel(ehci, temp, &ehci->regs->command);
df7c1ca2 211
c4f34764
AS
212 spin_unlock_irq(&ehci->lock);
213 synchronize_irq(ehci_to_hcd(ehci)->irq);
0bcfeb3e 214
c4f34764 215 return handshake(ehci, &ehci->regs->status,
083522d7 216 STS_HALT, STS_HALT, 16 * 125);
0bcfeb3e
DB
217}
218
1da177e4
LT
219/* put TDI/ARC silicon into EHCI mode */
220static void tdi_reset (struct ehci_hcd *ehci)
221{
1da177e4
LT
222 u32 tmp;
223
a46af4eb 224 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
d23a1377
VB
225 tmp |= USBMODE_CM_HC;
226 /* The default byte access to MMR space is LE after
227 * controller reset. Set the required endian mode
228 * for transfer buffers to match the host microprocessor
229 */
230 if (ehci_big_endian_mmio(ehci))
231 tmp |= USBMODE_BE;
a46af4eb 232 ehci_writel(ehci, tmp, &ehci->regs->usbmode);
1da177e4
LT
233}
234
c4f34764
AS
235/*
236 * Reset a non-running (STS_HALT == 1) controller.
237 * Must be called with interrupts enabled and the lock not held.
238 */
1da177e4
LT
239static int ehci_reset (struct ehci_hcd *ehci)
240{
241 int retval;
083522d7 242 u32 command = ehci_readl(ehci, &ehci->regs->command);
1da177e4 243
8d053c79
JW
244 /* If the EHCI debug controller is active, special care must be
245 * taken before and after a host controller reset */
9fa5780b 246 if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci)))
8d053c79
JW
247 ehci->debug = NULL;
248
1da177e4
LT
249 command |= CMD_RESET;
250 dbg_cmd (ehci, "reset", command);
083522d7 251 ehci_writel(ehci, command, &ehci->regs->command);
e8799906 252 ehci->rh_state = EHCI_RH_HALTED;
1da177e4 253 ehci->next_statechange = jiffies;
083522d7
BH
254 retval = handshake (ehci, &ehci->regs->command,
255 CMD_RESET, 0, 250 * 1000);
1da177e4 256
331ac6b2
AD
257 if (ehci->has_hostpc) {
258 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
a46af4eb
AS
259 &ehci->regs->usbmode_ex);
260 ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
331ac6b2 261 }
1da177e4
LT
262 if (retval)
263 return retval;
264
265 if (ehci_is_TDI(ehci))
266 tdi_reset (ehci);
267
8d053c79 268 if (ehci->debug)
9fa5780b 269 dbgp_external_startup(ehci_to_hcd(ehci));
8d053c79 270
a448e4dc
AS
271 ehci->port_c_suspend = ehci->suspended_ports =
272 ehci->resuming_ports = 0;
1da177e4
LT
273 return retval;
274}
275
c4f34764
AS
276/*
277 * Idle the controller (turn off the schedules).
278 * Must be called with interrupts enabled and the lock not held.
279 */
1da177e4
LT
280static void ehci_quiesce (struct ehci_hcd *ehci)
281{
282 u32 temp;
283
e8799906 284 if (ehci->rh_state != EHCI_RH_RUNNING)
c0c53dbc 285 return;
1da177e4
LT
286
287 /* wait for any schedule enables/disables to take effect */
3d9545cc 288 temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
9671cd7a 289 handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp, 16 * 125);
1da177e4
LT
290
291 /* then disable anything that's still active */
c4f34764 292 spin_lock_irq(&ehci->lock);
3d9545cc
AS
293 ehci->command &= ~(CMD_ASE | CMD_PSE);
294 ehci_writel(ehci, ehci->command, &ehci->regs->command);
c4f34764 295 spin_unlock_irq(&ehci->lock);
1da177e4
LT
296
297 /* hardware can take 16 microframes to turn off ... */
9671cd7a 298 handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0, 16 * 125);
1da177e4
LT
299}
300
301/*-------------------------------------------------------------------------*/
302
07d29b63 303static void end_unlink_async(struct ehci_hcd *ehci);
32830f20 304static void unlink_empty_async(struct ehci_hcd *ehci);
2a40f324 305static void unlink_empty_async_suspended(struct ehci_hcd *ehci);
7d12e780 306static void ehci_work(struct ehci_hcd *ehci);
df202255
AS
307static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
308static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
1da177e4 309
d58b4bcc 310#include "ehci-timer.c"
1da177e4
LT
311#include "ehci-hub.c"
312#include "ehci-mem.c"
313#include "ehci-q.c"
314#include "ehci-sched.c"
4c67045b 315#include "ehci-sysfs.c"
1da177e4
LT
316
317/*-------------------------------------------------------------------------*/
318
8903795a
AS
319/* On some systems, leaving remote wakeup enabled prevents system shutdown.
320 * The firmware seems to think that powering off is a wakeup event!
321 * This routine turns off remote wakeup and everything else, on all ports.
322 */
323static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
324{
325 int port = HCS_N_PORTS(ehci->hcs_params);
326
327 while (port--)
328 ehci_writel(ehci, PORT_RWC_BITS,
329 &ehci->regs->port_status[port]);
330}
331
21da84a8
SS
332/*
333 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
c4f34764 334 * Must be called with interrupts enabled and the lock not held.
72f30b6f 335 */
21da84a8 336static void ehci_silence_controller(struct ehci_hcd *ehci)
1da177e4 337{
21da84a8 338 ehci_halt(ehci);
c4f34764
AS
339
340 spin_lock_irq(&ehci->lock);
341 ehci->rh_state = EHCI_RH_HALTED;
8903795a 342 ehci_turn_off_all_ports(ehci);
1da177e4
LT
343
344 /* make BIOS/etc use companion controller during reboot */
083522d7 345 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
8903795a
AS
346
347 /* unblock posted writes */
348 ehci_readl(ehci, &ehci->regs->configured_flag);
c4f34764 349 spin_unlock_irq(&ehci->lock);
1da177e4
LT
350}
351
21da84a8
SS
352/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
353 * This forcibly disables dma and IRQs, helping kexec and other cases
354 * where the next system software may expect clean state.
355 */
356static void ehci_shutdown(struct usb_hcd *hcd)
357{
358 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
359
21da84a8 360 spin_lock_irq(&ehci->lock);
43fe3a99 361 ehci->shutdown = true;
c0c53dbc 362 ehci->rh_state = EHCI_RH_STOPPING;
d58b4bcc 363 ehci->enabled_hrtimer_events = 0;
21da84a8 364 spin_unlock_irq(&ehci->lock);
d58b4bcc 365
c4f34764
AS
366 ehci_silence_controller(ehci);
367
d58b4bcc 368 hrtimer_cancel(&ehci->hrtimer);
21da84a8
SS
369}
370
7ff71d6a 371/*-------------------------------------------------------------------------*/
1da177e4 372
7ff71d6a
MP
373/*
374 * ehci_work is called from some interrupts, timers, and so on.
375 * it calls driver completion functions, after dropping ehci->lock.
376 */
7d12e780 377static void ehci_work (struct ehci_hcd *ehci)
7ff71d6a 378{
7ff71d6a
MP
379 /* another CPU may drop ehci->lock during a schedule scan while
380 * it reports urb completions. this flag guards against bogus
381 * attempts at re-entrant schedule scanning.
382 */
361aabf3
AS
383 if (ehci->scanning) {
384 ehci->need_rescan = true;
7ff71d6a 385 return;
361aabf3
AS
386 }
387 ehci->scanning = true;
388
389 rescan:
390 ehci->need_rescan = false;
31446610
AS
391 if (ehci->async_count)
392 scan_async(ehci);
569b394f
AS
393 if (ehci->intr_count > 0)
394 scan_intr(ehci);
395 if (ehci->isoc_count > 0)
396 scan_isoc(ehci);
361aabf3
AS
397 if (ehci->need_rescan)
398 goto rescan;
399 ehci->scanning = false;
7ff71d6a
MP
400
401 /* the IO watchdog guards against hardware or driver bugs that
402 * misplace IRQs, and should let us run completely without IRQs.
403 * such lossage has been observed on both VT6202 and VT8235.
404 */
18aafe64 405 turn_on_io_watchdog(ehci);
7ff71d6a 406}
1da177e4 407
21da84a8
SS
408/*
409 * Called when the ehci_hcd module is removed.
410 */
7ff71d6a 411static void ehci_stop (struct usb_hcd *hcd)
1da177e4
LT
412{
413 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1da177e4 414
7ff71d6a 415 ehci_dbg (ehci, "stop\n");
1da177e4 416
7ff71d6a 417 /* no more interrupts ... */
56c1e26d 418
7ff71d6a 419 spin_lock_irq(&ehci->lock);
d58b4bcc 420 ehci->enabled_hrtimer_events = 0;
c4f34764 421 spin_unlock_irq(&ehci->lock);
1da177e4 422
c4f34764 423 ehci_quiesce(ehci);
21da84a8 424 ehci_silence_controller(ehci);
7ff71d6a 425 ehci_reset (ehci);
1da177e4 426
d58b4bcc 427 hrtimer_cancel(&ehci->hrtimer);
4c67045b 428 remove_sysfs_files(ehci);
7ff71d6a 429 remove_debug_files (ehci);
1da177e4 430
7ff71d6a
MP
431 /* root hub is shut down separately (first, when possible) */
432 spin_lock_irq (&ehci->lock);
55934eb3 433 end_free_itds(ehci);
7ff71d6a
MP
434 spin_unlock_irq (&ehci->lock);
435 ehci_mem_cleanup (ehci);
1da177e4 436
ad93562b
AX
437 if (ehci->amd_pll_fix == 1)
438 usb_amd_dev_put();
05570297 439
7ff71d6a 440#ifdef EHCI_STATS
99ac5b1e
AS
441 ehci_dbg(ehci, "irq normal %ld err %ld iaa %ld (lost %ld)\n",
442 ehci->stats.normal, ehci->stats.error, ehci->stats.iaa,
7ff71d6a
MP
443 ehci->stats.lost_iaa);
444 ehci_dbg (ehci, "complete %ld unlink %ld\n",
445 ehci->stats.complete, ehci->stats.unlink);
1da177e4 446#endif
1da177e4 447
083522d7
BH
448 dbg_status (ehci, "ehci_stop completed",
449 ehci_readl(ehci, &ehci->regs->status));
1da177e4
LT
450}
451
18807521
DB
452/* one-time init, only for memory state */
453static int ehci_init(struct usb_hcd *hcd)
1da177e4 454{
18807521 455 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1da177e4 456 u32 temp;
1da177e4
LT
457 int retval;
458 u32 hcc_params;
3807e26d 459 struct ehci_qh_hw *hw;
18807521
DB
460
461 spin_lock_init(&ehci->lock);
462
403dbd36
AD
463 /*
464 * keep io watchdog by default, those good HCDs could turn off it later
465 */
466 ehci->need_io_watchdog = 1;
1da177e4 467
d58b4bcc
AS
468 hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
469 ehci->hrtimer.function = ehci_hrtimer_func;
470 ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
07d29b63 471
f75593ce
AS
472 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
473
cc62a7eb
KS
474 /*
475 * by default set standard 80% (== 100 usec/uframe) max periodic
476 * bandwidth as required by USB 2.0
477 */
478 ehci->uframe_periodic_max = 100;
479
1da177e4
LT
480 /*
481 * hw default: 1K periodic list heads, one per frame.
482 * periodic_size can shrink by USBCMD update if hcc_params allows.
483 */
484 ehci->periodic_size = DEFAULT_I_TDPS;
569b394f 485 INIT_LIST_HEAD(&ehci->intr_qh_list);
9aa09d2f 486 INIT_LIST_HEAD(&ehci->cached_itd_list);
0e5f231b 487 INIT_LIST_HEAD(&ehci->cached_sitd_list);
f75593ce 488
8e192910 489 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
f75593ce
AS
490 /* periodic schedule size can be smaller than default */
491 switch (EHCI_TUNE_FLS) {
492 case 0: ehci->periodic_size = 1024; break;
493 case 1: ehci->periodic_size = 512; break;
494 case 2: ehci->periodic_size = 256; break;
495 default: BUG();
496 }
497 }
18807521 498 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
1da177e4
LT
499 return retval;
500
501 /* controllers may cache some of the periodic schedule ... */
53bd6a60 502 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
98cae42d 503 ehci->i_thresh = 0;
1da177e4 504 else // N microframes cached
18807521 505 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
1da177e4 506
1da177e4
LT
507 /*
508 * dedicate a qh for the async ring head, since we couldn't unlink
509 * a 'real' qh without stopping the async schedule [4.8]. use it
510 * as the 'reclamation list head' too.
511 * its dummy is used in hw_alt_next of many tds, to prevent the qh
512 * from automatically advancing to the next td after short reads.
513 */
18807521 514 ehci->async->qh_next.qh = NULL;
3807e26d
AD
515 hw = ehci->async->hw;
516 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
517 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
4f7a67e2 518#if defined(CONFIG_PPC_PS3)
4c53de72 519 hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
4f7a67e2 520#endif
3807e26d
AD
521 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
522 hw->hw_qtd_next = EHCI_LIST_END(ehci);
18807521 523 ehci->async->qh_state = QH_STATE_LINKED;
3807e26d 524 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
1da177e4
LT
525
526 /* clear interrupt enables, set irq latency */
527 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
528 log2_irq_thresh = 0;
529 temp = 1 << (16 + log2_irq_thresh);
5a9cdf33
AD
530 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
531 ehci->has_ppcd = 1;
532 ehci_dbg(ehci, "enable per-port change event\n");
533 temp |= CMD_PPCEE;
534 }
1da177e4
LT
535 if (HCC_CANPARK(hcc_params)) {
536 /* HW default park == 3, on hardware that supports it (like
537 * NVidia and ALI silicon), maximizes throughput on the async
538 * schedule by avoiding QH fetches between transfers.
539 *
540 * With fast usb storage devices and NForce2, "park" seems to
541 * make problems: throughput reduction (!), data errors...
542 */
543 if (park) {
18807521 544 park = min(park, (unsigned) 3);
1da177e4
LT
545 temp |= CMD_PARK;
546 temp |= park << 8;
547 }
18807521 548 ehci_dbg(ehci, "park %d\n", park);
1da177e4 549 }
18807521 550 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
1da177e4
LT
551 /* periodic schedule size can be smaller than default */
552 temp &= ~(3 << 2);
553 temp |= (EHCI_TUNE_FLS << 2);
1da177e4 554 }
18807521
DB
555 ehci->command = temp;
556
40f8db8f 557 /* Accept arbitrarily long scatter-gather lists */
4307a28e
AR
558 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
559 hcd->self.sg_tablesize = ~0;
18807521
DB
560 return 0;
561}
562
563/* start HC running; it's halted, ehci_init() has been run (once) */
564static int ehci_run (struct usb_hcd *hcd)
565{
566 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
18807521
DB
567 u32 temp;
568 u32 hcc_params;
569
1d619f12 570 hcd->uses_new_polling = 1;
1d619f12 571
18807521 572 /* EHCI spec section 4.1 */
876e0df9 573
083522d7
BH
574 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
575 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
18807521
DB
576
577 /*
578 * hcc_params controls whether ehci->regs->segment must (!!!)
579 * be used; it constrains QH/ITD/SITD and QTD locations.
580 * pci_pool consistent memory always uses segment zero.
581 * streaming mappings for I/O buffers, like pci_map_single(),
582 * can return segments above 4GB, if the device allows.
583 *
584 * NOTE: the dma mask is visible through dma_supported(), so
585 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
586 * Scsi_Host.highmem_io, and so forth. It's readonly to all
587 * host side drivers though.
588 */
083522d7 589 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
18807521 590 if (HCC_64BIT_ADDR(hcc_params)) {
083522d7 591 ehci_writel(ehci, 0, &ehci->regs->segment);
18807521
DB
592#if 0
593// this is deeply broken on almost all architectures
6a35528a 594 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
18807521
DB
595 ehci_info(ehci, "enabled 64bit DMA\n");
596#endif
597 }
598
599
1da177e4
LT
600 // Philips, Intel, and maybe others need CMD_RUN before the
601 // root hub will detect new devices (why?); NEC doesn't
18807521
DB
602 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
603 ehci->command |= CMD_RUN;
083522d7 604 ehci_writel(ehci, ehci->command, &ehci->regs->command);
18807521 605 dbg_cmd (ehci, "init", ehci->command);
1da177e4 606
1da177e4
LT
607 /*
608 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
609 * are explicitly handed to companion controller(s), so no TT is
610 * involved with the root hub. (Except where one is integrated,
611 * and there's no companion controller unless maybe for USB OTG.)
32fe0198
AS
612 *
613 * Turning on the CF flag will transfer ownership of all ports
614 * from the companions to the EHCI controller. If any of the
615 * companions are in the middle of a port reset at the time, it
616 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
1cb52658
DB
617 * guarantees that no resets are in progress. After we set CF,
618 * a short delay lets the hardware catch up; new resets shouldn't
619 * be started before the port switching actions could complete.
1da177e4 620 */
32fe0198 621 down_write(&ehci_cf_port_reset_rwsem);
e8799906 622 ehci->rh_state = EHCI_RH_RUNNING;
083522d7
BH
623 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
624 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1cb52658 625 msleep(5);
32fe0198 626 up_write(&ehci_cf_port_reset_rwsem);
ee4ecb8a 627 ehci->last_periodic_enable = ktime_get_real();
1da177e4 628
c430131a 629 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
1da177e4 630 ehci_info (ehci,
2b70f073 631 "USB %x.%x started, EHCI %x.%02x%s\n",
7ff71d6a 632 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
2b70f073 633 temp >> 8, temp & 0xff,
93f1a47c 634 ignore_oc ? ", overcurrent ignored" : "");
1da177e4 635
083522d7
BH
636 ehci_writel(ehci, INTR_MASK,
637 &ehci->regs->intr_enable); /* Turn On Interrupts */
1da177e4 638
18807521
DB
639 /* GRR this is run-once init(), being done every time the HC starts.
640 * So long as they're part of class devices, we can't do it init()
641 * since the class device isn't created that early.
642 */
643 create_debug_files(ehci);
4c67045b 644 create_sysfs_files(ehci);
1da177e4
LT
645
646 return 0;
647}
648
3e023203 649int ehci_setup(struct usb_hcd *hcd)
2093c6b4
MC
650{
651 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
652 int retval;
653
654 ehci->regs = (void __iomem *)ehci->caps +
655 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
656 dbg_hcs_params(ehci, "reset");
657 dbg_hcc_params(ehci, "reset");
658
659 /* cache this readonly data; minimize chip reads */
660 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
661
662 ehci->sbrn = HCD_USB2;
663
631fe9d9
AS
664 /* data structure init */
665 retval = ehci_init(hcd);
2093c6b4
MC
666 if (retval)
667 return retval;
668
631fe9d9 669 retval = ehci_halt(ehci);
2093c6b4
MC
670 if (retval)
671 return retval;
672
1a49e2ac
AS
673 if (ehci_is_TDI(ehci))
674 tdi_reset(ehci);
675
2093c6b4
MC
676 ehci_reset(ehci);
677
678 return 0;
679}
3e023203 680EXPORT_SYMBOL_GPL(ehci_setup);
2093c6b4 681
1da177e4
LT
682/*-------------------------------------------------------------------------*/
683
7d12e780 684static irqreturn_t ehci_irq (struct usb_hcd *hcd)
1da177e4
LT
685{
686 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
67b2e029 687 u32 status, masked_status, pcd_status = 0, cmd;
1da177e4
LT
688 int bh;
689
690 spin_lock (&ehci->lock);
691
083522d7 692 status = ehci_readl(ehci, &ehci->regs->status);
1da177e4
LT
693
694 /* e.g. cardbus physical eject */
695 if (status == ~(u32) 0) {
696 ehci_dbg (ehci, "device removed\n");
697 goto dead;
698 }
699
2fbe2bf1
AS
700 /*
701 * We don't use STS_FLR, but some controllers don't like it to
702 * remain on, so mask it out along with the other status bits.
703 */
704 masked_status = status & (INTR_MASK | STS_FLR);
705
69fff59d 706 /* Shared IRQ? */
e8799906 707 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
1da177e4
LT
708 spin_unlock(&ehci->lock);
709 return IRQ_NONE;
710 }
711
712 /* clear (just) interrupts */
67b2e029 713 ehci_writel(ehci, masked_status, &ehci->regs->status);
e82cc128 714 cmd = ehci_readl(ehci, &ehci->regs->command);
1da177e4
LT
715 bh = 0;
716
9776afc8 717#ifdef VERBOSE_DEBUG
1da177e4
LT
718 /* unrequested/ignored: Frame List Rollover */
719 dbg_status (ehci, "irq", status);
720#endif
721
722 /* INT, ERR, and IAA interrupt rates can be throttled */
723
724 /* normal [4.15.1.2] or error [4.15.1.1] completion */
725 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
726 if (likely ((status & STS_ERR) == 0))
727 COUNT (ehci->stats.normal);
728 else
729 COUNT (ehci->stats.error);
730 bh = 1;
731 }
732
733 /* complete the unlinking of some qh [4.15.2.3] */
734 if (status & STS_IAA) {
9d938747
AS
735
736 /* Turn off the IAA watchdog */
737 ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG);
738
739 /*
740 * Mild optimization: Allow another IAAD to reset the
741 * hrtimer, if one occurs before the next expiration.
742 * In theory we could always cancel the hrtimer, but
743 * tests show that about half the time it will be reset
744 * for some other event anyway.
745 */
746 if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG)
747 ++ehci->next_hrtimer_event;
748
e82cc128 749 /* guard against (alleged) silicon errata */
6feff1b9 750 if (cmd & CMD_IAAD)
e82cc128 751 ehci_dbg(ehci, "IAA with IAAD still set?\n");
6402c796 752 if (ehci->async_iaa)
99ac5b1e 753 COUNT(ehci->stats.iaa);
6402c796 754 end_unlink_async(ehci);
1da177e4
LT
755 }
756
757 /* remote wakeup [4.3.1] */
d97cc2f2 758 if (status & STS_PCD) {
1da177e4 759 unsigned i = HCS_N_PORTS (ehci->hcs_params);
5a9cdf33 760 u32 ppcd = 0;
d1b1842c
DB
761
762 /* kick root hub later */
1d619f12 763 pcd_status = status;
1da177e4
LT
764
765 /* resume root hub? */
dc75ce9d 766 if (ehci->rh_state == EHCI_RH_SUSPENDED)
8c03356a 767 usb_hcd_resume_root_hub(hcd);
1da177e4 768
5a9cdf33
AD
769 /* get per-port change detect bits */
770 if (ehci->has_ppcd)
771 ppcd = status >> 16;
772
1da177e4 773 while (i--) {
5a9cdf33
AD
774 int pstatus;
775
776 /* leverage per-port change bits feature */
777 if (ehci->has_ppcd && !(ppcd & (1 << i)))
778 continue;
779 pstatus = ehci_readl(ehci,
780 &ehci->regs->port_status[i]);
b972b68c
DB
781
782 if (pstatus & PORT_OWNER)
1da177e4 783 continue;
eafe5b99
AS
784 if (!(test_bit(i, &ehci->suspended_ports) &&
785 ((pstatus & PORT_RESUME) ||
786 !(pstatus & PORT_SUSPEND)) &&
787 (pstatus & PORT_PE) &&
788 ehci->reset_done[i] == 0))
1da177e4
LT
789 continue;
790
791 /* start 20 msec resume signaling from this port,
792 * and make khubd collect PORT_STAT_C_SUSPEND to
49d0f078
AS
793 * stop that signaling. Use 5 ms extra for safety,
794 * like usb_port_resume() does.
1da177e4 795 */
49d0f078 796 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
a448e4dc 797 set_bit(i, &ehci->resuming_ports);
1da177e4 798 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
f292e7f9 799 usb_hcd_start_port_resume(&hcd->self, i);
61e8b858 800 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
1da177e4
LT
801 }
802 }
803
804 /* PCI errors [4.15.2.4] */
805 if (unlikely ((status & STS_FATAL) != 0)) {
67b2e029 806 ehci_err(ehci, "fatal error\n");
eafe5b99
AS
807 dbg_cmd(ehci, "fatal", cmd);
808 dbg_status(ehci, "fatal", status);
1da177e4 809dead:
69fff59d 810 usb_hc_died(hcd);
bf6387bc
AS
811
812 /* Don't let the controller do anything more */
43fe3a99 813 ehci->shutdown = true;
bf6387bc
AS
814 ehci->rh_state = EHCI_RH_STOPPING;
815 ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
816 ehci_writel(ehci, ehci->command, &ehci->regs->command);
817 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
818 ehci_handle_controller_death(ehci);
819
820 /* Handle completions when the controller stops */
821 bh = 0;
1da177e4
LT
822 }
823
824 if (bh)
7d12e780 825 ehci_work (ehci);
1da177e4 826 spin_unlock (&ehci->lock);
d1b1842c 827 if (pcd_status)
1d619f12 828 usb_hcd_poll_rh_status(hcd);
1da177e4
LT
829 return IRQ_HANDLED;
830}
831
832/*-------------------------------------------------------------------------*/
833
834/*
835 * non-error returns are a promise to giveback() the urb later
836 * we drop ownership so next owner (or urb unlink) can get it
837 *
838 * urb + dev is in hcd.self.controller.urb_list
839 * we're queueing TDs onto software and hardware lists
840 *
841 * hcd-specific init for hcpriv hasn't been done yet
842 *
843 * NOTE: control, bulk, and interrupt share the same code to append TDs
844 * to a (possibly active) QH, and the same QH scanning code.
845 */
846static int ehci_urb_enqueue (
847 struct usb_hcd *hcd,
1da177e4 848 struct urb *urb,
55016f10 849 gfp_t mem_flags
1da177e4
LT
850) {
851 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
852 struct list_head qtd_list;
853
854 INIT_LIST_HEAD (&qtd_list);
855
856 switch (usb_pipetype (urb->pipe)) {
25b70a86
DB
857 case PIPE_CONTROL:
858 /* qh_completions() code doesn't handle all the fault cases
859 * in multi-TD control transfers. Even 1KB is rare anyway.
860 */
861 if (urb->transfer_buffer_length > (16 * 1024))
862 return -EMSGSIZE;
863 /* FALLTHROUGH */
864 /* case PIPE_BULK: */
1da177e4
LT
865 default:
866 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
867 return -ENOMEM;
e9df41c5 868 return submit_async(ehci, urb, &qtd_list, mem_flags);
1da177e4
LT
869
870 case PIPE_INTERRUPT:
871 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
872 return -ENOMEM;
e9df41c5 873 return intr_submit(ehci, urb, &qtd_list, mem_flags);
1da177e4
LT
874
875 case PIPE_ISOCHRONOUS:
876 if (urb->dev->speed == USB_SPEED_HIGH)
877 return itd_submit (ehci, urb, mem_flags);
878 else
879 return sitd_submit (ehci, urb, mem_flags);
880 }
881}
882
1da177e4
LT
883/* remove from hardware lists
884 * completions normally happen asynchronously
885 */
886
e9df41c5 887static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1da177e4
LT
888{
889 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
890 struct ehci_qh *qh;
891 unsigned long flags;
e9df41c5 892 int rc;
1da177e4
LT
893
894 spin_lock_irqsave (&ehci->lock, flags);
e9df41c5
AS
895 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
896 if (rc)
897 goto done;
898
1da177e4
LT
899 switch (usb_pipetype (urb->pipe)) {
900 // case PIPE_CONTROL:
901 // case PIPE_BULK:
902 default:
903 qh = (struct ehci_qh *) urb->hcpriv;
904 if (!qh)
905 break;
07d29b63
AS
906 switch (qh->qh_state) {
907 case QH_STATE_LINKED:
908 case QH_STATE_COMPLETING:
3c273a05 909 start_unlink_async(ehci, qh);
07d29b63
AS
910 break;
911 case QH_STATE_UNLINK:
912 case QH_STATE_UNLINK_WAIT:
913 /* already started */
914 break;
915 case QH_STATE_IDLE:
7a0f0d95
AS
916 /* QH might be waiting for a Clear-TT-Buffer */
917 qh_completions(ehci, qh);
07d29b63
AS
918 break;
919 }
1da177e4
LT
920 break;
921
922 case PIPE_INTERRUPT:
923 qh = (struct ehci_qh *) urb->hcpriv;
924 if (!qh)
925 break;
926 switch (qh->qh_state) {
927 case QH_STATE_LINKED:
a448c9d8 928 case QH_STATE_COMPLETING:
df202255 929 start_unlink_intr(ehci, qh);
a448c9d8 930 break;
1da177e4 931 case QH_STATE_IDLE:
7d12e780 932 qh_completions (ehci, qh);
1da177e4
LT
933 break;
934 default:
935 ehci_dbg (ehci, "bogus qh %p state %d\n",
936 qh, qh->qh_state);
937 goto done;
938 }
1da177e4
LT
939 break;
940
941 case PIPE_ISOCHRONOUS:
942 // itd or sitd ...
943
944 // wait till next completion, do it then.
945 // completion irqs can wait up to 1024 msec,
946 break;
947 }
948done:
949 spin_unlock_irqrestore (&ehci->lock, flags);
e9df41c5 950 return rc;
1da177e4
LT
951}
952
953/*-------------------------------------------------------------------------*/
954
955// bulk qh holds the data toggle
956
957static void
958ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
959{
960 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
961 unsigned long flags;
962 struct ehci_qh *qh, *tmp;
963
964 /* ASSERT: any requests/urbs are being unlinked */
965 /* ASSERT: nobody can be submitting urbs for this any more */
966
967rescan:
968 spin_lock_irqsave (&ehci->lock, flags);
969 qh = ep->hcpriv;
970 if (!qh)
971 goto done;
972
973 /* endpoints can be iso streams. for now, we don't
974 * accelerate iso completions ... so spin a while.
975 */
1082f57a 976 if (qh->hw == NULL) {
8c5bf7be
AS
977 struct ehci_iso_stream *stream = ep->hcpriv;
978
979 if (!list_empty(&stream->td_list))
980 goto idle_timeout;
981
982 /* BUG_ON(!list_empty(&stream->free_list)); */
983 kfree(stream);
984 goto done;
1da177e4
LT
985 }
986
c0c53dbc 987 if (ehci->rh_state < EHCI_RH_RUNNING)
1da177e4
LT
988 qh->qh_state = QH_STATE_IDLE;
989 switch (qh->qh_state) {
990 case QH_STATE_LINKED:
3a44494e 991 case QH_STATE_COMPLETING:
1da177e4
LT
992 for (tmp = ehci->async->qh_next.qh;
993 tmp && tmp != qh;
994 tmp = tmp->qh_next.qh)
995 continue;
02e2c51b
AS
996 /* periodic qh self-unlinks on empty, and a COMPLETING qh
997 * may already be unlinked.
998 */
999 if (tmp)
3c273a05 1000 start_unlink_async(ehci, qh);
1da177e4
LT
1001 /* FALL THROUGH */
1002 case QH_STATE_UNLINK: /* wait for hw to finish? */
07d29b63 1003 case QH_STATE_UNLINK_WAIT:
1da177e4
LT
1004idle_timeout:
1005 spin_unlock_irqrestore (&ehci->lock, flags);
22c43863 1006 schedule_timeout_uninterruptible(1);
1da177e4
LT
1007 goto rescan;
1008 case QH_STATE_IDLE: /* fully unlinked */
914b7012
AS
1009 if (qh->clearing_tt)
1010 goto idle_timeout;
1da177e4 1011 if (list_empty (&qh->qtd_list)) {
c83e1a9f 1012 qh_destroy(ehci, qh);
1da177e4
LT
1013 break;
1014 }
1015 /* else FALL THROUGH */
1016 default:
1da177e4
LT
1017 /* caller was supposed to have unlinked any requests;
1018 * that's not our job. just leak this memory.
1019 */
1020 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1021 qh, ep->desc.bEndpointAddress, qh->qh_state,
1022 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1023 break;
1024 }
8c5bf7be 1025 done:
1da177e4 1026 ep->hcpriv = NULL;
1da177e4 1027 spin_unlock_irqrestore (&ehci->lock, flags);
1da177e4
LT
1028}
1029
b18ffd49
AS
1030static void
1031ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1032{
1033 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1034 struct ehci_qh *qh;
1035 int eptype = usb_endpoint_type(&ep->desc);
a455212d
AS
1036 int epnum = usb_endpoint_num(&ep->desc);
1037 int is_out = usb_endpoint_dir_out(&ep->desc);
1038 unsigned long flags;
b18ffd49
AS
1039
1040 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1041 return;
1042
a455212d 1043 spin_lock_irqsave(&ehci->lock, flags);
b18ffd49
AS
1044 qh = ep->hcpriv;
1045
1046 /* For Bulk and Interrupt endpoints we maintain the toggle state
1047 * in the hardware; the toggle bits in udev aren't used at all.
1048 * When an endpoint is reset by usb_clear_halt() we must reset
1049 * the toggle bit in the QH.
1050 */
1051 if (qh) {
a455212d 1052 usb_settoggle(qh->dev, epnum, is_out, 0);
b18ffd49
AS
1053 if (!list_empty(&qh->qtd_list)) {
1054 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
3a44494e
AS
1055 } else if (qh->qh_state == QH_STATE_LINKED ||
1056 qh->qh_state == QH_STATE_COMPLETING) {
a455212d
AS
1057
1058 /* The toggle value in the QH can't be updated
1059 * while the QH is active. Unlink it now;
1060 * re-linking will call qh_refresh().
b18ffd49 1061 */
a448c9d8 1062 if (eptype == USB_ENDPOINT_XFER_BULK)
3c273a05 1063 start_unlink_async(ehci, qh);
a448c9d8 1064 else
df202255 1065 start_unlink_intr(ehci, qh);
b18ffd49
AS
1066 }
1067 }
a455212d 1068 spin_unlock_irqrestore(&ehci->lock, flags);
b18ffd49
AS
1069}
1070
7ff71d6a
MP
1071static int ehci_get_frame (struct usb_hcd *hcd)
1072{
1073 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
68aa95d5 1074 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
7ff71d6a 1075}
1da177e4
LT
1076
1077/*-------------------------------------------------------------------------*/
c5cf9212
AS
1078
1079#ifdef CONFIG_PM
1080
1081/* suspend/resume, section 4.3 */
1082
1083/* These routines handle the generic parts of controller suspend/resume */
1084
3e023203 1085int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
c5cf9212
AS
1086{
1087 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1088
1089 if (time_before(jiffies, ehci->next_statechange))
1090 msleep(10);
1091
1092 /*
1093 * Root hub was already suspended. Disable IRQ emission and
1094 * mark HW unaccessible. The PM and USB cores make sure that
1095 * the root hub is either suspended or stopped.
1096 */
1097 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
1098
1099 spin_lock_irq(&ehci->lock);
1100 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
1101 (void) ehci_readl(ehci, &ehci->regs->intr_enable);
1102
1103 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1104 spin_unlock_irq(&ehci->lock);
1105
1106 return 0;
1107}
3e023203 1108EXPORT_SYMBOL_GPL(ehci_suspend);
c5cf9212
AS
1109
1110/* Returns 0 if power was preserved, 1 if power was lost */
3e023203 1111int ehci_resume(struct usb_hcd *hcd, bool hibernated)
c5cf9212
AS
1112{
1113 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1114
1115 if (time_before(jiffies, ehci->next_statechange))
1116 msleep(100);
1117
1118 /* Mark hardware accessible again as we are back to full power by now */
1119 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1120
43fe3a99
AS
1121 if (ehci->shutdown)
1122 return 0; /* Controller is dead */
1123
c5cf9212
AS
1124 /*
1125 * If CF is still set and we aren't resuming from hibernation
1126 * then we maintained suspend power.
1127 * Just undo the effect of ehci_suspend().
1128 */
1129 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
1130 !hibernated) {
1131 int mask = INTR_MASK;
1132
1133 ehci_prepare_ports_for_controller_resume(ehci);
43fe3a99
AS
1134
1135 spin_lock_irq(&ehci->lock);
1136 if (ehci->shutdown)
1137 goto skip;
1138
c5cf9212
AS
1139 if (!hcd->self.root_hub->do_remote_wakeup)
1140 mask &= ~STS_PCD;
1141 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
1142 ehci_readl(ehci, &ehci->regs->intr_enable);
43fe3a99
AS
1143 skip:
1144 spin_unlock_irq(&ehci->lock);
c5cf9212
AS
1145 return 0;
1146 }
1147
1148 /*
1149 * Else reset, to cope with power loss or resume from hibernation
1150 * having let the firmware kick in during reboot.
1151 */
1152 usb_root_hub_lost_power(hcd->self.root_hub);
1153 (void) ehci_halt(ehci);
1154 (void) ehci_reset(ehci);
1155
43fe3a99
AS
1156 spin_lock_irq(&ehci->lock);
1157 if (ehci->shutdown)
1158 goto skip;
1159
c5cf9212
AS
1160 ehci_writel(ehci, ehci->command, &ehci->regs->command);
1161 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
1162 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1163
43fe3a99
AS
1164 ehci->rh_state = EHCI_RH_SUSPENDED;
1165 spin_unlock_irq(&ehci->lock);
1166
c5cf9212
AS
1167 return 1;
1168}
3e023203 1169EXPORT_SYMBOL_GPL(ehci_resume);
c5cf9212
AS
1170
1171#endif
1172
1173/*-------------------------------------------------------------------------*/
1174
3e023203
AS
1175/*
1176 * Generic structure: This gets copied for platform drivers so that
1177 * individual entries can be overridden as needed.
1178 */
1179
1180static const struct hc_driver ehci_hc_driver = {
1181 .description = hcd_name,
1182 .product_desc = "EHCI Host Controller",
1183 .hcd_priv_size = sizeof(struct ehci_hcd),
1184
1185 /*
1186 * generic hardware linkage
1187 */
1188 .irq = ehci_irq,
1189 .flags = HCD_MEMORY | HCD_USB2,
1190
1191 /*
1192 * basic lifecycle operations
1193 */
1194 .reset = ehci_setup,
1195 .start = ehci_run,
1196 .stop = ehci_stop,
1197 .shutdown = ehci_shutdown,
1198
1199 /*
1200 * managing i/o requests and associated device resources
1201 */
1202 .urb_enqueue = ehci_urb_enqueue,
1203 .urb_dequeue = ehci_urb_dequeue,
1204 .endpoint_disable = ehci_endpoint_disable,
1205 .endpoint_reset = ehci_endpoint_reset,
1206 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1207
1208 /*
1209 * scheduling support
1210 */
1211 .get_frame_number = ehci_get_frame,
1212
1213 /*
1214 * root hub support
1215 */
1216 .hub_status_data = ehci_hub_status_data,
1217 .hub_control = ehci_hub_control,
1218 .bus_suspend = ehci_bus_suspend,
1219 .bus_resume = ehci_bus_resume,
1220 .relinquish_port = ehci_relinquish_port,
1221 .port_handed_over = ehci_port_handed_over,
1222};
1223
1224void ehci_init_driver(struct hc_driver *drv,
1225 const struct ehci_driver_overrides *over)
1226{
1227 /* Copy the generic table to drv and then apply the overrides */
1228 *drv = ehci_hc_driver;
1229
1b36810e
AS
1230 if (over) {
1231 drv->hcd_priv_size += over->extra_priv_size;
1232 if (over->reset)
1233 drv->reset = over->reset;
1234 }
3e023203
AS
1235}
1236EXPORT_SYMBOL_GPL(ehci_init_driver);
1237
1238/*-------------------------------------------------------------------------*/
1239
2b70f073 1240MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4
LT
1241MODULE_AUTHOR (DRIVER_AUTHOR);
1242MODULE_LICENSE ("GPL");
1243
ba02978a 1244#ifdef CONFIG_USB_EHCI_FSL
80cb9aee 1245#include "ehci-fsl.c"
01cced25 1246#define PLATFORM_DRIVER ehci_fsl_driver
80cb9aee
RV
1247#endif
1248
60b0bf0f 1249#ifdef CONFIG_USB_EHCI_SH
63c84552
PM
1250#include "ehci-sh.c"
1251#define PLATFORM_DRIVER ehci_hcd_sh_driver
1252#endif
1253
7f124f4b 1254#ifdef CONFIG_USB_EHCI_HCD_OMAP
54ab2b02
FB
1255#include "ehci-omap.c"
1256#define PLATFORM_DRIVER ehci_hcd_omap_driver
1257#endif
1258
ad75a410
GL
1259#ifdef CONFIG_PPC_PS3
1260#include "ehci-ps3.c"
7a4eb7fd 1261#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
ad75a410
GL
1262#endif
1263
da0e8fb0
VB
1264#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1265#include "ehci-ppc-of.c"
1266#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1267#endif
1268
08d3c18e
JZ
1269#ifdef CONFIG_XPS_USB_HCD_XILINX
1270#include "ehci-xilinx-of.c"
1f23b2d9 1271#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
08d3c18e
JZ
1272#endif
1273
705a7521 1274#ifdef CONFIG_PLAT_ORION
e96ffe2f
TP
1275#include "ehci-orion.c"
1276#define PLATFORM_DRIVER ehci_orion_driver
1277#endif
1278
586dfc8c
WZ
1279#ifdef CONFIG_USB_W90X900_EHCI
1280#include "ehci-w90x900.c"
1281#define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1282#endif
1283
501c9c08
NF
1284#ifdef CONFIG_ARCH_AT91
1285#include "ehci-atmel.c"
1286#define PLATFORM_DRIVER ehci_atmel_driver
1287#endif
1288
1643accd
DD
1289#ifdef CONFIG_USB_OCTEON_EHCI
1290#include "ehci-octeon.c"
1291#define PLATFORM_DRIVER ehci_octeon_driver
1292#endif
1293
ad78acaf
AC
1294#ifdef CONFIG_ARCH_VT8500
1295#include "ehci-vt8500.c"
1296#define PLATFORM_DRIVER vt8500_ehci_driver
1297#endif
1298
c8c38de9
DS
1299#ifdef CONFIG_PLAT_SPEAR
1300#include "ehci-spear.c"
1301#define PLATFORM_DRIVER spear_ehci_hcd_driver
1302#endif
1303
b0848aea
PK
1304#ifdef CONFIG_USB_EHCI_MSM
1305#include "ehci-msm.c"
1306#define PLATFORM_DRIVER ehci_msm_driver
1307#endif
1308
47fc28bf
CM
1309#ifdef CONFIG_TILE_USB
1310#include "ehci-tilegx.c"
1311#define PLATFORM_DRIVER ehci_hcd_tilegx_driver
1312#endif
1313
22ced687
A
1314#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1315#include "ehci-pmcmsp.c"
1316#define PLATFORM_DRIVER ehci_hcd_msp_driver
1317#endif
1318
79ad3b5a
BG
1319#ifdef CONFIG_USB_EHCI_TEGRA
1320#include "ehci-tegra.c"
1321#define PLATFORM_DRIVER tegra_ehci_driver
1322#endif
1323
1bcc5aa8
JS
1324#ifdef CONFIG_USB_EHCI_S5P
1325#include "ehci-s5p.c"
1326#define PLATFORM_DRIVER s5p_ehci_driver
1327#endif
1328
9be03929
JA
1329#ifdef CONFIG_SPARC_LEON
1330#include "ehci-grlib.c"
1331#define PLATFORM_DRIVER ehci_grlib_driver
1332#endif
1333
3a082ec9
NZ
1334#ifdef CONFIG_USB_EHCI_MV
1335#include "ehci-mv.c"
1336#define PLATFORM_DRIVER ehci_mv_driver
1337#endif
f30cdbcb 1338
c256667f
SH
1339#ifdef CONFIG_MIPS_SEAD3
1340#include "ehci-sead3.c"
1341#define PLATFORM_DRIVER ehci_hcd_sead3_driver
1342#endif
1343
adfa79d1 1344#if !IS_ENABLED(CONFIG_USB_EHCI_PCI) && \
99f91934 1345 !IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) && \
9ce45ef8 1346 !IS_ENABLED(CONFIG_USB_CHIPIDEA_HOST) && \
dba63b2f 1347 !IS_ENABLED(CONFIG_USB_EHCI_MXC) && \
adfa79d1
AS
1348 !defined(PLATFORM_DRIVER) && \
1349 !defined(PS3_SYSTEM_BUS_DRIVER) && \
1350 !defined(OF_PLATFORM_DRIVER) && \
1351 !defined(XILINX_OF_PLATFORM_DRIVER)
7ff71d6a
MP
1352#error "missing bus glue for ehci-hcd"
1353#endif
01cced25
KG
1354
1355static int __init ehci_hcd_init(void)
1356{
1357 int retval = 0;
1358
2b70f073
AS
1359 if (usb_disabled())
1360 return -ENODEV;
1361
1362 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
9beeee65
AS
1363 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1364 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1365 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1366 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1367 " before uhci_hcd and ohci_hcd, not after\n");
1368
01cced25
KG
1369 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1370 hcd_name,
1371 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1372 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1373
694cc208 1374#ifdef DEBUG
08f4e586 1375 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
9beeee65
AS
1376 if (!ehci_debug_root) {
1377 retval = -ENOENT;
1378 goto err_debug;
1379 }
694cc208
TJ
1380#endif
1381
01cced25
KG
1382#ifdef PLATFORM_DRIVER
1383 retval = platform_driver_register(&PLATFORM_DRIVER);
da0e8fb0
VB
1384 if (retval < 0)
1385 goto clean0;
01cced25
KG
1386#endif
1387
ad75a410 1388#ifdef PS3_SYSTEM_BUS_DRIVER
7a4eb7fd 1389 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
da0e8fb0
VB
1390 if (retval < 0)
1391 goto clean2;
694cc208 1392#endif
da0e8fb0
VB
1393
1394#ifdef OF_PLATFORM_DRIVER
d35fb641 1395 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
da0e8fb0
VB
1396 if (retval < 0)
1397 goto clean3;
1398#endif
1f23b2d9
GL
1399
1400#ifdef XILINX_OF_PLATFORM_DRIVER
d35fb641 1401 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1f23b2d9
GL
1402 if (retval < 0)
1403 goto clean4;
1404#endif
da0e8fb0
VB
1405 return retval;
1406
1f23b2d9 1407#ifdef XILINX_OF_PLATFORM_DRIVER
d35fb641 1408 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1f23b2d9
GL
1409clean4:
1410#endif
da0e8fb0 1411#ifdef OF_PLATFORM_DRIVER
d35fb641 1412 platform_driver_unregister(&OF_PLATFORM_DRIVER);
da0e8fb0
VB
1413clean3:
1414#endif
1415#ifdef PS3_SYSTEM_BUS_DRIVER
1416 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1417clean2:
ad75a410 1418#endif
da0e8fb0
VB
1419#ifdef PLATFORM_DRIVER
1420 platform_driver_unregister(&PLATFORM_DRIVER);
1421clean0:
1422#endif
1423#ifdef DEBUG
1424 debugfs_remove(ehci_debug_root);
1425 ehci_debug_root = NULL;
9beeee65 1426err_debug:
a9b6148d 1427#endif
9beeee65 1428 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
01cced25
KG
1429 return retval;
1430}
1431module_init(ehci_hcd_init);
1432
1433static void __exit ehci_hcd_cleanup(void)
1434{
1f23b2d9 1435#ifdef XILINX_OF_PLATFORM_DRIVER
d35fb641 1436 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1f23b2d9 1437#endif
da0e8fb0 1438#ifdef OF_PLATFORM_DRIVER
d35fb641 1439 platform_driver_unregister(&OF_PLATFORM_DRIVER);
da0e8fb0 1440#endif
01cced25
KG
1441#ifdef PLATFORM_DRIVER
1442 platform_driver_unregister(&PLATFORM_DRIVER);
1443#endif
ad75a410 1444#ifdef PS3_SYSTEM_BUS_DRIVER
7a4eb7fd 1445 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
ad75a410 1446#endif
694cc208
TJ
1447#ifdef DEBUG
1448 debugfs_remove(ehci_debug_root);
1449#endif
9beeee65 1450 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
01cced25
KG
1451}
1452module_exit(ehci_hcd_cleanup);
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