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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000-2004 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/slab.h> | |
1da177e4 LT |
27 | #include <linux/errno.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/timer.h> | |
30 | #include <linux/list.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/reboot.h> | |
33 | #include <linux/usb.h> | |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/dma-mapping.h> | |
694cc208 | 36 | #include <linux/debugfs.h> |
1da177e4 LT |
37 | |
38 | #include "../core/hcd.h" | |
39 | ||
40 | #include <asm/byteorder.h> | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/unaligned.h> | |
1da177e4 LT |
45 | |
46 | /*-------------------------------------------------------------------------*/ | |
47 | ||
48 | /* | |
49 | * EHCI hc_driver implementation ... experimental, incomplete. | |
50 | * Based on the final 1.0 register interface specification. | |
51 | * | |
52 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
53 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
54 | * Next comes "CardBay", using USB 2.0 signals. | |
55 | * | |
56 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
57 | * Special thanks to Intel and VIA for providing host controllers to | |
58 | * test this driver on, and Cypress (including In-System Design) for | |
59 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
60 | */ |
61 | ||
62 | #define DRIVER_VERSION "10 Dec 2004" | |
63 | #define DRIVER_AUTHOR "David Brownell" | |
64 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
65 | ||
66 | static const char hcd_name [] = "ehci_hcd"; | |
67 | ||
68 | ||
9776afc8 | 69 | #undef VERBOSE_DEBUG |
1da177e4 LT |
70 | #undef EHCI_URB_TRACE |
71 | ||
72 | #ifdef DEBUG | |
73 | #define EHCI_STATS | |
74 | #endif | |
75 | ||
76 | /* magic numbers that can affect system performance */ | |
77 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
78 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
79 | #define EHCI_TUNE_RL_TT 0 | |
80 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
81 | #define EHCI_TUNE_MULT_TT 1 | |
82 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
83 | ||
07d29b63 | 84 | #define EHCI_IAA_MSECS 10 /* arbitrary */ |
1da177e4 LT |
85 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
86 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
87 | #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ | |
88 | ||
89 | /* Initial IRQ latency: faster than hw default */ | |
90 | static int log2_irq_thresh = 0; // 0 to 6 | |
91 | module_param (log2_irq_thresh, int, S_IRUGO); | |
92 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
93 | ||
94 | /* initial park setting: slower than hw default */ | |
95 | static unsigned park = 0; | |
96 | module_param (park, uint, S_IRUGO); | |
97 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
98 | ||
93f1a47c DB |
99 | /* for flakey hardware, ignore overcurrent indicators */ |
100 | static int ignore_oc = 0; | |
101 | module_param (ignore_oc, bool, S_IRUGO); | |
102 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
103 | ||
1da177e4 LT |
104 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
105 | ||
106 | /*-------------------------------------------------------------------------*/ | |
107 | ||
108 | #include "ehci.h" | |
109 | #include "ehci-dbg.c" | |
110 | ||
111 | /*-------------------------------------------------------------------------*/ | |
112 | ||
113 | /* | |
114 | * handshake - spin reading hc until handshake completes or fails | |
115 | * @ptr: address of hc register to be read | |
116 | * @mask: bits to look at in result of read | |
117 | * @done: value of those bits when handshake succeeds | |
118 | * @usec: timeout in microseconds | |
119 | * | |
120 | * Returns negative errno, or zero on success | |
121 | * | |
122 | * Success happens when the "mask" bits have the specified value (hardware | |
123 | * handshake done). There are two failure modes: "usec" have passed (major | |
124 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
125 | * | |
126 | * That last failure should_only happen in cases like physical cardbus eject | |
127 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
128 | * bridge shutdown: shutting down the bridge before the devices using it. | |
129 | */ | |
083522d7 BH |
130 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
131 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
132 | { |
133 | u32 result; | |
134 | ||
135 | do { | |
083522d7 | 136 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
137 | if (result == ~(u32)0) /* card removed */ |
138 | return -ENODEV; | |
139 | result &= mask; | |
140 | if (result == done) | |
141 | return 0; | |
142 | udelay (1); | |
143 | usec--; | |
144 | } while (usec > 0); | |
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
c765d4ca KW |
148 | static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, |
149 | u32 mask, u32 done, int usec) | |
150 | { | |
151 | int error = handshake(ehci, ptr, mask, done, usec); | |
152 | if (error) | |
153 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
154 | ||
155 | return error; | |
156 | } | |
157 | ||
1da177e4 LT |
158 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ |
159 | static int ehci_halt (struct ehci_hcd *ehci) | |
160 | { | |
083522d7 | 161 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 162 | |
72f30b6f | 163 | /* disable any irqs left enabled by previous code */ |
083522d7 | 164 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 165 | |
1da177e4 LT |
166 | if ((temp & STS_HALT) != 0) |
167 | return 0; | |
168 | ||
083522d7 | 169 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 170 | temp &= ~CMD_RUN; |
083522d7 BH |
171 | ehci_writel(ehci, temp, &ehci->regs->command); |
172 | return handshake (ehci, &ehci->regs->status, | |
173 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
174 | } |
175 | ||
176 | /* put TDI/ARC silicon into EHCI mode */ | |
177 | static void tdi_reset (struct ehci_hcd *ehci) | |
178 | { | |
179 | u32 __iomem *reg_ptr; | |
180 | u32 tmp; | |
181 | ||
d23a1377 | 182 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); |
083522d7 | 183 | tmp = ehci_readl(ehci, reg_ptr); |
d23a1377 VB |
184 | tmp |= USBMODE_CM_HC; |
185 | /* The default byte access to MMR space is LE after | |
186 | * controller reset. Set the required endian mode | |
187 | * for transfer buffers to match the host microprocessor | |
188 | */ | |
189 | if (ehci_big_endian_mmio(ehci)) | |
190 | tmp |= USBMODE_BE; | |
083522d7 | 191 | ehci_writel(ehci, tmp, reg_ptr); |
1da177e4 LT |
192 | } |
193 | ||
194 | /* reset a non-running (STS_HALT == 1) controller */ | |
195 | static int ehci_reset (struct ehci_hcd *ehci) | |
196 | { | |
197 | int retval; | |
083522d7 | 198 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
199 | |
200 | command |= CMD_RESET; | |
201 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 202 | ehci_writel(ehci, command, &ehci->regs->command); |
1da177e4 LT |
203 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; |
204 | ehci->next_statechange = jiffies; | |
083522d7 BH |
205 | retval = handshake (ehci, &ehci->regs->command, |
206 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 LT |
207 | |
208 | if (retval) | |
209 | return retval; | |
210 | ||
211 | if (ehci_is_TDI(ehci)) | |
212 | tdi_reset (ehci); | |
213 | ||
214 | return retval; | |
215 | } | |
216 | ||
217 | /* idle the controller (from running) */ | |
218 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
219 | { | |
220 | u32 temp; | |
221 | ||
222 | #ifdef DEBUG | |
223 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
224 | BUG (); | |
225 | #endif | |
226 | ||
227 | /* wait for any schedule enables/disables to take effect */ | |
083522d7 | 228 | temp = ehci_readl(ehci, &ehci->regs->command) << 10; |
1da177e4 | 229 | temp &= STS_ASS | STS_PSS; |
c765d4ca KW |
230 | if (handshake_on_error_set_halt(ehci, &ehci->regs->status, |
231 | STS_ASS | STS_PSS, temp, 16 * 125)) | |
1da177e4 | 232 | return; |
1da177e4 LT |
233 | |
234 | /* then disable anything that's still active */ | |
083522d7 | 235 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 236 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); |
083522d7 | 237 | ehci_writel(ehci, temp, &ehci->regs->command); |
1da177e4 LT |
238 | |
239 | /* hardware can take 16 microframes to turn off ... */ | |
c765d4ca KW |
240 | handshake_on_error_set_halt(ehci, &ehci->regs->status, |
241 | STS_ASS | STS_PSS, 0, 16 * 125); | |
1da177e4 LT |
242 | } |
243 | ||
244 | /*-------------------------------------------------------------------------*/ | |
245 | ||
07d29b63 | 246 | static void end_unlink_async(struct ehci_hcd *ehci); |
7d12e780 | 247 | static void ehci_work(struct ehci_hcd *ehci); |
1da177e4 LT |
248 | |
249 | #include "ehci-hub.c" | |
250 | #include "ehci-mem.c" | |
251 | #include "ehci-q.c" | |
252 | #include "ehci-sched.c" | |
253 | ||
254 | /*-------------------------------------------------------------------------*/ | |
255 | ||
07d29b63 | 256 | static void ehci_iaa_watchdog(unsigned long param) |
1da177e4 LT |
257 | { |
258 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
259 | unsigned long flags; | |
260 | ||
261 | spin_lock_irqsave (&ehci->lock, flags); | |
262 | ||
e82cc128 DB |
263 | /* Lost IAA irqs wedge things badly; seen first with a vt8235. |
264 | * So we need this watchdog, but must protect it against both | |
265 | * (a) SMP races against real IAA firing and retriggering, and | |
266 | * (b) clean HC shutdown, when IAA watchdog was pending. | |
267 | */ | |
268 | if (ehci->reclaim | |
269 | && !timer_pending(&ehci->iaa_watchdog) | |
270 | && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { | |
271 | u32 cmd, status; | |
272 | ||
273 | /* If we get here, IAA is *REALLY* late. It's barely | |
274 | * conceivable that the system is so busy that CMD_IAAD | |
275 | * is still legitimately set, so let's be sure it's | |
276 | * clear before we read STS_IAA. (The HC should clear | |
277 | * CMD_IAAD when it sets STS_IAA.) | |
278 | */ | |
279 | cmd = ehci_readl(ehci, &ehci->regs->command); | |
280 | if (cmd & CMD_IAAD) | |
281 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
282 | &ehci->regs->command); | |
283 | ||
284 | /* If IAA is set here it either legitimately triggered | |
285 | * before we cleared IAAD above (but _way_ late, so we'll | |
286 | * still count it as lost) ... or a silicon erratum: | |
287 | * - VIA seems to set IAA without triggering the IRQ; | |
288 | * - IAAD potentially cleared without setting IAA. | |
289 | */ | |
290 | status = ehci_readl(ehci, &ehci->regs->status); | |
291 | if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { | |
1da177e4 | 292 | COUNT (ehci->stats.lost_iaa); |
083522d7 | 293 | ehci_writel(ehci, STS_IAA, &ehci->regs->status); |
1da177e4 | 294 | } |
e82cc128 DB |
295 | |
296 | ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", | |
297 | status, cmd); | |
07d29b63 | 298 | end_unlink_async(ehci); |
1da177e4 LT |
299 | } |
300 | ||
07d29b63 AS |
301 | spin_unlock_irqrestore(&ehci->lock, flags); |
302 | } | |
303 | ||
304 | static void ehci_watchdog(unsigned long param) | |
305 | { | |
306 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
307 | unsigned long flags; | |
308 | ||
309 | spin_lock_irqsave(&ehci->lock, flags); | |
310 | ||
311 | /* stop async processing after it's idled a bit */ | |
1da177e4 | 312 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) |
26f953fd | 313 | start_unlink_async (ehci, ehci->async); |
1da177e4 LT |
314 | |
315 | /* ehci could run by timer, without IRQs ... */ | |
7d12e780 | 316 | ehci_work (ehci); |
1da177e4 LT |
317 | |
318 | spin_unlock_irqrestore (&ehci->lock, flags); | |
319 | } | |
320 | ||
8903795a AS |
321 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
322 | * The firmware seems to think that powering off is a wakeup event! | |
323 | * This routine turns off remote wakeup and everything else, on all ports. | |
324 | */ | |
325 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
326 | { | |
327 | int port = HCS_N_PORTS(ehci->hcs_params); | |
328 | ||
329 | while (port--) | |
330 | ehci_writel(ehci, PORT_RWC_BITS, | |
331 | &ehci->regs->port_status[port]); | |
332 | } | |
333 | ||
21da84a8 SS |
334 | /* |
335 | * Halt HC, turn off all ports, and let the BIOS use the companion controllers. | |
336 | * Should be called with ehci->lock held. | |
72f30b6f | 337 | */ |
21da84a8 | 338 | static void ehci_silence_controller(struct ehci_hcd *ehci) |
1da177e4 | 339 | { |
21da84a8 | 340 | ehci_halt(ehci); |
8903795a | 341 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
342 | |
343 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 344 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
345 | |
346 | /* unblock posted writes */ | |
347 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
348 | } |
349 | ||
21da84a8 SS |
350 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
351 | * This forcibly disables dma and IRQs, helping kexec and other cases | |
352 | * where the next system software may expect clean state. | |
353 | */ | |
354 | static void ehci_shutdown(struct usb_hcd *hcd) | |
355 | { | |
356 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
357 | ||
358 | del_timer_sync(&ehci->watchdog); | |
359 | del_timer_sync(&ehci->iaa_watchdog); | |
360 | ||
361 | spin_lock_irq(&ehci->lock); | |
362 | ehci_silence_controller(ehci); | |
363 | spin_unlock_irq(&ehci->lock); | |
364 | } | |
365 | ||
56c1e26d DB |
366 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
367 | { | |
368 | unsigned port; | |
369 | ||
370 | if (!HCS_PPC (ehci->hcs_params)) | |
371 | return; | |
372 | ||
373 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
374 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
375 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
376 | is_on ? SetPortFeature : ClearPortFeature, | |
377 | USB_PORT_FEAT_POWER, | |
378 | port--, NULL, 0); | |
383975d7 AS |
379 | /* Flush those writes */ |
380 | ehci_readl(ehci, &ehci->regs->command); | |
56c1e26d DB |
381 | msleep(20); |
382 | } | |
383 | ||
7ff71d6a | 384 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 385 | |
7ff71d6a MP |
386 | /* |
387 | * ehci_work is called from some interrupts, timers, and so on. | |
388 | * it calls driver completion functions, after dropping ehci->lock. | |
389 | */ | |
7d12e780 | 390 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
391 | { |
392 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
7ff71d6a MP |
393 | |
394 | /* another CPU may drop ehci->lock during a schedule scan while | |
395 | * it reports urb completions. this flag guards against bogus | |
396 | * attempts at re-entrant schedule scanning. | |
397 | */ | |
398 | if (ehci->scanning) | |
399 | return; | |
400 | ehci->scanning = 1; | |
7d12e780 | 401 | scan_async (ehci); |
7ff71d6a | 402 | if (ehci->next_uframe != -1) |
7d12e780 | 403 | scan_periodic (ehci); |
7ff71d6a MP |
404 | ehci->scanning = 0; |
405 | ||
406 | /* the IO watchdog guards against hardware or driver bugs that | |
407 | * misplace IRQs, and should let us run completely without IRQs. | |
408 | * such lossage has been observed on both VT6202 and VT8235. | |
409 | */ | |
410 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && | |
411 | (ehci->async->qh_next.ptr != NULL || | |
412 | ehci->periodic_sched != 0)) | |
413 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
414 | } | |
1da177e4 | 415 | |
21da84a8 SS |
416 | /* |
417 | * Called when the ehci_hcd module is removed. | |
418 | */ | |
7ff71d6a | 419 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
420 | { |
421 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 422 | |
7ff71d6a | 423 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 424 | |
7ff71d6a MP |
425 | /* no more interrupts ... */ |
426 | del_timer_sync (&ehci->watchdog); | |
07d29b63 | 427 | del_timer_sync(&ehci->iaa_watchdog); |
56c1e26d | 428 | |
7ff71d6a MP |
429 | spin_lock_irq(&ehci->lock); |
430 | if (HC_IS_RUNNING (hcd->state)) | |
431 | ehci_quiesce (ehci); | |
1da177e4 | 432 | |
21da84a8 | 433 | ehci_silence_controller(ehci); |
7ff71d6a | 434 | ehci_reset (ehci); |
7ff71d6a | 435 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 436 | |
57e06c11 | 437 | remove_companion_file(ehci); |
7ff71d6a | 438 | remove_debug_files (ehci); |
1da177e4 | 439 | |
7ff71d6a MP |
440 | /* root hub is shut down separately (first, when possible) */ |
441 | spin_lock_irq (&ehci->lock); | |
442 | if (ehci->async) | |
7d12e780 | 443 | ehci_work (ehci); |
7ff71d6a MP |
444 | spin_unlock_irq (&ehci->lock); |
445 | ehci_mem_cleanup (ehci); | |
1da177e4 | 446 | |
7ff71d6a MP |
447 | #ifdef EHCI_STATS |
448 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
449 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
450 | ehci->stats.lost_iaa); | |
451 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
452 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 453 | #endif |
1da177e4 | 454 | |
083522d7 BH |
455 | dbg_status (ehci, "ehci_stop completed", |
456 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
457 | } |
458 | ||
18807521 DB |
459 | /* one-time init, only for memory state */ |
460 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 461 | { |
18807521 | 462 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 463 | u32 temp; |
1da177e4 LT |
464 | int retval; |
465 | u32 hcc_params; | |
18807521 DB |
466 | |
467 | spin_lock_init(&ehci->lock); | |
468 | ||
469 | init_timer(&ehci->watchdog); | |
470 | ehci->watchdog.function = ehci_watchdog; | |
471 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 | 472 | |
07d29b63 AS |
473 | init_timer(&ehci->iaa_watchdog); |
474 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; | |
475 | ehci->iaa_watchdog.data = (unsigned long) ehci; | |
476 | ||
1da177e4 LT |
477 | /* |
478 | * hw default: 1K periodic list heads, one per frame. | |
479 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
480 | */ | |
481 | ehci->periodic_size = DEFAULT_I_TDPS; | |
18807521 | 482 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
483 | return retval; |
484 | ||
485 | /* controllers may cache some of the periodic schedule ... */ | |
083522d7 | 486 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
53bd6a60 | 487 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
1da177e4 LT |
488 | ehci->i_thresh = 8; |
489 | else // N microframes cached | |
18807521 | 490 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 LT |
491 | |
492 | ehci->reclaim = NULL; | |
1da177e4 LT |
493 | ehci->next_uframe = -1; |
494 | ||
1da177e4 LT |
495 | /* |
496 | * dedicate a qh for the async ring head, since we couldn't unlink | |
497 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
498 | * as the 'reclamation list head' too. | |
499 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
500 | * from automatically advancing to the next td after short reads. | |
501 | */ | |
18807521 | 502 | ehci->async->qh_next.qh = NULL; |
6dbd682b SR |
503 | ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); |
504 | ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
505 | ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); | |
506 | ehci->async->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 507 | ehci->async->qh_state = QH_STATE_LINKED; |
6dbd682b | 508 | ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
509 | |
510 | /* clear interrupt enables, set irq latency */ | |
511 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
512 | log2_irq_thresh = 0; | |
513 | temp = 1 << (16 + log2_irq_thresh); | |
514 | if (HCC_CANPARK(hcc_params)) { | |
515 | /* HW default park == 3, on hardware that supports it (like | |
516 | * NVidia and ALI silicon), maximizes throughput on the async | |
517 | * schedule by avoiding QH fetches between transfers. | |
518 | * | |
519 | * With fast usb storage devices and NForce2, "park" seems to | |
520 | * make problems: throughput reduction (!), data errors... | |
521 | */ | |
522 | if (park) { | |
18807521 | 523 | park = min(park, (unsigned) 3); |
1da177e4 LT |
524 | temp |= CMD_PARK; |
525 | temp |= park << 8; | |
526 | } | |
18807521 | 527 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 528 | } |
18807521 | 529 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
530 | /* periodic schedule size can be smaller than default */ |
531 | temp &= ~(3 << 2); | |
532 | temp |= (EHCI_TUNE_FLS << 2); | |
533 | switch (EHCI_TUNE_FLS) { | |
534 | case 0: ehci->periodic_size = 1024; break; | |
535 | case 1: ehci->periodic_size = 512; break; | |
536 | case 2: ehci->periodic_size = 256; break; | |
18807521 | 537 | default: BUG(); |
1da177e4 LT |
538 | } |
539 | } | |
18807521 DB |
540 | ehci->command = temp; |
541 | ||
18807521 DB |
542 | return 0; |
543 | } | |
544 | ||
545 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
546 | static int ehci_run (struct usb_hcd *hcd) | |
547 | { | |
548 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
549 | int retval; | |
550 | u32 temp; | |
551 | u32 hcc_params; | |
552 | ||
1d619f12 MT |
553 | hcd->uses_new_polling = 1; |
554 | hcd->poll_rh = 0; | |
555 | ||
18807521 DB |
556 | /* EHCI spec section 4.1 */ |
557 | if ((retval = ehci_reset(ehci)) != 0) { | |
18807521 DB |
558 | ehci_mem_cleanup(ehci); |
559 | return retval; | |
560 | } | |
083522d7 BH |
561 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
562 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
563 | |
564 | /* | |
565 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
566 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
567 | * pci_pool consistent memory always uses segment zero. | |
568 | * streaming mappings for I/O buffers, like pci_map_single(), | |
569 | * can return segments above 4GB, if the device allows. | |
570 | * | |
571 | * NOTE: the dma mask is visible through dma_supported(), so | |
572 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
573 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
574 | * host side drivers though. | |
575 | */ | |
083522d7 | 576 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 577 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 578 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
579 | #if 0 |
580 | // this is deeply broken on almost all architectures | |
581 | if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK)) | |
582 | ehci_info(ehci, "enabled 64bit DMA\n"); | |
583 | #endif | |
584 | } | |
585 | ||
586 | ||
1da177e4 LT |
587 | // Philips, Intel, and maybe others need CMD_RUN before the |
588 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
589 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
590 | ehci->command |= CMD_RUN; | |
083522d7 | 591 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 592 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 593 | |
1da177e4 LT |
594 | /* |
595 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
596 | * are explicitly handed to companion controller(s), so no TT is | |
597 | * involved with the root hub. (Except where one is integrated, | |
598 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
599 | * |
600 | * Turning on the CF flag will transfer ownership of all ports | |
601 | * from the companions to the EHCI controller. If any of the | |
602 | * companions are in the middle of a port reset at the time, it | |
603 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
604 | * guarantees that no resets are in progress. After we set CF, |
605 | * a short delay lets the hardware catch up; new resets shouldn't | |
606 | * be started before the port switching actions could complete. | |
1da177e4 | 607 | */ |
32fe0198 | 608 | down_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 609 | hcd->state = HC_STATE_RUNNING; |
083522d7 BH |
610 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
611 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 612 | msleep(5); |
32fe0198 | 613 | up_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 614 | |
083522d7 | 615 | temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 616 | ehci_info (ehci, |
93f1a47c | 617 | "USB %x.%x started, EHCI %x.%02x, driver %s%s\n", |
7ff71d6a | 618 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
93f1a47c DB |
619 | temp >> 8, temp & 0xff, DRIVER_VERSION, |
620 | ignore_oc ? ", overcurrent ignored" : ""); | |
1da177e4 | 621 | |
083522d7 BH |
622 | ehci_writel(ehci, INTR_MASK, |
623 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 624 | |
18807521 DB |
625 | /* GRR this is run-once init(), being done every time the HC starts. |
626 | * So long as they're part of class devices, we can't do it init() | |
627 | * since the class device isn't created that early. | |
628 | */ | |
629 | create_debug_files(ehci); | |
57e06c11 | 630 | create_companion_file(ehci); |
1da177e4 LT |
631 | |
632 | return 0; | |
633 | } | |
634 | ||
1da177e4 LT |
635 | /*-------------------------------------------------------------------------*/ |
636 | ||
7d12e780 | 637 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
638 | { |
639 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
e82cc128 | 640 | u32 status, pcd_status = 0, cmd; |
1da177e4 LT |
641 | int bh; |
642 | ||
643 | spin_lock (&ehci->lock); | |
644 | ||
083522d7 | 645 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
646 | |
647 | /* e.g. cardbus physical eject */ | |
648 | if (status == ~(u32) 0) { | |
649 | ehci_dbg (ehci, "device removed\n"); | |
650 | goto dead; | |
651 | } | |
652 | ||
653 | status &= INTR_MASK; | |
654 | if (!status) { /* irq sharing? */ | |
655 | spin_unlock(&ehci->lock); | |
656 | return IRQ_NONE; | |
657 | } | |
658 | ||
659 | /* clear (just) interrupts */ | |
083522d7 | 660 | ehci_writel(ehci, status, &ehci->regs->status); |
e82cc128 | 661 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
662 | bh = 0; |
663 | ||
9776afc8 | 664 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
665 | /* unrequested/ignored: Frame List Rollover */ |
666 | dbg_status (ehci, "irq", status); | |
667 | #endif | |
668 | ||
669 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
670 | ||
671 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
672 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
673 | if (likely ((status & STS_ERR) == 0)) | |
674 | COUNT (ehci->stats.normal); | |
675 | else | |
676 | COUNT (ehci->stats.error); | |
677 | bh = 1; | |
678 | } | |
679 | ||
680 | /* complete the unlinking of some qh [4.15.2.3] */ | |
681 | if (status & STS_IAA) { | |
e82cc128 DB |
682 | /* guard against (alleged) silicon errata */ |
683 | if (cmd & CMD_IAAD) { | |
684 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
685 | &ehci->regs->command); | |
686 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); | |
687 | } | |
688 | if (ehci->reclaim) { | |
689 | COUNT(ehci->stats.reclaim); | |
690 | end_unlink_async(ehci); | |
691 | } else | |
692 | ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); | |
1da177e4 LT |
693 | } |
694 | ||
695 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 696 | if (status & STS_PCD) { |
1da177e4 | 697 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
d1b1842c DB |
698 | |
699 | /* kick root hub later */ | |
1d619f12 | 700 | pcd_status = status; |
1da177e4 LT |
701 | |
702 | /* resume root hub? */ | |
083522d7 | 703 | if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN)) |
8c03356a | 704 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
705 | |
706 | while (i--) { | |
083522d7 BH |
707 | int pstatus = ehci_readl(ehci, |
708 | &ehci->regs->port_status [i]); | |
b972b68c DB |
709 | |
710 | if (pstatus & PORT_OWNER) | |
1da177e4 | 711 | continue; |
b972b68c | 712 | if (!(pstatus & PORT_RESUME) |
1da177e4 LT |
713 | || ehci->reset_done [i] != 0) |
714 | continue; | |
715 | ||
716 | /* start 20 msec resume signaling from this port, | |
717 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
718 | * stop that signaling. | |
719 | */ | |
720 | ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); | |
1da177e4 | 721 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 722 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
723 | } |
724 | } | |
725 | ||
726 | /* PCI errors [4.15.2.4] */ | |
727 | if (unlikely ((status & STS_FATAL) != 0)) { | |
083522d7 BH |
728 | dbg_cmd (ehci, "fatal", ehci_readl(ehci, |
729 | &ehci->regs->command)); | |
1da177e4 LT |
730 | dbg_status (ehci, "fatal", status); |
731 | if (status & STS_HALT) { | |
732 | ehci_err (ehci, "fatal error\n"); | |
733 | dead: | |
734 | ehci_reset (ehci); | |
083522d7 | 735 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
1da177e4 LT |
736 | /* generic layer kills/unlinks all urbs, then |
737 | * uses ehci_stop to clean up the rest | |
738 | */ | |
739 | bh = 1; | |
740 | } | |
741 | } | |
742 | ||
743 | if (bh) | |
7d12e780 | 744 | ehci_work (ehci); |
1da177e4 | 745 | spin_unlock (&ehci->lock); |
d1b1842c | 746 | if (pcd_status) |
1d619f12 | 747 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
748 | return IRQ_HANDLED; |
749 | } | |
750 | ||
751 | /*-------------------------------------------------------------------------*/ | |
752 | ||
753 | /* | |
754 | * non-error returns are a promise to giveback() the urb later | |
755 | * we drop ownership so next owner (or urb unlink) can get it | |
756 | * | |
757 | * urb + dev is in hcd.self.controller.urb_list | |
758 | * we're queueing TDs onto software and hardware lists | |
759 | * | |
760 | * hcd-specific init for hcpriv hasn't been done yet | |
761 | * | |
762 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
763 | * to a (possibly active) QH, and the same QH scanning code. | |
764 | */ | |
765 | static int ehci_urb_enqueue ( | |
766 | struct usb_hcd *hcd, | |
1da177e4 | 767 | struct urb *urb, |
55016f10 | 768 | gfp_t mem_flags |
1da177e4 LT |
769 | ) { |
770 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
771 | struct list_head qtd_list; | |
772 | ||
773 | INIT_LIST_HEAD (&qtd_list); | |
774 | ||
775 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
776 | case PIPE_CONTROL: |
777 | /* qh_completions() code doesn't handle all the fault cases | |
778 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
779 | */ | |
780 | if (urb->transfer_buffer_length > (16 * 1024)) | |
781 | return -EMSGSIZE; | |
782 | /* FALLTHROUGH */ | |
783 | /* case PIPE_BULK: */ | |
1da177e4 LT |
784 | default: |
785 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
786 | return -ENOMEM; | |
e9df41c5 | 787 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
788 | |
789 | case PIPE_INTERRUPT: | |
790 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
791 | return -ENOMEM; | |
e9df41c5 | 792 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
793 | |
794 | case PIPE_ISOCHRONOUS: | |
795 | if (urb->dev->speed == USB_SPEED_HIGH) | |
796 | return itd_submit (ehci, urb, mem_flags); | |
797 | else | |
798 | return sitd_submit (ehci, urb, mem_flags); | |
799 | } | |
800 | } | |
801 | ||
802 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
803 | { | |
07d29b63 | 804 | /* failfast */ |
e82cc128 | 805 | if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) |
07d29b63 AS |
806 | end_unlink_async(ehci); |
807 | ||
808 | /* if it's not linked then there's nothing to do */ | |
809 | if (qh->qh_state != QH_STATE_LINKED) | |
810 | ; | |
811 | ||
812 | /* defer till later if busy */ | |
813 | else if (ehci->reclaim) { | |
1da177e4 LT |
814 | struct ehci_qh *last; |
815 | ||
816 | for (last = ehci->reclaim; | |
817 | last->reclaim; | |
818 | last = last->reclaim) | |
819 | continue; | |
820 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
821 | last->reclaim = qh; | |
822 | ||
07d29b63 AS |
823 | /* start IAA cycle */ |
824 | } else | |
1da177e4 LT |
825 | start_unlink_async (ehci, qh); |
826 | } | |
827 | ||
828 | /* remove from hardware lists | |
829 | * completions normally happen asynchronously | |
830 | */ | |
831 | ||
e9df41c5 | 832 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
833 | { |
834 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
835 | struct ehci_qh *qh; | |
836 | unsigned long flags; | |
e9df41c5 | 837 | int rc; |
1da177e4 LT |
838 | |
839 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
840 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
841 | if (rc) | |
842 | goto done; | |
843 | ||
1da177e4 LT |
844 | switch (usb_pipetype (urb->pipe)) { |
845 | // case PIPE_CONTROL: | |
846 | // case PIPE_BULK: | |
847 | default: | |
848 | qh = (struct ehci_qh *) urb->hcpriv; | |
849 | if (!qh) | |
850 | break; | |
07d29b63 AS |
851 | switch (qh->qh_state) { |
852 | case QH_STATE_LINKED: | |
853 | case QH_STATE_COMPLETING: | |
854 | unlink_async(ehci, qh); | |
855 | break; | |
856 | case QH_STATE_UNLINK: | |
857 | case QH_STATE_UNLINK_WAIT: | |
858 | /* already started */ | |
859 | break; | |
860 | case QH_STATE_IDLE: | |
861 | WARN_ON(1); | |
862 | break; | |
863 | } | |
1da177e4 LT |
864 | break; |
865 | ||
866 | case PIPE_INTERRUPT: | |
867 | qh = (struct ehci_qh *) urb->hcpriv; | |
868 | if (!qh) | |
869 | break; | |
870 | switch (qh->qh_state) { | |
871 | case QH_STATE_LINKED: | |
872 | intr_deschedule (ehci, qh); | |
873 | /* FALL THROUGH */ | |
874 | case QH_STATE_IDLE: | |
7d12e780 | 875 | qh_completions (ehci, qh); |
1da177e4 LT |
876 | break; |
877 | default: | |
878 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
879 | qh, qh->qh_state); | |
880 | goto done; | |
881 | } | |
882 | ||
883 | /* reschedule QH iff another request is queued */ | |
884 | if (!list_empty (&qh->qtd_list) | |
885 | && HC_IS_RUNNING (hcd->state)) { | |
e1a49142 DB |
886 | rc = qh_schedule(ehci, qh); |
887 | ||
888 | /* An error here likely indicates handshake failure | |
889 | * or no space left in the schedule. Neither fault | |
890 | * should happen often ... | |
891 | * | |
892 | * FIXME kill the now-dysfunctional queued urbs | |
893 | */ | |
894 | if (rc != 0) | |
895 | ehci_err(ehci, | |
896 | "can't reschedule qh %p, err %d", | |
897 | qh, rc); | |
1da177e4 LT |
898 | } |
899 | break; | |
900 | ||
901 | case PIPE_ISOCHRONOUS: | |
902 | // itd or sitd ... | |
903 | ||
904 | // wait till next completion, do it then. | |
905 | // completion irqs can wait up to 1024 msec, | |
906 | break; | |
907 | } | |
908 | done: | |
909 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 910 | return rc; |
1da177e4 LT |
911 | } |
912 | ||
913 | /*-------------------------------------------------------------------------*/ | |
914 | ||
915 | // bulk qh holds the data toggle | |
916 | ||
917 | static void | |
918 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
919 | { | |
920 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
921 | unsigned long flags; | |
922 | struct ehci_qh *qh, *tmp; | |
923 | ||
924 | /* ASSERT: any requests/urbs are being unlinked */ | |
925 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
926 | ||
927 | rescan: | |
928 | spin_lock_irqsave (&ehci->lock, flags); | |
929 | qh = ep->hcpriv; | |
930 | if (!qh) | |
931 | goto done; | |
932 | ||
933 | /* endpoints can be iso streams. for now, we don't | |
934 | * accelerate iso completions ... so spin a while. | |
935 | */ | |
936 | if (qh->hw_info1 == 0) { | |
937 | ehci_vdbg (ehci, "iso delay\n"); | |
938 | goto idle_timeout; | |
939 | } | |
940 | ||
941 | if (!HC_IS_RUNNING (hcd->state)) | |
942 | qh->qh_state = QH_STATE_IDLE; | |
943 | switch (qh->qh_state) { | |
944 | case QH_STATE_LINKED: | |
945 | for (tmp = ehci->async->qh_next.qh; | |
946 | tmp && tmp != qh; | |
947 | tmp = tmp->qh_next.qh) | |
948 | continue; | |
949 | /* periodic qh self-unlinks on empty */ | |
950 | if (!tmp) | |
951 | goto nogood; | |
952 | unlink_async (ehci, qh); | |
953 | /* FALL THROUGH */ | |
954 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
07d29b63 | 955 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
956 | idle_timeout: |
957 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 958 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
959 | goto rescan; |
960 | case QH_STATE_IDLE: /* fully unlinked */ | |
961 | if (list_empty (&qh->qtd_list)) { | |
962 | qh_put (qh); | |
963 | break; | |
964 | } | |
965 | /* else FALL THROUGH */ | |
966 | default: | |
967 | nogood: | |
968 | /* caller was supposed to have unlinked any requests; | |
969 | * that's not our job. just leak this memory. | |
970 | */ | |
971 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
972 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
973 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
974 | break; | |
975 | } | |
976 | ep->hcpriv = NULL; | |
977 | done: | |
978 | spin_unlock_irqrestore (&ehci->lock, flags); | |
979 | return; | |
980 | } | |
981 | ||
7ff71d6a MP |
982 | static int ehci_get_frame (struct usb_hcd *hcd) |
983 | { | |
984 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
083522d7 BH |
985 | return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % |
986 | ehci->periodic_size; | |
7ff71d6a | 987 | } |
1da177e4 LT |
988 | |
989 | /*-------------------------------------------------------------------------*/ | |
990 | ||
1da177e4 LT |
991 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC |
992 | ||
993 | MODULE_DESCRIPTION (DRIVER_INFO); | |
994 | MODULE_AUTHOR (DRIVER_AUTHOR); | |
995 | MODULE_LICENSE ("GPL"); | |
996 | ||
7ff71d6a MP |
997 | #ifdef CONFIG_PCI |
998 | #include "ehci-pci.c" | |
01cced25 | 999 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 1000 | #endif |
1da177e4 | 1001 | |
ba02978a | 1002 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 1003 | #include "ehci-fsl.c" |
01cced25 | 1004 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
1005 | #endif |
1006 | ||
dfbaa7d8 | 1007 | #ifdef CONFIG_SOC_AU1200 |
76fa9a24 | 1008 | #include "ehci-au1xxx.c" |
01cced25 | 1009 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1010 | #endif |
1011 | ||
ad75a410 GL |
1012 | #ifdef CONFIG_PPC_PS3 |
1013 | #include "ehci-ps3.c" | |
7a4eb7fd | 1014 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1015 | #endif |
1016 | ||
da0e8fb0 | 1017 | #if defined(CONFIG_440EPX) && !defined(CONFIG_PPC_MERGE) |
fc65a15f SR |
1018 | #include "ehci-ppc-soc.c" |
1019 | #define PLATFORM_DRIVER ehci_ppc_soc_driver | |
1020 | #endif | |
1021 | ||
da0e8fb0 VB |
1022 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1023 | #include "ehci-ppc-of.c" | |
1024 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1025 | #endif | |
1026 | ||
705a7521 | 1027 | #ifdef CONFIG_PLAT_ORION |
e96ffe2f TP |
1028 | #include "ehci-orion.c" |
1029 | #define PLATFORM_DRIVER ehci_orion_driver | |
1030 | #endif | |
1031 | ||
91bc4d31 VB |
1032 | #ifdef CONFIG_ARCH_IXP4XX |
1033 | #include "ehci-ixp4xx.c" | |
1034 | #define PLATFORM_DRIVER ixp4xx_ehci_driver | |
1035 | #endif | |
1036 | ||
ad75a410 | 1037 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
c6dd2e61 | 1038 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) |
7ff71d6a MP |
1039 | #error "missing bus glue for ehci-hcd" |
1040 | #endif | |
01cced25 KG |
1041 | |
1042 | static int __init ehci_hcd_init(void) | |
1043 | { | |
1044 | int retval = 0; | |
1045 | ||
1046 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", | |
1047 | hcd_name, | |
1048 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1049 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1050 | ||
694cc208 TJ |
1051 | #ifdef DEBUG |
1052 | ehci_debug_root = debugfs_create_dir("ehci", NULL); | |
1053 | if (!ehci_debug_root) | |
1054 | return -ENOENT; | |
1055 | #endif | |
1056 | ||
01cced25 KG |
1057 | #ifdef PLATFORM_DRIVER |
1058 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1059 | if (retval < 0) |
1060 | goto clean0; | |
01cced25 KG |
1061 | #endif |
1062 | ||
1063 | #ifdef PCI_DRIVER | |
1064 | retval = pci_register_driver(&PCI_DRIVER); | |
da0e8fb0 VB |
1065 | if (retval < 0) |
1066 | goto clean1; | |
ad75a410 GL |
1067 | #endif |
1068 | ||
1069 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
7a4eb7fd | 1070 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1071 | if (retval < 0) |
1072 | goto clean2; | |
694cc208 | 1073 | #endif |
da0e8fb0 VB |
1074 | |
1075 | #ifdef OF_PLATFORM_DRIVER | |
1076 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
1077 | if (retval < 0) | |
1078 | goto clean3; | |
1079 | #endif | |
1080 | return retval; | |
1081 | ||
1082 | #ifdef OF_PLATFORM_DRIVER | |
1083 | /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */ | |
1084 | clean3: | |
1085 | #endif | |
1086 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1087 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1088 | clean2: | |
ad75a410 GL |
1089 | #endif |
1090 | #ifdef PCI_DRIVER | |
da0e8fb0 VB |
1091 | pci_unregister_driver(&PCI_DRIVER); |
1092 | clean1: | |
ad75a410 | 1093 | #endif |
da0e8fb0 VB |
1094 | #ifdef PLATFORM_DRIVER |
1095 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1096 | clean0: | |
1097 | #endif | |
1098 | #ifdef DEBUG | |
1099 | debugfs_remove(ehci_debug_root); | |
1100 | ehci_debug_root = NULL; | |
01cced25 | 1101 | #endif |
01cced25 KG |
1102 | return retval; |
1103 | } | |
1104 | module_init(ehci_hcd_init); | |
1105 | ||
1106 | static void __exit ehci_hcd_cleanup(void) | |
1107 | { | |
da0e8fb0 VB |
1108 | #ifdef OF_PLATFORM_DRIVER |
1109 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
1110 | #endif | |
01cced25 KG |
1111 | #ifdef PLATFORM_DRIVER |
1112 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1113 | #endif | |
1114 | #ifdef PCI_DRIVER | |
1115 | pci_unregister_driver(&PCI_DRIVER); | |
1116 | #endif | |
ad75a410 | 1117 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1118 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1119 | #endif |
694cc208 TJ |
1120 | #ifdef DEBUG |
1121 | debugfs_remove(ehci_debug_root); | |
1122 | #endif | |
01cced25 KG |
1123 | } |
1124 | module_exit(ehci_hcd_cleanup); | |
1125 |