Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2000-2004 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/dmapool.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/slab.h> | |
1da177e4 LT |
27 | #include <linux/errno.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/timer.h> | |
30 | #include <linux/list.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/reboot.h> | |
33 | #include <linux/usb.h> | |
34 | #include <linux/moduleparam.h> | |
35 | #include <linux/dma-mapping.h> | |
694cc208 | 36 | #include <linux/debugfs.h> |
1da177e4 LT |
37 | |
38 | #include "../core/hcd.h" | |
39 | ||
40 | #include <asm/byteorder.h> | |
41 | #include <asm/io.h> | |
42 | #include <asm/irq.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/unaligned.h> | |
1da177e4 LT |
45 | |
46 | /*-------------------------------------------------------------------------*/ | |
47 | ||
48 | /* | |
49 | * EHCI hc_driver implementation ... experimental, incomplete. | |
50 | * Based on the final 1.0 register interface specification. | |
51 | * | |
52 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
53 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
54 | * Next comes "CardBay", using USB 2.0 signals. | |
55 | * | |
56 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
57 | * Special thanks to Intel and VIA for providing host controllers to | |
58 | * test this driver on, and Cypress (including In-System Design) for | |
59 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
60 | */ |
61 | ||
62 | #define DRIVER_VERSION "10 Dec 2004" | |
63 | #define DRIVER_AUTHOR "David Brownell" | |
64 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
65 | ||
66 | static const char hcd_name [] = "ehci_hcd"; | |
67 | ||
68 | ||
9776afc8 | 69 | #undef VERBOSE_DEBUG |
1da177e4 LT |
70 | #undef EHCI_URB_TRACE |
71 | ||
72 | #ifdef DEBUG | |
73 | #define EHCI_STATS | |
74 | #endif | |
75 | ||
76 | /* magic numbers that can affect system performance */ | |
77 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
78 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
79 | #define EHCI_TUNE_RL_TT 0 | |
80 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
81 | #define EHCI_TUNE_MULT_TT 1 | |
82 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
83 | ||
07d29b63 | 84 | #define EHCI_IAA_MSECS 10 /* arbitrary */ |
1da177e4 LT |
85 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
86 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
87 | #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ | |
88 | ||
89 | /* Initial IRQ latency: faster than hw default */ | |
90 | static int log2_irq_thresh = 0; // 0 to 6 | |
91 | module_param (log2_irq_thresh, int, S_IRUGO); | |
92 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
93 | ||
94 | /* initial park setting: slower than hw default */ | |
95 | static unsigned park = 0; | |
96 | module_param (park, uint, S_IRUGO); | |
97 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
98 | ||
93f1a47c DB |
99 | /* for flakey hardware, ignore overcurrent indicators */ |
100 | static int ignore_oc = 0; | |
101 | module_param (ignore_oc, bool, S_IRUGO); | |
102 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
103 | ||
1da177e4 LT |
104 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
105 | ||
106 | /*-------------------------------------------------------------------------*/ | |
107 | ||
108 | #include "ehci.h" | |
109 | #include "ehci-dbg.c" | |
110 | ||
111 | /*-------------------------------------------------------------------------*/ | |
112 | ||
113 | /* | |
114 | * handshake - spin reading hc until handshake completes or fails | |
115 | * @ptr: address of hc register to be read | |
116 | * @mask: bits to look at in result of read | |
117 | * @done: value of those bits when handshake succeeds | |
118 | * @usec: timeout in microseconds | |
119 | * | |
120 | * Returns negative errno, or zero on success | |
121 | * | |
122 | * Success happens when the "mask" bits have the specified value (hardware | |
123 | * handshake done). There are two failure modes: "usec" have passed (major | |
124 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
125 | * | |
126 | * That last failure should_only happen in cases like physical cardbus eject | |
127 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
128 | * bridge shutdown: shutting down the bridge before the devices using it. | |
129 | */ | |
083522d7 BH |
130 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
131 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
132 | { |
133 | u32 result; | |
134 | ||
135 | do { | |
083522d7 | 136 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
137 | if (result == ~(u32)0) /* card removed */ |
138 | return -ENODEV; | |
139 | result &= mask; | |
140 | if (result == done) | |
141 | return 0; | |
142 | udelay (1); | |
143 | usec--; | |
144 | } while (usec > 0); | |
145 | return -ETIMEDOUT; | |
146 | } | |
147 | ||
c765d4ca KW |
148 | static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, |
149 | u32 mask, u32 done, int usec) | |
150 | { | |
151 | int error = handshake(ehci, ptr, mask, done, usec); | |
152 | if (error) | |
153 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; | |
154 | ||
155 | return error; | |
156 | } | |
157 | ||
1da177e4 LT |
158 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ |
159 | static int ehci_halt (struct ehci_hcd *ehci) | |
160 | { | |
083522d7 | 161 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 162 | |
72f30b6f | 163 | /* disable any irqs left enabled by previous code */ |
083522d7 | 164 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 165 | |
1da177e4 LT |
166 | if ((temp & STS_HALT) != 0) |
167 | return 0; | |
168 | ||
083522d7 | 169 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 170 | temp &= ~CMD_RUN; |
083522d7 BH |
171 | ehci_writel(ehci, temp, &ehci->regs->command); |
172 | return handshake (ehci, &ehci->regs->status, | |
173 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
174 | } |
175 | ||
176 | /* put TDI/ARC silicon into EHCI mode */ | |
177 | static void tdi_reset (struct ehci_hcd *ehci) | |
178 | { | |
179 | u32 __iomem *reg_ptr; | |
180 | u32 tmp; | |
181 | ||
d23a1377 | 182 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); |
083522d7 | 183 | tmp = ehci_readl(ehci, reg_ptr); |
d23a1377 VB |
184 | tmp |= USBMODE_CM_HC; |
185 | /* The default byte access to MMR space is LE after | |
186 | * controller reset. Set the required endian mode | |
187 | * for transfer buffers to match the host microprocessor | |
188 | */ | |
189 | if (ehci_big_endian_mmio(ehci)) | |
190 | tmp |= USBMODE_BE; | |
083522d7 | 191 | ehci_writel(ehci, tmp, reg_ptr); |
1da177e4 LT |
192 | } |
193 | ||
194 | /* reset a non-running (STS_HALT == 1) controller */ | |
195 | static int ehci_reset (struct ehci_hcd *ehci) | |
196 | { | |
197 | int retval; | |
083522d7 | 198 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
199 | |
200 | command |= CMD_RESET; | |
201 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 202 | ehci_writel(ehci, command, &ehci->regs->command); |
1da177e4 LT |
203 | ehci_to_hcd(ehci)->state = HC_STATE_HALT; |
204 | ehci->next_statechange = jiffies; | |
083522d7 BH |
205 | retval = handshake (ehci, &ehci->regs->command, |
206 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 LT |
207 | |
208 | if (retval) | |
209 | return retval; | |
210 | ||
211 | if (ehci_is_TDI(ehci)) | |
212 | tdi_reset (ehci); | |
213 | ||
214 | return retval; | |
215 | } | |
216 | ||
217 | /* idle the controller (from running) */ | |
218 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
219 | { | |
220 | u32 temp; | |
221 | ||
222 | #ifdef DEBUG | |
223 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) | |
224 | BUG (); | |
225 | #endif | |
226 | ||
227 | /* wait for any schedule enables/disables to take effect */ | |
083522d7 | 228 | temp = ehci_readl(ehci, &ehci->regs->command) << 10; |
1da177e4 | 229 | temp &= STS_ASS | STS_PSS; |
c765d4ca KW |
230 | if (handshake_on_error_set_halt(ehci, &ehci->regs->status, |
231 | STS_ASS | STS_PSS, temp, 16 * 125)) | |
1da177e4 | 232 | return; |
1da177e4 LT |
233 | |
234 | /* then disable anything that's still active */ | |
083522d7 | 235 | temp = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 236 | temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); |
083522d7 | 237 | ehci_writel(ehci, temp, &ehci->regs->command); |
1da177e4 LT |
238 | |
239 | /* hardware can take 16 microframes to turn off ... */ | |
c765d4ca KW |
240 | handshake_on_error_set_halt(ehci, &ehci->regs->status, |
241 | STS_ASS | STS_PSS, 0, 16 * 125); | |
1da177e4 LT |
242 | } |
243 | ||
244 | /*-------------------------------------------------------------------------*/ | |
245 | ||
07d29b63 | 246 | static void end_unlink_async(struct ehci_hcd *ehci); |
7d12e780 | 247 | static void ehci_work(struct ehci_hcd *ehci); |
1da177e4 LT |
248 | |
249 | #include "ehci-hub.c" | |
250 | #include "ehci-mem.c" | |
251 | #include "ehci-q.c" | |
252 | #include "ehci-sched.c" | |
253 | ||
254 | /*-------------------------------------------------------------------------*/ | |
255 | ||
07d29b63 | 256 | static void ehci_iaa_watchdog(unsigned long param) |
1da177e4 LT |
257 | { |
258 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
259 | unsigned long flags; | |
260 | ||
261 | spin_lock_irqsave (&ehci->lock, flags); | |
262 | ||
e82cc128 DB |
263 | /* Lost IAA irqs wedge things badly; seen first with a vt8235. |
264 | * So we need this watchdog, but must protect it against both | |
265 | * (a) SMP races against real IAA firing and retriggering, and | |
266 | * (b) clean HC shutdown, when IAA watchdog was pending. | |
267 | */ | |
268 | if (ehci->reclaim | |
269 | && !timer_pending(&ehci->iaa_watchdog) | |
270 | && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { | |
271 | u32 cmd, status; | |
272 | ||
273 | /* If we get here, IAA is *REALLY* late. It's barely | |
274 | * conceivable that the system is so busy that CMD_IAAD | |
275 | * is still legitimately set, so let's be sure it's | |
276 | * clear before we read STS_IAA. (The HC should clear | |
277 | * CMD_IAAD when it sets STS_IAA.) | |
278 | */ | |
279 | cmd = ehci_readl(ehci, &ehci->regs->command); | |
280 | if (cmd & CMD_IAAD) | |
281 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
282 | &ehci->regs->command); | |
283 | ||
284 | /* If IAA is set here it either legitimately triggered | |
285 | * before we cleared IAAD above (but _way_ late, so we'll | |
286 | * still count it as lost) ... or a silicon erratum: | |
287 | * - VIA seems to set IAA without triggering the IRQ; | |
288 | * - IAAD potentially cleared without setting IAA. | |
289 | */ | |
290 | status = ehci_readl(ehci, &ehci->regs->status); | |
291 | if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { | |
1da177e4 | 292 | COUNT (ehci->stats.lost_iaa); |
083522d7 | 293 | ehci_writel(ehci, STS_IAA, &ehci->regs->status); |
1da177e4 | 294 | } |
e82cc128 DB |
295 | |
296 | ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", | |
297 | status, cmd); | |
07d29b63 | 298 | end_unlink_async(ehci); |
1da177e4 LT |
299 | } |
300 | ||
07d29b63 AS |
301 | spin_unlock_irqrestore(&ehci->lock, flags); |
302 | } | |
303 | ||
304 | static void ehci_watchdog(unsigned long param) | |
305 | { | |
306 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
307 | unsigned long flags; | |
308 | ||
309 | spin_lock_irqsave(&ehci->lock, flags); | |
310 | ||
311 | /* stop async processing after it's idled a bit */ | |
1da177e4 | 312 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) |
26f953fd | 313 | start_unlink_async (ehci, ehci->async); |
1da177e4 LT |
314 | |
315 | /* ehci could run by timer, without IRQs ... */ | |
7d12e780 | 316 | ehci_work (ehci); |
1da177e4 LT |
317 | |
318 | spin_unlock_irqrestore (&ehci->lock, flags); | |
319 | } | |
320 | ||
8903795a AS |
321 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
322 | * The firmware seems to think that powering off is a wakeup event! | |
323 | * This routine turns off remote wakeup and everything else, on all ports. | |
324 | */ | |
325 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
326 | { | |
327 | int port = HCS_N_PORTS(ehci->hcs_params); | |
328 | ||
329 | while (port--) | |
330 | ehci_writel(ehci, PORT_RWC_BITS, | |
331 | &ehci->regs->port_status[port]); | |
332 | } | |
333 | ||
64a21d02 | 334 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
72f30b6f DB |
335 | * This forcibly disables dma and IRQs, helping kexec and other cases |
336 | * where the next system software may expect clean state. | |
337 | */ | |
64a21d02 AG |
338 | static void |
339 | ehci_shutdown (struct usb_hcd *hcd) | |
1da177e4 | 340 | { |
64a21d02 | 341 | struct ehci_hcd *ehci; |
1da177e4 | 342 | |
64a21d02 | 343 | ehci = hcd_to_ehci (hcd); |
72f30b6f | 344 | (void) ehci_halt (ehci); |
8903795a | 345 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
346 | |
347 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 348 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
349 | |
350 | /* unblock posted writes */ | |
351 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
352 | } |
353 | ||
56c1e26d DB |
354 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
355 | { | |
356 | unsigned port; | |
357 | ||
358 | if (!HCS_PPC (ehci->hcs_params)) | |
359 | return; | |
360 | ||
361 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
362 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
363 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
364 | is_on ? SetPortFeature : ClearPortFeature, | |
365 | USB_PORT_FEAT_POWER, | |
366 | port--, NULL, 0); | |
383975d7 AS |
367 | /* Flush those writes */ |
368 | ehci_readl(ehci, &ehci->regs->command); | |
56c1e26d DB |
369 | msleep(20); |
370 | } | |
371 | ||
7ff71d6a | 372 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 373 | |
7ff71d6a MP |
374 | /* |
375 | * ehci_work is called from some interrupts, timers, and so on. | |
376 | * it calls driver completion functions, after dropping ehci->lock. | |
377 | */ | |
7d12e780 | 378 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
379 | { |
380 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
7ff71d6a MP |
381 | |
382 | /* another CPU may drop ehci->lock during a schedule scan while | |
383 | * it reports urb completions. this flag guards against bogus | |
384 | * attempts at re-entrant schedule scanning. | |
385 | */ | |
386 | if (ehci->scanning) | |
387 | return; | |
388 | ehci->scanning = 1; | |
7d12e780 | 389 | scan_async (ehci); |
7ff71d6a | 390 | if (ehci->next_uframe != -1) |
7d12e780 | 391 | scan_periodic (ehci); |
7ff71d6a MP |
392 | ehci->scanning = 0; |
393 | ||
394 | /* the IO watchdog guards against hardware or driver bugs that | |
395 | * misplace IRQs, and should let us run completely without IRQs. | |
396 | * such lossage has been observed on both VT6202 and VT8235. | |
397 | */ | |
398 | if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && | |
399 | (ehci->async->qh_next.ptr != NULL || | |
400 | ehci->periodic_sched != 0)) | |
401 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
402 | } | |
1da177e4 | 403 | |
7ff71d6a | 404 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
405 | { |
406 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 407 | |
7ff71d6a | 408 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 409 | |
7ff71d6a MP |
410 | /* Turn off port power on all root hub ports. */ |
411 | ehci_port_power (ehci, 0); | |
1da177e4 | 412 | |
7ff71d6a MP |
413 | /* no more interrupts ... */ |
414 | del_timer_sync (&ehci->watchdog); | |
07d29b63 | 415 | del_timer_sync(&ehci->iaa_watchdog); |
56c1e26d | 416 | |
7ff71d6a MP |
417 | spin_lock_irq(&ehci->lock); |
418 | if (HC_IS_RUNNING (hcd->state)) | |
419 | ehci_quiesce (ehci); | |
1da177e4 | 420 | |
7ff71d6a | 421 | ehci_reset (ehci); |
083522d7 | 422 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
7ff71d6a | 423 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 424 | |
7ff71d6a | 425 | /* let companion controllers work when we aren't */ |
083522d7 | 426 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
56c1e26d | 427 | |
57e06c11 | 428 | remove_companion_file(ehci); |
7ff71d6a | 429 | remove_debug_files (ehci); |
1da177e4 | 430 | |
7ff71d6a MP |
431 | /* root hub is shut down separately (first, when possible) */ |
432 | spin_lock_irq (&ehci->lock); | |
433 | if (ehci->async) | |
7d12e780 | 434 | ehci_work (ehci); |
7ff71d6a MP |
435 | spin_unlock_irq (&ehci->lock); |
436 | ehci_mem_cleanup (ehci); | |
1da177e4 | 437 | |
7ff71d6a MP |
438 | #ifdef EHCI_STATS |
439 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
440 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
441 | ehci->stats.lost_iaa); | |
442 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
443 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 444 | #endif |
1da177e4 | 445 | |
083522d7 BH |
446 | dbg_status (ehci, "ehci_stop completed", |
447 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
448 | } |
449 | ||
18807521 DB |
450 | /* one-time init, only for memory state */ |
451 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 452 | { |
18807521 | 453 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 454 | u32 temp; |
1da177e4 LT |
455 | int retval; |
456 | u32 hcc_params; | |
18807521 DB |
457 | |
458 | spin_lock_init(&ehci->lock); | |
459 | ||
460 | init_timer(&ehci->watchdog); | |
461 | ehci->watchdog.function = ehci_watchdog; | |
462 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 | 463 | |
07d29b63 AS |
464 | init_timer(&ehci->iaa_watchdog); |
465 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; | |
466 | ehci->iaa_watchdog.data = (unsigned long) ehci; | |
467 | ||
1da177e4 LT |
468 | /* |
469 | * hw default: 1K periodic list heads, one per frame. | |
470 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
471 | */ | |
472 | ehci->periodic_size = DEFAULT_I_TDPS; | |
18807521 | 473 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
474 | return retval; |
475 | ||
476 | /* controllers may cache some of the periodic schedule ... */ | |
083522d7 | 477 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
53bd6a60 | 478 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
1da177e4 LT |
479 | ehci->i_thresh = 8; |
480 | else // N microframes cached | |
18807521 | 481 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 LT |
482 | |
483 | ehci->reclaim = NULL; | |
1da177e4 LT |
484 | ehci->next_uframe = -1; |
485 | ||
1da177e4 LT |
486 | /* |
487 | * dedicate a qh for the async ring head, since we couldn't unlink | |
488 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
489 | * as the 'reclamation list head' too. | |
490 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
491 | * from automatically advancing to the next td after short reads. | |
492 | */ | |
18807521 | 493 | ehci->async->qh_next.qh = NULL; |
6dbd682b SR |
494 | ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); |
495 | ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
496 | ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); | |
497 | ehci->async->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 498 | ehci->async->qh_state = QH_STATE_LINKED; |
6dbd682b | 499 | ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
500 | |
501 | /* clear interrupt enables, set irq latency */ | |
502 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
503 | log2_irq_thresh = 0; | |
504 | temp = 1 << (16 + log2_irq_thresh); | |
505 | if (HCC_CANPARK(hcc_params)) { | |
506 | /* HW default park == 3, on hardware that supports it (like | |
507 | * NVidia and ALI silicon), maximizes throughput on the async | |
508 | * schedule by avoiding QH fetches between transfers. | |
509 | * | |
510 | * With fast usb storage devices and NForce2, "park" seems to | |
511 | * make problems: throughput reduction (!), data errors... | |
512 | */ | |
513 | if (park) { | |
18807521 | 514 | park = min(park, (unsigned) 3); |
1da177e4 LT |
515 | temp |= CMD_PARK; |
516 | temp |= park << 8; | |
517 | } | |
18807521 | 518 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 519 | } |
18807521 | 520 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
521 | /* periodic schedule size can be smaller than default */ |
522 | temp &= ~(3 << 2); | |
523 | temp |= (EHCI_TUNE_FLS << 2); | |
524 | switch (EHCI_TUNE_FLS) { | |
525 | case 0: ehci->periodic_size = 1024; break; | |
526 | case 1: ehci->periodic_size = 512; break; | |
527 | case 2: ehci->periodic_size = 256; break; | |
18807521 | 528 | default: BUG(); |
1da177e4 LT |
529 | } |
530 | } | |
18807521 DB |
531 | ehci->command = temp; |
532 | ||
18807521 DB |
533 | return 0; |
534 | } | |
535 | ||
536 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
537 | static int ehci_run (struct usb_hcd *hcd) | |
538 | { | |
539 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
540 | int retval; | |
541 | u32 temp; | |
542 | u32 hcc_params; | |
543 | ||
1d619f12 MT |
544 | hcd->uses_new_polling = 1; |
545 | hcd->poll_rh = 0; | |
546 | ||
18807521 DB |
547 | /* EHCI spec section 4.1 */ |
548 | if ((retval = ehci_reset(ehci)) != 0) { | |
18807521 DB |
549 | ehci_mem_cleanup(ehci); |
550 | return retval; | |
551 | } | |
083522d7 BH |
552 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
553 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
554 | |
555 | /* | |
556 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
557 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
558 | * pci_pool consistent memory always uses segment zero. | |
559 | * streaming mappings for I/O buffers, like pci_map_single(), | |
560 | * can return segments above 4GB, if the device allows. | |
561 | * | |
562 | * NOTE: the dma mask is visible through dma_supported(), so | |
563 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
564 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
565 | * host side drivers though. | |
566 | */ | |
083522d7 | 567 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 568 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 569 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
570 | #if 0 |
571 | // this is deeply broken on almost all architectures | |
572 | if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK)) | |
573 | ehci_info(ehci, "enabled 64bit DMA\n"); | |
574 | #endif | |
575 | } | |
576 | ||
577 | ||
1da177e4 LT |
578 | // Philips, Intel, and maybe others need CMD_RUN before the |
579 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
580 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
581 | ehci->command |= CMD_RUN; | |
083522d7 | 582 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 583 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 584 | |
1da177e4 LT |
585 | /* |
586 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
587 | * are explicitly handed to companion controller(s), so no TT is | |
588 | * involved with the root hub. (Except where one is integrated, | |
589 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
590 | * |
591 | * Turning on the CF flag will transfer ownership of all ports | |
592 | * from the companions to the EHCI controller. If any of the | |
593 | * companions are in the middle of a port reset at the time, it | |
594 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
595 | * guarantees that no resets are in progress. After we set CF, |
596 | * a short delay lets the hardware catch up; new resets shouldn't | |
597 | * be started before the port switching actions could complete. | |
1da177e4 | 598 | */ |
32fe0198 | 599 | down_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 600 | hcd->state = HC_STATE_RUNNING; |
083522d7 BH |
601 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
602 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 603 | msleep(5); |
32fe0198 | 604 | up_write(&ehci_cf_port_reset_rwsem); |
1da177e4 | 605 | |
083522d7 | 606 | temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 607 | ehci_info (ehci, |
93f1a47c | 608 | "USB %x.%x started, EHCI %x.%02x, driver %s%s\n", |
7ff71d6a | 609 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
93f1a47c DB |
610 | temp >> 8, temp & 0xff, DRIVER_VERSION, |
611 | ignore_oc ? ", overcurrent ignored" : ""); | |
1da177e4 | 612 | |
083522d7 BH |
613 | ehci_writel(ehci, INTR_MASK, |
614 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 615 | |
18807521 DB |
616 | /* GRR this is run-once init(), being done every time the HC starts. |
617 | * So long as they're part of class devices, we can't do it init() | |
618 | * since the class device isn't created that early. | |
619 | */ | |
620 | create_debug_files(ehci); | |
57e06c11 | 621 | create_companion_file(ehci); |
1da177e4 LT |
622 | |
623 | return 0; | |
624 | } | |
625 | ||
1da177e4 LT |
626 | /*-------------------------------------------------------------------------*/ |
627 | ||
7d12e780 | 628 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
629 | { |
630 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
e82cc128 | 631 | u32 status, pcd_status = 0, cmd; |
1da177e4 LT |
632 | int bh; |
633 | ||
634 | spin_lock (&ehci->lock); | |
635 | ||
083522d7 | 636 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
637 | |
638 | /* e.g. cardbus physical eject */ | |
639 | if (status == ~(u32) 0) { | |
640 | ehci_dbg (ehci, "device removed\n"); | |
641 | goto dead; | |
642 | } | |
643 | ||
644 | status &= INTR_MASK; | |
645 | if (!status) { /* irq sharing? */ | |
646 | spin_unlock(&ehci->lock); | |
647 | return IRQ_NONE; | |
648 | } | |
649 | ||
650 | /* clear (just) interrupts */ | |
083522d7 | 651 | ehci_writel(ehci, status, &ehci->regs->status); |
e82cc128 | 652 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
653 | bh = 0; |
654 | ||
9776afc8 | 655 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
656 | /* unrequested/ignored: Frame List Rollover */ |
657 | dbg_status (ehci, "irq", status); | |
658 | #endif | |
659 | ||
660 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
661 | ||
662 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
663 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
664 | if (likely ((status & STS_ERR) == 0)) | |
665 | COUNT (ehci->stats.normal); | |
666 | else | |
667 | COUNT (ehci->stats.error); | |
668 | bh = 1; | |
669 | } | |
670 | ||
671 | /* complete the unlinking of some qh [4.15.2.3] */ | |
672 | if (status & STS_IAA) { | |
e82cc128 DB |
673 | /* guard against (alleged) silicon errata */ |
674 | if (cmd & CMD_IAAD) { | |
675 | ehci_writel(ehci, cmd & ~CMD_IAAD, | |
676 | &ehci->regs->command); | |
677 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); | |
678 | } | |
679 | if (ehci->reclaim) { | |
680 | COUNT(ehci->stats.reclaim); | |
681 | end_unlink_async(ehci); | |
682 | } else | |
683 | ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); | |
1da177e4 LT |
684 | } |
685 | ||
686 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 687 | if (status & STS_PCD) { |
1da177e4 | 688 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
d1b1842c DB |
689 | |
690 | /* kick root hub later */ | |
1d619f12 | 691 | pcd_status = status; |
1da177e4 LT |
692 | |
693 | /* resume root hub? */ | |
083522d7 | 694 | if (!(ehci_readl(ehci, &ehci->regs->command) & CMD_RUN)) |
8c03356a | 695 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
696 | |
697 | while (i--) { | |
083522d7 BH |
698 | int pstatus = ehci_readl(ehci, |
699 | &ehci->regs->port_status [i]); | |
b972b68c DB |
700 | |
701 | if (pstatus & PORT_OWNER) | |
1da177e4 | 702 | continue; |
b972b68c | 703 | if (!(pstatus & PORT_RESUME) |
1da177e4 LT |
704 | || ehci->reset_done [i] != 0) |
705 | continue; | |
706 | ||
707 | /* start 20 msec resume signaling from this port, | |
708 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
709 | * stop that signaling. | |
710 | */ | |
711 | ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); | |
1da177e4 | 712 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 713 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
714 | } |
715 | } | |
716 | ||
717 | /* PCI errors [4.15.2.4] */ | |
718 | if (unlikely ((status & STS_FATAL) != 0)) { | |
083522d7 BH |
719 | dbg_cmd (ehci, "fatal", ehci_readl(ehci, |
720 | &ehci->regs->command)); | |
1da177e4 LT |
721 | dbg_status (ehci, "fatal", status); |
722 | if (status & STS_HALT) { | |
723 | ehci_err (ehci, "fatal error\n"); | |
724 | dead: | |
725 | ehci_reset (ehci); | |
083522d7 | 726 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
1da177e4 LT |
727 | /* generic layer kills/unlinks all urbs, then |
728 | * uses ehci_stop to clean up the rest | |
729 | */ | |
730 | bh = 1; | |
731 | } | |
732 | } | |
733 | ||
734 | if (bh) | |
7d12e780 | 735 | ehci_work (ehci); |
1da177e4 | 736 | spin_unlock (&ehci->lock); |
d1b1842c | 737 | if (pcd_status) |
1d619f12 | 738 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
739 | return IRQ_HANDLED; |
740 | } | |
741 | ||
742 | /*-------------------------------------------------------------------------*/ | |
743 | ||
744 | /* | |
745 | * non-error returns are a promise to giveback() the urb later | |
746 | * we drop ownership so next owner (or urb unlink) can get it | |
747 | * | |
748 | * urb + dev is in hcd.self.controller.urb_list | |
749 | * we're queueing TDs onto software and hardware lists | |
750 | * | |
751 | * hcd-specific init for hcpriv hasn't been done yet | |
752 | * | |
753 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
754 | * to a (possibly active) QH, and the same QH scanning code. | |
755 | */ | |
756 | static int ehci_urb_enqueue ( | |
757 | struct usb_hcd *hcd, | |
1da177e4 | 758 | struct urb *urb, |
55016f10 | 759 | gfp_t mem_flags |
1da177e4 LT |
760 | ) { |
761 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
762 | struct list_head qtd_list; | |
763 | ||
764 | INIT_LIST_HEAD (&qtd_list); | |
765 | ||
766 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
767 | case PIPE_CONTROL: |
768 | /* qh_completions() code doesn't handle all the fault cases | |
769 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
770 | */ | |
771 | if (urb->transfer_buffer_length > (16 * 1024)) | |
772 | return -EMSGSIZE; | |
773 | /* FALLTHROUGH */ | |
774 | /* case PIPE_BULK: */ | |
1da177e4 LT |
775 | default: |
776 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
777 | return -ENOMEM; | |
e9df41c5 | 778 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
779 | |
780 | case PIPE_INTERRUPT: | |
781 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
782 | return -ENOMEM; | |
e9df41c5 | 783 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
784 | |
785 | case PIPE_ISOCHRONOUS: | |
786 | if (urb->dev->speed == USB_SPEED_HIGH) | |
787 | return itd_submit (ehci, urb, mem_flags); | |
788 | else | |
789 | return sitd_submit (ehci, urb, mem_flags); | |
790 | } | |
791 | } | |
792 | ||
793 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
794 | { | |
07d29b63 | 795 | /* failfast */ |
e82cc128 | 796 | if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) |
07d29b63 AS |
797 | end_unlink_async(ehci); |
798 | ||
799 | /* if it's not linked then there's nothing to do */ | |
800 | if (qh->qh_state != QH_STATE_LINKED) | |
801 | ; | |
802 | ||
803 | /* defer till later if busy */ | |
804 | else if (ehci->reclaim) { | |
1da177e4 LT |
805 | struct ehci_qh *last; |
806 | ||
807 | for (last = ehci->reclaim; | |
808 | last->reclaim; | |
809 | last = last->reclaim) | |
810 | continue; | |
811 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
812 | last->reclaim = qh; | |
813 | ||
07d29b63 AS |
814 | /* start IAA cycle */ |
815 | } else | |
1da177e4 LT |
816 | start_unlink_async (ehci, qh); |
817 | } | |
818 | ||
819 | /* remove from hardware lists | |
820 | * completions normally happen asynchronously | |
821 | */ | |
822 | ||
e9df41c5 | 823 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
824 | { |
825 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
826 | struct ehci_qh *qh; | |
827 | unsigned long flags; | |
e9df41c5 | 828 | int rc; |
1da177e4 LT |
829 | |
830 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
831 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
832 | if (rc) | |
833 | goto done; | |
834 | ||
1da177e4 LT |
835 | switch (usb_pipetype (urb->pipe)) { |
836 | // case PIPE_CONTROL: | |
837 | // case PIPE_BULK: | |
838 | default: | |
839 | qh = (struct ehci_qh *) urb->hcpriv; | |
840 | if (!qh) | |
841 | break; | |
07d29b63 AS |
842 | switch (qh->qh_state) { |
843 | case QH_STATE_LINKED: | |
844 | case QH_STATE_COMPLETING: | |
845 | unlink_async(ehci, qh); | |
846 | break; | |
847 | case QH_STATE_UNLINK: | |
848 | case QH_STATE_UNLINK_WAIT: | |
849 | /* already started */ | |
850 | break; | |
851 | case QH_STATE_IDLE: | |
852 | WARN_ON(1); | |
853 | break; | |
854 | } | |
1da177e4 LT |
855 | break; |
856 | ||
857 | case PIPE_INTERRUPT: | |
858 | qh = (struct ehci_qh *) urb->hcpriv; | |
859 | if (!qh) | |
860 | break; | |
861 | switch (qh->qh_state) { | |
862 | case QH_STATE_LINKED: | |
863 | intr_deschedule (ehci, qh); | |
864 | /* FALL THROUGH */ | |
865 | case QH_STATE_IDLE: | |
7d12e780 | 866 | qh_completions (ehci, qh); |
1da177e4 LT |
867 | break; |
868 | default: | |
869 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
870 | qh, qh->qh_state); | |
871 | goto done; | |
872 | } | |
873 | ||
874 | /* reschedule QH iff another request is queued */ | |
875 | if (!list_empty (&qh->qtd_list) | |
876 | && HC_IS_RUNNING (hcd->state)) { | |
e1a49142 DB |
877 | rc = qh_schedule(ehci, qh); |
878 | ||
879 | /* An error here likely indicates handshake failure | |
880 | * or no space left in the schedule. Neither fault | |
881 | * should happen often ... | |
882 | * | |
883 | * FIXME kill the now-dysfunctional queued urbs | |
884 | */ | |
885 | if (rc != 0) | |
886 | ehci_err(ehci, | |
887 | "can't reschedule qh %p, err %d", | |
888 | qh, rc); | |
1da177e4 LT |
889 | } |
890 | break; | |
891 | ||
892 | case PIPE_ISOCHRONOUS: | |
893 | // itd or sitd ... | |
894 | ||
895 | // wait till next completion, do it then. | |
896 | // completion irqs can wait up to 1024 msec, | |
897 | break; | |
898 | } | |
899 | done: | |
900 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 901 | return rc; |
1da177e4 LT |
902 | } |
903 | ||
904 | /*-------------------------------------------------------------------------*/ | |
905 | ||
906 | // bulk qh holds the data toggle | |
907 | ||
908 | static void | |
909 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
910 | { | |
911 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
912 | unsigned long flags; | |
913 | struct ehci_qh *qh, *tmp; | |
914 | ||
915 | /* ASSERT: any requests/urbs are being unlinked */ | |
916 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
917 | ||
918 | rescan: | |
919 | spin_lock_irqsave (&ehci->lock, flags); | |
920 | qh = ep->hcpriv; | |
921 | if (!qh) | |
922 | goto done; | |
923 | ||
924 | /* endpoints can be iso streams. for now, we don't | |
925 | * accelerate iso completions ... so spin a while. | |
926 | */ | |
927 | if (qh->hw_info1 == 0) { | |
928 | ehci_vdbg (ehci, "iso delay\n"); | |
929 | goto idle_timeout; | |
930 | } | |
931 | ||
932 | if (!HC_IS_RUNNING (hcd->state)) | |
933 | qh->qh_state = QH_STATE_IDLE; | |
934 | switch (qh->qh_state) { | |
935 | case QH_STATE_LINKED: | |
936 | for (tmp = ehci->async->qh_next.qh; | |
937 | tmp && tmp != qh; | |
938 | tmp = tmp->qh_next.qh) | |
939 | continue; | |
940 | /* periodic qh self-unlinks on empty */ | |
941 | if (!tmp) | |
942 | goto nogood; | |
943 | unlink_async (ehci, qh); | |
944 | /* FALL THROUGH */ | |
945 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
07d29b63 | 946 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
947 | idle_timeout: |
948 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 949 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
950 | goto rescan; |
951 | case QH_STATE_IDLE: /* fully unlinked */ | |
952 | if (list_empty (&qh->qtd_list)) { | |
953 | qh_put (qh); | |
954 | break; | |
955 | } | |
956 | /* else FALL THROUGH */ | |
957 | default: | |
958 | nogood: | |
959 | /* caller was supposed to have unlinked any requests; | |
960 | * that's not our job. just leak this memory. | |
961 | */ | |
962 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
963 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
964 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
965 | break; | |
966 | } | |
967 | ep->hcpriv = NULL; | |
968 | done: | |
969 | spin_unlock_irqrestore (&ehci->lock, flags); | |
970 | return; | |
971 | } | |
972 | ||
7ff71d6a MP |
973 | static int ehci_get_frame (struct usb_hcd *hcd) |
974 | { | |
975 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
083522d7 BH |
976 | return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % |
977 | ehci->periodic_size; | |
7ff71d6a | 978 | } |
1da177e4 LT |
979 | |
980 | /*-------------------------------------------------------------------------*/ | |
981 | ||
1da177e4 LT |
982 | #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC |
983 | ||
984 | MODULE_DESCRIPTION (DRIVER_INFO); | |
985 | MODULE_AUTHOR (DRIVER_AUTHOR); | |
986 | MODULE_LICENSE ("GPL"); | |
987 | ||
7ff71d6a MP |
988 | #ifdef CONFIG_PCI |
989 | #include "ehci-pci.c" | |
01cced25 | 990 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 991 | #endif |
1da177e4 | 992 | |
ba02978a | 993 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 994 | #include "ehci-fsl.c" |
01cced25 | 995 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
996 | #endif |
997 | ||
dfbaa7d8 | 998 | #ifdef CONFIG_SOC_AU1200 |
76fa9a24 | 999 | #include "ehci-au1xxx.c" |
01cced25 | 1000 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1001 | #endif |
1002 | ||
ad75a410 GL |
1003 | #ifdef CONFIG_PPC_PS3 |
1004 | #include "ehci-ps3.c" | |
7a4eb7fd | 1005 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1006 | #endif |
1007 | ||
da0e8fb0 | 1008 | #if defined(CONFIG_440EPX) && !defined(CONFIG_PPC_MERGE) |
fc65a15f SR |
1009 | #include "ehci-ppc-soc.c" |
1010 | #define PLATFORM_DRIVER ehci_ppc_soc_driver | |
1011 | #endif | |
1012 | ||
da0e8fb0 VB |
1013 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1014 | #include "ehci-ppc-of.c" | |
1015 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1016 | #endif | |
1017 | ||
705a7521 | 1018 | #ifdef CONFIG_PLAT_ORION |
e96ffe2f TP |
1019 | #include "ehci-orion.c" |
1020 | #define PLATFORM_DRIVER ehci_orion_driver | |
1021 | #endif | |
1022 | ||
91bc4d31 VB |
1023 | #ifdef CONFIG_ARCH_IXP4XX |
1024 | #include "ehci-ixp4xx.c" | |
1025 | #define PLATFORM_DRIVER ixp4xx_ehci_driver | |
1026 | #endif | |
1027 | ||
ad75a410 | 1028 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
c6dd2e61 | 1029 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) |
7ff71d6a MP |
1030 | #error "missing bus glue for ehci-hcd" |
1031 | #endif | |
01cced25 KG |
1032 | |
1033 | static int __init ehci_hcd_init(void) | |
1034 | { | |
1035 | int retval = 0; | |
1036 | ||
1037 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", | |
1038 | hcd_name, | |
1039 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1040 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1041 | ||
694cc208 TJ |
1042 | #ifdef DEBUG |
1043 | ehci_debug_root = debugfs_create_dir("ehci", NULL); | |
1044 | if (!ehci_debug_root) | |
1045 | return -ENOENT; | |
1046 | #endif | |
1047 | ||
01cced25 KG |
1048 | #ifdef PLATFORM_DRIVER |
1049 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1050 | if (retval < 0) |
1051 | goto clean0; | |
01cced25 KG |
1052 | #endif |
1053 | ||
1054 | #ifdef PCI_DRIVER | |
1055 | retval = pci_register_driver(&PCI_DRIVER); | |
da0e8fb0 VB |
1056 | if (retval < 0) |
1057 | goto clean1; | |
ad75a410 GL |
1058 | #endif |
1059 | ||
1060 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
7a4eb7fd | 1061 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1062 | if (retval < 0) |
1063 | goto clean2; | |
694cc208 | 1064 | #endif |
da0e8fb0 VB |
1065 | |
1066 | #ifdef OF_PLATFORM_DRIVER | |
1067 | retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); | |
1068 | if (retval < 0) | |
1069 | goto clean3; | |
1070 | #endif | |
1071 | return retval; | |
1072 | ||
1073 | #ifdef OF_PLATFORM_DRIVER | |
1074 | /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */ | |
1075 | clean3: | |
1076 | #endif | |
1077 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1078 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1079 | clean2: | |
ad75a410 GL |
1080 | #endif |
1081 | #ifdef PCI_DRIVER | |
da0e8fb0 VB |
1082 | pci_unregister_driver(&PCI_DRIVER); |
1083 | clean1: | |
ad75a410 | 1084 | #endif |
da0e8fb0 VB |
1085 | #ifdef PLATFORM_DRIVER |
1086 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1087 | clean0: | |
1088 | #endif | |
1089 | #ifdef DEBUG | |
1090 | debugfs_remove(ehci_debug_root); | |
1091 | ehci_debug_root = NULL; | |
01cced25 | 1092 | #endif |
01cced25 KG |
1093 | return retval; |
1094 | } | |
1095 | module_init(ehci_hcd_init); | |
1096 | ||
1097 | static void __exit ehci_hcd_cleanup(void) | |
1098 | { | |
da0e8fb0 VB |
1099 | #ifdef OF_PLATFORM_DRIVER |
1100 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
1101 | #endif | |
01cced25 KG |
1102 | #ifdef PLATFORM_DRIVER |
1103 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1104 | #endif | |
1105 | #ifdef PCI_DRIVER | |
1106 | pci_unregister_driver(&PCI_DRIVER); | |
1107 | #endif | |
ad75a410 | 1108 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1109 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1110 | #endif |
694cc208 TJ |
1111 | #ifdef DEBUG |
1112 | debugfs_remove(ehci_debug_root); | |
1113 | #endif | |
01cced25 KG |
1114 | } |
1115 | module_exit(ehci_hcd_cleanup); | |
1116 |