Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
578333ab AS |
2 | * Enhanced Host Controller Interface (EHCI) driver for USB. |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
1da177e4 | 6 | * Copyright (c) 2000-2004 by David Brownell |
53bd6a60 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/dmapool.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/sched.h> | |
3c04e20e | 30 | #include <linux/vmalloc.h> |
1da177e4 LT |
31 | #include <linux/errno.h> |
32 | #include <linux/init.h> | |
d58b4bcc | 33 | #include <linux/hrtimer.h> |
1da177e4 LT |
34 | #include <linux/list.h> |
35 | #include <linux/interrupt.h> | |
1da177e4 | 36 | #include <linux/usb.h> |
27729aad | 37 | #include <linux/usb/hcd.h> |
1da177e4 LT |
38 | #include <linux/moduleparam.h> |
39 | #include <linux/dma-mapping.h> | |
694cc208 | 40 | #include <linux/debugfs.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
1da177e4 | 42 | |
1da177e4 LT |
43 | #include <asm/byteorder.h> |
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
1da177e4 | 46 | #include <asm/unaligned.h> |
1da177e4 | 47 | |
df7c1ca2 GL |
48 | #if defined(CONFIG_PPC_PS3) |
49 | #include <asm/firmware.h> | |
50 | #endif | |
51 | ||
1da177e4 LT |
52 | /*-------------------------------------------------------------------------*/ |
53 | ||
54 | /* | |
55 | * EHCI hc_driver implementation ... experimental, incomplete. | |
56 | * Based on the final 1.0 register interface specification. | |
57 | * | |
58 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
59 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
60 | * Next comes "CardBay", using USB 2.0 signals. | |
61 | * | |
62 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
63 | * Special thanks to Intel and VIA for providing host controllers to | |
64 | * test this driver on, and Cypress (including In-System Design) for | |
65 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
66 | */ |
67 | ||
1da177e4 LT |
68 | #define DRIVER_AUTHOR "David Brownell" |
69 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
70 | ||
71 | static const char hcd_name [] = "ehci_hcd"; | |
72 | ||
73 | ||
9776afc8 | 74 | #undef VERBOSE_DEBUG |
1da177e4 LT |
75 | #undef EHCI_URB_TRACE |
76 | ||
1da177e4 LT |
77 | /* magic numbers that can affect system performance */ |
78 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
79 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
80 | #define EHCI_TUNE_RL_TT 0 | |
81 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
82 | #define EHCI_TUNE_MULT_TT 1 | |
ffda0803 AS |
83 | /* |
84 | * Some drivers think it's safe to schedule isochronous transfers more than | |
85 | * 256 ms into the future (partly as a result of an old bug in the scheduling | |
86 | * code). In an attempt to avoid trouble, we will use a minimum scheduling | |
87 | * length of 512 frames instead of 256. | |
88 | */ | |
89 | #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ | |
1da177e4 | 90 | |
1da177e4 LT |
91 | /* Initial IRQ latency: faster than hw default */ |
92 | static int log2_irq_thresh = 0; // 0 to 6 | |
93 | module_param (log2_irq_thresh, int, S_IRUGO); | |
94 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
95 | ||
96 | /* initial park setting: slower than hw default */ | |
97 | static unsigned park = 0; | |
98 | module_param (park, uint, S_IRUGO); | |
99 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
100 | ||
93f1a47c | 101 | /* for flakey hardware, ignore overcurrent indicators */ |
90ab5ee9 | 102 | static bool ignore_oc = 0; |
93f1a47c DB |
103 | module_param (ignore_oc, bool, S_IRUGO); |
104 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
105 | ||
1da177e4 LT |
106 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
107 | ||
108 | /*-------------------------------------------------------------------------*/ | |
109 | ||
110 | #include "ehci.h" | |
ad93562b | 111 | #include "pci-quirks.h" |
1da177e4 | 112 | |
acc08503 AS |
113 | /* |
114 | * The MosChip MCS9990 controller updates its microframe counter | |
115 | * a little before the frame counter, and occasionally we will read | |
116 | * the invalid intermediate value. Avoid problems by checking the | |
117 | * microframe number (the low-order 3 bits); if they are 0 then | |
118 | * re-read the register to get the correct value. | |
119 | */ | |
120 | static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci) | |
121 | { | |
122 | unsigned uf; | |
123 | ||
124 | uf = ehci_readl(ehci, &ehci->regs->frame_index); | |
125 | if (unlikely((uf & 7) == 0)) | |
126 | uf = ehci_readl(ehci, &ehci->regs->frame_index); | |
127 | return uf; | |
128 | } | |
129 | ||
130 | static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci) | |
131 | { | |
132 | if (ehci->frame_index_bug) | |
133 | return ehci_moschip_read_frame_index(ehci); | |
134 | return ehci_readl(ehci, &ehci->regs->frame_index); | |
135 | } | |
136 | ||
137 | #include "ehci-dbg.c" | |
138 | ||
1da177e4 LT |
139 | /*-------------------------------------------------------------------------*/ |
140 | ||
141 | /* | |
2f3a6b86 | 142 | * ehci_handshake - spin reading hc until handshake completes or fails |
1da177e4 LT |
143 | * @ptr: address of hc register to be read |
144 | * @mask: bits to look at in result of read | |
145 | * @done: value of those bits when handshake succeeds | |
146 | * @usec: timeout in microseconds | |
147 | * | |
148 | * Returns negative errno, or zero on success | |
149 | * | |
150 | * Success happens when the "mask" bits have the specified value (hardware | |
151 | * handshake done). There are two failure modes: "usec" have passed (major | |
152 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
153 | * | |
154 | * That last failure should_only happen in cases like physical cardbus eject | |
155 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
156 | * bridge shutdown: shutting down the bridge before the devices using it. | |
157 | */ | |
2f3a6b86 MG |
158 | int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, |
159 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
160 | { |
161 | u32 result; | |
162 | ||
163 | do { | |
083522d7 | 164 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
165 | if (result == ~(u32)0) /* card removed */ |
166 | return -ENODEV; | |
167 | result &= mask; | |
168 | if (result == done) | |
169 | return 0; | |
170 | udelay (1); | |
171 | usec--; | |
172 | } while (usec > 0); | |
173 | return -ETIMEDOUT; | |
174 | } | |
2f3a6b86 | 175 | EXPORT_SYMBOL_GPL(ehci_handshake); |
1da177e4 | 176 | |
65fd4272 MC |
177 | /* check TDI/ARC silicon is in host mode */ |
178 | static int tdi_in_host_mode (struct ehci_hcd *ehci) | |
179 | { | |
65fd4272 MC |
180 | u32 tmp; |
181 | ||
a46af4eb | 182 | tmp = ehci_readl(ehci, &ehci->regs->usbmode); |
65fd4272 MC |
183 | return (tmp & 3) == USBMODE_CM_HC; |
184 | } | |
185 | ||
c4f34764 AS |
186 | /* |
187 | * Force HC to halt state from unknown (EHCI spec section 2.3). | |
188 | * Must be called with interrupts enabled and the lock not held. | |
189 | */ | |
1da177e4 LT |
190 | static int ehci_halt (struct ehci_hcd *ehci) |
191 | { | |
c4f34764 AS |
192 | u32 temp; |
193 | ||
194 | spin_lock_irq(&ehci->lock); | |
1da177e4 | 195 | |
72f30b6f | 196 | /* disable any irqs left enabled by previous code */ |
083522d7 | 197 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 198 | |
c4f34764 AS |
199 | if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) { |
200 | spin_unlock_irq(&ehci->lock); | |
65fd4272 MC |
201 | return 0; |
202 | } | |
203 | ||
3d9545cc AS |
204 | /* |
205 | * This routine gets called during probe before ehci->command | |
206 | * has been initialized, so we can't rely on its value. | |
207 | */ | |
208 | ehci->command &= ~CMD_RUN; | |
083522d7 | 209 | temp = ehci_readl(ehci, &ehci->regs->command); |
3d9545cc | 210 | temp &= ~(CMD_RUN | CMD_IAAD); |
083522d7 | 211 | ehci_writel(ehci, temp, &ehci->regs->command); |
df7c1ca2 | 212 | |
c4f34764 AS |
213 | spin_unlock_irq(&ehci->lock); |
214 | synchronize_irq(ehci_to_hcd(ehci)->irq); | |
0bcfeb3e | 215 | |
2f3a6b86 | 216 | return ehci_handshake(ehci, &ehci->regs->status, |
083522d7 | 217 | STS_HALT, STS_HALT, 16 * 125); |
0bcfeb3e DB |
218 | } |
219 | ||
1da177e4 LT |
220 | /* put TDI/ARC silicon into EHCI mode */ |
221 | static void tdi_reset (struct ehci_hcd *ehci) | |
222 | { | |
1da177e4 LT |
223 | u32 tmp; |
224 | ||
a46af4eb | 225 | tmp = ehci_readl(ehci, &ehci->regs->usbmode); |
d23a1377 VB |
226 | tmp |= USBMODE_CM_HC; |
227 | /* The default byte access to MMR space is LE after | |
228 | * controller reset. Set the required endian mode | |
229 | * for transfer buffers to match the host microprocessor | |
230 | */ | |
231 | if (ehci_big_endian_mmio(ehci)) | |
232 | tmp |= USBMODE_BE; | |
a46af4eb | 233 | ehci_writel(ehci, tmp, &ehci->regs->usbmode); |
1da177e4 LT |
234 | } |
235 | ||
c4f34764 AS |
236 | /* |
237 | * Reset a non-running (STS_HALT == 1) controller. | |
238 | * Must be called with interrupts enabled and the lock not held. | |
239 | */ | |
1da177e4 LT |
240 | static int ehci_reset (struct ehci_hcd *ehci) |
241 | { | |
242 | int retval; | |
083522d7 | 243 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 244 | |
8d053c79 JW |
245 | /* If the EHCI debug controller is active, special care must be |
246 | * taken before and after a host controller reset */ | |
9fa5780b | 247 | if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci))) |
8d053c79 JW |
248 | ehci->debug = NULL; |
249 | ||
1da177e4 LT |
250 | command |= CMD_RESET; |
251 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 252 | ehci_writel(ehci, command, &ehci->regs->command); |
e8799906 | 253 | ehci->rh_state = EHCI_RH_HALTED; |
1da177e4 | 254 | ehci->next_statechange = jiffies; |
2f3a6b86 | 255 | retval = ehci_handshake(ehci, &ehci->regs->command, |
083522d7 | 256 | CMD_RESET, 0, 250 * 1000); |
1da177e4 | 257 | |
331ac6b2 AD |
258 | if (ehci->has_hostpc) { |
259 | ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, | |
a46af4eb AS |
260 | &ehci->regs->usbmode_ex); |
261 | ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning); | |
331ac6b2 | 262 | } |
1da177e4 LT |
263 | if (retval) |
264 | return retval; | |
265 | ||
266 | if (ehci_is_TDI(ehci)) | |
267 | tdi_reset (ehci); | |
268 | ||
8d053c79 | 269 | if (ehci->debug) |
9fa5780b | 270 | dbgp_external_startup(ehci_to_hcd(ehci)); |
8d053c79 | 271 | |
a448e4dc AS |
272 | ehci->port_c_suspend = ehci->suspended_ports = |
273 | ehci->resuming_ports = 0; | |
1da177e4 LT |
274 | return retval; |
275 | } | |
276 | ||
c4f34764 AS |
277 | /* |
278 | * Idle the controller (turn off the schedules). | |
279 | * Must be called with interrupts enabled and the lock not held. | |
280 | */ | |
1da177e4 LT |
281 | static void ehci_quiesce (struct ehci_hcd *ehci) |
282 | { | |
283 | u32 temp; | |
284 | ||
e8799906 | 285 | if (ehci->rh_state != EHCI_RH_RUNNING) |
c0c53dbc | 286 | return; |
1da177e4 LT |
287 | |
288 | /* wait for any schedule enables/disables to take effect */ | |
3d9545cc | 289 | temp = (ehci->command << 10) & (STS_ASS | STS_PSS); |
2f3a6b86 MG |
290 | ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp, |
291 | 16 * 125); | |
1da177e4 LT |
292 | |
293 | /* then disable anything that's still active */ | |
c4f34764 | 294 | spin_lock_irq(&ehci->lock); |
3d9545cc AS |
295 | ehci->command &= ~(CMD_ASE | CMD_PSE); |
296 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | |
c4f34764 | 297 | spin_unlock_irq(&ehci->lock); |
1da177e4 LT |
298 | |
299 | /* hardware can take 16 microframes to turn off ... */ | |
2f3a6b86 MG |
300 | ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0, |
301 | 16 * 125); | |
1da177e4 LT |
302 | } |
303 | ||
304 | /*-------------------------------------------------------------------------*/ | |
305 | ||
07d29b63 | 306 | static void end_unlink_async(struct ehci_hcd *ehci); |
32830f20 | 307 | static void unlink_empty_async(struct ehci_hcd *ehci); |
2a40f324 | 308 | static void unlink_empty_async_suspended(struct ehci_hcd *ehci); |
7d12e780 | 309 | static void ehci_work(struct ehci_hcd *ehci); |
df202255 AS |
310 | static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh); |
311 | static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh); | |
1da177e4 | 312 | |
d58b4bcc | 313 | #include "ehci-timer.c" |
1da177e4 LT |
314 | #include "ehci-hub.c" |
315 | #include "ehci-mem.c" | |
316 | #include "ehci-q.c" | |
317 | #include "ehci-sched.c" | |
4c67045b | 318 | #include "ehci-sysfs.c" |
1da177e4 LT |
319 | |
320 | /*-------------------------------------------------------------------------*/ | |
321 | ||
8903795a AS |
322 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
323 | * The firmware seems to think that powering off is a wakeup event! | |
324 | * This routine turns off remote wakeup and everything else, on all ports. | |
325 | */ | |
326 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
327 | { | |
328 | int port = HCS_N_PORTS(ehci->hcs_params); | |
329 | ||
330 | while (port--) | |
331 | ehci_writel(ehci, PORT_RWC_BITS, | |
332 | &ehci->regs->port_status[port]); | |
333 | } | |
334 | ||
21da84a8 SS |
335 | /* |
336 | * Halt HC, turn off all ports, and let the BIOS use the companion controllers. | |
c4f34764 | 337 | * Must be called with interrupts enabled and the lock not held. |
72f30b6f | 338 | */ |
21da84a8 | 339 | static void ehci_silence_controller(struct ehci_hcd *ehci) |
1da177e4 | 340 | { |
21da84a8 | 341 | ehci_halt(ehci); |
c4f34764 AS |
342 | |
343 | spin_lock_irq(&ehci->lock); | |
344 | ehci->rh_state = EHCI_RH_HALTED; | |
8903795a | 345 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
346 | |
347 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 348 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
349 | |
350 | /* unblock posted writes */ | |
351 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
c4f34764 | 352 | spin_unlock_irq(&ehci->lock); |
1da177e4 LT |
353 | } |
354 | ||
21da84a8 SS |
355 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
356 | * This forcibly disables dma and IRQs, helping kexec and other cases | |
357 | * where the next system software may expect clean state. | |
358 | */ | |
359 | static void ehci_shutdown(struct usb_hcd *hcd) | |
360 | { | |
361 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
362 | ||
21da84a8 | 363 | spin_lock_irq(&ehci->lock); |
43fe3a99 | 364 | ehci->shutdown = true; |
c0c53dbc | 365 | ehci->rh_state = EHCI_RH_STOPPING; |
d58b4bcc | 366 | ehci->enabled_hrtimer_events = 0; |
21da84a8 | 367 | spin_unlock_irq(&ehci->lock); |
d58b4bcc | 368 | |
c4f34764 AS |
369 | ehci_silence_controller(ehci); |
370 | ||
d58b4bcc | 371 | hrtimer_cancel(&ehci->hrtimer); |
21da84a8 SS |
372 | } |
373 | ||
7ff71d6a | 374 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 375 | |
7ff71d6a MP |
376 | /* |
377 | * ehci_work is called from some interrupts, timers, and so on. | |
378 | * it calls driver completion functions, after dropping ehci->lock. | |
379 | */ | |
7d12e780 | 380 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a | 381 | { |
7ff71d6a MP |
382 | /* another CPU may drop ehci->lock during a schedule scan while |
383 | * it reports urb completions. this flag guards against bogus | |
384 | * attempts at re-entrant schedule scanning. | |
385 | */ | |
361aabf3 AS |
386 | if (ehci->scanning) { |
387 | ehci->need_rescan = true; | |
7ff71d6a | 388 | return; |
361aabf3 AS |
389 | } |
390 | ehci->scanning = true; | |
391 | ||
392 | rescan: | |
393 | ehci->need_rescan = false; | |
31446610 AS |
394 | if (ehci->async_count) |
395 | scan_async(ehci); | |
569b394f AS |
396 | if (ehci->intr_count > 0) |
397 | scan_intr(ehci); | |
398 | if (ehci->isoc_count > 0) | |
399 | scan_isoc(ehci); | |
361aabf3 AS |
400 | if (ehci->need_rescan) |
401 | goto rescan; | |
402 | ehci->scanning = false; | |
7ff71d6a MP |
403 | |
404 | /* the IO watchdog guards against hardware or driver bugs that | |
405 | * misplace IRQs, and should let us run completely without IRQs. | |
406 | * such lossage has been observed on both VT6202 and VT8235. | |
407 | */ | |
18aafe64 | 408 | turn_on_io_watchdog(ehci); |
7ff71d6a | 409 | } |
1da177e4 | 410 | |
21da84a8 SS |
411 | /* |
412 | * Called when the ehci_hcd module is removed. | |
413 | */ | |
7ff71d6a | 414 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
415 | { |
416 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 417 | |
7ff71d6a | 418 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 419 | |
7ff71d6a | 420 | /* no more interrupts ... */ |
56c1e26d | 421 | |
7ff71d6a | 422 | spin_lock_irq(&ehci->lock); |
d58b4bcc | 423 | ehci->enabled_hrtimer_events = 0; |
c4f34764 | 424 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 425 | |
c4f34764 | 426 | ehci_quiesce(ehci); |
21da84a8 | 427 | ehci_silence_controller(ehci); |
7ff71d6a | 428 | ehci_reset (ehci); |
1da177e4 | 429 | |
d58b4bcc | 430 | hrtimer_cancel(&ehci->hrtimer); |
4c67045b | 431 | remove_sysfs_files(ehci); |
7ff71d6a | 432 | remove_debug_files (ehci); |
1da177e4 | 433 | |
7ff71d6a MP |
434 | /* root hub is shut down separately (first, when possible) */ |
435 | spin_lock_irq (&ehci->lock); | |
55934eb3 | 436 | end_free_itds(ehci); |
7ff71d6a MP |
437 | spin_unlock_irq (&ehci->lock); |
438 | ehci_mem_cleanup (ehci); | |
1da177e4 | 439 | |
ad93562b AX |
440 | if (ehci->amd_pll_fix == 1) |
441 | usb_amd_dev_put(); | |
05570297 | 442 | |
083522d7 BH |
443 | dbg_status (ehci, "ehci_stop completed", |
444 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
445 | } |
446 | ||
18807521 DB |
447 | /* one-time init, only for memory state */ |
448 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 449 | { |
18807521 | 450 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 451 | u32 temp; |
1da177e4 LT |
452 | int retval; |
453 | u32 hcc_params; | |
3807e26d | 454 | struct ehci_qh_hw *hw; |
18807521 DB |
455 | |
456 | spin_lock_init(&ehci->lock); | |
457 | ||
403dbd36 AD |
458 | /* |
459 | * keep io watchdog by default, those good HCDs could turn off it later | |
460 | */ | |
461 | ehci->need_io_watchdog = 1; | |
1da177e4 | 462 | |
d58b4bcc AS |
463 | hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); |
464 | ehci->hrtimer.function = ehci_hrtimer_func; | |
465 | ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT; | |
07d29b63 | 466 | |
f75593ce AS |
467 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
468 | ||
cc62a7eb KS |
469 | /* |
470 | * by default set standard 80% (== 100 usec/uframe) max periodic | |
471 | * bandwidth as required by USB 2.0 | |
472 | */ | |
473 | ehci->uframe_periodic_max = 100; | |
474 | ||
1da177e4 LT |
475 | /* |
476 | * hw default: 1K periodic list heads, one per frame. | |
477 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
478 | */ | |
479 | ehci->periodic_size = DEFAULT_I_TDPS; | |
6e018751 | 480 | INIT_LIST_HEAD(&ehci->async_unlink); |
214ac7a0 | 481 | INIT_LIST_HEAD(&ehci->async_idle); |
9118f9eb | 482 | INIT_LIST_HEAD(&ehci->intr_unlink_wait); |
6e018751 | 483 | INIT_LIST_HEAD(&ehci->intr_unlink); |
569b394f | 484 | INIT_LIST_HEAD(&ehci->intr_qh_list); |
9aa09d2f | 485 | INIT_LIST_HEAD(&ehci->cached_itd_list); |
0e5f231b | 486 | INIT_LIST_HEAD(&ehci->cached_sitd_list); |
f75593ce | 487 | |
8e192910 | 488 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
f75593ce AS |
489 | /* periodic schedule size can be smaller than default */ |
490 | switch (EHCI_TUNE_FLS) { | |
491 | case 0: ehci->periodic_size = 1024; break; | |
492 | case 1: ehci->periodic_size = 512; break; | |
493 | case 2: ehci->periodic_size = 256; break; | |
494 | default: BUG(); | |
495 | } | |
496 | } | |
18807521 | 497 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
498 | return retval; |
499 | ||
500 | /* controllers may cache some of the periodic schedule ... */ | |
53bd6a60 | 501 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
98cae42d | 502 | ehci->i_thresh = 0; |
1da177e4 | 503 | else // N microframes cached |
18807521 | 504 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 | 505 | |
1da177e4 LT |
506 | /* |
507 | * dedicate a qh for the async ring head, since we couldn't unlink | |
508 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
509 | * as the 'reclamation list head' too. | |
510 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
511 | * from automatically advancing to the next td after short reads. | |
512 | */ | |
18807521 | 513 | ehci->async->qh_next.qh = NULL; |
3807e26d AD |
514 | hw = ehci->async->hw; |
515 | hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); | |
516 | hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
4f7a67e2 | 517 | #if defined(CONFIG_PPC_PS3) |
4c53de72 | 518 | hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE); |
4f7a67e2 | 519 | #endif |
3807e26d AD |
520 | hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); |
521 | hw->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 522 | ehci->async->qh_state = QH_STATE_LINKED; |
3807e26d | 523 | hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
524 | |
525 | /* clear interrupt enables, set irq latency */ | |
526 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
527 | log2_irq_thresh = 0; | |
528 | temp = 1 << (16 + log2_irq_thresh); | |
5a9cdf33 AD |
529 | if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { |
530 | ehci->has_ppcd = 1; | |
531 | ehci_dbg(ehci, "enable per-port change event\n"); | |
532 | temp |= CMD_PPCEE; | |
533 | } | |
1da177e4 LT |
534 | if (HCC_CANPARK(hcc_params)) { |
535 | /* HW default park == 3, on hardware that supports it (like | |
536 | * NVidia and ALI silicon), maximizes throughput on the async | |
537 | * schedule by avoiding QH fetches between transfers. | |
538 | * | |
539 | * With fast usb storage devices and NForce2, "park" seems to | |
540 | * make problems: throughput reduction (!), data errors... | |
541 | */ | |
542 | if (park) { | |
18807521 | 543 | park = min(park, (unsigned) 3); |
1da177e4 LT |
544 | temp |= CMD_PARK; |
545 | temp |= park << 8; | |
546 | } | |
18807521 | 547 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 548 | } |
18807521 | 549 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
550 | /* periodic schedule size can be smaller than default */ |
551 | temp &= ~(3 << 2); | |
552 | temp |= (EHCI_TUNE_FLS << 2); | |
1da177e4 | 553 | } |
18807521 DB |
554 | ehci->command = temp; |
555 | ||
40f8db8f | 556 | /* Accept arbitrarily long scatter-gather lists */ |
4307a28e AR |
557 | if (!(hcd->driver->flags & HCD_LOCAL_MEM)) |
558 | hcd->self.sg_tablesize = ~0; | |
18807521 DB |
559 | return 0; |
560 | } | |
561 | ||
562 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
563 | static int ehci_run (struct usb_hcd *hcd) | |
564 | { | |
565 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
18807521 DB |
566 | u32 temp; |
567 | u32 hcc_params; | |
568 | ||
1d619f12 | 569 | hcd->uses_new_polling = 1; |
1d619f12 | 570 | |
18807521 | 571 | /* EHCI spec section 4.1 */ |
876e0df9 | 572 | |
083522d7 BH |
573 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
574 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
575 | |
576 | /* | |
577 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
578 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
579 | * pci_pool consistent memory always uses segment zero. | |
580 | * streaming mappings for I/O buffers, like pci_map_single(), | |
581 | * can return segments above 4GB, if the device allows. | |
582 | * | |
583 | * NOTE: the dma mask is visible through dma_supported(), so | |
584 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
585 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
586 | * host side drivers though. | |
587 | */ | |
083522d7 | 588 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 589 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 590 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
591 | #if 0 |
592 | // this is deeply broken on almost all architectures | |
6a35528a | 593 | if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) |
18807521 DB |
594 | ehci_info(ehci, "enabled 64bit DMA\n"); |
595 | #endif | |
596 | } | |
597 | ||
598 | ||
1da177e4 LT |
599 | // Philips, Intel, and maybe others need CMD_RUN before the |
600 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
601 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
602 | ehci->command |= CMD_RUN; | |
083522d7 | 603 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 604 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 605 | |
1da177e4 LT |
606 | /* |
607 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
608 | * are explicitly handed to companion controller(s), so no TT is | |
609 | * involved with the root hub. (Except where one is integrated, | |
610 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
611 | * |
612 | * Turning on the CF flag will transfer ownership of all ports | |
613 | * from the companions to the EHCI controller. If any of the | |
614 | * companions are in the middle of a port reset at the time, it | |
615 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
616 | * guarantees that no resets are in progress. After we set CF, |
617 | * a short delay lets the hardware catch up; new resets shouldn't | |
618 | * be started before the port switching actions could complete. | |
1da177e4 | 619 | */ |
32fe0198 | 620 | down_write(&ehci_cf_port_reset_rwsem); |
e8799906 | 621 | ehci->rh_state = EHCI_RH_RUNNING; |
083522d7 BH |
622 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
623 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 624 | msleep(5); |
32fe0198 | 625 | up_write(&ehci_cf_port_reset_rwsem); |
ee4ecb8a | 626 | ehci->last_periodic_enable = ktime_get_real(); |
1da177e4 | 627 | |
c430131a | 628 | temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 629 | ehci_info (ehci, |
2b70f073 | 630 | "USB %x.%x started, EHCI %x.%02x%s\n", |
7ff71d6a | 631 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
2b70f073 | 632 | temp >> 8, temp & 0xff, |
93f1a47c | 633 | ignore_oc ? ", overcurrent ignored" : ""); |
1da177e4 | 634 | |
083522d7 BH |
635 | ehci_writel(ehci, INTR_MASK, |
636 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 637 | |
18807521 DB |
638 | /* GRR this is run-once init(), being done every time the HC starts. |
639 | * So long as they're part of class devices, we can't do it init() | |
640 | * since the class device isn't created that early. | |
641 | */ | |
642 | create_debug_files(ehci); | |
4c67045b | 643 | create_sysfs_files(ehci); |
1da177e4 LT |
644 | |
645 | return 0; | |
646 | } | |
647 | ||
3e023203 | 648 | int ehci_setup(struct usb_hcd *hcd) |
2093c6b4 MC |
649 | { |
650 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
651 | int retval; | |
652 | ||
653 | ehci->regs = (void __iomem *)ehci->caps + | |
654 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | |
655 | dbg_hcs_params(ehci, "reset"); | |
656 | dbg_hcc_params(ehci, "reset"); | |
657 | ||
658 | /* cache this readonly data; minimize chip reads */ | |
659 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | |
660 | ||
661 | ehci->sbrn = HCD_USB2; | |
662 | ||
631fe9d9 AS |
663 | /* data structure init */ |
664 | retval = ehci_init(hcd); | |
2093c6b4 MC |
665 | if (retval) |
666 | return retval; | |
667 | ||
631fe9d9 | 668 | retval = ehci_halt(ehci); |
2093c6b4 MC |
669 | if (retval) |
670 | return retval; | |
671 | ||
672 | ehci_reset(ehci); | |
673 | ||
674 | return 0; | |
675 | } | |
3e023203 | 676 | EXPORT_SYMBOL_GPL(ehci_setup); |
2093c6b4 | 677 | |
1da177e4 LT |
678 | /*-------------------------------------------------------------------------*/ |
679 | ||
7d12e780 | 680 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
681 | { |
682 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
67b2e029 | 683 | u32 status, masked_status, pcd_status = 0, cmd; |
1da177e4 LT |
684 | int bh; |
685 | ||
686 | spin_lock (&ehci->lock); | |
687 | ||
083522d7 | 688 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
689 | |
690 | /* e.g. cardbus physical eject */ | |
691 | if (status == ~(u32) 0) { | |
692 | ehci_dbg (ehci, "device removed\n"); | |
693 | goto dead; | |
694 | } | |
695 | ||
2fbe2bf1 AS |
696 | /* |
697 | * We don't use STS_FLR, but some controllers don't like it to | |
698 | * remain on, so mask it out along with the other status bits. | |
699 | */ | |
700 | masked_status = status & (INTR_MASK | STS_FLR); | |
701 | ||
69fff59d | 702 | /* Shared IRQ? */ |
e8799906 | 703 | if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { |
1da177e4 LT |
704 | spin_unlock(&ehci->lock); |
705 | return IRQ_NONE; | |
706 | } | |
707 | ||
708 | /* clear (just) interrupts */ | |
67b2e029 | 709 | ehci_writel(ehci, masked_status, &ehci->regs->status); |
e82cc128 | 710 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
711 | bh = 0; |
712 | ||
9776afc8 | 713 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
714 | /* unrequested/ignored: Frame List Rollover */ |
715 | dbg_status (ehci, "irq", status); | |
716 | #endif | |
717 | ||
718 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
719 | ||
720 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
721 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
722 | if (likely ((status & STS_ERR) == 0)) | |
723 | COUNT (ehci->stats.normal); | |
724 | else | |
725 | COUNT (ehci->stats.error); | |
726 | bh = 1; | |
727 | } | |
728 | ||
729 | /* complete the unlinking of some qh [4.15.2.3] */ | |
730 | if (status & STS_IAA) { | |
9d938747 AS |
731 | |
732 | /* Turn off the IAA watchdog */ | |
733 | ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG); | |
734 | ||
735 | /* | |
736 | * Mild optimization: Allow another IAAD to reset the | |
737 | * hrtimer, if one occurs before the next expiration. | |
738 | * In theory we could always cancel the hrtimer, but | |
739 | * tests show that about half the time it will be reset | |
740 | * for some other event anyway. | |
741 | */ | |
742 | if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG) | |
743 | ++ehci->next_hrtimer_event; | |
744 | ||
e82cc128 | 745 | /* guard against (alleged) silicon errata */ |
6feff1b9 | 746 | if (cmd & CMD_IAAD) |
e82cc128 | 747 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); |
214ac7a0 | 748 | if (ehci->iaa_in_progress) |
99ac5b1e | 749 | COUNT(ehci->stats.iaa); |
6402c796 | 750 | end_unlink_async(ehci); |
1da177e4 LT |
751 | } |
752 | ||
753 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 754 | if (status & STS_PCD) { |
1da177e4 | 755 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
4dd405a4 | 756 | u32 ppcd = ~0; |
d1b1842c DB |
757 | |
758 | /* kick root hub later */ | |
1d619f12 | 759 | pcd_status = status; |
1da177e4 LT |
760 | |
761 | /* resume root hub? */ | |
dc75ce9d | 762 | if (ehci->rh_state == EHCI_RH_SUSPENDED) |
8c03356a | 763 | usb_hcd_resume_root_hub(hcd); |
1da177e4 | 764 | |
5a9cdf33 AD |
765 | /* get per-port change detect bits */ |
766 | if (ehci->has_ppcd) | |
767 | ppcd = status >> 16; | |
768 | ||
1da177e4 | 769 | while (i--) { |
5a9cdf33 AD |
770 | int pstatus; |
771 | ||
772 | /* leverage per-port change bits feature */ | |
4dd405a4 | 773 | if (!(ppcd & (1 << i))) |
5a9cdf33 AD |
774 | continue; |
775 | pstatus = ehci_readl(ehci, | |
776 | &ehci->regs->port_status[i]); | |
b972b68c DB |
777 | |
778 | if (pstatus & PORT_OWNER) | |
1da177e4 | 779 | continue; |
eafe5b99 AS |
780 | if (!(test_bit(i, &ehci->suspended_ports) && |
781 | ((pstatus & PORT_RESUME) || | |
782 | !(pstatus & PORT_SUSPEND)) && | |
783 | (pstatus & PORT_PE) && | |
784 | ehci->reset_done[i] == 0)) | |
1da177e4 LT |
785 | continue; |
786 | ||
787 | /* start 20 msec resume signaling from this port, | |
788 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
49d0f078 AS |
789 | * stop that signaling. Use 5 ms extra for safety, |
790 | * like usb_port_resume() does. | |
1da177e4 | 791 | */ |
49d0f078 | 792 | ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); |
a448e4dc | 793 | set_bit(i, &ehci->resuming_ports); |
1da177e4 | 794 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
f292e7f9 | 795 | usb_hcd_start_port_resume(&hcd->self, i); |
61e8b858 | 796 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
797 | } |
798 | } | |
799 | ||
800 | /* PCI errors [4.15.2.4] */ | |
801 | if (unlikely ((status & STS_FATAL) != 0)) { | |
67b2e029 | 802 | ehci_err(ehci, "fatal error\n"); |
eafe5b99 AS |
803 | dbg_cmd(ehci, "fatal", cmd); |
804 | dbg_status(ehci, "fatal", status); | |
1da177e4 | 805 | dead: |
69fff59d | 806 | usb_hc_died(hcd); |
bf6387bc AS |
807 | |
808 | /* Don't let the controller do anything more */ | |
43fe3a99 | 809 | ehci->shutdown = true; |
bf6387bc AS |
810 | ehci->rh_state = EHCI_RH_STOPPING; |
811 | ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE); | |
812 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | |
813 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
814 | ehci_handle_controller_death(ehci); | |
815 | ||
816 | /* Handle completions when the controller stops */ | |
817 | bh = 0; | |
1da177e4 LT |
818 | } |
819 | ||
820 | if (bh) | |
7d12e780 | 821 | ehci_work (ehci); |
1da177e4 | 822 | spin_unlock (&ehci->lock); |
d1b1842c | 823 | if (pcd_status) |
1d619f12 | 824 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
825 | return IRQ_HANDLED; |
826 | } | |
827 | ||
828 | /*-------------------------------------------------------------------------*/ | |
829 | ||
830 | /* | |
831 | * non-error returns are a promise to giveback() the urb later | |
832 | * we drop ownership so next owner (or urb unlink) can get it | |
833 | * | |
834 | * urb + dev is in hcd.self.controller.urb_list | |
835 | * we're queueing TDs onto software and hardware lists | |
836 | * | |
837 | * hcd-specific init for hcpriv hasn't been done yet | |
838 | * | |
839 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
840 | * to a (possibly active) QH, and the same QH scanning code. | |
841 | */ | |
842 | static int ehci_urb_enqueue ( | |
843 | struct usb_hcd *hcd, | |
1da177e4 | 844 | struct urb *urb, |
55016f10 | 845 | gfp_t mem_flags |
1da177e4 LT |
846 | ) { |
847 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
848 | struct list_head qtd_list; | |
849 | ||
850 | INIT_LIST_HEAD (&qtd_list); | |
851 | ||
852 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
853 | case PIPE_CONTROL: |
854 | /* qh_completions() code doesn't handle all the fault cases | |
855 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
856 | */ | |
857 | if (urb->transfer_buffer_length > (16 * 1024)) | |
858 | return -EMSGSIZE; | |
859 | /* FALLTHROUGH */ | |
860 | /* case PIPE_BULK: */ | |
1da177e4 LT |
861 | default: |
862 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
863 | return -ENOMEM; | |
e9df41c5 | 864 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
865 | |
866 | case PIPE_INTERRUPT: | |
867 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
868 | return -ENOMEM; | |
e9df41c5 | 869 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
870 | |
871 | case PIPE_ISOCHRONOUS: | |
872 | if (urb->dev->speed == USB_SPEED_HIGH) | |
873 | return itd_submit (ehci, urb, mem_flags); | |
874 | else | |
875 | return sitd_submit (ehci, urb, mem_flags); | |
876 | } | |
877 | } | |
878 | ||
1da177e4 LT |
879 | /* remove from hardware lists |
880 | * completions normally happen asynchronously | |
881 | */ | |
882 | ||
e9df41c5 | 883 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
884 | { |
885 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
886 | struct ehci_qh *qh; | |
887 | unsigned long flags; | |
e9df41c5 | 888 | int rc; |
1da177e4 LT |
889 | |
890 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
891 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
892 | if (rc) | |
893 | goto done; | |
894 | ||
7655e316 AS |
895 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
896 | /* | |
897 | * We don't expedite dequeue for isochronous URBs. | |
898 | * Just wait until they complete normally or their | |
899 | * time slot expires. | |
900 | */ | |
901 | } else { | |
1da177e4 | 902 | qh = (struct ehci_qh *) urb->hcpriv; |
7bc782d7 | 903 | qh->exception = 1; |
07d29b63 AS |
904 | switch (qh->qh_state) { |
905 | case QH_STATE_LINKED: | |
7655e316 AS |
906 | if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT) |
907 | start_unlink_intr(ehci, qh); | |
908 | else | |
909 | start_unlink_async(ehci, qh); | |
07d29b63 | 910 | break; |
7bc782d7 AS |
911 | case QH_STATE_COMPLETING: |
912 | qh->dequeue_during_giveback = 1; | |
913 | break; | |
07d29b63 AS |
914 | case QH_STATE_UNLINK: |
915 | case QH_STATE_UNLINK_WAIT: | |
916 | /* already started */ | |
917 | break; | |
918 | case QH_STATE_IDLE: | |
7a0f0d95 AS |
919 | /* QH might be waiting for a Clear-TT-Buffer */ |
920 | qh_completions(ehci, qh); | |
07d29b63 AS |
921 | break; |
922 | } | |
1da177e4 LT |
923 | } |
924 | done: | |
925 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 926 | return rc; |
1da177e4 LT |
927 | } |
928 | ||
929 | /*-------------------------------------------------------------------------*/ | |
930 | ||
931 | // bulk qh holds the data toggle | |
932 | ||
933 | static void | |
934 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
935 | { | |
936 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
937 | unsigned long flags; | |
35371e4f | 938 | struct ehci_qh *qh; |
1da177e4 LT |
939 | |
940 | /* ASSERT: any requests/urbs are being unlinked */ | |
941 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
942 | ||
943 | rescan: | |
944 | spin_lock_irqsave (&ehci->lock, flags); | |
945 | qh = ep->hcpriv; | |
946 | if (!qh) | |
947 | goto done; | |
948 | ||
949 | /* endpoints can be iso streams. for now, we don't | |
950 | * accelerate iso completions ... so spin a while. | |
951 | */ | |
1082f57a | 952 | if (qh->hw == NULL) { |
8c5bf7be AS |
953 | struct ehci_iso_stream *stream = ep->hcpriv; |
954 | ||
955 | if (!list_empty(&stream->td_list)) | |
956 | goto idle_timeout; | |
957 | ||
958 | /* BUG_ON(!list_empty(&stream->free_list)); */ | |
959 | kfree(stream); | |
960 | goto done; | |
1da177e4 LT |
961 | } |
962 | ||
7bc782d7 | 963 | qh->exception = 1; |
c0c53dbc | 964 | if (ehci->rh_state < EHCI_RH_RUNNING) |
1da177e4 LT |
965 | qh->qh_state = QH_STATE_IDLE; |
966 | switch (qh->qh_state) { | |
967 | case QH_STATE_LINKED: | |
35371e4f ML |
968 | WARN_ON(!list_empty(&qh->qtd_list)); |
969 | if (usb_endpoint_type(&ep->desc) != USB_ENDPOINT_XFER_INT) | |
3c273a05 | 970 | start_unlink_async(ehci, qh); |
35371e4f ML |
971 | else |
972 | start_unlink_intr(ehci, qh); | |
1da177e4 | 973 | /* FALL THROUGH */ |
35371e4f | 974 | case QH_STATE_COMPLETING: /* already in unlinking */ |
1da177e4 | 975 | case QH_STATE_UNLINK: /* wait for hw to finish? */ |
07d29b63 | 976 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
977 | idle_timeout: |
978 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 979 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
980 | goto rescan; |
981 | case QH_STATE_IDLE: /* fully unlinked */ | |
914b7012 AS |
982 | if (qh->clearing_tt) |
983 | goto idle_timeout; | |
1da177e4 | 984 | if (list_empty (&qh->qtd_list)) { |
c83e1a9f | 985 | qh_destroy(ehci, qh); |
1da177e4 LT |
986 | break; |
987 | } | |
988 | /* else FALL THROUGH */ | |
989 | default: | |
1da177e4 LT |
990 | /* caller was supposed to have unlinked any requests; |
991 | * that's not our job. just leak this memory. | |
992 | */ | |
993 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
994 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
995 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
996 | break; | |
997 | } | |
8c5bf7be | 998 | done: |
1da177e4 | 999 | ep->hcpriv = NULL; |
1da177e4 | 1000 | spin_unlock_irqrestore (&ehci->lock, flags); |
1da177e4 LT |
1001 | } |
1002 | ||
b18ffd49 AS |
1003 | static void |
1004 | ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1005 | { | |
1006 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1007 | struct ehci_qh *qh; | |
1008 | int eptype = usb_endpoint_type(&ep->desc); | |
a455212d AS |
1009 | int epnum = usb_endpoint_num(&ep->desc); |
1010 | int is_out = usb_endpoint_dir_out(&ep->desc); | |
1011 | unsigned long flags; | |
b18ffd49 AS |
1012 | |
1013 | if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) | |
1014 | return; | |
1015 | ||
a455212d | 1016 | spin_lock_irqsave(&ehci->lock, flags); |
b18ffd49 AS |
1017 | qh = ep->hcpriv; |
1018 | ||
1019 | /* For Bulk and Interrupt endpoints we maintain the toggle state | |
1020 | * in the hardware; the toggle bits in udev aren't used at all. | |
1021 | * When an endpoint is reset by usb_clear_halt() we must reset | |
1022 | * the toggle bit in the QH. | |
1023 | */ | |
1024 | if (qh) { | |
a455212d | 1025 | usb_settoggle(qh->dev, epnum, is_out, 0); |
b18ffd49 AS |
1026 | if (!list_empty(&qh->qtd_list)) { |
1027 | WARN_ONCE(1, "clear_halt for a busy endpoint\n"); | |
7bc782d7 | 1028 | } else { |
a455212d AS |
1029 | /* The toggle value in the QH can't be updated |
1030 | * while the QH is active. Unlink it now; | |
1031 | * re-linking will call qh_refresh(). | |
b18ffd49 | 1032 | */ |
7bc782d7 | 1033 | qh->exception = 1; |
a448c9d8 | 1034 | if (eptype == USB_ENDPOINT_XFER_BULK) |
3c273a05 | 1035 | start_unlink_async(ehci, qh); |
a448c9d8 | 1036 | else |
df202255 | 1037 | start_unlink_intr(ehci, qh); |
b18ffd49 AS |
1038 | } |
1039 | } | |
a455212d | 1040 | spin_unlock_irqrestore(&ehci->lock, flags); |
b18ffd49 AS |
1041 | } |
1042 | ||
7ff71d6a MP |
1043 | static int ehci_get_frame (struct usb_hcd *hcd) |
1044 | { | |
1045 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
68aa95d5 | 1046 | return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; |
7ff71d6a | 1047 | } |
1da177e4 LT |
1048 | |
1049 | /*-------------------------------------------------------------------------*/ | |
c5cf9212 AS |
1050 | |
1051 | #ifdef CONFIG_PM | |
1052 | ||
1053 | /* suspend/resume, section 4.3 */ | |
1054 | ||
1055 | /* These routines handle the generic parts of controller suspend/resume */ | |
1056 | ||
3e023203 | 1057 | int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
c5cf9212 AS |
1058 | { |
1059 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1060 | ||
1061 | if (time_before(jiffies, ehci->next_statechange)) | |
1062 | msleep(10); | |
1063 | ||
1064 | /* | |
1065 | * Root hub was already suspended. Disable IRQ emission and | |
1066 | * mark HW unaccessible. The PM and USB cores make sure that | |
1067 | * the root hub is either suspended or stopped. | |
1068 | */ | |
1069 | ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); | |
1070 | ||
1071 | spin_lock_irq(&ehci->lock); | |
1072 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
1073 | (void) ehci_readl(ehci, &ehci->regs->intr_enable); | |
1074 | ||
1075 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
1076 | spin_unlock_irq(&ehci->lock); | |
1077 | ||
1078 | return 0; | |
1079 | } | |
3e023203 | 1080 | EXPORT_SYMBOL_GPL(ehci_suspend); |
c5cf9212 AS |
1081 | |
1082 | /* Returns 0 if power was preserved, 1 if power was lost */ | |
3e023203 | 1083 | int ehci_resume(struct usb_hcd *hcd, bool hibernated) |
c5cf9212 AS |
1084 | { |
1085 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1086 | ||
1087 | if (time_before(jiffies, ehci->next_statechange)) | |
1088 | msleep(100); | |
1089 | ||
1090 | /* Mark hardware accessible again as we are back to full power by now */ | |
1091 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
1092 | ||
43fe3a99 AS |
1093 | if (ehci->shutdown) |
1094 | return 0; /* Controller is dead */ | |
1095 | ||
c5cf9212 AS |
1096 | /* |
1097 | * If CF is still set and we aren't resuming from hibernation | |
1098 | * then we maintained suspend power. | |
1099 | * Just undo the effect of ehci_suspend(). | |
1100 | */ | |
1101 | if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && | |
1102 | !hibernated) { | |
1103 | int mask = INTR_MASK; | |
1104 | ||
1105 | ehci_prepare_ports_for_controller_resume(ehci); | |
43fe3a99 AS |
1106 | |
1107 | spin_lock_irq(&ehci->lock); | |
1108 | if (ehci->shutdown) | |
1109 | goto skip; | |
1110 | ||
c5cf9212 AS |
1111 | if (!hcd->self.root_hub->do_remote_wakeup) |
1112 | mask &= ~STS_PCD; | |
1113 | ehci_writel(ehci, mask, &ehci->regs->intr_enable); | |
1114 | ehci_readl(ehci, &ehci->regs->intr_enable); | |
43fe3a99 AS |
1115 | skip: |
1116 | spin_unlock_irq(&ehci->lock); | |
c5cf9212 AS |
1117 | return 0; |
1118 | } | |
1119 | ||
1120 | /* | |
1121 | * Else reset, to cope with power loss or resume from hibernation | |
1122 | * having let the firmware kick in during reboot. | |
1123 | */ | |
1124 | usb_root_hub_lost_power(hcd->self.root_hub); | |
1125 | (void) ehci_halt(ehci); | |
1126 | (void) ehci_reset(ehci); | |
1127 | ||
43fe3a99 AS |
1128 | spin_lock_irq(&ehci->lock); |
1129 | if (ehci->shutdown) | |
1130 | goto skip; | |
1131 | ||
c5cf9212 AS |
1132 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
1133 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | |
1134 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1135 | ||
43fe3a99 AS |
1136 | ehci->rh_state = EHCI_RH_SUSPENDED; |
1137 | spin_unlock_irq(&ehci->lock); | |
1138 | ||
c5cf9212 AS |
1139 | return 1; |
1140 | } | |
3e023203 | 1141 | EXPORT_SYMBOL_GPL(ehci_resume); |
c5cf9212 AS |
1142 | |
1143 | #endif | |
1144 | ||
1145 | /*-------------------------------------------------------------------------*/ | |
1146 | ||
3e023203 AS |
1147 | /* |
1148 | * Generic structure: This gets copied for platform drivers so that | |
1149 | * individual entries can be overridden as needed. | |
1150 | */ | |
1151 | ||
1152 | static const struct hc_driver ehci_hc_driver = { | |
1153 | .description = hcd_name, | |
1154 | .product_desc = "EHCI Host Controller", | |
1155 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
1156 | ||
1157 | /* | |
1158 | * generic hardware linkage | |
1159 | */ | |
1160 | .irq = ehci_irq, | |
3b8d7321 | 1161 | .flags = HCD_MEMORY | HCD_USB2, |
3e023203 AS |
1162 | |
1163 | /* | |
1164 | * basic lifecycle operations | |
1165 | */ | |
1166 | .reset = ehci_setup, | |
1167 | .start = ehci_run, | |
1168 | .stop = ehci_stop, | |
1169 | .shutdown = ehci_shutdown, | |
1170 | ||
1171 | /* | |
1172 | * managing i/o requests and associated device resources | |
1173 | */ | |
1174 | .urb_enqueue = ehci_urb_enqueue, | |
1175 | .urb_dequeue = ehci_urb_dequeue, | |
1176 | .endpoint_disable = ehci_endpoint_disable, | |
1177 | .endpoint_reset = ehci_endpoint_reset, | |
1178 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | |
1179 | ||
1180 | /* | |
1181 | * scheduling support | |
1182 | */ | |
1183 | .get_frame_number = ehci_get_frame, | |
1184 | ||
1185 | /* | |
1186 | * root hub support | |
1187 | */ | |
1188 | .hub_status_data = ehci_hub_status_data, | |
1189 | .hub_control = ehci_hub_control, | |
1190 | .bus_suspend = ehci_bus_suspend, | |
1191 | .bus_resume = ehci_bus_resume, | |
1192 | .relinquish_port = ehci_relinquish_port, | |
1193 | .port_handed_over = ehci_port_handed_over, | |
1194 | }; | |
1195 | ||
1196 | void ehci_init_driver(struct hc_driver *drv, | |
1197 | const struct ehci_driver_overrides *over) | |
1198 | { | |
1199 | /* Copy the generic table to drv and then apply the overrides */ | |
1200 | *drv = ehci_hc_driver; | |
1201 | ||
1b36810e AS |
1202 | if (over) { |
1203 | drv->hcd_priv_size += over->extra_priv_size; | |
1204 | if (over->reset) | |
1205 | drv->reset = over->reset; | |
1206 | } | |
3e023203 AS |
1207 | } |
1208 | EXPORT_SYMBOL_GPL(ehci_init_driver); | |
1209 | ||
1210 | /*-------------------------------------------------------------------------*/ | |
1211 | ||
2b70f073 | 1212 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1213 | MODULE_AUTHOR (DRIVER_AUTHOR); |
1214 | MODULE_LICENSE ("GPL"); | |
1215 | ||
ba02978a | 1216 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 1217 | #include "ehci-fsl.c" |
01cced25 | 1218 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
1219 | #endif |
1220 | ||
60b0bf0f | 1221 | #ifdef CONFIG_USB_EHCI_SH |
63c84552 PM |
1222 | #include "ehci-sh.c" |
1223 | #define PLATFORM_DRIVER ehci_hcd_sh_driver | |
1224 | #endif | |
1225 | ||
ad75a410 GL |
1226 | #ifdef CONFIG_PPC_PS3 |
1227 | #include "ehci-ps3.c" | |
7a4eb7fd | 1228 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1229 | #endif |
1230 | ||
da0e8fb0 VB |
1231 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1232 | #include "ehci-ppc-of.c" | |
1233 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1234 | #endif | |
1235 | ||
08d3c18e JZ |
1236 | #ifdef CONFIG_XPS_USB_HCD_XILINX |
1237 | #include "ehci-xilinx-of.c" | |
1f23b2d9 | 1238 | #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver |
08d3c18e JZ |
1239 | #endif |
1240 | ||
586dfc8c WZ |
1241 | #ifdef CONFIG_USB_W90X900_EHCI |
1242 | #include "ehci-w90x900.c" | |
1243 | #define PLATFORM_DRIVER ehci_hcd_w90x900_driver | |
1244 | #endif | |
1245 | ||
1643accd DD |
1246 | #ifdef CONFIG_USB_OCTEON_EHCI |
1247 | #include "ehci-octeon.c" | |
1248 | #define PLATFORM_DRIVER ehci_octeon_driver | |
1249 | #endif | |
1250 | ||
47fc28bf CM |
1251 | #ifdef CONFIG_TILE_USB |
1252 | #include "ehci-tilegx.c" | |
1253 | #define PLATFORM_DRIVER ehci_hcd_tilegx_driver | |
1254 | #endif | |
1255 | ||
22ced687 A |
1256 | #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP |
1257 | #include "ehci-pmcmsp.c" | |
1258 | #define PLATFORM_DRIVER ehci_hcd_msp_driver | |
1259 | #endif | |
1260 | ||
9be03929 JA |
1261 | #ifdef CONFIG_SPARC_LEON |
1262 | #include "ehci-grlib.c" | |
1263 | #define PLATFORM_DRIVER ehci_grlib_driver | |
1264 | #endif | |
1265 | ||
3a082ec9 NZ |
1266 | #ifdef CONFIG_USB_EHCI_MV |
1267 | #include "ehci-mv.c" | |
1268 | #define PLATFORM_DRIVER ehci_mv_driver | |
1269 | #endif | |
f30cdbcb | 1270 | |
c256667f SH |
1271 | #ifdef CONFIG_MIPS_SEAD3 |
1272 | #include "ehci-sead3.c" | |
1273 | #define PLATFORM_DRIVER ehci_hcd_sead3_driver | |
1274 | #endif | |
1275 | ||
01cced25 KG |
1276 | static int __init ehci_hcd_init(void) |
1277 | { | |
1278 | int retval = 0; | |
1279 | ||
2b70f073 AS |
1280 | if (usb_disabled()) |
1281 | return -ENODEV; | |
1282 | ||
1283 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); | |
9beeee65 AS |
1284 | set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
1285 | if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || | |
1286 | test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) | |
1287 | printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" | |
1288 | " before uhci_hcd and ohci_hcd, not after\n"); | |
1289 | ||
01cced25 KG |
1290 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", |
1291 | hcd_name, | |
1292 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1293 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1294 | ||
1512c91f | 1295 | #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) |
08f4e586 | 1296 | ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); |
9beeee65 AS |
1297 | if (!ehci_debug_root) { |
1298 | retval = -ENOENT; | |
1299 | goto err_debug; | |
1300 | } | |
694cc208 TJ |
1301 | #endif |
1302 | ||
01cced25 KG |
1303 | #ifdef PLATFORM_DRIVER |
1304 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1305 | if (retval < 0) |
1306 | goto clean0; | |
01cced25 KG |
1307 | #endif |
1308 | ||
ad75a410 | 1309 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1310 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1311 | if (retval < 0) |
1312 | goto clean2; | |
694cc208 | 1313 | #endif |
da0e8fb0 VB |
1314 | |
1315 | #ifdef OF_PLATFORM_DRIVER | |
d35fb641 | 1316 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1317 | if (retval < 0) |
1318 | goto clean3; | |
1319 | #endif | |
1f23b2d9 GL |
1320 | |
1321 | #ifdef XILINX_OF_PLATFORM_DRIVER | |
d35fb641 | 1322 | retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); |
1f23b2d9 GL |
1323 | if (retval < 0) |
1324 | goto clean4; | |
1325 | #endif | |
da0e8fb0 VB |
1326 | return retval; |
1327 | ||
1f23b2d9 | 1328 | #ifdef XILINX_OF_PLATFORM_DRIVER |
d35fb641 | 1329 | /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ |
1f23b2d9 GL |
1330 | clean4: |
1331 | #endif | |
da0e8fb0 | 1332 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1333 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1334 | clean3: |
1335 | #endif | |
1336 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1337 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1338 | clean2: | |
ad75a410 | 1339 | #endif |
da0e8fb0 VB |
1340 | #ifdef PLATFORM_DRIVER |
1341 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1342 | clean0: | |
1343 | #endif | |
1512c91f | 1344 | #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) |
da0e8fb0 VB |
1345 | debugfs_remove(ehci_debug_root); |
1346 | ehci_debug_root = NULL; | |
9beeee65 | 1347 | err_debug: |
a9b6148d | 1348 | #endif |
9beeee65 | 1349 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1350 | return retval; |
1351 | } | |
1352 | module_init(ehci_hcd_init); | |
1353 | ||
1354 | static void __exit ehci_hcd_cleanup(void) | |
1355 | { | |
1f23b2d9 | 1356 | #ifdef XILINX_OF_PLATFORM_DRIVER |
d35fb641 | 1357 | platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); |
1f23b2d9 | 1358 | #endif |
da0e8fb0 | 1359 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1360 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
da0e8fb0 | 1361 | #endif |
01cced25 KG |
1362 | #ifdef PLATFORM_DRIVER |
1363 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1364 | #endif | |
ad75a410 | 1365 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1366 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1367 | #endif |
1512c91f | 1368 | #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) |
694cc208 TJ |
1369 | debugfs_remove(ehci_debug_root); |
1370 | #endif | |
9beeee65 | 1371 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1372 | } |
1373 | module_exit(ehci_hcd_cleanup); |