USB: fix race between root-hub suspend and remote wakeup
[deliverable/linux.git] / drivers / usb / host / ehci-hcd.c
CommitLineData
1da177e4 1/*
578333ab
AS
2 * Enhanced Host Controller Interface (EHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
1da177e4 6 * Copyright (c) 2000-2004 by David Brownell
53bd6a60 7 *
1da177e4
LT
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
1da177e4
LT
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/dmapool.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
3c04e20e 30#include <linux/vmalloc.h>
1da177e4
LT
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/timer.h>
ee4ecb8a 34#include <linux/ktime.h>
1da177e4
LT
35#include <linux/list.h>
36#include <linux/interrupt.h>
1da177e4 37#include <linux/usb.h>
27729aad 38#include <linux/usb/hcd.h>
1da177e4
LT
39#include <linux/moduleparam.h>
40#include <linux/dma-mapping.h>
694cc208 41#include <linux/debugfs.h>
5a0e3ad6 42#include <linux/slab.h>
aa4d8342 43#include <linux/uaccess.h>
1da177e4 44
1da177e4
LT
45#include <asm/byteorder.h>
46#include <asm/io.h>
47#include <asm/irq.h>
1da177e4 48#include <asm/unaligned.h>
1da177e4 49
df7c1ca2
GL
50#if defined(CONFIG_PPC_PS3)
51#include <asm/firmware.h>
52#endif
53
1da177e4
LT
54/*-------------------------------------------------------------------------*/
55
56/*
57 * EHCI hc_driver implementation ... experimental, incomplete.
58 * Based on the final 1.0 register interface specification.
59 *
60 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
61 * First was PCMCIA, like ISA; then CardBus, which is PCI.
62 * Next comes "CardBay", using USB 2.0 signals.
63 *
64 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
65 * Special thanks to Intel and VIA for providing host controllers to
66 * test this driver on, and Cypress (including In-System Design) for
67 * providing early devices for those host controllers to talk to!
1da177e4
LT
68 */
69
1da177e4
LT
70#define DRIVER_AUTHOR "David Brownell"
71#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
72
73static const char hcd_name [] = "ehci_hcd";
74
75
9776afc8 76#undef VERBOSE_DEBUG
1da177e4
LT
77#undef EHCI_URB_TRACE
78
79#ifdef DEBUG
80#define EHCI_STATS
81#endif
82
83/* magic numbers that can affect system performance */
84#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
85#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
86#define EHCI_TUNE_RL_TT 0
87#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
88#define EHCI_TUNE_MULT_TT 1
ffda0803
AS
89/*
90 * Some drivers think it's safe to schedule isochronous transfers more than
91 * 256 ms into the future (partly as a result of an old bug in the scheduling
92 * code). In an attempt to avoid trouble, we will use a minimum scheduling
93 * length of 512 frames instead of 256.
94 */
95#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
1da177e4 96
07d29b63 97#define EHCI_IAA_MSECS 10 /* arbitrary */
1da177e4
LT
98#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
99#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
004c1968 100#define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1)
fcda37cb 101 /* 5-ms async qh unlink delay */
1da177e4
LT
102
103/* Initial IRQ latency: faster than hw default */
104static int log2_irq_thresh = 0; // 0 to 6
105module_param (log2_irq_thresh, int, S_IRUGO);
106MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
107
108/* initial park setting: slower than hw default */
109static unsigned park = 0;
110module_param (park, uint, S_IRUGO);
111MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
112
93f1a47c 113/* for flakey hardware, ignore overcurrent indicators */
90ab5ee9 114static bool ignore_oc = 0;
93f1a47c
DB
115module_param (ignore_oc, bool, S_IRUGO);
116MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
117
48f24970
AD
118/* for link power management(LPM) feature */
119static unsigned int hird;
120module_param(hird, int, S_IRUGO);
cc556871 121MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
48f24970 122
1da177e4
LT
123#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
124
125/*-------------------------------------------------------------------------*/
126
127#include "ehci.h"
128#include "ehci-dbg.c"
ad93562b 129#include "pci-quirks.h"
1da177e4
LT
130
131/*-------------------------------------------------------------------------*/
132
bc29847e
AS
133static void
134timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
135{
136 /* Don't override timeouts which shrink or (later) disable
137 * the async ring; just the I/O watchdog. Note that if a
138 * SHRINK were pending, OFF would never be requested.
139 */
140 if (timer_pending(&ehci->watchdog)
141 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
142 & ehci->actions))
143 return;
144
145 if (!test_and_set_bit(action, &ehci->actions)) {
146 unsigned long t;
147
148 switch (action) {
149 case TIMER_IO_WATCHDOG:
403dbd36
AD
150 if (!ehci->need_io_watchdog)
151 return;
bc29847e
AS
152 t = EHCI_IO_JIFFIES;
153 break;
154 case TIMER_ASYNC_OFF:
155 t = EHCI_ASYNC_JIFFIES;
156 break;
157 /* case TIMER_ASYNC_SHRINK: */
158 default:
004c1968 159 t = EHCI_SHRINK_JIFFIES;
bc29847e
AS
160 break;
161 }
162 mod_timer(&ehci->watchdog, t + jiffies);
163 }
164}
165
166/*-------------------------------------------------------------------------*/
167
1da177e4
LT
168/*
169 * handshake - spin reading hc until handshake completes or fails
170 * @ptr: address of hc register to be read
171 * @mask: bits to look at in result of read
172 * @done: value of those bits when handshake succeeds
173 * @usec: timeout in microseconds
174 *
175 * Returns negative errno, or zero on success
176 *
177 * Success happens when the "mask" bits have the specified value (hardware
178 * handshake done). There are two failure modes: "usec" have passed (major
179 * hardware flakeout), or the register reads as all-ones (hardware removed).
180 *
181 * That last failure should_only happen in cases like physical cardbus eject
182 * before driver shutdown. But it also seems to be caused by bugs in cardbus
183 * bridge shutdown: shutting down the bridge before the devices using it.
184 */
083522d7
BH
185static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
186 u32 mask, u32 done, int usec)
1da177e4
LT
187{
188 u32 result;
189
190 do {
083522d7 191 result = ehci_readl(ehci, ptr);
1da177e4
LT
192 if (result == ~(u32)0) /* card removed */
193 return -ENODEV;
194 result &= mask;
195 if (result == done)
196 return 0;
197 udelay (1);
198 usec--;
199 } while (usec > 0);
200 return -ETIMEDOUT;
201}
202
65fd4272
MC
203/* check TDI/ARC silicon is in host mode */
204static int tdi_in_host_mode (struct ehci_hcd *ehci)
205{
206 u32 __iomem *reg_ptr;
207 u32 tmp;
208
209 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
210 tmp = ehci_readl(ehci, reg_ptr);
211 return (tmp & 3) == USBMODE_CM_HC;
212}
213
1da177e4
LT
214/* force HC to halt state from unknown (EHCI spec section 2.3) */
215static int ehci_halt (struct ehci_hcd *ehci)
216{
083522d7 217 u32 temp = ehci_readl(ehci, &ehci->regs->status);
1da177e4 218
72f30b6f 219 /* disable any irqs left enabled by previous code */
083522d7 220 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
72f30b6f 221
65fd4272
MC
222 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
223 return 0;
224 }
225
1da177e4
LT
226 if ((temp & STS_HALT) != 0)
227 return 0;
228
083522d7 229 temp = ehci_readl(ehci, &ehci->regs->command);
1da177e4 230 temp &= ~CMD_RUN;
083522d7
BH
231 ehci_writel(ehci, temp, &ehci->regs->command);
232 return handshake (ehci, &ehci->regs->status,
233 STS_HALT, STS_HALT, 16 * 125);
1da177e4
LT
234}
235
df7c1ca2
GL
236#if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3)
237
238/*
239 * The EHCI controller of the Cell Super Companion Chip used in the
240 * PS3 will stop the root hub after all root hub ports are suspended.
241 * When in this condition handshake will return -ETIMEDOUT. The
242 * STS_HLT bit will not be set, so inspection of the frame index is
243 * used here to test for the condition. If the condition is found
244 * return success to allow the USB suspend to complete.
245 */
246
247static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
248 void __iomem *ptr, u32 mask, u32 done,
249 int usec)
250{
251 unsigned int old_index;
252 int error;
253
254 if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
255 return -ETIMEDOUT;
256
257 old_index = ehci_read_frame_index(ehci);
258
259 error = handshake(ehci, ptr, mask, done, usec);
260
261 if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index)
262 return 0;
263
264 return error;
265}
266
267#else
268
269static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
270 void __iomem *ptr, u32 mask, u32 done,
271 int usec)
272{
273 return -ETIMEDOUT;
274}
275
276#endif
277
0bcfeb3e
DB
278static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
279 u32 mask, u32 done, int usec)
280{
281 int error;
282
283 error = handshake(ehci, ptr, mask, done, usec);
df7c1ca2
GL
284 if (error == -ETIMEDOUT)
285 error = handshake_for_broken_root_hub(ehci, ptr, mask, done,
286 usec);
287
0bcfeb3e
DB
288 if (error) {
289 ehci_halt(ehci);
e8799906 290 ehci->rh_state = EHCI_RH_HALTED;
65cb76ba 291 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
0bcfeb3e
DB
292 ptr, mask, done, error);
293 }
294
295 return error;
296}
297
1da177e4
LT
298/* put TDI/ARC silicon into EHCI mode */
299static void tdi_reset (struct ehci_hcd *ehci)
300{
301 u32 __iomem *reg_ptr;
302 u32 tmp;
303
d23a1377 304 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
083522d7 305 tmp = ehci_readl(ehci, reg_ptr);
d23a1377
VB
306 tmp |= USBMODE_CM_HC;
307 /* The default byte access to MMR space is LE after
308 * controller reset. Set the required endian mode
309 * for transfer buffers to match the host microprocessor
310 */
311 if (ehci_big_endian_mmio(ehci))
312 tmp |= USBMODE_BE;
083522d7 313 ehci_writel(ehci, tmp, reg_ptr);
1da177e4
LT
314}
315
316/* reset a non-running (STS_HALT == 1) controller */
317static int ehci_reset (struct ehci_hcd *ehci)
318{
319 int retval;
083522d7 320 u32 command = ehci_readl(ehci, &ehci->regs->command);
1da177e4 321
8d053c79
JW
322 /* If the EHCI debug controller is active, special care must be
323 * taken before and after a host controller reset */
324 if (ehci->debug && !dbgp_reset_prep())
325 ehci->debug = NULL;
326
1da177e4
LT
327 command |= CMD_RESET;
328 dbg_cmd (ehci, "reset", command);
083522d7 329 ehci_writel(ehci, command, &ehci->regs->command);
e8799906 330 ehci->rh_state = EHCI_RH_HALTED;
1da177e4 331 ehci->next_statechange = jiffies;
083522d7
BH
332 retval = handshake (ehci, &ehci->regs->command,
333 CMD_RESET, 0, 250 * 1000);
1da177e4 334
331ac6b2
AD
335 if (ehci->has_hostpc) {
336 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
337 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
338 ehci_writel(ehci, TXFIFO_DEFAULT,
339 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
340 }
1da177e4
LT
341 if (retval)
342 return retval;
343
344 if (ehci_is_TDI(ehci))
345 tdi_reset (ehci);
346
8d053c79
JW
347 if (ehci->debug)
348 dbgp_external_startup();
349
1da177e4
LT
350 return retval;
351}
352
353/* idle the controller (from running) */
354static void ehci_quiesce (struct ehci_hcd *ehci)
355{
356 u32 temp;
357
358#ifdef DEBUG
e8799906 359 if (ehci->rh_state != EHCI_RH_RUNNING)
1da177e4
LT
360 BUG ();
361#endif
362
363 /* wait for any schedule enables/disables to take effect */
083522d7 364 temp = ehci_readl(ehci, &ehci->regs->command) << 10;
1da177e4 365 temp &= STS_ASS | STS_PSS;
c765d4ca
KW
366 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
367 STS_ASS | STS_PSS, temp, 16 * 125))
1da177e4 368 return;
1da177e4
LT
369
370 /* then disable anything that's still active */
083522d7 371 temp = ehci_readl(ehci, &ehci->regs->command);
1da177e4 372 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
083522d7 373 ehci_writel(ehci, temp, &ehci->regs->command);
1da177e4
LT
374
375 /* hardware can take 16 microframes to turn off ... */
c765d4ca
KW
376 handshake_on_error_set_halt(ehci, &ehci->regs->status,
377 STS_ASS | STS_PSS, 0, 16 * 125);
1da177e4
LT
378}
379
380/*-------------------------------------------------------------------------*/
381
07d29b63 382static void end_unlink_async(struct ehci_hcd *ehci);
7d12e780 383static void ehci_work(struct ehci_hcd *ehci);
1da177e4
LT
384
385#include "ehci-hub.c"
48f24970 386#include "ehci-lpm.c"
1da177e4
LT
387#include "ehci-mem.c"
388#include "ehci-q.c"
389#include "ehci-sched.c"
4c67045b 390#include "ehci-sysfs.c"
1da177e4
LT
391
392/*-------------------------------------------------------------------------*/
393
07d29b63 394static void ehci_iaa_watchdog(unsigned long param)
1da177e4
LT
395{
396 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
397 unsigned long flags;
398
399 spin_lock_irqsave (&ehci->lock, flags);
400
e82cc128
DB
401 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
402 * So we need this watchdog, but must protect it against both
403 * (a) SMP races against real IAA firing and retriggering, and
404 * (b) clean HC shutdown, when IAA watchdog was pending.
405 */
406 if (ehci->reclaim
407 && !timer_pending(&ehci->iaa_watchdog)
e8799906 408 && ehci->rh_state == EHCI_RH_RUNNING) {
e82cc128
DB
409 u32 cmd, status;
410
411 /* If we get here, IAA is *REALLY* late. It's barely
412 * conceivable that the system is so busy that CMD_IAAD
413 * is still legitimately set, so let's be sure it's
414 * clear before we read STS_IAA. (The HC should clear
415 * CMD_IAAD when it sets STS_IAA.)
416 */
417 cmd = ehci_readl(ehci, &ehci->regs->command);
418 if (cmd & CMD_IAAD)
419 ehci_writel(ehci, cmd & ~CMD_IAAD,
420 &ehci->regs->command);
421
422 /* If IAA is set here it either legitimately triggered
423 * before we cleared IAAD above (but _way_ late, so we'll
424 * still count it as lost) ... or a silicon erratum:
425 * - VIA seems to set IAA without triggering the IRQ;
426 * - IAAD potentially cleared without setting IAA.
427 */
428 status = ehci_readl(ehci, &ehci->regs->status);
429 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
1da177e4 430 COUNT (ehci->stats.lost_iaa);
083522d7 431 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
1da177e4 432 }
e82cc128
DB
433
434 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
435 status, cmd);
07d29b63 436 end_unlink_async(ehci);
1da177e4
LT
437 }
438
07d29b63
AS
439 spin_unlock_irqrestore(&ehci->lock, flags);
440}
441
442static void ehci_watchdog(unsigned long param)
443{
444 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
445 unsigned long flags;
446
447 spin_lock_irqsave(&ehci->lock, flags);
448
449 /* stop async processing after it's idled a bit */
1da177e4 450 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
26f953fd 451 start_unlink_async (ehci, ehci->async);
1da177e4
LT
452
453 /* ehci could run by timer, without IRQs ... */
7d12e780 454 ehci_work (ehci);
1da177e4
LT
455
456 spin_unlock_irqrestore (&ehci->lock, flags);
457}
458
8903795a
AS
459/* On some systems, leaving remote wakeup enabled prevents system shutdown.
460 * The firmware seems to think that powering off is a wakeup event!
461 * This routine turns off remote wakeup and everything else, on all ports.
462 */
463static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
464{
465 int port = HCS_N_PORTS(ehci->hcs_params);
466
467 while (port--)
468 ehci_writel(ehci, PORT_RWC_BITS,
469 &ehci->regs->port_status[port]);
470}
471
21da84a8
SS
472/*
473 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
474 * Should be called with ehci->lock held.
72f30b6f 475 */
21da84a8 476static void ehci_silence_controller(struct ehci_hcd *ehci)
1da177e4 477{
21da84a8 478 ehci_halt(ehci);
8903795a 479 ehci_turn_off_all_ports(ehci);
1da177e4
LT
480
481 /* make BIOS/etc use companion controller during reboot */
083522d7 482 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
8903795a
AS
483
484 /* unblock posted writes */
485 ehci_readl(ehci, &ehci->regs->configured_flag);
1da177e4
LT
486}
487
21da84a8
SS
488/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
489 * This forcibly disables dma and IRQs, helping kexec and other cases
490 * where the next system software may expect clean state.
491 */
492static void ehci_shutdown(struct usb_hcd *hcd)
493{
494 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
495
496 del_timer_sync(&ehci->watchdog);
497 del_timer_sync(&ehci->iaa_watchdog);
498
499 spin_lock_irq(&ehci->lock);
500 ehci_silence_controller(ehci);
501 spin_unlock_irq(&ehci->lock);
502}
503
56c1e26d
DB
504static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
505{
506 unsigned port;
507
508 if (!HCS_PPC (ehci->hcs_params))
509 return;
510
511 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
512 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
513 (void) ehci_hub_control(ehci_to_hcd(ehci),
514 is_on ? SetPortFeature : ClearPortFeature,
515 USB_PORT_FEAT_POWER,
516 port--, NULL, 0);
383975d7
AS
517 /* Flush those writes */
518 ehci_readl(ehci, &ehci->regs->command);
56c1e26d
DB
519 msleep(20);
520}
521
7ff71d6a 522/*-------------------------------------------------------------------------*/
1da177e4 523
7ff71d6a
MP
524/*
525 * ehci_work is called from some interrupts, timers, and so on.
526 * it calls driver completion functions, after dropping ehci->lock.
527 */
7d12e780 528static void ehci_work (struct ehci_hcd *ehci)
7ff71d6a
MP
529{
530 timer_action_done (ehci, TIMER_IO_WATCHDOG);
7ff71d6a
MP
531
532 /* another CPU may drop ehci->lock during a schedule scan while
533 * it reports urb completions. this flag guards against bogus
534 * attempts at re-entrant schedule scanning.
535 */
536 if (ehci->scanning)
537 return;
538 ehci->scanning = 1;
7d12e780 539 scan_async (ehci);
7ff71d6a 540 if (ehci->next_uframe != -1)
7d12e780 541 scan_periodic (ehci);
7ff71d6a
MP
542 ehci->scanning = 0;
543
544 /* the IO watchdog guards against hardware or driver bugs that
545 * misplace IRQs, and should let us run completely without IRQs.
546 * such lossage has been observed on both VT6202 and VT8235.
547 */
e8799906 548 if (ehci->rh_state == EHCI_RH_RUNNING &&
7ff71d6a
MP
549 (ehci->async->qh_next.ptr != NULL ||
550 ehci->periodic_sched != 0))
551 timer_action (ehci, TIMER_IO_WATCHDOG);
552}
1da177e4 553
21da84a8
SS
554/*
555 * Called when the ehci_hcd module is removed.
556 */
7ff71d6a 557static void ehci_stop (struct usb_hcd *hcd)
1da177e4
LT
558{
559 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1da177e4 560
7ff71d6a 561 ehci_dbg (ehci, "stop\n");
1da177e4 562
7ff71d6a
MP
563 /* no more interrupts ... */
564 del_timer_sync (&ehci->watchdog);
07d29b63 565 del_timer_sync(&ehci->iaa_watchdog);
56c1e26d 566
7ff71d6a 567 spin_lock_irq(&ehci->lock);
e8799906 568 if (ehci->rh_state == EHCI_RH_RUNNING)
7ff71d6a 569 ehci_quiesce (ehci);
1da177e4 570
21da84a8 571 ehci_silence_controller(ehci);
7ff71d6a 572 ehci_reset (ehci);
7ff71d6a 573 spin_unlock_irq(&ehci->lock);
1da177e4 574
4c67045b 575 remove_sysfs_files(ehci);
7ff71d6a 576 remove_debug_files (ehci);
1da177e4 577
7ff71d6a
MP
578 /* root hub is shut down separately (first, when possible) */
579 spin_lock_irq (&ehci->lock);
580 if (ehci->async)
7d12e780 581 ehci_work (ehci);
7ff71d6a
MP
582 spin_unlock_irq (&ehci->lock);
583 ehci_mem_cleanup (ehci);
1da177e4 584
ad93562b
AX
585 if (ehci->amd_pll_fix == 1)
586 usb_amd_dev_put();
05570297 587
7ff71d6a
MP
588#ifdef EHCI_STATS
589 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
590 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
591 ehci->stats.lost_iaa);
592 ehci_dbg (ehci, "complete %ld unlink %ld\n",
593 ehci->stats.complete, ehci->stats.unlink);
1da177e4 594#endif
1da177e4 595
083522d7
BH
596 dbg_status (ehci, "ehci_stop completed",
597 ehci_readl(ehci, &ehci->regs->status));
1da177e4
LT
598}
599
18807521
DB
600/* one-time init, only for memory state */
601static int ehci_init(struct usb_hcd *hcd)
1da177e4 602{
18807521 603 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1da177e4 604 u32 temp;
1da177e4
LT
605 int retval;
606 u32 hcc_params;
3807e26d 607 struct ehci_qh_hw *hw;
18807521
DB
608
609 spin_lock_init(&ehci->lock);
610
403dbd36
AD
611 /*
612 * keep io watchdog by default, those good HCDs could turn off it later
613 */
614 ehci->need_io_watchdog = 1;
18807521
DB
615 init_timer(&ehci->watchdog);
616 ehci->watchdog.function = ehci_watchdog;
617 ehci->watchdog.data = (unsigned long) ehci;
1da177e4 618
07d29b63
AS
619 init_timer(&ehci->iaa_watchdog);
620 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
621 ehci->iaa_watchdog.data = (unsigned long) ehci;
622
f75593ce
AS
623 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
624
cc62a7eb
KS
625 /*
626 * by default set standard 80% (== 100 usec/uframe) max periodic
627 * bandwidth as required by USB 2.0
628 */
629 ehci->uframe_periodic_max = 100;
630
1da177e4
LT
631 /*
632 * hw default: 1K periodic list heads, one per frame.
633 * periodic_size can shrink by USBCMD update if hcc_params allows.
634 */
635 ehci->periodic_size = DEFAULT_I_TDPS;
9aa09d2f 636 INIT_LIST_HEAD(&ehci->cached_itd_list);
0e5f231b 637 INIT_LIST_HEAD(&ehci->cached_sitd_list);
f75593ce
AS
638
639 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
640 /* periodic schedule size can be smaller than default */
641 switch (EHCI_TUNE_FLS) {
642 case 0: ehci->periodic_size = 1024; break;
643 case 1: ehci->periodic_size = 512; break;
644 case 2: ehci->periodic_size = 256; break;
645 default: BUG();
646 }
647 }
18807521 648 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
1da177e4
LT
649 return retval;
650
651 /* controllers may cache some of the periodic schedule ... */
53bd6a60 652 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
dccd574c 653 ehci->i_thresh = 2 + 8;
1da177e4 654 else // N microframes cached
18807521 655 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
1da177e4
LT
656
657 ehci->reclaim = NULL;
1da177e4 658 ehci->next_uframe = -1;
9aa09d2f 659 ehci->clock_frame = -1;
1da177e4 660
1da177e4
LT
661 /*
662 * dedicate a qh for the async ring head, since we couldn't unlink
663 * a 'real' qh without stopping the async schedule [4.8]. use it
664 * as the 'reclamation list head' too.
665 * its dummy is used in hw_alt_next of many tds, to prevent the qh
666 * from automatically advancing to the next td after short reads.
667 */
18807521 668 ehci->async->qh_next.qh = NULL;
3807e26d
AD
669 hw = ehci->async->hw;
670 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
671 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
aaa0ef28 672 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */
3807e26d
AD
673 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
674 hw->hw_qtd_next = EHCI_LIST_END(ehci);
18807521 675 ehci->async->qh_state = QH_STATE_LINKED;
3807e26d 676 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
1da177e4
LT
677
678 /* clear interrupt enables, set irq latency */
679 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
680 log2_irq_thresh = 0;
681 temp = 1 << (16 + log2_irq_thresh);
5a9cdf33
AD
682 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
683 ehci->has_ppcd = 1;
684 ehci_dbg(ehci, "enable per-port change event\n");
685 temp |= CMD_PPCEE;
686 }
1da177e4
LT
687 if (HCC_CANPARK(hcc_params)) {
688 /* HW default park == 3, on hardware that supports it (like
689 * NVidia and ALI silicon), maximizes throughput on the async
690 * schedule by avoiding QH fetches between transfers.
691 *
692 * With fast usb storage devices and NForce2, "park" seems to
693 * make problems: throughput reduction (!), data errors...
694 */
695 if (park) {
18807521 696 park = min(park, (unsigned) 3);
1da177e4
LT
697 temp |= CMD_PARK;
698 temp |= park << 8;
699 }
18807521 700 ehci_dbg(ehci, "park %d\n", park);
1da177e4 701 }
18807521 702 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
1da177e4
LT
703 /* periodic schedule size can be smaller than default */
704 temp &= ~(3 << 2);
705 temp |= (EHCI_TUNE_FLS << 2);
1da177e4 706 }
48f24970
AD
707 if (HCC_LPM(hcc_params)) {
708 /* support link power management EHCI 1.1 addendum */
709 ehci_dbg(ehci, "support lpm\n");
710 ehci->has_lpm = 1;
711 if (hird > 0xf) {
712 ehci_dbg(ehci, "hird %d invalid, use default 0",
713 hird);
714 hird = 0;
715 }
716 temp |= hird << 24;
717 }
18807521
DB
718 ehci->command = temp;
719
40f8db8f 720 /* Accept arbitrarily long scatter-gather lists */
4307a28e
AR
721 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
722 hcd->self.sg_tablesize = ~0;
18807521
DB
723 return 0;
724}
725
726/* start HC running; it's halted, ehci_init() has been run (once) */
727static int ehci_run (struct usb_hcd *hcd)
728{
729 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
18807521
DB
730 u32 temp;
731 u32 hcc_params;
732
1d619f12 733 hcd->uses_new_polling = 1;
1d619f12 734
18807521 735 /* EHCI spec section 4.1 */
876e0df9 736
083522d7
BH
737 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
738 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
18807521
DB
739
740 /*
741 * hcc_params controls whether ehci->regs->segment must (!!!)
742 * be used; it constrains QH/ITD/SITD and QTD locations.
743 * pci_pool consistent memory always uses segment zero.
744 * streaming mappings for I/O buffers, like pci_map_single(),
745 * can return segments above 4GB, if the device allows.
746 *
747 * NOTE: the dma mask is visible through dma_supported(), so
748 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
749 * Scsi_Host.highmem_io, and so forth. It's readonly to all
750 * host side drivers though.
751 */
083522d7 752 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
18807521 753 if (HCC_64BIT_ADDR(hcc_params)) {
083522d7 754 ehci_writel(ehci, 0, &ehci->regs->segment);
18807521
DB
755#if 0
756// this is deeply broken on almost all architectures
6a35528a 757 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
18807521
DB
758 ehci_info(ehci, "enabled 64bit DMA\n");
759#endif
760 }
761
762
1da177e4
LT
763 // Philips, Intel, and maybe others need CMD_RUN before the
764 // root hub will detect new devices (why?); NEC doesn't
18807521
DB
765 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
766 ehci->command |= CMD_RUN;
083522d7 767 ehci_writel(ehci, ehci->command, &ehci->regs->command);
18807521 768 dbg_cmd (ehci, "init", ehci->command);
1da177e4 769
1da177e4
LT
770 /*
771 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
772 * are explicitly handed to companion controller(s), so no TT is
773 * involved with the root hub. (Except where one is integrated,
774 * and there's no companion controller unless maybe for USB OTG.)
32fe0198
AS
775 *
776 * Turning on the CF flag will transfer ownership of all ports
777 * from the companions to the EHCI controller. If any of the
778 * companions are in the middle of a port reset at the time, it
779 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
1cb52658
DB
780 * guarantees that no resets are in progress. After we set CF,
781 * a short delay lets the hardware catch up; new resets shouldn't
782 * be started before the port switching actions could complete.
1da177e4 783 */
32fe0198 784 down_write(&ehci_cf_port_reset_rwsem);
e8799906 785 ehci->rh_state = EHCI_RH_RUNNING;
083522d7
BH
786 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
787 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1cb52658 788 msleep(5);
32fe0198 789 up_write(&ehci_cf_port_reset_rwsem);
ee4ecb8a 790 ehci->last_periodic_enable = ktime_get_real();
1da177e4 791
c430131a 792 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
1da177e4 793 ehci_info (ehci,
2b70f073 794 "USB %x.%x started, EHCI %x.%02x%s\n",
7ff71d6a 795 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
2b70f073 796 temp >> 8, temp & 0xff,
93f1a47c 797 ignore_oc ? ", overcurrent ignored" : "");
1da177e4 798
083522d7
BH
799 ehci_writel(ehci, INTR_MASK,
800 &ehci->regs->intr_enable); /* Turn On Interrupts */
1da177e4 801
18807521
DB
802 /* GRR this is run-once init(), being done every time the HC starts.
803 * So long as they're part of class devices, we can't do it init()
804 * since the class device isn't created that early.
805 */
806 create_debug_files(ehci);
4c67045b 807 create_sysfs_files(ehci);
1da177e4
LT
808
809 return 0;
810}
811
2093c6b4
MC
812static int __maybe_unused ehci_setup (struct usb_hcd *hcd)
813{
814 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
815 int retval;
816
817 ehci->regs = (void __iomem *)ehci->caps +
818 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
819 dbg_hcs_params(ehci, "reset");
820 dbg_hcc_params(ehci, "reset");
821
822 /* cache this readonly data; minimize chip reads */
823 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
824
825 ehci->sbrn = HCD_USB2;
826
827 retval = ehci_halt(ehci);
828 if (retval)
829 return retval;
830
831 /* data structure init */
832 retval = ehci_init(hcd);
833 if (retval)
834 return retval;
835
836 ehci_reset(ehci);
837
838 return 0;
839}
840
1da177e4
LT
841/*-------------------------------------------------------------------------*/
842
7d12e780 843static irqreturn_t ehci_irq (struct usb_hcd *hcd)
1da177e4
LT
844{
845 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
67b2e029 846 u32 status, masked_status, pcd_status = 0, cmd;
1da177e4
LT
847 int bh;
848
849 spin_lock (&ehci->lock);
850
083522d7 851 status = ehci_readl(ehci, &ehci->regs->status);
1da177e4
LT
852
853 /* e.g. cardbus physical eject */
854 if (status == ~(u32) 0) {
855 ehci_dbg (ehci, "device removed\n");
856 goto dead;
857 }
858
69fff59d 859 /* Shared IRQ? */
67b2e029 860 masked_status = status & INTR_MASK;
e8799906 861 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
1da177e4
LT
862 spin_unlock(&ehci->lock);
863 return IRQ_NONE;
864 }
865
866 /* clear (just) interrupts */
67b2e029 867 ehci_writel(ehci, masked_status, &ehci->regs->status);
e82cc128 868 cmd = ehci_readl(ehci, &ehci->regs->command);
1da177e4
LT
869 bh = 0;
870
9776afc8 871#ifdef VERBOSE_DEBUG
1da177e4
LT
872 /* unrequested/ignored: Frame List Rollover */
873 dbg_status (ehci, "irq", status);
874#endif
875
876 /* INT, ERR, and IAA interrupt rates can be throttled */
877
878 /* normal [4.15.1.2] or error [4.15.1.1] completion */
879 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
880 if (likely ((status & STS_ERR) == 0))
881 COUNT (ehci->stats.normal);
882 else
883 COUNT (ehci->stats.error);
884 bh = 1;
885 }
886
887 /* complete the unlinking of some qh [4.15.2.3] */
888 if (status & STS_IAA) {
e82cc128
DB
889 /* guard against (alleged) silicon errata */
890 if (cmd & CMD_IAAD) {
891 ehci_writel(ehci, cmd & ~CMD_IAAD,
892 &ehci->regs->command);
893 ehci_dbg(ehci, "IAA with IAAD still set?\n");
894 }
895 if (ehci->reclaim) {
896 COUNT(ehci->stats.reclaim);
897 end_unlink_async(ehci);
898 } else
899 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
1da177e4
LT
900 }
901
902 /* remote wakeup [4.3.1] */
d97cc2f2 903 if (status & STS_PCD) {
1da177e4 904 unsigned i = HCS_N_PORTS (ehci->hcs_params);
5a9cdf33 905 u32 ppcd = 0;
d1b1842c
DB
906
907 /* kick root hub later */
1d619f12 908 pcd_status = status;
1da177e4
LT
909
910 /* resume root hub? */
eafe5b99 911 if (!(cmd & CMD_RUN))
8c03356a 912 usb_hcd_resume_root_hub(hcd);
1da177e4 913
5a9cdf33
AD
914 /* get per-port change detect bits */
915 if (ehci->has_ppcd)
916 ppcd = status >> 16;
917
1da177e4 918 while (i--) {
5a9cdf33
AD
919 int pstatus;
920
921 /* leverage per-port change bits feature */
922 if (ehci->has_ppcd && !(ppcd & (1 << i)))
923 continue;
924 pstatus = ehci_readl(ehci,
925 &ehci->regs->port_status[i]);
b972b68c
DB
926
927 if (pstatus & PORT_OWNER)
1da177e4 928 continue;
eafe5b99
AS
929 if (!(test_bit(i, &ehci->suspended_ports) &&
930 ((pstatus & PORT_RESUME) ||
931 !(pstatus & PORT_SUSPEND)) &&
932 (pstatus & PORT_PE) &&
933 ehci->reset_done[i] == 0))
1da177e4
LT
934 continue;
935
936 /* start 20 msec resume signaling from this port,
937 * and make khubd collect PORT_STAT_C_SUSPEND to
49d0f078
AS
938 * stop that signaling. Use 5 ms extra for safety,
939 * like usb_port_resume() does.
1da177e4 940 */
49d0f078 941 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
1da177e4 942 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
61e8b858 943 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
1da177e4
LT
944 }
945 }
946
947 /* PCI errors [4.15.2.4] */
948 if (unlikely ((status & STS_FATAL) != 0)) {
67b2e029 949 ehci_err(ehci, "fatal error\n");
eafe5b99
AS
950 dbg_cmd(ehci, "fatal", cmd);
951 dbg_status(ehci, "fatal", status);
67b2e029 952 ehci_halt(ehci);
1da177e4 953dead:
67b2e029
AS
954 ehci_reset(ehci);
955 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
69fff59d 956 usb_hc_died(hcd);
67b2e029
AS
957 /* generic layer kills/unlinks all urbs, then
958 * uses ehci_stop to clean up the rest
959 */
960 bh = 1;
1da177e4
LT
961 }
962
963 if (bh)
7d12e780 964 ehci_work (ehci);
1da177e4 965 spin_unlock (&ehci->lock);
d1b1842c 966 if (pcd_status)
1d619f12 967 usb_hcd_poll_rh_status(hcd);
1da177e4
LT
968 return IRQ_HANDLED;
969}
970
971/*-------------------------------------------------------------------------*/
972
973/*
974 * non-error returns are a promise to giveback() the urb later
975 * we drop ownership so next owner (or urb unlink) can get it
976 *
977 * urb + dev is in hcd.self.controller.urb_list
978 * we're queueing TDs onto software and hardware lists
979 *
980 * hcd-specific init for hcpriv hasn't been done yet
981 *
982 * NOTE: control, bulk, and interrupt share the same code to append TDs
983 * to a (possibly active) QH, and the same QH scanning code.
984 */
985static int ehci_urb_enqueue (
986 struct usb_hcd *hcd,
1da177e4 987 struct urb *urb,
55016f10 988 gfp_t mem_flags
1da177e4
LT
989) {
990 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
991 struct list_head qtd_list;
992
993 INIT_LIST_HEAD (&qtd_list);
994
995 switch (usb_pipetype (urb->pipe)) {
25b70a86
DB
996 case PIPE_CONTROL:
997 /* qh_completions() code doesn't handle all the fault cases
998 * in multi-TD control transfers. Even 1KB is rare anyway.
999 */
1000 if (urb->transfer_buffer_length > (16 * 1024))
1001 return -EMSGSIZE;
1002 /* FALLTHROUGH */
1003 /* case PIPE_BULK: */
1da177e4
LT
1004 default:
1005 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1006 return -ENOMEM;
e9df41c5 1007 return submit_async(ehci, urb, &qtd_list, mem_flags);
1da177e4
LT
1008
1009 case PIPE_INTERRUPT:
1010 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1011 return -ENOMEM;
e9df41c5 1012 return intr_submit(ehci, urb, &qtd_list, mem_flags);
1da177e4
LT
1013
1014 case PIPE_ISOCHRONOUS:
1015 if (urb->dev->speed == USB_SPEED_HIGH)
1016 return itd_submit (ehci, urb, mem_flags);
1017 else
1018 return sitd_submit (ehci, urb, mem_flags);
1019 }
1020}
1021
1022static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
1023{
07d29b63 1024 /* failfast */
e8799906 1025 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim)
07d29b63
AS
1026 end_unlink_async(ehci);
1027
3a44494e
AS
1028 /* If the QH isn't linked then there's nothing we can do
1029 * unless we were called during a giveback, in which case
1030 * qh_completions() has to deal with it.
1031 */
1032 if (qh->qh_state != QH_STATE_LINKED) {
1033 if (qh->qh_state == QH_STATE_COMPLETING)
1034 qh->needs_rescan = 1;
1035 return;
1036 }
07d29b63
AS
1037
1038 /* defer till later if busy */
3a44494e 1039 if (ehci->reclaim) {
1da177e4
LT
1040 struct ehci_qh *last;
1041
1042 for (last = ehci->reclaim;
1043 last->reclaim;
1044 last = last->reclaim)
1045 continue;
1046 qh->qh_state = QH_STATE_UNLINK_WAIT;
1047 last->reclaim = qh;
1048
07d29b63
AS
1049 /* start IAA cycle */
1050 } else
1da177e4
LT
1051 start_unlink_async (ehci, qh);
1052}
1053
1054/* remove from hardware lists
1055 * completions normally happen asynchronously
1056 */
1057
e9df41c5 1058static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1da177e4
LT
1059{
1060 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1061 struct ehci_qh *qh;
1062 unsigned long flags;
e9df41c5 1063 int rc;
1da177e4
LT
1064
1065 spin_lock_irqsave (&ehci->lock, flags);
e9df41c5
AS
1066 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
1067 if (rc)
1068 goto done;
1069
1da177e4
LT
1070 switch (usb_pipetype (urb->pipe)) {
1071 // case PIPE_CONTROL:
1072 // case PIPE_BULK:
1073 default:
1074 qh = (struct ehci_qh *) urb->hcpriv;
1075 if (!qh)
1076 break;
07d29b63
AS
1077 switch (qh->qh_state) {
1078 case QH_STATE_LINKED:
1079 case QH_STATE_COMPLETING:
1080 unlink_async(ehci, qh);
1081 break;
1082 case QH_STATE_UNLINK:
1083 case QH_STATE_UNLINK_WAIT:
1084 /* already started */
1085 break;
1086 case QH_STATE_IDLE:
7a0f0d95
AS
1087 /* QH might be waiting for a Clear-TT-Buffer */
1088 qh_completions(ehci, qh);
07d29b63
AS
1089 break;
1090 }
1da177e4
LT
1091 break;
1092
1093 case PIPE_INTERRUPT:
1094 qh = (struct ehci_qh *) urb->hcpriv;
1095 if (!qh)
1096 break;
1097 switch (qh->qh_state) {
1098 case QH_STATE_LINKED:
a448c9d8 1099 case QH_STATE_COMPLETING:
1da177e4 1100 intr_deschedule (ehci, qh);
a448c9d8 1101 break;
1da177e4 1102 case QH_STATE_IDLE:
7d12e780 1103 qh_completions (ehci, qh);
1da177e4
LT
1104 break;
1105 default:
1106 ehci_dbg (ehci, "bogus qh %p state %d\n",
1107 qh, qh->qh_state);
1108 goto done;
1109 }
1da177e4
LT
1110 break;
1111
1112 case PIPE_ISOCHRONOUS:
1113 // itd or sitd ...
1114
1115 // wait till next completion, do it then.
1116 // completion irqs can wait up to 1024 msec,
1117 break;
1118 }
1119done:
1120 spin_unlock_irqrestore (&ehci->lock, flags);
e9df41c5 1121 return rc;
1da177e4
LT
1122}
1123
1124/*-------------------------------------------------------------------------*/
1125
1126// bulk qh holds the data toggle
1127
1128static void
1129ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1130{
1131 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1132 unsigned long flags;
1133 struct ehci_qh *qh, *tmp;
1134
1135 /* ASSERT: any requests/urbs are being unlinked */
1136 /* ASSERT: nobody can be submitting urbs for this any more */
1137
1138rescan:
1139 spin_lock_irqsave (&ehci->lock, flags);
1140 qh = ep->hcpriv;
1141 if (!qh)
1142 goto done;
1143
1144 /* endpoints can be iso streams. for now, we don't
1145 * accelerate iso completions ... so spin a while.
1146 */
1082f57a 1147 if (qh->hw == NULL) {
1da177e4
LT
1148 ehci_vdbg (ehci, "iso delay\n");
1149 goto idle_timeout;
1150 }
1151
e8799906 1152 if (ehci->rh_state != EHCI_RH_RUNNING)
1da177e4
LT
1153 qh->qh_state = QH_STATE_IDLE;
1154 switch (qh->qh_state) {
1155 case QH_STATE_LINKED:
3a44494e 1156 case QH_STATE_COMPLETING:
1da177e4
LT
1157 for (tmp = ehci->async->qh_next.qh;
1158 tmp && tmp != qh;
1159 tmp = tmp->qh_next.qh)
1160 continue;
02e2c51b
AS
1161 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1162 * may already be unlinked.
1163 */
1164 if (tmp)
1165 unlink_async(ehci, qh);
1da177e4
LT
1166 /* FALL THROUGH */
1167 case QH_STATE_UNLINK: /* wait for hw to finish? */
07d29b63 1168 case QH_STATE_UNLINK_WAIT:
1da177e4
LT
1169idle_timeout:
1170 spin_unlock_irqrestore (&ehci->lock, flags);
22c43863 1171 schedule_timeout_uninterruptible(1);
1da177e4
LT
1172 goto rescan;
1173 case QH_STATE_IDLE: /* fully unlinked */
914b7012
AS
1174 if (qh->clearing_tt)
1175 goto idle_timeout;
1da177e4
LT
1176 if (list_empty (&qh->qtd_list)) {
1177 qh_put (qh);
1178 break;
1179 }
1180 /* else FALL THROUGH */
1181 default:
1da177e4
LT
1182 /* caller was supposed to have unlinked any requests;
1183 * that's not our job. just leak this memory.
1184 */
1185 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1186 qh, ep->desc.bEndpointAddress, qh->qh_state,
1187 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1188 break;
1189 }
1190 ep->hcpriv = NULL;
1191done:
1192 spin_unlock_irqrestore (&ehci->lock, flags);
1da177e4
LT
1193}
1194
b18ffd49
AS
1195static void
1196ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1197{
1198 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1199 struct ehci_qh *qh;
1200 int eptype = usb_endpoint_type(&ep->desc);
a455212d
AS
1201 int epnum = usb_endpoint_num(&ep->desc);
1202 int is_out = usb_endpoint_dir_out(&ep->desc);
1203 unsigned long flags;
b18ffd49
AS
1204
1205 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1206 return;
1207
a455212d 1208 spin_lock_irqsave(&ehci->lock, flags);
b18ffd49
AS
1209 qh = ep->hcpriv;
1210
1211 /* For Bulk and Interrupt endpoints we maintain the toggle state
1212 * in the hardware; the toggle bits in udev aren't used at all.
1213 * When an endpoint is reset by usb_clear_halt() we must reset
1214 * the toggle bit in the QH.
1215 */
1216 if (qh) {
a455212d 1217 usb_settoggle(qh->dev, epnum, is_out, 0);
b18ffd49
AS
1218 if (!list_empty(&qh->qtd_list)) {
1219 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
3a44494e
AS
1220 } else if (qh->qh_state == QH_STATE_LINKED ||
1221 qh->qh_state == QH_STATE_COMPLETING) {
a455212d
AS
1222
1223 /* The toggle value in the QH can't be updated
1224 * while the QH is active. Unlink it now;
1225 * re-linking will call qh_refresh().
b18ffd49 1226 */
a448c9d8 1227 if (eptype == USB_ENDPOINT_XFER_BULK)
a455212d 1228 unlink_async(ehci, qh);
a448c9d8 1229 else
a455212d 1230 intr_deschedule(ehci, qh);
b18ffd49
AS
1231 }
1232 }
a455212d 1233 spin_unlock_irqrestore(&ehci->lock, flags);
b18ffd49
AS
1234}
1235
7ff71d6a
MP
1236static int ehci_get_frame (struct usb_hcd *hcd)
1237{
1238 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
68aa95d5 1239 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
7ff71d6a 1240}
1da177e4
LT
1241
1242/*-------------------------------------------------------------------------*/
1243
2b70f073 1244MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4
LT
1245MODULE_AUTHOR (DRIVER_AUTHOR);
1246MODULE_LICENSE ("GPL");
1247
7ff71d6a
MP
1248#ifdef CONFIG_PCI
1249#include "ehci-pci.c"
01cced25 1250#define PCI_DRIVER ehci_pci_driver
7ff71d6a 1251#endif
1da177e4 1252
ba02978a 1253#ifdef CONFIG_USB_EHCI_FSL
80cb9aee 1254#include "ehci-fsl.c"
01cced25 1255#define PLATFORM_DRIVER ehci_fsl_driver
80cb9aee
RV
1256#endif
1257
7e8d5cd9
DM
1258#ifdef CONFIG_USB_EHCI_MXC
1259#include "ehci-mxc.c"
1260#define PLATFORM_DRIVER ehci_mxc_driver
1261#endif
1262
60b0bf0f 1263#ifdef CONFIG_USB_EHCI_SH
63c84552
PM
1264#include "ehci-sh.c"
1265#define PLATFORM_DRIVER ehci_hcd_sh_driver
1266#endif
1267
37663860 1268#ifdef CONFIG_MIPS_ALCHEMY
76fa9a24 1269#include "ehci-au1xxx.c"
01cced25 1270#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
76fa9a24
JC
1271#endif
1272
7f124f4b 1273#ifdef CONFIG_USB_EHCI_HCD_OMAP
54ab2b02
FB
1274#include "ehci-omap.c"
1275#define PLATFORM_DRIVER ehci_hcd_omap_driver
1276#endif
1277
ad75a410
GL
1278#ifdef CONFIG_PPC_PS3
1279#include "ehci-ps3.c"
7a4eb7fd 1280#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
ad75a410
GL
1281#endif
1282
da0e8fb0
VB
1283#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1284#include "ehci-ppc-of.c"
1285#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1286#endif
1287
08d3c18e
JZ
1288#ifdef CONFIG_XPS_USB_HCD_XILINX
1289#include "ehci-xilinx-of.c"
1f23b2d9 1290#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
08d3c18e
JZ
1291#endif
1292
705a7521 1293#ifdef CONFIG_PLAT_ORION
e96ffe2f
TP
1294#include "ehci-orion.c"
1295#define PLATFORM_DRIVER ehci_orion_driver
1296#endif
1297
91bc4d31
VB
1298#ifdef CONFIG_ARCH_IXP4XX
1299#include "ehci-ixp4xx.c"
1300#define PLATFORM_DRIVER ixp4xx_ehci_driver
1301#endif
1302
586dfc8c
WZ
1303#ifdef CONFIG_USB_W90X900_EHCI
1304#include "ehci-w90x900.c"
1305#define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1306#endif
1307
501c9c08
NF
1308#ifdef CONFIG_ARCH_AT91
1309#include "ehci-atmel.c"
1310#define PLATFORM_DRIVER ehci_atmel_driver
1311#endif
1312
1643accd
DD
1313#ifdef CONFIG_USB_OCTEON_EHCI
1314#include "ehci-octeon.c"
1315#define PLATFORM_DRIVER ehci_octeon_driver
1316#endif
1317
760efe69
ML
1318#ifdef CONFIG_USB_CNS3XXX_EHCI
1319#include "ehci-cns3xxx.c"
1320#define PLATFORM_DRIVER cns3xxx_ehci_driver
1321#endif
1322
ad78acaf
AC
1323#ifdef CONFIG_ARCH_VT8500
1324#include "ehci-vt8500.c"
1325#define PLATFORM_DRIVER vt8500_ehci_driver
1326#endif
1327
c8c38de9
DS
1328#ifdef CONFIG_PLAT_SPEAR
1329#include "ehci-spear.c"
1330#define PLATFORM_DRIVER spear_ehci_hcd_driver
1331#endif
1332
b0848aea
PK
1333#ifdef CONFIG_USB_EHCI_MSM
1334#include "ehci-msm.c"
1335#define PLATFORM_DRIVER ehci_msm_driver
1336#endif
1337
22ced687
A
1338#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1339#include "ehci-pmcmsp.c"
1340#define PLATFORM_DRIVER ehci_hcd_msp_driver
1341#endif
1342
79ad3b5a
BG
1343#ifdef CONFIG_USB_EHCI_TEGRA
1344#include "ehci-tegra.c"
1345#define PLATFORM_DRIVER tegra_ehci_driver
1346#endif
1347
1bcc5aa8
JS
1348#ifdef CONFIG_USB_EHCI_S5P
1349#include "ehci-s5p.c"
1350#define PLATFORM_DRIVER s5p_ehci_driver
1351#endif
1352
9be03929
JA
1353#ifdef CONFIG_SPARC_LEON
1354#include "ehci-grlib.c"
1355#define PLATFORM_DRIVER ehci_grlib_driver
1356#endif
1357
3af5154a 1358#ifdef CONFIG_CPU_XLR
23106343
J
1359#include "ehci-xls.c"
1360#define PLATFORM_DRIVER ehci_xls_driver
1361#endif
1362
3a082ec9
NZ
1363#ifdef CONFIG_USB_EHCI_MV
1364#include "ehci-mv.c"
1365#define PLATFORM_DRIVER ehci_mv_driver
1366#endif
1367
f30cdbcb
KC
1368#ifdef CONFIG_MACH_LOONGSON1
1369#include "ehci-ls1x.c"
1370#define PLATFORM_DRIVER ehci_ls1x_driver
1371#endif
1372
7a7a4a59
HM
1373#ifdef CONFIG_USB_EHCI_HCD_PLATFORM
1374#include "ehci-platform.c"
1375#define PLATFORM_DRIVER ehci_platform_driver
1376#endif
1377
ad75a410 1378#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1f23b2d9
GL
1379 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1380 !defined(XILINX_OF_PLATFORM_DRIVER)
7ff71d6a
MP
1381#error "missing bus glue for ehci-hcd"
1382#endif
01cced25
KG
1383
1384static int __init ehci_hcd_init(void)
1385{
1386 int retval = 0;
1387
2b70f073
AS
1388 if (usb_disabled())
1389 return -ENODEV;
1390
1391 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
9beeee65
AS
1392 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1393 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1394 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1395 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1396 " before uhci_hcd and ohci_hcd, not after\n");
1397
01cced25
KG
1398 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1399 hcd_name,
1400 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1401 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1402
694cc208 1403#ifdef DEBUG
08f4e586 1404 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
9beeee65
AS
1405 if (!ehci_debug_root) {
1406 retval = -ENOENT;
1407 goto err_debug;
1408 }
694cc208
TJ
1409#endif
1410
01cced25
KG
1411#ifdef PLATFORM_DRIVER
1412 retval = platform_driver_register(&PLATFORM_DRIVER);
da0e8fb0
VB
1413 if (retval < 0)
1414 goto clean0;
01cced25
KG
1415#endif
1416
1417#ifdef PCI_DRIVER
1418 retval = pci_register_driver(&PCI_DRIVER);
da0e8fb0
VB
1419 if (retval < 0)
1420 goto clean1;
ad75a410
GL
1421#endif
1422
1423#ifdef PS3_SYSTEM_BUS_DRIVER
7a4eb7fd 1424 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
da0e8fb0
VB
1425 if (retval < 0)
1426 goto clean2;
694cc208 1427#endif
da0e8fb0
VB
1428
1429#ifdef OF_PLATFORM_DRIVER
d35fb641 1430 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
da0e8fb0
VB
1431 if (retval < 0)
1432 goto clean3;
1433#endif
1f23b2d9
GL
1434
1435#ifdef XILINX_OF_PLATFORM_DRIVER
d35fb641 1436 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1f23b2d9
GL
1437 if (retval < 0)
1438 goto clean4;
1439#endif
da0e8fb0
VB
1440 return retval;
1441
1f23b2d9 1442#ifdef XILINX_OF_PLATFORM_DRIVER
d35fb641 1443 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1f23b2d9
GL
1444clean4:
1445#endif
da0e8fb0 1446#ifdef OF_PLATFORM_DRIVER
d35fb641 1447 platform_driver_unregister(&OF_PLATFORM_DRIVER);
da0e8fb0
VB
1448clean3:
1449#endif
1450#ifdef PS3_SYSTEM_BUS_DRIVER
1451 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1452clean2:
ad75a410
GL
1453#endif
1454#ifdef PCI_DRIVER
da0e8fb0
VB
1455 pci_unregister_driver(&PCI_DRIVER);
1456clean1:
ad75a410 1457#endif
da0e8fb0
VB
1458#ifdef PLATFORM_DRIVER
1459 platform_driver_unregister(&PLATFORM_DRIVER);
1460clean0:
1461#endif
1462#ifdef DEBUG
1463 debugfs_remove(ehci_debug_root);
1464 ehci_debug_root = NULL;
9beeee65 1465err_debug:
a9b6148d 1466#endif
9beeee65 1467 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
01cced25
KG
1468 return retval;
1469}
1470module_init(ehci_hcd_init);
1471
1472static void __exit ehci_hcd_cleanup(void)
1473{
1f23b2d9 1474#ifdef XILINX_OF_PLATFORM_DRIVER
d35fb641 1475 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1f23b2d9 1476#endif
da0e8fb0 1477#ifdef OF_PLATFORM_DRIVER
d35fb641 1478 platform_driver_unregister(&OF_PLATFORM_DRIVER);
da0e8fb0 1479#endif
01cced25
KG
1480#ifdef PLATFORM_DRIVER
1481 platform_driver_unregister(&PLATFORM_DRIVER);
1482#endif
1483#ifdef PCI_DRIVER
1484 pci_unregister_driver(&PCI_DRIVER);
1485#endif
ad75a410 1486#ifdef PS3_SYSTEM_BUS_DRIVER
7a4eb7fd 1487 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
ad75a410 1488#endif
694cc208
TJ
1489#ifdef DEBUG
1490 debugfs_remove(ehci_debug_root);
1491#endif
9beeee65 1492 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
01cced25
KG
1493}
1494module_exit(ehci_hcd_cleanup);
1495
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