Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
578333ab AS |
2 | * Enhanced Host Controller Interface (EHCI) driver for USB. |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
5 | * | |
1da177e4 | 6 | * Copyright (c) 2000-2004 by David Brownell |
53bd6a60 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/dmapool.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/sched.h> | |
3c04e20e | 30 | #include <linux/vmalloc.h> |
1da177e4 LT |
31 | #include <linux/errno.h> |
32 | #include <linux/init.h> | |
33 | #include <linux/timer.h> | |
ee4ecb8a | 34 | #include <linux/ktime.h> |
1da177e4 LT |
35 | #include <linux/list.h> |
36 | #include <linux/interrupt.h> | |
1da177e4 | 37 | #include <linux/usb.h> |
27729aad | 38 | #include <linux/usb/hcd.h> |
1da177e4 LT |
39 | #include <linux/moduleparam.h> |
40 | #include <linux/dma-mapping.h> | |
694cc208 | 41 | #include <linux/debugfs.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
aa4d8342 | 43 | #include <linux/uaccess.h> |
1da177e4 | 44 | |
1da177e4 LT |
45 | #include <asm/byteorder.h> |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
1da177e4 | 48 | #include <asm/unaligned.h> |
1da177e4 | 49 | |
df7c1ca2 GL |
50 | #if defined(CONFIG_PPC_PS3) |
51 | #include <asm/firmware.h> | |
52 | #endif | |
53 | ||
1da177e4 LT |
54 | /*-------------------------------------------------------------------------*/ |
55 | ||
56 | /* | |
57 | * EHCI hc_driver implementation ... experimental, incomplete. | |
58 | * Based on the final 1.0 register interface specification. | |
59 | * | |
60 | * USB 2.0 shows up in upcoming www.pcmcia.org technology. | |
61 | * First was PCMCIA, like ISA; then CardBus, which is PCI. | |
62 | * Next comes "CardBay", using USB 2.0 signals. | |
63 | * | |
64 | * Contains additional contributions by Brad Hards, Rory Bolt, and others. | |
65 | * Special thanks to Intel and VIA for providing host controllers to | |
66 | * test this driver on, and Cypress (including In-System Design) for | |
67 | * providing early devices for those host controllers to talk to! | |
1da177e4 LT |
68 | */ |
69 | ||
1da177e4 LT |
70 | #define DRIVER_AUTHOR "David Brownell" |
71 | #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" | |
72 | ||
73 | static const char hcd_name [] = "ehci_hcd"; | |
74 | ||
75 | ||
9776afc8 | 76 | #undef VERBOSE_DEBUG |
1da177e4 LT |
77 | #undef EHCI_URB_TRACE |
78 | ||
79 | #ifdef DEBUG | |
80 | #define EHCI_STATS | |
81 | #endif | |
82 | ||
83 | /* magic numbers that can affect system performance */ | |
84 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
85 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
86 | #define EHCI_TUNE_RL_TT 0 | |
87 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
88 | #define EHCI_TUNE_MULT_TT 1 | |
ffda0803 AS |
89 | /* |
90 | * Some drivers think it's safe to schedule isochronous transfers more than | |
91 | * 256 ms into the future (partly as a result of an old bug in the scheduling | |
92 | * code). In an attempt to avoid trouble, we will use a minimum scheduling | |
93 | * length of 512 frames instead of 256. | |
94 | */ | |
95 | #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ | |
1da177e4 | 96 | |
07d29b63 | 97 | #define EHCI_IAA_MSECS 10 /* arbitrary */ |
1da177e4 LT |
98 | #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ |
99 | #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ | |
004c1968 | 100 | #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1) |
fcda37cb | 101 | /* 5-ms async qh unlink delay */ |
1da177e4 LT |
102 | |
103 | /* Initial IRQ latency: faster than hw default */ | |
104 | static int log2_irq_thresh = 0; // 0 to 6 | |
105 | module_param (log2_irq_thresh, int, S_IRUGO); | |
106 | MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); | |
107 | ||
108 | /* initial park setting: slower than hw default */ | |
109 | static unsigned park = 0; | |
110 | module_param (park, uint, S_IRUGO); | |
111 | MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); | |
112 | ||
93f1a47c | 113 | /* for flakey hardware, ignore overcurrent indicators */ |
90ab5ee9 | 114 | static bool ignore_oc = 0; |
93f1a47c DB |
115 | module_param (ignore_oc, bool, S_IRUGO); |
116 | MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); | |
117 | ||
48f24970 AD |
118 | /* for link power management(LPM) feature */ |
119 | static unsigned int hird; | |
120 | module_param(hird, int, S_IRUGO); | |
cc556871 | 121 | MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us"); |
48f24970 | 122 | |
1da177e4 LT |
123 | #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) |
124 | ||
125 | /*-------------------------------------------------------------------------*/ | |
126 | ||
127 | #include "ehci.h" | |
128 | #include "ehci-dbg.c" | |
ad93562b | 129 | #include "pci-quirks.h" |
1da177e4 LT |
130 | |
131 | /*-------------------------------------------------------------------------*/ | |
132 | ||
bc29847e AS |
133 | static void |
134 | timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) | |
135 | { | |
136 | /* Don't override timeouts which shrink or (later) disable | |
137 | * the async ring; just the I/O watchdog. Note that if a | |
138 | * SHRINK were pending, OFF would never be requested. | |
139 | */ | |
140 | if (timer_pending(&ehci->watchdog) | |
141 | && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) | |
142 | & ehci->actions)) | |
143 | return; | |
144 | ||
145 | if (!test_and_set_bit(action, &ehci->actions)) { | |
146 | unsigned long t; | |
147 | ||
148 | switch (action) { | |
149 | case TIMER_IO_WATCHDOG: | |
403dbd36 AD |
150 | if (!ehci->need_io_watchdog) |
151 | return; | |
bc29847e AS |
152 | t = EHCI_IO_JIFFIES; |
153 | break; | |
154 | case TIMER_ASYNC_OFF: | |
155 | t = EHCI_ASYNC_JIFFIES; | |
156 | break; | |
157 | /* case TIMER_ASYNC_SHRINK: */ | |
158 | default: | |
004c1968 | 159 | t = EHCI_SHRINK_JIFFIES; |
bc29847e AS |
160 | break; |
161 | } | |
162 | mod_timer(&ehci->watchdog, t + jiffies); | |
163 | } | |
164 | } | |
165 | ||
166 | /*-------------------------------------------------------------------------*/ | |
167 | ||
1da177e4 LT |
168 | /* |
169 | * handshake - spin reading hc until handshake completes or fails | |
170 | * @ptr: address of hc register to be read | |
171 | * @mask: bits to look at in result of read | |
172 | * @done: value of those bits when handshake succeeds | |
173 | * @usec: timeout in microseconds | |
174 | * | |
175 | * Returns negative errno, or zero on success | |
176 | * | |
177 | * Success happens when the "mask" bits have the specified value (hardware | |
178 | * handshake done). There are two failure modes: "usec" have passed (major | |
179 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
180 | * | |
181 | * That last failure should_only happen in cases like physical cardbus eject | |
182 | * before driver shutdown. But it also seems to be caused by bugs in cardbus | |
183 | * bridge shutdown: shutting down the bridge before the devices using it. | |
184 | */ | |
083522d7 BH |
185 | static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, |
186 | u32 mask, u32 done, int usec) | |
1da177e4 LT |
187 | { |
188 | u32 result; | |
189 | ||
190 | do { | |
083522d7 | 191 | result = ehci_readl(ehci, ptr); |
1da177e4 LT |
192 | if (result == ~(u32)0) /* card removed */ |
193 | return -ENODEV; | |
194 | result &= mask; | |
195 | if (result == done) | |
196 | return 0; | |
197 | udelay (1); | |
198 | usec--; | |
199 | } while (usec > 0); | |
200 | return -ETIMEDOUT; | |
201 | } | |
202 | ||
65fd4272 MC |
203 | /* check TDI/ARC silicon is in host mode */ |
204 | static int tdi_in_host_mode (struct ehci_hcd *ehci) | |
205 | { | |
206 | u32 __iomem *reg_ptr; | |
207 | u32 tmp; | |
208 | ||
209 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); | |
210 | tmp = ehci_readl(ehci, reg_ptr); | |
211 | return (tmp & 3) == USBMODE_CM_HC; | |
212 | } | |
213 | ||
1da177e4 LT |
214 | /* force HC to halt state from unknown (EHCI spec section 2.3) */ |
215 | static int ehci_halt (struct ehci_hcd *ehci) | |
216 | { | |
083522d7 | 217 | u32 temp = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 | 218 | |
72f30b6f | 219 | /* disable any irqs left enabled by previous code */ |
083522d7 | 220 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
72f30b6f | 221 | |
65fd4272 MC |
222 | if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { |
223 | return 0; | |
224 | } | |
225 | ||
1da177e4 LT |
226 | if ((temp & STS_HALT) != 0) |
227 | return 0; | |
228 | ||
3d9545cc AS |
229 | /* |
230 | * This routine gets called during probe before ehci->command | |
231 | * has been initialized, so we can't rely on its value. | |
232 | */ | |
233 | ehci->command &= ~CMD_RUN; | |
083522d7 | 234 | temp = ehci_readl(ehci, &ehci->regs->command); |
3d9545cc | 235 | temp &= ~(CMD_RUN | CMD_IAAD); |
083522d7 BH |
236 | ehci_writel(ehci, temp, &ehci->regs->command); |
237 | return handshake (ehci, &ehci->regs->status, | |
238 | STS_HALT, STS_HALT, 16 * 125); | |
1da177e4 LT |
239 | } |
240 | ||
df7c1ca2 GL |
241 | #if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3) |
242 | ||
243 | /* | |
244 | * The EHCI controller of the Cell Super Companion Chip used in the | |
245 | * PS3 will stop the root hub after all root hub ports are suspended. | |
246 | * When in this condition handshake will return -ETIMEDOUT. The | |
247 | * STS_HLT bit will not be set, so inspection of the frame index is | |
248 | * used here to test for the condition. If the condition is found | |
249 | * return success to allow the USB suspend to complete. | |
250 | */ | |
251 | ||
252 | static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, | |
253 | void __iomem *ptr, u32 mask, u32 done, | |
254 | int usec) | |
255 | { | |
256 | unsigned int old_index; | |
257 | int error; | |
258 | ||
259 | if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) | |
260 | return -ETIMEDOUT; | |
261 | ||
262 | old_index = ehci_read_frame_index(ehci); | |
263 | ||
264 | error = handshake(ehci, ptr, mask, done, usec); | |
265 | ||
266 | if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index) | |
267 | return 0; | |
268 | ||
269 | return error; | |
270 | } | |
271 | ||
272 | #else | |
273 | ||
274 | static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, | |
275 | void __iomem *ptr, u32 mask, u32 done, | |
276 | int usec) | |
277 | { | |
278 | return -ETIMEDOUT; | |
279 | } | |
280 | ||
281 | #endif | |
282 | ||
0bcfeb3e DB |
283 | static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, |
284 | u32 mask, u32 done, int usec) | |
285 | { | |
286 | int error; | |
287 | ||
288 | error = handshake(ehci, ptr, mask, done, usec); | |
df7c1ca2 GL |
289 | if (error == -ETIMEDOUT) |
290 | error = handshake_for_broken_root_hub(ehci, ptr, mask, done, | |
291 | usec); | |
292 | ||
0bcfeb3e DB |
293 | if (error) { |
294 | ehci_halt(ehci); | |
e8799906 | 295 | ehci->rh_state = EHCI_RH_HALTED; |
65cb76ba | 296 | ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", |
0bcfeb3e DB |
297 | ptr, mask, done, error); |
298 | } | |
299 | ||
300 | return error; | |
301 | } | |
302 | ||
1da177e4 LT |
303 | /* put TDI/ARC silicon into EHCI mode */ |
304 | static void tdi_reset (struct ehci_hcd *ehci) | |
305 | { | |
306 | u32 __iomem *reg_ptr; | |
307 | u32 tmp; | |
308 | ||
d23a1377 | 309 | reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); |
083522d7 | 310 | tmp = ehci_readl(ehci, reg_ptr); |
d23a1377 VB |
311 | tmp |= USBMODE_CM_HC; |
312 | /* The default byte access to MMR space is LE after | |
313 | * controller reset. Set the required endian mode | |
314 | * for transfer buffers to match the host microprocessor | |
315 | */ | |
316 | if (ehci_big_endian_mmio(ehci)) | |
317 | tmp |= USBMODE_BE; | |
083522d7 | 318 | ehci_writel(ehci, tmp, reg_ptr); |
1da177e4 LT |
319 | } |
320 | ||
321 | /* reset a non-running (STS_HALT == 1) controller */ | |
322 | static int ehci_reset (struct ehci_hcd *ehci) | |
323 | { | |
324 | int retval; | |
083522d7 | 325 | u32 command = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 | 326 | |
8d053c79 JW |
327 | /* If the EHCI debug controller is active, special care must be |
328 | * taken before and after a host controller reset */ | |
329 | if (ehci->debug && !dbgp_reset_prep()) | |
330 | ehci->debug = NULL; | |
331 | ||
1da177e4 LT |
332 | command |= CMD_RESET; |
333 | dbg_cmd (ehci, "reset", command); | |
083522d7 | 334 | ehci_writel(ehci, command, &ehci->regs->command); |
e8799906 | 335 | ehci->rh_state = EHCI_RH_HALTED; |
1da177e4 | 336 | ehci->next_statechange = jiffies; |
083522d7 BH |
337 | retval = handshake (ehci, &ehci->regs->command, |
338 | CMD_RESET, 0, 250 * 1000); | |
1da177e4 | 339 | |
331ac6b2 AD |
340 | if (ehci->has_hostpc) { |
341 | ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, | |
342 | (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); | |
343 | ehci_writel(ehci, TXFIFO_DEFAULT, | |
344 | (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); | |
345 | } | |
1da177e4 LT |
346 | if (retval) |
347 | return retval; | |
348 | ||
349 | if (ehci_is_TDI(ehci)) | |
350 | tdi_reset (ehci); | |
351 | ||
8d053c79 JW |
352 | if (ehci->debug) |
353 | dbgp_external_startup(); | |
354 | ||
a448e4dc AS |
355 | ehci->port_c_suspend = ehci->suspended_ports = |
356 | ehci->resuming_ports = 0; | |
1da177e4 LT |
357 | return retval; |
358 | } | |
359 | ||
360 | /* idle the controller (from running) */ | |
361 | static void ehci_quiesce (struct ehci_hcd *ehci) | |
362 | { | |
363 | u32 temp; | |
364 | ||
365 | #ifdef DEBUG | |
e8799906 | 366 | if (ehci->rh_state != EHCI_RH_RUNNING) |
1da177e4 LT |
367 | BUG (); |
368 | #endif | |
369 | ||
370 | /* wait for any schedule enables/disables to take effect */ | |
3d9545cc | 371 | temp = (ehci->command << 10) & (STS_ASS | STS_PSS); |
c765d4ca KW |
372 | if (handshake_on_error_set_halt(ehci, &ehci->regs->status, |
373 | STS_ASS | STS_PSS, temp, 16 * 125)) | |
1da177e4 | 374 | return; |
1da177e4 LT |
375 | |
376 | /* then disable anything that's still active */ | |
3d9545cc AS |
377 | ehci->command &= ~(CMD_ASE | CMD_PSE); |
378 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | |
1da177e4 LT |
379 | |
380 | /* hardware can take 16 microframes to turn off ... */ | |
c765d4ca KW |
381 | handshake_on_error_set_halt(ehci, &ehci->regs->status, |
382 | STS_ASS | STS_PSS, 0, 16 * 125); | |
1da177e4 LT |
383 | } |
384 | ||
385 | /*-------------------------------------------------------------------------*/ | |
386 | ||
07d29b63 | 387 | static void end_unlink_async(struct ehci_hcd *ehci); |
7d12e780 | 388 | static void ehci_work(struct ehci_hcd *ehci); |
1da177e4 LT |
389 | |
390 | #include "ehci-hub.c" | |
48f24970 | 391 | #include "ehci-lpm.c" |
1da177e4 LT |
392 | #include "ehci-mem.c" |
393 | #include "ehci-q.c" | |
394 | #include "ehci-sched.c" | |
4c67045b | 395 | #include "ehci-sysfs.c" |
1da177e4 LT |
396 | |
397 | /*-------------------------------------------------------------------------*/ | |
398 | ||
07d29b63 | 399 | static void ehci_iaa_watchdog(unsigned long param) |
1da177e4 LT |
400 | { |
401 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
402 | unsigned long flags; | |
403 | ||
404 | spin_lock_irqsave (&ehci->lock, flags); | |
405 | ||
e82cc128 DB |
406 | /* Lost IAA irqs wedge things badly; seen first with a vt8235. |
407 | * So we need this watchdog, but must protect it against both | |
408 | * (a) SMP races against real IAA firing and retriggering, and | |
409 | * (b) clean HC shutdown, when IAA watchdog was pending. | |
410 | */ | |
411 | if (ehci->reclaim | |
412 | && !timer_pending(&ehci->iaa_watchdog) | |
e8799906 | 413 | && ehci->rh_state == EHCI_RH_RUNNING) { |
e82cc128 DB |
414 | u32 cmd, status; |
415 | ||
416 | /* If we get here, IAA is *REALLY* late. It's barely | |
417 | * conceivable that the system is so busy that CMD_IAAD | |
418 | * is still legitimately set, so let's be sure it's | |
419 | * clear before we read STS_IAA. (The HC should clear | |
420 | * CMD_IAAD when it sets STS_IAA.) | |
421 | */ | |
422 | cmd = ehci_readl(ehci, &ehci->regs->command); | |
e82cc128 DB |
423 | |
424 | /* If IAA is set here it either legitimately triggered | |
425 | * before we cleared IAAD above (but _way_ late, so we'll | |
426 | * still count it as lost) ... or a silicon erratum: | |
427 | * - VIA seems to set IAA without triggering the IRQ; | |
428 | * - IAAD potentially cleared without setting IAA. | |
429 | */ | |
430 | status = ehci_readl(ehci, &ehci->regs->status); | |
431 | if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { | |
1da177e4 | 432 | COUNT (ehci->stats.lost_iaa); |
083522d7 | 433 | ehci_writel(ehci, STS_IAA, &ehci->regs->status); |
1da177e4 | 434 | } |
e82cc128 DB |
435 | |
436 | ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", | |
437 | status, cmd); | |
07d29b63 | 438 | end_unlink_async(ehci); |
1da177e4 LT |
439 | } |
440 | ||
07d29b63 AS |
441 | spin_unlock_irqrestore(&ehci->lock, flags); |
442 | } | |
443 | ||
444 | static void ehci_watchdog(unsigned long param) | |
445 | { | |
446 | struct ehci_hcd *ehci = (struct ehci_hcd *) param; | |
447 | unsigned long flags; | |
448 | ||
449 | spin_lock_irqsave(&ehci->lock, flags); | |
450 | ||
451 | /* stop async processing after it's idled a bit */ | |
1da177e4 | 452 | if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) |
26f953fd | 453 | start_unlink_async (ehci, ehci->async); |
1da177e4 LT |
454 | |
455 | /* ehci could run by timer, without IRQs ... */ | |
7d12e780 | 456 | ehci_work (ehci); |
1da177e4 LT |
457 | |
458 | spin_unlock_irqrestore (&ehci->lock, flags); | |
459 | } | |
460 | ||
8903795a AS |
461 | /* On some systems, leaving remote wakeup enabled prevents system shutdown. |
462 | * The firmware seems to think that powering off is a wakeup event! | |
463 | * This routine turns off remote wakeup and everything else, on all ports. | |
464 | */ | |
465 | static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) | |
466 | { | |
467 | int port = HCS_N_PORTS(ehci->hcs_params); | |
468 | ||
469 | while (port--) | |
470 | ehci_writel(ehci, PORT_RWC_BITS, | |
471 | &ehci->regs->port_status[port]); | |
472 | } | |
473 | ||
21da84a8 SS |
474 | /* |
475 | * Halt HC, turn off all ports, and let the BIOS use the companion controllers. | |
476 | * Should be called with ehci->lock held. | |
72f30b6f | 477 | */ |
21da84a8 | 478 | static void ehci_silence_controller(struct ehci_hcd *ehci) |
1da177e4 | 479 | { |
21da84a8 | 480 | ehci_halt(ehci); |
8903795a | 481 | ehci_turn_off_all_ports(ehci); |
1da177e4 LT |
482 | |
483 | /* make BIOS/etc use companion controller during reboot */ | |
083522d7 | 484 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); |
8903795a AS |
485 | |
486 | /* unblock posted writes */ | |
487 | ehci_readl(ehci, &ehci->regs->configured_flag); | |
1da177e4 LT |
488 | } |
489 | ||
21da84a8 SS |
490 | /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). |
491 | * This forcibly disables dma and IRQs, helping kexec and other cases | |
492 | * where the next system software may expect clean state. | |
493 | */ | |
494 | static void ehci_shutdown(struct usb_hcd *hcd) | |
495 | { | |
496 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
497 | ||
498 | del_timer_sync(&ehci->watchdog); | |
499 | del_timer_sync(&ehci->iaa_watchdog); | |
500 | ||
501 | spin_lock_irq(&ehci->lock); | |
502 | ehci_silence_controller(ehci); | |
503 | spin_unlock_irq(&ehci->lock); | |
504 | } | |
505 | ||
56c1e26d DB |
506 | static void ehci_port_power (struct ehci_hcd *ehci, int is_on) |
507 | { | |
508 | unsigned port; | |
509 | ||
510 | if (!HCS_PPC (ehci->hcs_params)) | |
511 | return; | |
512 | ||
513 | ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); | |
514 | for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) | |
515 | (void) ehci_hub_control(ehci_to_hcd(ehci), | |
516 | is_on ? SetPortFeature : ClearPortFeature, | |
517 | USB_PORT_FEAT_POWER, | |
518 | port--, NULL, 0); | |
383975d7 AS |
519 | /* Flush those writes */ |
520 | ehci_readl(ehci, &ehci->regs->command); | |
56c1e26d DB |
521 | msleep(20); |
522 | } | |
523 | ||
7ff71d6a | 524 | /*-------------------------------------------------------------------------*/ |
1da177e4 | 525 | |
7ff71d6a MP |
526 | /* |
527 | * ehci_work is called from some interrupts, timers, and so on. | |
528 | * it calls driver completion functions, after dropping ehci->lock. | |
529 | */ | |
7d12e780 | 530 | static void ehci_work (struct ehci_hcd *ehci) |
7ff71d6a MP |
531 | { |
532 | timer_action_done (ehci, TIMER_IO_WATCHDOG); | |
7ff71d6a MP |
533 | |
534 | /* another CPU may drop ehci->lock during a schedule scan while | |
535 | * it reports urb completions. this flag guards against bogus | |
536 | * attempts at re-entrant schedule scanning. | |
537 | */ | |
538 | if (ehci->scanning) | |
539 | return; | |
540 | ehci->scanning = 1; | |
7d12e780 | 541 | scan_async (ehci); |
7ff71d6a | 542 | if (ehci->next_uframe != -1) |
7d12e780 | 543 | scan_periodic (ehci); |
7ff71d6a MP |
544 | ehci->scanning = 0; |
545 | ||
546 | /* the IO watchdog guards against hardware or driver bugs that | |
547 | * misplace IRQs, and should let us run completely without IRQs. | |
548 | * such lossage has been observed on both VT6202 and VT8235. | |
549 | */ | |
e8799906 | 550 | if (ehci->rh_state == EHCI_RH_RUNNING && |
7ff71d6a MP |
551 | (ehci->async->qh_next.ptr != NULL || |
552 | ehci->periodic_sched != 0)) | |
553 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
554 | } | |
1da177e4 | 555 | |
21da84a8 SS |
556 | /* |
557 | * Called when the ehci_hcd module is removed. | |
558 | */ | |
7ff71d6a | 559 | static void ehci_stop (struct usb_hcd *hcd) |
1da177e4 LT |
560 | { |
561 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1da177e4 | 562 | |
7ff71d6a | 563 | ehci_dbg (ehci, "stop\n"); |
1da177e4 | 564 | |
7ff71d6a MP |
565 | /* no more interrupts ... */ |
566 | del_timer_sync (&ehci->watchdog); | |
07d29b63 | 567 | del_timer_sync(&ehci->iaa_watchdog); |
56c1e26d | 568 | |
7ff71d6a | 569 | spin_lock_irq(&ehci->lock); |
e8799906 | 570 | if (ehci->rh_state == EHCI_RH_RUNNING) |
7ff71d6a | 571 | ehci_quiesce (ehci); |
1da177e4 | 572 | |
21da84a8 | 573 | ehci_silence_controller(ehci); |
7ff71d6a | 574 | ehci_reset (ehci); |
7ff71d6a | 575 | spin_unlock_irq(&ehci->lock); |
1da177e4 | 576 | |
4c67045b | 577 | remove_sysfs_files(ehci); |
7ff71d6a | 578 | remove_debug_files (ehci); |
1da177e4 | 579 | |
7ff71d6a MP |
580 | /* root hub is shut down separately (first, when possible) */ |
581 | spin_lock_irq (&ehci->lock); | |
582 | if (ehci->async) | |
7d12e780 | 583 | ehci_work (ehci); |
7ff71d6a MP |
584 | spin_unlock_irq (&ehci->lock); |
585 | ehci_mem_cleanup (ehci); | |
1da177e4 | 586 | |
ad93562b AX |
587 | if (ehci->amd_pll_fix == 1) |
588 | usb_amd_dev_put(); | |
05570297 | 589 | |
7ff71d6a MP |
590 | #ifdef EHCI_STATS |
591 | ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", | |
592 | ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, | |
593 | ehci->stats.lost_iaa); | |
594 | ehci_dbg (ehci, "complete %ld unlink %ld\n", | |
595 | ehci->stats.complete, ehci->stats.unlink); | |
1da177e4 | 596 | #endif |
1da177e4 | 597 | |
083522d7 BH |
598 | dbg_status (ehci, "ehci_stop completed", |
599 | ehci_readl(ehci, &ehci->regs->status)); | |
1da177e4 LT |
600 | } |
601 | ||
18807521 DB |
602 | /* one-time init, only for memory state */ |
603 | static int ehci_init(struct usb_hcd *hcd) | |
1da177e4 | 604 | { |
18807521 | 605 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
1da177e4 | 606 | u32 temp; |
1da177e4 LT |
607 | int retval; |
608 | u32 hcc_params; | |
3807e26d | 609 | struct ehci_qh_hw *hw; |
18807521 DB |
610 | |
611 | spin_lock_init(&ehci->lock); | |
612 | ||
403dbd36 AD |
613 | /* |
614 | * keep io watchdog by default, those good HCDs could turn off it later | |
615 | */ | |
616 | ehci->need_io_watchdog = 1; | |
18807521 DB |
617 | init_timer(&ehci->watchdog); |
618 | ehci->watchdog.function = ehci_watchdog; | |
619 | ehci->watchdog.data = (unsigned long) ehci; | |
1da177e4 | 620 | |
07d29b63 AS |
621 | init_timer(&ehci->iaa_watchdog); |
622 | ehci->iaa_watchdog.function = ehci_iaa_watchdog; | |
623 | ehci->iaa_watchdog.data = (unsigned long) ehci; | |
624 | ||
f75593ce AS |
625 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
626 | ||
cc62a7eb KS |
627 | /* |
628 | * by default set standard 80% (== 100 usec/uframe) max periodic | |
629 | * bandwidth as required by USB 2.0 | |
630 | */ | |
631 | ehci->uframe_periodic_max = 100; | |
632 | ||
1da177e4 LT |
633 | /* |
634 | * hw default: 1K periodic list heads, one per frame. | |
635 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
636 | */ | |
637 | ehci->periodic_size = DEFAULT_I_TDPS; | |
9aa09d2f | 638 | INIT_LIST_HEAD(&ehci->cached_itd_list); |
0e5f231b | 639 | INIT_LIST_HEAD(&ehci->cached_sitd_list); |
f75593ce | 640 | |
8e192910 | 641 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
f75593ce AS |
642 | /* periodic schedule size can be smaller than default */ |
643 | switch (EHCI_TUNE_FLS) { | |
644 | case 0: ehci->periodic_size = 1024; break; | |
645 | case 1: ehci->periodic_size = 512; break; | |
646 | case 2: ehci->periodic_size = 256; break; | |
647 | default: BUG(); | |
648 | } | |
649 | } | |
18807521 | 650 | if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) |
1da177e4 LT |
651 | return retval; |
652 | ||
653 | /* controllers may cache some of the periodic schedule ... */ | |
53bd6a60 | 654 | if (HCC_ISOC_CACHE(hcc_params)) // full frame cache |
dccd574c | 655 | ehci->i_thresh = 2 + 8; |
1da177e4 | 656 | else // N microframes cached |
18807521 | 657 | ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); |
1da177e4 LT |
658 | |
659 | ehci->reclaim = NULL; | |
1da177e4 | 660 | ehci->next_uframe = -1; |
9aa09d2f | 661 | ehci->clock_frame = -1; |
1da177e4 | 662 | |
1da177e4 LT |
663 | /* |
664 | * dedicate a qh for the async ring head, since we couldn't unlink | |
665 | * a 'real' qh without stopping the async schedule [4.8]. use it | |
666 | * as the 'reclamation list head' too. | |
667 | * its dummy is used in hw_alt_next of many tds, to prevent the qh | |
668 | * from automatically advancing to the next td after short reads. | |
669 | */ | |
18807521 | 670 | ehci->async->qh_next.qh = NULL; |
3807e26d AD |
671 | hw = ehci->async->hw; |
672 | hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); | |
673 | hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); | |
4f7a67e2 | 674 | #if defined(CONFIG_PPC_PS3) |
aaa0ef28 | 675 | hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */ |
4f7a67e2 | 676 | #endif |
3807e26d AD |
677 | hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); |
678 | hw->hw_qtd_next = EHCI_LIST_END(ehci); | |
18807521 | 679 | ehci->async->qh_state = QH_STATE_LINKED; |
3807e26d | 680 | hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); |
1da177e4 LT |
681 | |
682 | /* clear interrupt enables, set irq latency */ | |
683 | if (log2_irq_thresh < 0 || log2_irq_thresh > 6) | |
684 | log2_irq_thresh = 0; | |
685 | temp = 1 << (16 + log2_irq_thresh); | |
5a9cdf33 AD |
686 | if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { |
687 | ehci->has_ppcd = 1; | |
688 | ehci_dbg(ehci, "enable per-port change event\n"); | |
689 | temp |= CMD_PPCEE; | |
690 | } | |
1da177e4 LT |
691 | if (HCC_CANPARK(hcc_params)) { |
692 | /* HW default park == 3, on hardware that supports it (like | |
693 | * NVidia and ALI silicon), maximizes throughput on the async | |
694 | * schedule by avoiding QH fetches between transfers. | |
695 | * | |
696 | * With fast usb storage devices and NForce2, "park" seems to | |
697 | * make problems: throughput reduction (!), data errors... | |
698 | */ | |
699 | if (park) { | |
18807521 | 700 | park = min(park, (unsigned) 3); |
1da177e4 LT |
701 | temp |= CMD_PARK; |
702 | temp |= park << 8; | |
703 | } | |
18807521 | 704 | ehci_dbg(ehci, "park %d\n", park); |
1da177e4 | 705 | } |
18807521 | 706 | if (HCC_PGM_FRAMELISTLEN(hcc_params)) { |
1da177e4 LT |
707 | /* periodic schedule size can be smaller than default */ |
708 | temp &= ~(3 << 2); | |
709 | temp |= (EHCI_TUNE_FLS << 2); | |
1da177e4 | 710 | } |
48f24970 AD |
711 | if (HCC_LPM(hcc_params)) { |
712 | /* support link power management EHCI 1.1 addendum */ | |
713 | ehci_dbg(ehci, "support lpm\n"); | |
714 | ehci->has_lpm = 1; | |
715 | if (hird > 0xf) { | |
716 | ehci_dbg(ehci, "hird %d invalid, use default 0", | |
717 | hird); | |
718 | hird = 0; | |
719 | } | |
720 | temp |= hird << 24; | |
721 | } | |
18807521 DB |
722 | ehci->command = temp; |
723 | ||
40f8db8f | 724 | /* Accept arbitrarily long scatter-gather lists */ |
4307a28e AR |
725 | if (!(hcd->driver->flags & HCD_LOCAL_MEM)) |
726 | hcd->self.sg_tablesize = ~0; | |
18807521 DB |
727 | return 0; |
728 | } | |
729 | ||
730 | /* start HC running; it's halted, ehci_init() has been run (once) */ | |
731 | static int ehci_run (struct usb_hcd *hcd) | |
732 | { | |
733 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
18807521 DB |
734 | u32 temp; |
735 | u32 hcc_params; | |
736 | ||
1d619f12 | 737 | hcd->uses_new_polling = 1; |
1d619f12 | 738 | |
18807521 | 739 | /* EHCI spec section 4.1 */ |
876e0df9 | 740 | |
083522d7 BH |
741 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); |
742 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
18807521 DB |
743 | |
744 | /* | |
745 | * hcc_params controls whether ehci->regs->segment must (!!!) | |
746 | * be used; it constrains QH/ITD/SITD and QTD locations. | |
747 | * pci_pool consistent memory always uses segment zero. | |
748 | * streaming mappings for I/O buffers, like pci_map_single(), | |
749 | * can return segments above 4GB, if the device allows. | |
750 | * | |
751 | * NOTE: the dma mask is visible through dma_supported(), so | |
752 | * drivers can pass this info along ... like NETIF_F_HIGHDMA, | |
753 | * Scsi_Host.highmem_io, and so forth. It's readonly to all | |
754 | * host side drivers though. | |
755 | */ | |
083522d7 | 756 | hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); |
18807521 | 757 | if (HCC_64BIT_ADDR(hcc_params)) { |
083522d7 | 758 | ehci_writel(ehci, 0, &ehci->regs->segment); |
18807521 DB |
759 | #if 0 |
760 | // this is deeply broken on almost all architectures | |
6a35528a | 761 | if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) |
18807521 DB |
762 | ehci_info(ehci, "enabled 64bit DMA\n"); |
763 | #endif | |
764 | } | |
765 | ||
766 | ||
1da177e4 LT |
767 | // Philips, Intel, and maybe others need CMD_RUN before the |
768 | // root hub will detect new devices (why?); NEC doesn't | |
18807521 DB |
769 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); |
770 | ehci->command |= CMD_RUN; | |
083522d7 | 771 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
18807521 | 772 | dbg_cmd (ehci, "init", ehci->command); |
1da177e4 | 773 | |
1da177e4 LT |
774 | /* |
775 | * Start, enabling full USB 2.0 functionality ... usb 1.1 devices | |
776 | * are explicitly handed to companion controller(s), so no TT is | |
777 | * involved with the root hub. (Except where one is integrated, | |
778 | * and there's no companion controller unless maybe for USB OTG.) | |
32fe0198 AS |
779 | * |
780 | * Turning on the CF flag will transfer ownership of all ports | |
781 | * from the companions to the EHCI controller. If any of the | |
782 | * companions are in the middle of a port reset at the time, it | |
783 | * could cause trouble. Write-locking ehci_cf_port_reset_rwsem | |
1cb52658 DB |
784 | * guarantees that no resets are in progress. After we set CF, |
785 | * a short delay lets the hardware catch up; new resets shouldn't | |
786 | * be started before the port switching actions could complete. | |
1da177e4 | 787 | */ |
32fe0198 | 788 | down_write(&ehci_cf_port_reset_rwsem); |
e8799906 | 789 | ehci->rh_state = EHCI_RH_RUNNING; |
083522d7 BH |
790 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); |
791 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
1cb52658 | 792 | msleep(5); |
32fe0198 | 793 | up_write(&ehci_cf_port_reset_rwsem); |
ee4ecb8a | 794 | ehci->last_periodic_enable = ktime_get_real(); |
1da177e4 | 795 | |
c430131a | 796 | temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
1da177e4 | 797 | ehci_info (ehci, |
2b70f073 | 798 | "USB %x.%x started, EHCI %x.%02x%s\n", |
7ff71d6a | 799 | ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), |
2b70f073 | 800 | temp >> 8, temp & 0xff, |
93f1a47c | 801 | ignore_oc ? ", overcurrent ignored" : ""); |
1da177e4 | 802 | |
083522d7 BH |
803 | ehci_writel(ehci, INTR_MASK, |
804 | &ehci->regs->intr_enable); /* Turn On Interrupts */ | |
1da177e4 | 805 | |
18807521 DB |
806 | /* GRR this is run-once init(), being done every time the HC starts. |
807 | * So long as they're part of class devices, we can't do it init() | |
808 | * since the class device isn't created that early. | |
809 | */ | |
810 | create_debug_files(ehci); | |
4c67045b | 811 | create_sysfs_files(ehci); |
1da177e4 LT |
812 | |
813 | return 0; | |
814 | } | |
815 | ||
2093c6b4 MC |
816 | static int __maybe_unused ehci_setup (struct usb_hcd *hcd) |
817 | { | |
818 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
819 | int retval; | |
820 | ||
821 | ehci->regs = (void __iomem *)ehci->caps + | |
822 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); | |
823 | dbg_hcs_params(ehci, "reset"); | |
824 | dbg_hcc_params(ehci, "reset"); | |
825 | ||
826 | /* cache this readonly data; minimize chip reads */ | |
827 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); | |
828 | ||
829 | ehci->sbrn = HCD_USB2; | |
830 | ||
831 | retval = ehci_halt(ehci); | |
832 | if (retval) | |
833 | return retval; | |
834 | ||
835 | /* data structure init */ | |
836 | retval = ehci_init(hcd); | |
837 | if (retval) | |
838 | return retval; | |
839 | ||
840 | ehci_reset(ehci); | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
1da177e4 LT |
845 | /*-------------------------------------------------------------------------*/ |
846 | ||
7d12e780 | 847 | static irqreturn_t ehci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
848 | { |
849 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
67b2e029 | 850 | u32 status, masked_status, pcd_status = 0, cmd; |
1da177e4 LT |
851 | int bh; |
852 | ||
853 | spin_lock (&ehci->lock); | |
854 | ||
083522d7 | 855 | status = ehci_readl(ehci, &ehci->regs->status); |
1da177e4 LT |
856 | |
857 | /* e.g. cardbus physical eject */ | |
858 | if (status == ~(u32) 0) { | |
859 | ehci_dbg (ehci, "device removed\n"); | |
860 | goto dead; | |
861 | } | |
862 | ||
2fbe2bf1 AS |
863 | /* |
864 | * We don't use STS_FLR, but some controllers don't like it to | |
865 | * remain on, so mask it out along with the other status bits. | |
866 | */ | |
867 | masked_status = status & (INTR_MASK | STS_FLR); | |
868 | ||
69fff59d | 869 | /* Shared IRQ? */ |
e8799906 | 870 | if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { |
1da177e4 LT |
871 | spin_unlock(&ehci->lock); |
872 | return IRQ_NONE; | |
873 | } | |
874 | ||
875 | /* clear (just) interrupts */ | |
67b2e029 | 876 | ehci_writel(ehci, masked_status, &ehci->regs->status); |
e82cc128 | 877 | cmd = ehci_readl(ehci, &ehci->regs->command); |
1da177e4 LT |
878 | bh = 0; |
879 | ||
9776afc8 | 880 | #ifdef VERBOSE_DEBUG |
1da177e4 LT |
881 | /* unrequested/ignored: Frame List Rollover */ |
882 | dbg_status (ehci, "irq", status); | |
883 | #endif | |
884 | ||
885 | /* INT, ERR, and IAA interrupt rates can be throttled */ | |
886 | ||
887 | /* normal [4.15.1.2] or error [4.15.1.1] completion */ | |
888 | if (likely ((status & (STS_INT|STS_ERR)) != 0)) { | |
889 | if (likely ((status & STS_ERR) == 0)) | |
890 | COUNT (ehci->stats.normal); | |
891 | else | |
892 | COUNT (ehci->stats.error); | |
893 | bh = 1; | |
894 | } | |
895 | ||
896 | /* complete the unlinking of some qh [4.15.2.3] */ | |
897 | if (status & STS_IAA) { | |
e82cc128 | 898 | /* guard against (alleged) silicon errata */ |
6feff1b9 | 899 | if (cmd & CMD_IAAD) |
e82cc128 | 900 | ehci_dbg(ehci, "IAA with IAAD still set?\n"); |
e82cc128 DB |
901 | if (ehci->reclaim) { |
902 | COUNT(ehci->stats.reclaim); | |
903 | end_unlink_async(ehci); | |
904 | } else | |
905 | ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); | |
1da177e4 LT |
906 | } |
907 | ||
908 | /* remote wakeup [4.3.1] */ | |
d97cc2f2 | 909 | if (status & STS_PCD) { |
1da177e4 | 910 | unsigned i = HCS_N_PORTS (ehci->hcs_params); |
5a9cdf33 | 911 | u32 ppcd = 0; |
d1b1842c DB |
912 | |
913 | /* kick root hub later */ | |
1d619f12 | 914 | pcd_status = status; |
1da177e4 LT |
915 | |
916 | /* resume root hub? */ | |
dc75ce9d | 917 | if (ehci->rh_state == EHCI_RH_SUSPENDED) |
8c03356a | 918 | usb_hcd_resume_root_hub(hcd); |
1da177e4 | 919 | |
5a9cdf33 AD |
920 | /* get per-port change detect bits */ |
921 | if (ehci->has_ppcd) | |
922 | ppcd = status >> 16; | |
923 | ||
1da177e4 | 924 | while (i--) { |
5a9cdf33 AD |
925 | int pstatus; |
926 | ||
927 | /* leverage per-port change bits feature */ | |
928 | if (ehci->has_ppcd && !(ppcd & (1 << i))) | |
929 | continue; | |
930 | pstatus = ehci_readl(ehci, | |
931 | &ehci->regs->port_status[i]); | |
b972b68c DB |
932 | |
933 | if (pstatus & PORT_OWNER) | |
1da177e4 | 934 | continue; |
eafe5b99 AS |
935 | if (!(test_bit(i, &ehci->suspended_ports) && |
936 | ((pstatus & PORT_RESUME) || | |
937 | !(pstatus & PORT_SUSPEND)) && | |
938 | (pstatus & PORT_PE) && | |
939 | ehci->reset_done[i] == 0)) | |
1da177e4 LT |
940 | continue; |
941 | ||
942 | /* start 20 msec resume signaling from this port, | |
943 | * and make khubd collect PORT_STAT_C_SUSPEND to | |
49d0f078 AS |
944 | * stop that signaling. Use 5 ms extra for safety, |
945 | * like usb_port_resume() does. | |
1da177e4 | 946 | */ |
49d0f078 | 947 | ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); |
a448e4dc | 948 | set_bit(i, &ehci->resuming_ports); |
1da177e4 | 949 | ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); |
61e8b858 | 950 | mod_timer(&hcd->rh_timer, ehci->reset_done[i]); |
1da177e4 LT |
951 | } |
952 | } | |
953 | ||
954 | /* PCI errors [4.15.2.4] */ | |
955 | if (unlikely ((status & STS_FATAL) != 0)) { | |
67b2e029 | 956 | ehci_err(ehci, "fatal error\n"); |
eafe5b99 AS |
957 | dbg_cmd(ehci, "fatal", cmd); |
958 | dbg_status(ehci, "fatal", status); | |
67b2e029 | 959 | ehci_halt(ehci); |
1da177e4 | 960 | dead: |
67b2e029 AS |
961 | ehci_reset(ehci); |
962 | ehci_writel(ehci, 0, &ehci->regs->configured_flag); | |
69fff59d | 963 | usb_hc_died(hcd); |
67b2e029 AS |
964 | /* generic layer kills/unlinks all urbs, then |
965 | * uses ehci_stop to clean up the rest | |
966 | */ | |
967 | bh = 1; | |
1da177e4 LT |
968 | } |
969 | ||
970 | if (bh) | |
7d12e780 | 971 | ehci_work (ehci); |
1da177e4 | 972 | spin_unlock (&ehci->lock); |
d1b1842c | 973 | if (pcd_status) |
1d619f12 | 974 | usb_hcd_poll_rh_status(hcd); |
1da177e4 LT |
975 | return IRQ_HANDLED; |
976 | } | |
977 | ||
978 | /*-------------------------------------------------------------------------*/ | |
979 | ||
980 | /* | |
981 | * non-error returns are a promise to giveback() the urb later | |
982 | * we drop ownership so next owner (or urb unlink) can get it | |
983 | * | |
984 | * urb + dev is in hcd.self.controller.urb_list | |
985 | * we're queueing TDs onto software and hardware lists | |
986 | * | |
987 | * hcd-specific init for hcpriv hasn't been done yet | |
988 | * | |
989 | * NOTE: control, bulk, and interrupt share the same code to append TDs | |
990 | * to a (possibly active) QH, and the same QH scanning code. | |
991 | */ | |
992 | static int ehci_urb_enqueue ( | |
993 | struct usb_hcd *hcd, | |
1da177e4 | 994 | struct urb *urb, |
55016f10 | 995 | gfp_t mem_flags |
1da177e4 LT |
996 | ) { |
997 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
998 | struct list_head qtd_list; | |
999 | ||
1000 | INIT_LIST_HEAD (&qtd_list); | |
1001 | ||
1002 | switch (usb_pipetype (urb->pipe)) { | |
25b70a86 DB |
1003 | case PIPE_CONTROL: |
1004 | /* qh_completions() code doesn't handle all the fault cases | |
1005 | * in multi-TD control transfers. Even 1KB is rare anyway. | |
1006 | */ | |
1007 | if (urb->transfer_buffer_length > (16 * 1024)) | |
1008 | return -EMSGSIZE; | |
1009 | /* FALLTHROUGH */ | |
1010 | /* case PIPE_BULK: */ | |
1da177e4 LT |
1011 | default: |
1012 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
1013 | return -ENOMEM; | |
e9df41c5 | 1014 | return submit_async(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
1015 | |
1016 | case PIPE_INTERRUPT: | |
1017 | if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) | |
1018 | return -ENOMEM; | |
e9df41c5 | 1019 | return intr_submit(ehci, urb, &qtd_list, mem_flags); |
1da177e4 LT |
1020 | |
1021 | case PIPE_ISOCHRONOUS: | |
1022 | if (urb->dev->speed == USB_SPEED_HIGH) | |
1023 | return itd_submit (ehci, urb, mem_flags); | |
1024 | else | |
1025 | return sitd_submit (ehci, urb, mem_flags); | |
1026 | } | |
1027 | } | |
1028 | ||
1029 | static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
1030 | { | |
07d29b63 | 1031 | /* failfast */ |
e8799906 | 1032 | if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim) |
07d29b63 AS |
1033 | end_unlink_async(ehci); |
1034 | ||
3a44494e AS |
1035 | /* If the QH isn't linked then there's nothing we can do |
1036 | * unless we were called during a giveback, in which case | |
1037 | * qh_completions() has to deal with it. | |
1038 | */ | |
1039 | if (qh->qh_state != QH_STATE_LINKED) { | |
1040 | if (qh->qh_state == QH_STATE_COMPLETING) | |
1041 | qh->needs_rescan = 1; | |
1042 | return; | |
1043 | } | |
07d29b63 AS |
1044 | |
1045 | /* defer till later if busy */ | |
3a44494e | 1046 | if (ehci->reclaim) { |
1da177e4 LT |
1047 | struct ehci_qh *last; |
1048 | ||
1049 | for (last = ehci->reclaim; | |
1050 | last->reclaim; | |
1051 | last = last->reclaim) | |
1052 | continue; | |
1053 | qh->qh_state = QH_STATE_UNLINK_WAIT; | |
1054 | last->reclaim = qh; | |
1055 | ||
07d29b63 AS |
1056 | /* start IAA cycle */ |
1057 | } else | |
1da177e4 LT |
1058 | start_unlink_async (ehci, qh); |
1059 | } | |
1060 | ||
1061 | /* remove from hardware lists | |
1062 | * completions normally happen asynchronously | |
1063 | */ | |
1064 | ||
e9df41c5 | 1065 | static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
1066 | { |
1067 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1068 | struct ehci_qh *qh; | |
1069 | unsigned long flags; | |
e9df41c5 | 1070 | int rc; |
1da177e4 LT |
1071 | |
1072 | spin_lock_irqsave (&ehci->lock, flags); | |
e9df41c5 AS |
1073 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
1074 | if (rc) | |
1075 | goto done; | |
1076 | ||
1da177e4 LT |
1077 | switch (usb_pipetype (urb->pipe)) { |
1078 | // case PIPE_CONTROL: | |
1079 | // case PIPE_BULK: | |
1080 | default: | |
1081 | qh = (struct ehci_qh *) urb->hcpriv; | |
1082 | if (!qh) | |
1083 | break; | |
07d29b63 AS |
1084 | switch (qh->qh_state) { |
1085 | case QH_STATE_LINKED: | |
1086 | case QH_STATE_COMPLETING: | |
1087 | unlink_async(ehci, qh); | |
1088 | break; | |
1089 | case QH_STATE_UNLINK: | |
1090 | case QH_STATE_UNLINK_WAIT: | |
1091 | /* already started */ | |
1092 | break; | |
1093 | case QH_STATE_IDLE: | |
7a0f0d95 AS |
1094 | /* QH might be waiting for a Clear-TT-Buffer */ |
1095 | qh_completions(ehci, qh); | |
07d29b63 AS |
1096 | break; |
1097 | } | |
1da177e4 LT |
1098 | break; |
1099 | ||
1100 | case PIPE_INTERRUPT: | |
1101 | qh = (struct ehci_qh *) urb->hcpriv; | |
1102 | if (!qh) | |
1103 | break; | |
1104 | switch (qh->qh_state) { | |
1105 | case QH_STATE_LINKED: | |
a448c9d8 | 1106 | case QH_STATE_COMPLETING: |
1da177e4 | 1107 | intr_deschedule (ehci, qh); |
a448c9d8 | 1108 | break; |
1da177e4 | 1109 | case QH_STATE_IDLE: |
7d12e780 | 1110 | qh_completions (ehci, qh); |
1da177e4 LT |
1111 | break; |
1112 | default: | |
1113 | ehci_dbg (ehci, "bogus qh %p state %d\n", | |
1114 | qh, qh->qh_state); | |
1115 | goto done; | |
1116 | } | |
1da177e4 LT |
1117 | break; |
1118 | ||
1119 | case PIPE_ISOCHRONOUS: | |
1120 | // itd or sitd ... | |
1121 | ||
1122 | // wait till next completion, do it then. | |
1123 | // completion irqs can wait up to 1024 msec, | |
1124 | break; | |
1125 | } | |
1126 | done: | |
1127 | spin_unlock_irqrestore (&ehci->lock, flags); | |
e9df41c5 | 1128 | return rc; |
1da177e4 LT |
1129 | } |
1130 | ||
1131 | /*-------------------------------------------------------------------------*/ | |
1132 | ||
1133 | // bulk qh holds the data toggle | |
1134 | ||
1135 | static void | |
1136 | ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1137 | { | |
1138 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
1139 | unsigned long flags; | |
1140 | struct ehci_qh *qh, *tmp; | |
1141 | ||
1142 | /* ASSERT: any requests/urbs are being unlinked */ | |
1143 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
1144 | ||
1145 | rescan: | |
1146 | spin_lock_irqsave (&ehci->lock, flags); | |
1147 | qh = ep->hcpriv; | |
1148 | if (!qh) | |
1149 | goto done; | |
1150 | ||
1151 | /* endpoints can be iso streams. for now, we don't | |
1152 | * accelerate iso completions ... so spin a while. | |
1153 | */ | |
1082f57a | 1154 | if (qh->hw == NULL) { |
1da177e4 LT |
1155 | ehci_vdbg (ehci, "iso delay\n"); |
1156 | goto idle_timeout; | |
1157 | } | |
1158 | ||
e8799906 | 1159 | if (ehci->rh_state != EHCI_RH_RUNNING) |
1da177e4 LT |
1160 | qh->qh_state = QH_STATE_IDLE; |
1161 | switch (qh->qh_state) { | |
1162 | case QH_STATE_LINKED: | |
3a44494e | 1163 | case QH_STATE_COMPLETING: |
1da177e4 LT |
1164 | for (tmp = ehci->async->qh_next.qh; |
1165 | tmp && tmp != qh; | |
1166 | tmp = tmp->qh_next.qh) | |
1167 | continue; | |
02e2c51b AS |
1168 | /* periodic qh self-unlinks on empty, and a COMPLETING qh |
1169 | * may already be unlinked. | |
1170 | */ | |
1171 | if (tmp) | |
1172 | unlink_async(ehci, qh); | |
1da177e4 LT |
1173 | /* FALL THROUGH */ |
1174 | case QH_STATE_UNLINK: /* wait for hw to finish? */ | |
07d29b63 | 1175 | case QH_STATE_UNLINK_WAIT: |
1da177e4 LT |
1176 | idle_timeout: |
1177 | spin_unlock_irqrestore (&ehci->lock, flags); | |
22c43863 | 1178 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
1179 | goto rescan; |
1180 | case QH_STATE_IDLE: /* fully unlinked */ | |
914b7012 AS |
1181 | if (qh->clearing_tt) |
1182 | goto idle_timeout; | |
1da177e4 LT |
1183 | if (list_empty (&qh->qtd_list)) { |
1184 | qh_put (qh); | |
1185 | break; | |
1186 | } | |
1187 | /* else FALL THROUGH */ | |
1188 | default: | |
1da177e4 LT |
1189 | /* caller was supposed to have unlinked any requests; |
1190 | * that's not our job. just leak this memory. | |
1191 | */ | |
1192 | ehci_err (ehci, "qh %p (#%02x) state %d%s\n", | |
1193 | qh, ep->desc.bEndpointAddress, qh->qh_state, | |
1194 | list_empty (&qh->qtd_list) ? "" : "(has tds)"); | |
1195 | break; | |
1196 | } | |
1197 | ep->hcpriv = NULL; | |
1198 | done: | |
1199 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1da177e4 LT |
1200 | } |
1201 | ||
b18ffd49 AS |
1202 | static void |
1203 | ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
1204 | { | |
1205 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
1206 | struct ehci_qh *qh; | |
1207 | int eptype = usb_endpoint_type(&ep->desc); | |
a455212d AS |
1208 | int epnum = usb_endpoint_num(&ep->desc); |
1209 | int is_out = usb_endpoint_dir_out(&ep->desc); | |
1210 | unsigned long flags; | |
b18ffd49 AS |
1211 | |
1212 | if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) | |
1213 | return; | |
1214 | ||
a455212d | 1215 | spin_lock_irqsave(&ehci->lock, flags); |
b18ffd49 AS |
1216 | qh = ep->hcpriv; |
1217 | ||
1218 | /* For Bulk and Interrupt endpoints we maintain the toggle state | |
1219 | * in the hardware; the toggle bits in udev aren't used at all. | |
1220 | * When an endpoint is reset by usb_clear_halt() we must reset | |
1221 | * the toggle bit in the QH. | |
1222 | */ | |
1223 | if (qh) { | |
a455212d | 1224 | usb_settoggle(qh->dev, epnum, is_out, 0); |
b18ffd49 AS |
1225 | if (!list_empty(&qh->qtd_list)) { |
1226 | WARN_ONCE(1, "clear_halt for a busy endpoint\n"); | |
3a44494e AS |
1227 | } else if (qh->qh_state == QH_STATE_LINKED || |
1228 | qh->qh_state == QH_STATE_COMPLETING) { | |
a455212d AS |
1229 | |
1230 | /* The toggle value in the QH can't be updated | |
1231 | * while the QH is active. Unlink it now; | |
1232 | * re-linking will call qh_refresh(). | |
b18ffd49 | 1233 | */ |
a448c9d8 | 1234 | if (eptype == USB_ENDPOINT_XFER_BULK) |
a455212d | 1235 | unlink_async(ehci, qh); |
a448c9d8 | 1236 | else |
a455212d | 1237 | intr_deschedule(ehci, qh); |
b18ffd49 AS |
1238 | } |
1239 | } | |
a455212d | 1240 | spin_unlock_irqrestore(&ehci->lock, flags); |
b18ffd49 AS |
1241 | } |
1242 | ||
7ff71d6a MP |
1243 | static int ehci_get_frame (struct usb_hcd *hcd) |
1244 | { | |
1245 | struct ehci_hcd *ehci = hcd_to_ehci (hcd); | |
68aa95d5 | 1246 | return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; |
7ff71d6a | 1247 | } |
1da177e4 LT |
1248 | |
1249 | /*-------------------------------------------------------------------------*/ | |
eb70e5ab AS |
1250 | /* |
1251 | * The EHCI in ChipIdea HDRC cannot be a separate module or device, | |
1252 | * because its registers (and irq) are shared between host/gadget/otg | |
1253 | * functions and in order to facilitate role switching we cannot | |
1254 | * give the ehci driver exclusive access to those. | |
1255 | */ | |
1256 | #ifndef CHIPIDEA_EHCI | |
1da177e4 | 1257 | |
2b70f073 | 1258 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1259 | MODULE_AUTHOR (DRIVER_AUTHOR); |
1260 | MODULE_LICENSE ("GPL"); | |
1261 | ||
7ff71d6a MP |
1262 | #ifdef CONFIG_PCI |
1263 | #include "ehci-pci.c" | |
01cced25 | 1264 | #define PCI_DRIVER ehci_pci_driver |
7ff71d6a | 1265 | #endif |
1da177e4 | 1266 | |
ba02978a | 1267 | #ifdef CONFIG_USB_EHCI_FSL |
80cb9aee | 1268 | #include "ehci-fsl.c" |
01cced25 | 1269 | #define PLATFORM_DRIVER ehci_fsl_driver |
80cb9aee RV |
1270 | #endif |
1271 | ||
7e8d5cd9 DM |
1272 | #ifdef CONFIG_USB_EHCI_MXC |
1273 | #include "ehci-mxc.c" | |
1274 | #define PLATFORM_DRIVER ehci_mxc_driver | |
1275 | #endif | |
1276 | ||
60b0bf0f | 1277 | #ifdef CONFIG_USB_EHCI_SH |
63c84552 PM |
1278 | #include "ehci-sh.c" |
1279 | #define PLATFORM_DRIVER ehci_hcd_sh_driver | |
1280 | #endif | |
1281 | ||
37663860 | 1282 | #ifdef CONFIG_MIPS_ALCHEMY |
76fa9a24 | 1283 | #include "ehci-au1xxx.c" |
01cced25 | 1284 | #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver |
76fa9a24 JC |
1285 | #endif |
1286 | ||
7f124f4b | 1287 | #ifdef CONFIG_USB_EHCI_HCD_OMAP |
54ab2b02 FB |
1288 | #include "ehci-omap.c" |
1289 | #define PLATFORM_DRIVER ehci_hcd_omap_driver | |
1290 | #endif | |
1291 | ||
ad75a410 GL |
1292 | #ifdef CONFIG_PPC_PS3 |
1293 | #include "ehci-ps3.c" | |
7a4eb7fd | 1294 | #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver |
ad75a410 GL |
1295 | #endif |
1296 | ||
da0e8fb0 VB |
1297 | #ifdef CONFIG_USB_EHCI_HCD_PPC_OF |
1298 | #include "ehci-ppc-of.c" | |
1299 | #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver | |
1300 | #endif | |
1301 | ||
08d3c18e JZ |
1302 | #ifdef CONFIG_XPS_USB_HCD_XILINX |
1303 | #include "ehci-xilinx-of.c" | |
1f23b2d9 | 1304 | #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver |
08d3c18e JZ |
1305 | #endif |
1306 | ||
705a7521 | 1307 | #ifdef CONFIG_PLAT_ORION |
e96ffe2f TP |
1308 | #include "ehci-orion.c" |
1309 | #define PLATFORM_DRIVER ehci_orion_driver | |
1310 | #endif | |
1311 | ||
91bc4d31 VB |
1312 | #ifdef CONFIG_ARCH_IXP4XX |
1313 | #include "ehci-ixp4xx.c" | |
1314 | #define PLATFORM_DRIVER ixp4xx_ehci_driver | |
1315 | #endif | |
1316 | ||
586dfc8c WZ |
1317 | #ifdef CONFIG_USB_W90X900_EHCI |
1318 | #include "ehci-w90x900.c" | |
1319 | #define PLATFORM_DRIVER ehci_hcd_w90x900_driver | |
1320 | #endif | |
1321 | ||
501c9c08 NF |
1322 | #ifdef CONFIG_ARCH_AT91 |
1323 | #include "ehci-atmel.c" | |
1324 | #define PLATFORM_DRIVER ehci_atmel_driver | |
1325 | #endif | |
1326 | ||
1643accd DD |
1327 | #ifdef CONFIG_USB_OCTEON_EHCI |
1328 | #include "ehci-octeon.c" | |
1329 | #define PLATFORM_DRIVER ehci_octeon_driver | |
1330 | #endif | |
1331 | ||
760efe69 ML |
1332 | #ifdef CONFIG_USB_CNS3XXX_EHCI |
1333 | #include "ehci-cns3xxx.c" | |
1334 | #define PLATFORM_DRIVER cns3xxx_ehci_driver | |
1335 | #endif | |
1336 | ||
ad78acaf AC |
1337 | #ifdef CONFIG_ARCH_VT8500 |
1338 | #include "ehci-vt8500.c" | |
1339 | #define PLATFORM_DRIVER vt8500_ehci_driver | |
1340 | #endif | |
1341 | ||
c8c38de9 DS |
1342 | #ifdef CONFIG_PLAT_SPEAR |
1343 | #include "ehci-spear.c" | |
1344 | #define PLATFORM_DRIVER spear_ehci_hcd_driver | |
1345 | #endif | |
1346 | ||
b0848aea PK |
1347 | #ifdef CONFIG_USB_EHCI_MSM |
1348 | #include "ehci-msm.c" | |
1349 | #define PLATFORM_DRIVER ehci_msm_driver | |
1350 | #endif | |
1351 | ||
22ced687 A |
1352 | #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP |
1353 | #include "ehci-pmcmsp.c" | |
1354 | #define PLATFORM_DRIVER ehci_hcd_msp_driver | |
1355 | #endif | |
1356 | ||
79ad3b5a BG |
1357 | #ifdef CONFIG_USB_EHCI_TEGRA |
1358 | #include "ehci-tegra.c" | |
1359 | #define PLATFORM_DRIVER tegra_ehci_driver | |
1360 | #endif | |
1361 | ||
1bcc5aa8 JS |
1362 | #ifdef CONFIG_USB_EHCI_S5P |
1363 | #include "ehci-s5p.c" | |
1364 | #define PLATFORM_DRIVER s5p_ehci_driver | |
1365 | #endif | |
1366 | ||
9be03929 JA |
1367 | #ifdef CONFIG_SPARC_LEON |
1368 | #include "ehci-grlib.c" | |
1369 | #define PLATFORM_DRIVER ehci_grlib_driver | |
1370 | #endif | |
1371 | ||
3af5154a | 1372 | #ifdef CONFIG_CPU_XLR |
23106343 J |
1373 | #include "ehci-xls.c" |
1374 | #define PLATFORM_DRIVER ehci_xls_driver | |
1375 | #endif | |
1376 | ||
3a082ec9 NZ |
1377 | #ifdef CONFIG_USB_EHCI_MV |
1378 | #include "ehci-mv.c" | |
1379 | #define PLATFORM_DRIVER ehci_mv_driver | |
1380 | #endif | |
1381 | ||
f30cdbcb KC |
1382 | #ifdef CONFIG_MACH_LOONGSON1 |
1383 | #include "ehci-ls1x.c" | |
1384 | #define PLATFORM_DRIVER ehci_ls1x_driver | |
1385 | #endif | |
1386 | ||
c256667f SH |
1387 | #ifdef CONFIG_MIPS_SEAD3 |
1388 | #include "ehci-sead3.c" | |
1389 | #define PLATFORM_DRIVER ehci_hcd_sead3_driver | |
1390 | #endif | |
1391 | ||
7a7a4a59 HM |
1392 | #ifdef CONFIG_USB_EHCI_HCD_PLATFORM |
1393 | #include "ehci-platform.c" | |
1394 | #define PLATFORM_DRIVER ehci_platform_driver | |
1395 | #endif | |
1396 | ||
ad75a410 | 1397 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
1f23b2d9 GL |
1398 | !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ |
1399 | !defined(XILINX_OF_PLATFORM_DRIVER) | |
7ff71d6a MP |
1400 | #error "missing bus glue for ehci-hcd" |
1401 | #endif | |
01cced25 KG |
1402 | |
1403 | static int __init ehci_hcd_init(void) | |
1404 | { | |
1405 | int retval = 0; | |
1406 | ||
2b70f073 AS |
1407 | if (usb_disabled()) |
1408 | return -ENODEV; | |
1409 | ||
1410 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); | |
9beeee65 AS |
1411 | set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
1412 | if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || | |
1413 | test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) | |
1414 | printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" | |
1415 | " before uhci_hcd and ohci_hcd, not after\n"); | |
1416 | ||
01cced25 KG |
1417 | pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", |
1418 | hcd_name, | |
1419 | sizeof(struct ehci_qh), sizeof(struct ehci_qtd), | |
1420 | sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); | |
1421 | ||
694cc208 | 1422 | #ifdef DEBUG |
08f4e586 | 1423 | ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); |
9beeee65 AS |
1424 | if (!ehci_debug_root) { |
1425 | retval = -ENOENT; | |
1426 | goto err_debug; | |
1427 | } | |
694cc208 TJ |
1428 | #endif |
1429 | ||
01cced25 KG |
1430 | #ifdef PLATFORM_DRIVER |
1431 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
da0e8fb0 VB |
1432 | if (retval < 0) |
1433 | goto clean0; | |
01cced25 KG |
1434 | #endif |
1435 | ||
1436 | #ifdef PCI_DRIVER | |
1437 | retval = pci_register_driver(&PCI_DRIVER); | |
da0e8fb0 VB |
1438 | if (retval < 0) |
1439 | goto clean1; | |
ad75a410 GL |
1440 | #endif |
1441 | ||
1442 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
7a4eb7fd | 1443 | retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
da0e8fb0 VB |
1444 | if (retval < 0) |
1445 | goto clean2; | |
694cc208 | 1446 | #endif |
da0e8fb0 VB |
1447 | |
1448 | #ifdef OF_PLATFORM_DRIVER | |
d35fb641 | 1449 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1450 | if (retval < 0) |
1451 | goto clean3; | |
1452 | #endif | |
1f23b2d9 GL |
1453 | |
1454 | #ifdef XILINX_OF_PLATFORM_DRIVER | |
d35fb641 | 1455 | retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); |
1f23b2d9 GL |
1456 | if (retval < 0) |
1457 | goto clean4; | |
1458 | #endif | |
da0e8fb0 VB |
1459 | return retval; |
1460 | ||
1f23b2d9 | 1461 | #ifdef XILINX_OF_PLATFORM_DRIVER |
d35fb641 | 1462 | /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ |
1f23b2d9 GL |
1463 | clean4: |
1464 | #endif | |
da0e8fb0 | 1465 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1466 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
da0e8fb0 VB |
1467 | clean3: |
1468 | #endif | |
1469 | #ifdef PS3_SYSTEM_BUS_DRIVER | |
1470 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); | |
1471 | clean2: | |
ad75a410 GL |
1472 | #endif |
1473 | #ifdef PCI_DRIVER | |
da0e8fb0 VB |
1474 | pci_unregister_driver(&PCI_DRIVER); |
1475 | clean1: | |
ad75a410 | 1476 | #endif |
da0e8fb0 VB |
1477 | #ifdef PLATFORM_DRIVER |
1478 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1479 | clean0: | |
1480 | #endif | |
1481 | #ifdef DEBUG | |
1482 | debugfs_remove(ehci_debug_root); | |
1483 | ehci_debug_root = NULL; | |
9beeee65 | 1484 | err_debug: |
a9b6148d | 1485 | #endif |
9beeee65 | 1486 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1487 | return retval; |
1488 | } | |
1489 | module_init(ehci_hcd_init); | |
1490 | ||
1491 | static void __exit ehci_hcd_cleanup(void) | |
1492 | { | |
1f23b2d9 | 1493 | #ifdef XILINX_OF_PLATFORM_DRIVER |
d35fb641 | 1494 | platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); |
1f23b2d9 | 1495 | #endif |
da0e8fb0 | 1496 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1497 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
da0e8fb0 | 1498 | #endif |
01cced25 KG |
1499 | #ifdef PLATFORM_DRIVER |
1500 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1501 | #endif | |
1502 | #ifdef PCI_DRIVER | |
1503 | pci_unregister_driver(&PCI_DRIVER); | |
1504 | #endif | |
ad75a410 | 1505 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1506 | ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
ad75a410 | 1507 | #endif |
694cc208 TJ |
1508 | #ifdef DEBUG |
1509 | debugfs_remove(ehci_debug_root); | |
1510 | #endif | |
9beeee65 | 1511 | clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); |
01cced25 KG |
1512 | } |
1513 | module_exit(ehci_hcd_cleanup); | |
1514 | ||
eb70e5ab | 1515 | #endif /* CHIPIDEA_EHCI */ |