[deliverable/linux.git] / drivers / usb / host / ehci-mem.c

/*
 * Copyright (c) 2001 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* this file is part of ehci-hcd.c */

/*-------------------------------------------------------------------------*/

/*
 * There's basically three types of memory:
 *	- data used only by the HCD ... kmalloc is fine
 *	- async and periodic schedules, shared by HC and HCD ... these
 *	  need to use dma_pool or dma_alloc_coherent
 *	- driver buffers, read/written by HC ... single shot DMA mapped
 *
 * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
 * No memory seen by this driver is pageable.
 */

/*-------------------------------------------------------------------------*/

/* Allocate the key transfer structures from the previously allocated pool */

static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
				  dma_addr_t dma)
{
	memset (qtd, 0, sizeof *qtd);
	qtd->qtd_dma = dma;
	qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
	qtd->hw_next = EHCI_LIST_END(ehci);
	qtd->hw_alt_next = EHCI_LIST_END(ehci);
	INIT_LIST_HEAD (&qtd->qtd_list);
}

static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
{
	struct ehci_qtd		*qtd;
	dma_addr_t		dma;

	qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
	if (qtd != NULL) {
		ehci_qtd_init(ehci, qtd, dma);
	}
	return qtd;
}

static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
{
	dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
}


static void qh_destroy(struct ehci_qh *qh)
{
	struct ehci_hcd *ehci = qh->ehci;

	/* clean qtds first, and know this is not linked */
	if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
		ehci_dbg (ehci, "unused qh not empty!\n");
		BUG ();
	}
	if (qh->dummy)
		ehci_qtd_free (ehci, qh->dummy);
	dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
	kfree(qh);
}

static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
{
	struct ehci_qh		*qh;
	dma_addr_t		dma;

	qh = kzalloc(sizeof *qh, GFP_ATOMIC);
	if (!qh)
		goto done;
	qh->hw = (struct ehci_qh_hw *)
		dma_pool_alloc(ehci->qh_pool, flags, &dma);
	if (!qh->hw)
		goto fail;
	memset(qh->hw, 0, sizeof *qh->hw);
	qh->refcount = 1;
	qh->ehci = ehci;
	qh->qh_dma = dma;
	// INIT_LIST_HEAD (&qh->qh_list);
	INIT_LIST_HEAD (&qh->qtd_list);

	/* dummy td enables safe urb queuing */
	qh->dummy = ehci_qtd_alloc (ehci, flags);
	if (qh->dummy == NULL) {
		ehci_dbg (ehci, "no dummy td\n");
		goto fail1;
	}
done:
	return qh;
fail1:
	dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
fail:
	kfree(qh);
	return NULL;
}

/* to share a qh (cpu threads, or hc) */
static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
{
	WARN_ON(!qh->refcount);
	qh->refcount++;
	return qh;
}

static inline void qh_put (struct ehci_qh *qh)
{
	if (!--qh->refcount)
		qh_destroy(qh);
}

/*-------------------------------------------------------------------------*/

/* The queue heads and transfer descriptors are managed from pools tied
 * to each of the "per device" structures.
 * This is the initialisation and cleanup code.
 */

static void ehci_mem_cleanup (struct ehci_hcd *ehci)
{
	free_cached_lists(ehci);
	if (ehci->async)
		qh_put (ehci->async);
	ehci->async = NULL;

	/* DMA consistent memory and pools */
	if (ehci->qtd_pool)
		dma_pool_destroy (ehci->qtd_pool);
	ehci->qtd_pool = NULL;

	if (ehci->qh_pool) {
		dma_pool_destroy (ehci->qh_pool);
		ehci->qh_pool = NULL;
	}

	if (ehci->itd_pool)
		dma_pool_destroy (ehci->itd_pool);
	ehci->itd_pool = NULL;

	if (ehci->sitd_pool)
		dma_pool_destroy (ehci->sitd_pool);
	ehci->sitd_pool = NULL;

	if (ehci->periodic)
		dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
			ehci->periodic_size * sizeof (u32),
			ehci->periodic, ehci->periodic_dma);
	ehci->periodic = NULL;

	/* shadow periodic table */
	kfree(ehci->pshadow);
	ehci->pshadow = NULL;
}

/* remember to add cleanup code (above) if you add anything here */
static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
{
	int i;

	/* QTDs for control/bulk/intr transfers */
	ehci->qtd_pool = dma_pool_create ("ehci_qtd",
			ehci_to_hcd(ehci)->self.controller,
			sizeof (struct ehci_qtd),
			32 /* byte alignment (for hw parts) */,
			4096 /* can't cross 4K */);
	if (!ehci->qtd_pool) {
		goto fail;
	}

	/* QHs for control/bulk/intr transfers */
	ehci->qh_pool = dma_pool_create ("ehci_qh",
			ehci_to_hcd(ehci)->self.controller,
			sizeof(struct ehci_qh_hw),
			32 /* byte alignment (for hw parts) */,
			4096 /* can't cross 4K */);
	if (!ehci->qh_pool) {
		goto fail;
	}
	ehci->async = ehci_qh_alloc (ehci, flags);
	if (!ehci->async) {
		goto fail;
	}

	/* ITD for high speed ISO transfers */
	ehci->itd_pool = dma_pool_create ("ehci_itd",
			ehci_to_hcd(ehci)->self.controller,
			sizeof (struct ehci_itd),
			32 /* byte alignment (for hw parts) */,
			4096 /* can't cross 4K */);
	if (!ehci->itd_pool) {
		goto fail;
	}

	/* SITD for full/low speed split ISO transfers */
	ehci->sitd_pool = dma_pool_create ("ehci_sitd",
			ehci_to_hcd(ehci)->self.controller,
			sizeof (struct ehci_sitd),
			32 /* byte alignment (for hw parts) */,
			4096 /* can't cross 4K */);
	if (!ehci->sitd_pool) {
		goto fail;
	}

	/* Hardware periodic table */
	ehci->periodic = (__le32 *)
		dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
			ehci->periodic_size * sizeof(__le32),
			&ehci->periodic_dma, 0);
	if (ehci->periodic == NULL) {
		goto fail;
	}
	for (i = 0; i < ehci->periodic_size; i++)
		ehci->periodic [i] = EHCI_LIST_END(ehci);

	/* software shadow of hardware table */
	ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
	if (ehci->pshadow != NULL)
		return 0;

fail:
	ehci_dbg (ehci, "couldn't init memory\n");
	ehci_mem_cleanup (ehci);
	return -ENOMEM;
}
Commit	Line	Data
1da177e4 LT	1	/*
1da177e4 LT	2	* Copyright (c) 2001 by David Brownell
53bd6a60	3	*
1da177e4 LT	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the
	6	* Free Software Foundation; either version 2 of the License, or (at your
	7	* option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but
	10	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	11	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	12	* for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software Foundation,
	16	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*/
	18
	19	/* this file is part of ehci-hcd.c */
	20
	21	/-------------------------------------------------------------------------/
	22
	23	/*
	24	* There's basically three types of memory:
	25	* - data used only by the HCD ... kmalloc is fine
	26	* - async and periodic schedules, shared by HC and HCD ... these
	27	* need to use dma_pool or dma_alloc_coherent
53bd6a60	28	* - driver buffers, read/written by HC ... single shot DMA mapped
1da177e4	29	*
6dbd682b	30	* There's also "register" data (e.g. PCI or SOC), which is memory mapped.
1da177e4 LT	31	* No memory seen by this driver is pageable.
	32	*/
	33
	34	/-------------------------------------------------------------------------/
	35
	36	/* Allocate the key transfer structures from the previously allocated pool */
	37
6dbd682b SR	38	static inline void ehci_qtd_init(struct ehci_hcd ehci, struct ehci_qtd qtd,
6dbd682b SR	39	dma_addr_t dma)
1da177e4 LT	40	{
	41	memset (qtd, 0, sizeof *qtd);
	42	qtd->qtd_dma = dma;
	43	qtd->hw_token = cpu_to_le32 (QTD_STS_HALT);
6dbd682b SR	44	qtd->hw_next = EHCI_LIST_END(ehci);
6dbd682b SR	45	qtd->hw_alt_next = EHCI_LIST_END(ehci);
1da177e4 LT	46	INIT_LIST_HEAD (&qtd->qtd_list);
	47	}
	48
55016f10	49	static struct ehci_qtd ehci_qtd_alloc (struct ehci_hcd ehci, gfp_t flags)
1da177e4 LT	50	{
	51	struct ehci_qtd *qtd;
	52	dma_addr_t dma;
	53
	54	qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
	55	if (qtd != NULL) {
6dbd682b	56	ehci_qtd_init(ehci, qtd, dma);
1da177e4 LT	57	}
	58	return qtd;
	59	}
	60
	61	static inline void ehci_qtd_free (struct ehci_hcd ehci, struct ehci_qtd qtd)
	62	{
	63	dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
	64	}
	65
	66
9c033e81	67	static void qh_destroy(struct ehci_qh *qh)
1da177e4	68	{
1da177e4 LT	69	struct ehci_hcd *ehci = qh->ehci;
	70
	71	/* clean qtds first, and know this is not linked */
	72	if (!list_empty (&qh->qtd_list) \|\| qh->qh_next.ptr) {
	73	ehci_dbg (ehci, "unused qh not empty!\n");
	74	BUG ();
	75	}
	76	if (qh->dummy)
	77	ehci_qtd_free (ehci, qh->dummy);
3807e26d AD	78	dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
3807e26d AD	79	kfree(qh);
1da177e4 LT	80	}
1da177e4 LT	81
55016f10	82	static struct ehci_qh ehci_qh_alloc (struct ehci_hcd ehci, gfp_t flags)
1da177e4 LT	83	{
	84	struct ehci_qh *qh;
	85	dma_addr_t dma;
	86
3807e26d	87	qh = kzalloc(sizeof *qh, GFP_ATOMIC);
1da177e4	88	if (!qh)
3807e26d AD	89	goto done;
	90	qh->hw = (struct ehci_qh_hw *)
	91	dma_pool_alloc(ehci->qh_pool, flags, &dma);
	92	if (!qh->hw)
	93	goto fail;
	94	memset(qh->hw, 0, sizeof *qh->hw);
9c033e81	95	qh->refcount = 1;
1da177e4 LT	96	qh->ehci = ehci;
	97	qh->qh_dma = dma;
	98	// INIT_LIST_HEAD (&qh->qh_list);
	99	INIT_LIST_HEAD (&qh->qtd_list);
	100
	101	/* dummy td enables safe urb queuing */
	102	qh->dummy = ehci_qtd_alloc (ehci, flags);
	103	if (qh->dummy == NULL) {
	104	ehci_dbg (ehci, "no dummy td\n");
3807e26d	105	goto fail1;
1da177e4	106	}
3807e26d	107	done:
1da177e4	108	return qh;
3807e26d AD	109	fail1:
	110	dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
	111	fail:
	112	kfree(qh);
	113	return NULL;
1da177e4 LT	114	}
	115
	116	/* to share a qh (cpu threads, or hc) */
	117	static inline struct ehci_qh qh_get (struct ehci_qh qh)
	118	{
9c033e81 DB	119	WARN_ON(!qh->refcount);
9c033e81 DB	120	qh->refcount++;
1da177e4 LT	121	return qh;
	122	}
	123
	124	static inline void qh_put (struct ehci_qh *qh)
	125	{
9c033e81 DB	126	if (!--qh->refcount)
9c033e81 DB	127	qh_destroy(qh);
1da177e4 LT	128	}
	129
	130	/-------------------------------------------------------------------------/
	131
53bd6a60	132	/* The queue heads and transfer descriptors are managed from pools tied
1da177e4 LT	133	* to each of the "per device" structures.
	134	* This is the initialisation and cleanup code.
	135	*/
	136
	137	static void ehci_mem_cleanup (struct ehci_hcd *ehci)
	138	{
0e5f231b	139	free_cached_lists(ehci);
1da177e4 LT	140	if (ehci->async)
	141	qh_put (ehci->async);
	142	ehci->async = NULL;
	143
	144	/* DMA consistent memory and pools */
	145	if (ehci->qtd_pool)
	146	dma_pool_destroy (ehci->qtd_pool);
	147	ehci->qtd_pool = NULL;
	148
	149	if (ehci->qh_pool) {
	150	dma_pool_destroy (ehci->qh_pool);
	151	ehci->qh_pool = NULL;
	152	}
	153
	154	if (ehci->itd_pool)
	155	dma_pool_destroy (ehci->itd_pool);
	156	ehci->itd_pool = NULL;
	157
	158	if (ehci->sitd_pool)
	159	dma_pool_destroy (ehci->sitd_pool);
	160	ehci->sitd_pool = NULL;
	161
	162	if (ehci->periodic)
	163	dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
	164	ehci->periodic_size * sizeof (u32),
	165	ehci->periodic, ehci->periodic_dma);
	166	ehci->periodic = NULL;
	167
	168	/* shadow periodic table */
1bc3c9e1	169	kfree(ehci->pshadow);
1da177e4 LT	170	ehci->pshadow = NULL;
	171	}
	172
	173	/* remember to add cleanup code (above) if you add anything here */
55016f10	174	static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
1da177e4 LT	175	{
	176	int i;
	177
	178	/* QTDs for control/bulk/intr transfers */
53bd6a60	179	ehci->qtd_pool = dma_pool_create ("ehci_qtd",
1da177e4 LT	180	ehci_to_hcd(ehci)->self.controller,
	181	sizeof (struct ehci_qtd),
	182	32 /* byte alignment (for hw parts) */,
	183	4096 /* can't cross 4K */);
	184	if (!ehci->qtd_pool) {
	185	goto fail;
	186	}
	187
	188	/* QHs for control/bulk/intr transfers */
53bd6a60	189	ehci->qh_pool = dma_pool_create ("ehci_qh",
1da177e4	190	ehci_to_hcd(ehci)->self.controller,
3807e26d	191	sizeof(struct ehci_qh_hw),
1da177e4 LT	192	32 /* byte alignment (for hw parts) */,
	193	4096 /* can't cross 4K */);
	194	if (!ehci->qh_pool) {
	195	goto fail;
	196	}
	197	ehci->async = ehci_qh_alloc (ehci, flags);
	198	if (!ehci->async) {
	199	goto fail;
	200	}
	201
	202	/* ITD for high speed ISO transfers */
53bd6a60	203	ehci->itd_pool = dma_pool_create ("ehci_itd",
1da177e4 LT	204	ehci_to_hcd(ehci)->self.controller,
	205	sizeof (struct ehci_itd),
	206	32 /* byte alignment (for hw parts) */,
	207	4096 /* can't cross 4K */);
	208	if (!ehci->itd_pool) {
	209	goto fail;
	210	}
	211
	212	/* SITD for full/low speed split ISO transfers */
53bd6a60	213	ehci->sitd_pool = dma_pool_create ("ehci_sitd",
1da177e4 LT	214	ehci_to_hcd(ehci)->self.controller,
	215	sizeof (struct ehci_sitd),
	216	32 /* byte alignment (for hw parts) */,
	217	4096 /* can't cross 4K */);
	218	if (!ehci->sitd_pool) {
	219	goto fail;
	220	}
	221
	222	/* Hardware periodic table */
	223	ehci->periodic = (__le32 *)
	224	dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
	225	ehci->periodic_size * sizeof(__le32),
	226	&ehci->periodic_dma, 0);
	227	if (ehci->periodic == NULL) {
	228	goto fail;
	229	}
	230	for (i = 0; i < ehci->periodic_size; i++)
6dbd682b	231	ehci->periodic [i] = EHCI_LIST_END(ehci);
1da177e4 LT	232
1da177e4 LT	233	/* software shadow of hardware table */
80b6ca48 ES	234	ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
	235	if (ehci->pshadow != NULL)
	236	return 0;
1da177e4 LT	237
	238	fail:
	239	ehci_dbg (ehci, "couldn't init memory\n");
	240	ehci_mem_cleanup (ehci);
	241	return -ENOMEM;
	242	}