[deliverable/linux.git] / drivers / usb / host / ehci-pci.c

/*
 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
 *
 * Copyright (c) 2000-2004 by David Brownell
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/usb.h>
#include <linux/usb/hcd.h>

#include "ehci.h"
#include "pci-quirks.h"

#define DRIVER_DESC "EHCI PCI platform driver"

static const char hcd_name[] = "ehci-pci";

/* defined here to avoid adding to pci_ids.h for single instance use */
#define PCI_DEVICE_ID_INTEL_CE4100_USB	0x2e70

/*-------------------------------------------------------------------------*/

/* called after powerup, by probe or system-pm "wakeup" */
static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
{
	int			retval;

	/* we expect static quirk code to handle the "extended capabilities"
	 * (currently just BIOS handoff) allowed starting with EHCI 0.96
	 */

	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	retval = pci_set_mwi(pdev);
	if (!retval)
		ehci_dbg(ehci, "MWI active\n");

	return 0;
}

/* called during probe() after chip reset completes */
static int ehci_pci_setup(struct usb_hcd *hcd)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
	u32			temp;
	int			retval;

	ehci->caps = hcd->regs;

	/*
	 * ehci_init() causes memory for DMA transfers to be
	 * allocated.  Thus, any vendor-specific workarounds based on
	 * limiting the type of memory used for DMA transfers must
	 * happen before ehci_setup() is called.
	 *
	 * Most other workarounds can be done either before or after
	 * init and reset; they are located here too.
	 */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_TOSHIBA_2:
		/* celleb's companion chip */
		if (pdev->device == 0x01b5) {
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
			ehci->big_endian_mmio = 1;
#else
			ehci_warn(ehci,
				  "unsupported big endian Toshiba quirk\n");
#endif
		}
		break;
	case PCI_VENDOR_ID_NVIDIA:
		/* NVidia reports that certain chips don't handle
		 * QH, ITD, or SITD addresses above 2GB.  (But TD,
		 * data buffer, and periodic schedule are normal.)
		 */
		switch (pdev->device) {
		case 0x003c:	/* MCP04 */
		case 0x005b:	/* CK804 */
		case 0x00d8:	/* CK8 */
		case 0x00e8:	/* CK8S */
			if (pci_set_consistent_dma_mask(pdev,
						DMA_BIT_MASK(31)) < 0)
				ehci_warn(ehci, "can't enable NVidia "
					"workaround for >2GB RAM\n");
			break;

		/* Some NForce2 chips have problems with selective suspend;
		 * fixed in newer silicon.
		 */
		case 0x0068:
			if (pdev->revision < 0xa4)
				ehci->no_selective_suspend = 1;
			break;
		}
		break;
	case PCI_VENDOR_ID_INTEL:
		if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
			hcd->has_tt = 1;
		break;
	case PCI_VENDOR_ID_TDI:
		if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
			hcd->has_tt = 1;
		break;
	case PCI_VENDOR_ID_AMD:
		/* AMD PLL quirk */
		if (usb_amd_find_chipset_info())
			ehci->amd_pll_fix = 1;
		/* AMD8111 EHCI doesn't work, according to AMD errata */
		if (pdev->device == 0x7463) {
			ehci_info(ehci, "ignoring AMD8111 (errata)\n");
			retval = -EIO;
			goto done;
		}

		/*
		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
		 * read/write memory space which does not belong to it when
		 * there is NULL pointer with T-bit set to 1 in the frame list
		 * table. To avoid the issue, the frame list link pointer
		 * should always contain a valid pointer to a inactive qh.
		 */
		if (pdev->device == 0x7808) {
			ehci->use_dummy_qh = 1;
			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
		}
		break;
	case PCI_VENDOR_ID_VIA:
		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
			u8 tmp;

			/* The VT6212 defaults to a 1 usec EHCI sleep time which
			 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
			 * that sleep time use the conventional 10 usec.
			 */
			pci_read_config_byte(pdev, 0x4b, &tmp);
			if (tmp & 0x20)
				break;
			pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
		}
		break;
	case PCI_VENDOR_ID_ATI:
		/* AMD PLL quirk */
		if (usb_amd_find_chipset_info())
			ehci->amd_pll_fix = 1;

		/*
		 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
		 * read/write memory space which does not belong to it when
		 * there is NULL pointer with T-bit set to 1 in the frame list
		 * table. To avoid the issue, the frame list link pointer
		 * should always contain a valid pointer to a inactive qh.
		 */
		if (pdev->device == 0x4396) {
			ehci->use_dummy_qh = 1;
			ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
		}
		/* SB600 and old version of SB700 have a bug in EHCI controller,
		 * which causes usb devices lose response in some cases.
		 */
		if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
				usb_amd_hang_symptom_quirk()) {
			u8 tmp;
			ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
			pci_read_config_byte(pdev, 0x53, &tmp);
			pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
		}
		break;
	case PCI_VENDOR_ID_NETMOS:
		/* MosChip frame-index-register bug */
		ehci_info(ehci, "applying MosChip frame-index workaround\n");
		ehci->frame_index_bug = 1;
		break;
	}

	/* optional debug port, normally in the first BAR */
	temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
	if (temp) {
		pci_read_config_dword(pdev, temp, &temp);
		temp >>= 16;
		if (((temp >> 13) & 7) == 1) {
			u32 hcs_params = ehci_readl(ehci,
						    &ehci->caps->hcs_params);

			temp &= 0x1fff;
			ehci->debug = hcd->regs + temp;
			temp = ehci_readl(ehci, &ehci->debug->control);
			ehci_info(ehci, "debug port %d%s\n",
				  HCS_DEBUG_PORT(hcs_params),
				  (temp & DBGP_ENABLED) ? " IN USE" : "");
			if (!(temp & DBGP_ENABLED))
				ehci->debug = NULL;
		}
	}

	retval = ehci_setup(hcd);
	if (retval)
		return retval;

	/* These workarounds need to be applied after ehci_setup() */
	switch (pdev->vendor) {
	case PCI_VENDOR_ID_NEC:
		ehci->need_io_watchdog = 0;
		break;
	case PCI_VENDOR_ID_INTEL:
		ehci->need_io_watchdog = 0;
		break;
	case PCI_VENDOR_ID_NVIDIA:
		switch (pdev->device) {
		/* MCP89 chips on the MacBookAir3,1 give EPROTO when
		 * fetching device descriptors unless LPM is disabled.
		 * There are also intermittent problems enumerating
		 * devices with PPCD enabled.
		 */
		case 0x0d9d:
			ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
			ehci->has_ppcd = 0;
			ehci->command &= ~CMD_PPCEE;
			break;
		}
		break;
	}

	/* at least the Genesys GL880S needs fixup here */
	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	temp &= 0x0f;
	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
		ehci_dbg(ehci, "bogus port configuration: "
			"cc=%d x pcc=%d < ports=%d\n",
			HCS_N_CC(ehci->hcs_params),
			HCS_N_PCC(ehci->hcs_params),
			HCS_N_PORTS(ehci->hcs_params));

		switch (pdev->vendor) {
		case 0x17a0:		/* GENESYS */
			/* GL880S: should be PORTS=2 */
			temp |= (ehci->hcs_params & ~0xf);
			ehci->hcs_params = temp;
			break;
		case PCI_VENDOR_ID_NVIDIA:
			/* NF4: should be PCC=10 */
			break;
		}
	}

	/* Serial Bus Release Number is at PCI 0x60 offset */
	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
	    && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
		;	/* ConneXT has no sbrn register */
	else
		pci_read_config_byte(pdev, 0x60, &ehci->sbrn);

	/* Keep this around for a while just in case some EHCI
	 * implementation uses legacy PCI PM support.  This test
	 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
	 * been triggered by then.
	 */
	if (!device_can_wakeup(&pdev->dev)) {
		u16	port_wake;

		pci_read_config_word(pdev, 0x62, &port_wake);
		if (port_wake & 0x0001) {
			dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
			device_set_wakeup_capable(&pdev->dev, 1);
		}
	}

#ifdef	CONFIG_PM_RUNTIME
	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
		ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
#endif

	retval = ehci_pci_reinit(ehci, pdev);
done:
	return retval;
}

/*-------------------------------------------------------------------------*/

#ifdef	CONFIG_PM

/* suspend/resume, section 4.3 */

/* These routines rely on the PCI bus glue
 * to handle powerdown and wakeup, and currently also on
 * transceivers that don't need any software attention to set up
 * the right sort of wakeup.
 * Also they depend on separate root hub suspend/resume.
 */

static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
{
	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	if (ehci_resume(hcd, hibernated) != 0)
		(void) ehci_pci_reinit(ehci, pdev);
	return 0;
}

#else

#define ehci_suspend		NULL
#define ehci_pci_resume		NULL
#endif	/* CONFIG_PM */

static struct hc_driver __read_mostly ehci_pci_hc_driver;

static const struct ehci_driver_overrides pci_overrides __initconst = {
	.reset =		ehci_pci_setup,
};

/*-------------------------------------------------------------------------*/

/* PCI driver selection metadata; PCI hotplugging uses this */
static const struct pci_device_id pci_ids [] = { {
	/* handle any USB 2.0 EHCI controller */
	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
	.driver_data =	(unsigned long) &ehci_pci_hc_driver,
	}, {
	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
	.driver_data = (unsigned long) &ehci_pci_hc_driver,
	},
	{ /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, pci_ids);

/* pci driver glue; this is a "new style" PCI driver module */
static struct pci_driver ehci_pci_driver = {
	.name =		(char *) hcd_name,
	.id_table =	pci_ids,

	.probe =	usb_hcd_pci_probe,
	.remove =	usb_hcd_pci_remove,
	.shutdown = 	usb_hcd_pci_shutdown,

#ifdef CONFIG_PM
	.driver =	{
		.pm =	&usb_hcd_pci_pm_ops
	},
#endif
};

static int __init ehci_pci_init(void)
{
	if (usb_disabled())
		return -ENODEV;

	pr_info("%s: " DRIVER_DESC "\n", hcd_name);

	ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);

	/* Entries for the PCI suspend/resume callbacks are special */
	ehci_pci_hc_driver.pci_suspend = ehci_suspend;
	ehci_pci_hc_driver.pci_resume = ehci_pci_resume;

	return pci_register_driver(&ehci_pci_driver);
}
module_init(ehci_pci_init);

static void __exit ehci_pci_cleanup(void)
{
	pci_unregister_driver(&ehci_pci_driver);
}
module_exit(ehci_pci_cleanup);

MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_AUTHOR("David Brownell");
MODULE_AUTHOR("Alan Stern");
MODULE_LICENSE("GPL");
Commit	Line	Data
7ff71d6a MP	1	/*
	2	* EHCI HCD (Host Controller Driver) PCI Bus Glue.
	3	*
	4	* Copyright (c) 2000-2004 by David Brownell
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	13	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software Foundation,
	18	* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
adfa79d1 AS	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/pci.h>
	24	#include <linux/usb.h>
	25	#include <linux/usb/hcd.h>
	26
	27	#include "ehci.h"
	28	#include "pci-quirks.h"
	29
	30	#define DRIVER_DESC "EHCI PCI platform driver"
	31
	32	static const char hcd_name[] = "ehci-pci";
7ff71d6a	33
4f683843 DB	34	/* defined here to avoid adding to pci_ids.h for single instance use */
	35	#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
	36
7ff71d6a MP	37	/-------------------------------------------------------------------------/
7ff71d6a MP	38
18807521 DB	39	/* called after powerup, by probe or system-pm "wakeup" */
	40	static int ehci_pci_reinit(struct ehci_hcd ehci, struct pci_dev pdev)
	41	{
18807521	42	int retval;
18807521	43
401feafa DB	44	/* we expect static quirk code to handle the "extended capabilities"
	45	* (currently just BIOS handoff) allowed starting with EHCI 0.96
	46	*/
18807521 DB	47
	48	/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
	49	retval = pci_set_mwi(pdev);
	50	if (!retval)
	51	ehci_dbg(ehci, "MWI active\n");
	52
18807521 DB	53	return 0;
	54	}
	55
8926bfa7 DB	56	/* called during probe() after chip reset completes */
8926bfa7 DB	57	static int ehci_pci_setup(struct usb_hcd *hcd)
7ff71d6a	58	{
abcc9448 DB	59	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
abcc9448 DB	60	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	61	u32 temp;
18807521	62	int retval;
7ff71d6a	63
1a49e2ac AS	64	ehci->caps = hcd->regs;
	65
	66	/*
	67	* ehci_init() causes memory for DMA transfers to be
	68	* allocated. Thus, any vendor-specific workarounds based on
	69	* limiting the type of memory used for DMA transfers must
	70	* happen before ehci_setup() is called.
	71	*
	72	* Most other workarounds can be done either before or after
	73	* init and reset; they are located here too.
	74	*/
083522d7 BH	75	switch (pdev->vendor) {
	76	case PCI_VENDOR_ID_TOSHIBA_2:
	77	/* celleb's companion chip */
	78	if (pdev->device == 0x01b5) {
	79	#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
	80	ehci->big_endian_mmio = 1;
	81	#else
	82	ehci_warn(ehci,
	83	"unsupported big endian Toshiba quirk\n");
	84	#endif
	85	}
	86	break;
c32ba30f PS	87	case PCI_VENDOR_ID_NVIDIA:
	88	/* NVidia reports that certain chips don't handle
	89	* QH, ITD, or SITD addresses above 2GB. (But TD,
	90	* data buffer, and periodic schedule are normal.)
	91	*/
	92	switch (pdev->device) {
	93	case 0x003c: /* MCP04 */
	94	case 0x005b: /* CK804 */
	95	case 0x00d8: /* CK8 */
	96	case 0x00e8: /* CK8S */
	97	if (pci_set_consistent_dma_mask(pdev,
929a22a5	98	DMA_BIT_MASK(31)) < 0)
c32ba30f PS	99	ehci_warn(ehci, "can't enable NVidia "
	100	"workaround for >2GB RAM\n");
	101	break;
7ff71d6a	102
1a49e2ac AS	103	/* Some NForce2 chips have problems with selective suspend;
1a49e2ac AS	104	* fixed in newer silicon.
3d091a6f	105	*/
1a49e2ac AS	106	case 0x0068:
	107	if (pdev->revision < 0xa4)
	108	ehci->no_selective_suspend = 1;
	109	break;
	110	}
3681d8f3	111	break;
403dbd36	112	case PCI_VENDOR_ID_INTEL:
1a49e2ac	113	if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
4f683843	114	hcd->has_tt = 1;
403dbd36	115	break;
abcc9448	116	case PCI_VENDOR_ID_TDI:
1a49e2ac	117	if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
7329e211	118	hcd->has_tt = 1;
abcc9448 DB	119	break;
abcc9448 DB	120	case PCI_VENDOR_ID_AMD:
ad93562b AX	121	/* AMD PLL quirk */
	122	if (usb_amd_find_chipset_info())
	123	ehci->amd_pll_fix = 1;
abcc9448 DB	124	/* AMD8111 EHCI doesn't work, according to AMD errata */
	125	if (pdev->device == 0x7463) {
	126	ehci_info(ehci, "ignoring AMD8111 (errata)\n");
8926bfa7 DB	127	retval = -EIO;
8926bfa7 DB	128	goto done;
abcc9448	129	}
a85b4e7f	130
1a49e2ac AS	131	/*
	132	* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
	133	* read/write memory space which does not belong to it when
	134	* there is NULL pointer with T-bit set to 1 in the frame list
	135	* table. To avoid the issue, the frame list link pointer
	136	* should always contain a valid pointer to a inactive qh.
a85b4e7f	137	*/
1a49e2ac AS	138	if (pdev->device == 0x7808) {
	139	ehci->use_dummy_qh = 1;
	140	ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
7ff71d6a	141	}
abcc9448	142	break;
055b93c9 RH	143	case PCI_VENDOR_ID_VIA:
	144	if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
	145	u8 tmp;
	146
	147	/* The VT6212 defaults to a 1 usec EHCI sleep time which
	148	* hogs the PCI bus badly. Setting bit 5 of 0x4B makes
	149	* that sleep time use the conventional 10 usec.
	150	*/
	151	pci_read_config_byte(pdev, 0x4b, &tmp);
	152	if (tmp & 0x20)
	153	break;
	154	pci_write_config_byte(pdev, 0x4b, tmp \| 0x20);
	155	}
	156	break;
b09bc6cb	157	case PCI_VENDOR_ID_ATI:
ad93562b AX	158	/* AMD PLL quirk */
	159	if (usb_amd_find_chipset_info())
	160	ehci->amd_pll_fix = 1;
1a49e2ac AS	161
	162	/*
	163	* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
	164	* read/write memory space which does not belong to it when
	165	* there is NULL pointer with T-bit set to 1 in the frame list
	166	* table. To avoid the issue, the frame list link pointer
	167	* should always contain a valid pointer to a inactive qh.
	168	*/
	169	if (pdev->device == 0x4396) {
	170	ehci->use_dummy_qh = 1;
	171	ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
	172	}
0a99e8ac	173	/* SB600 and old version of SB700 have a bug in EHCI controller,
b09bc6cb AX	174	* which causes usb devices lose response in some cases.
b09bc6cb AX	175	*/
3ad145b6 HR	176	if ((pdev->device == 0x4386 \|\| pdev->device == 0x4396) &&
	177	usb_amd_hang_symptom_quirk()) {
	178	u8 tmp;
	179	ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
	180	pci_read_config_byte(pdev, 0x53, &tmp);
	181	pci_write_config_byte(pdev, 0x53, tmp \| (1<<3));
b09bc6cb AX	182	}
b09bc6cb AX	183	break;
68aa95d5 AS	184	case PCI_VENDOR_ID_NETMOS:
	185	/* MosChip frame-index-register bug */
	186	ehci_info(ehci, "applying MosChip frame-index workaround\n");
	187	ehci->frame_index_bug = 1;
	188	break;
abcc9448	189	}
7ff71d6a	190
75e1a2ae JB	191	/* optional debug port, normally in the first BAR */
	192	temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
	193	if (temp) {
	194	pci_read_config_dword(pdev, temp, &temp);
	195	temp >>= 16;
	196	if (((temp >> 13) & 7) == 1) {
	197	u32 hcs_params = ehci_readl(ehci,
	198	&ehci->caps->hcs_params);
	199
	200	temp &= 0x1fff;
	201	ehci->debug = hcd->regs + temp;
	202	temp = ehci_readl(ehci, &ehci->debug->control);
	203	ehci_info(ehci, "debug port %d%s\n",
	204	HCS_DEBUG_PORT(hcs_params),
	205	(temp & DBGP_ENABLED) ? " IN USE" : "");
	206	if (!(temp & DBGP_ENABLED))
	207	ehci->debug = NULL;
	208	}
	209	}
	210
1a49e2ac AS	211	retval = ehci_setup(hcd);
	212	if (retval)
	213	return retval;
	214
	215	/* These workarounds need to be applied after ehci_setup() */
	216	switch (pdev->vendor) {
	217	case PCI_VENDOR_ID_NEC:
	218	ehci->need_io_watchdog = 0;
	219	break;
	220	case PCI_VENDOR_ID_INTEL:
	221	ehci->need_io_watchdog = 0;
1a49e2ac AS	222	break;
	223	case PCI_VENDOR_ID_NVIDIA:
	224	switch (pdev->device) {
	225	/* MCP89 chips on the MacBookAir3,1 give EPROTO when
	226	* fetching device descriptors unless LPM is disabled.
	227	* There are also intermittent problems enumerating
	228	* devices with PPCD enabled.
	229	*/
	230	case 0x0d9d:
4968f951	231	ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
1a49e2ac AS	232	ehci->has_ppcd = 0;
	233	ehci->command &= ~CMD_PPCEE;
	234	break;
	235	}
	236	break;
	237	}
	238
7ff71d6a MP	239	/* at least the Genesys GL880S needs fixup here */
	240	temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
	241	temp &= 0x0f;
	242	if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
abcc9448	243	ehci_dbg(ehci, "bogus port configuration: "
7ff71d6a MP	244	"cc=%d x pcc=%d < ports=%d\n",
	245	HCS_N_CC(ehci->hcs_params),
	246	HCS_N_PCC(ehci->hcs_params),
	247	HCS_N_PORTS(ehci->hcs_params));
	248
abcc9448 DB	249	switch (pdev->vendor) {
	250	case 0x17a0: /* GENESYS */
	251	/* GL880S: should be PORTS=2 */
	252	temp \|= (ehci->hcs_params & ~0xf);
	253	ehci->hcs_params = temp;
	254	break;
	255	case PCI_VENDOR_ID_NVIDIA:
	256	/* NF4: should be PCC=10 */
	257	break;
7ff71d6a MP	258	}
	259	}
	260
abcc9448	261	/* Serial Bus Release Number is at PCI 0x60 offset */
3a0bac06 AR	262	if (pdev->vendor == PCI_VENDOR_ID_STMICRO
3a0bac06 AR	263	&& pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
1a49e2ac AS	264	; /* ConneXT has no sbrn register */
	265	else
	266	pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
7ff71d6a	267
6fd9086a AS	268	/* Keep this around for a while just in case some EHCI
	269	* implementation uses legacy PCI PM support. This test
	270	* can be removed on 17 Dec 2009 if the dev_warn() hasn't
	271	* been triggered by then.
2c1c3c4c DB	272	*/
	273	if (!device_can_wakeup(&pdev->dev)) {
	274	u16 port_wake;
	275
	276	pci_read_config_word(pdev, 0x62, &port_wake);
6fd9086a AS	277	if (port_wake & 0x0001) {
6fd9086a AS	278	dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
bcca06ef	279	device_set_wakeup_capable(&pdev->dev, 1);
6fd9086a	280	}
2c1c3c4c	281	}
7ff71d6a	282
84ebc102	283	#ifdef CONFIG_PM_RUNTIME
f8aeb3bb DB	284	if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
	285	ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
	286	#endif
	287
18807521	288	retval = ehci_pci_reinit(ehci, pdev);
8926bfa7 DB	289	done:
8926bfa7 DB	290	return retval;
7ff71d6a MP	291	}
	292
	293	/-------------------------------------------------------------------------/
	294
	295	#ifdef CONFIG_PM
	296
	297	/* suspend/resume, section 4.3 */
	298
f03c17fc	299	/* These routines rely on the PCI bus glue
7ff71d6a MP	300	* to handle powerdown and wakeup, and currently also on
	301	* transceivers that don't need any software attention to set up
	302	* the right sort of wakeup.
f03c17fc	303	* Also they depend on separate root hub suspend/resume.
7ff71d6a MP	304	*/
7ff71d6a MP	305
6ec4beb5	306	static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
7ff71d6a	307	{
abcc9448	308	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
18807521	309	struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
7ff71d6a	310
c5cf9212 AS	311	if (ehci_resume(hcd, hibernated) != 0)
c5cf9212 AS	312	(void) ehci_pci_reinit(ehci, pdev);
8c03356a	313	return 0;
7ff71d6a	314	}
7ff71d6a	315
adfa79d1	316	#else
7ff71d6a	317
adfa79d1 AS	318	#define ehci_suspend NULL
	319	#define ehci_pci_resume NULL
	320	#endif /* CONFIG_PM */
7ff71d6a	321
adfa79d1	322	static struct hc_driver __read_mostly ehci_pci_hc_driver;
7ff71d6a	323
62d08a11	324	static const struct ehci_driver_overrides pci_overrides __initconst = {
adfa79d1	325	.reset = ehci_pci_setup,
7ff71d6a MP	326	};
	327
	328	/-------------------------------------------------------------------------/
	329
	330	/* PCI driver selection metadata; PCI hotplugging uses this */
	331	static const struct pci_device_id pci_ids [] = { {
	332	/* handle any USB 2.0 EHCI controller */
c67808ee	333	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
7ff71d6a	334	.driver_data = (unsigned long) &ehci_pci_hc_driver,
3a0bac06 AR	335	}, {
	336	PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
	337	.driver_data = (unsigned long) &ehci_pci_hc_driver,
7ff71d6a MP	338	},
	339	{ /* end: all zeroes */ }
	340	};
abcc9448	341	MODULE_DEVICE_TABLE(pci, pci_ids);
7ff71d6a MP	342
	343	/* pci driver glue; this is a "new style" PCI driver module */
	344	static struct pci_driver ehci_pci_driver = {
	345	.name = (char *) hcd_name,
	346	.id_table = pci_ids,
	347
	348	.probe = usb_hcd_pci_probe,
	349	.remove = usb_hcd_pci_remove,
abb30641	350	.shutdown = usb_hcd_pci_shutdown,
7ff71d6a	351
f875fdbf	352	#ifdef CONFIG_PM
abb30641 AS	353	.driver = {
	354	.pm = &usb_hcd_pci_pm_ops
	355	},
7ff71d6a MP	356	#endif
7ff71d6a MP	357	};
adfa79d1 AS	358
	359	static int __init ehci_pci_init(void)
	360	{
	361	if (usb_disabled())
	362	return -ENODEV;
	363
	364	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
	365
1b36810e	366	ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
adfa79d1 AS	367
	368	/* Entries for the PCI suspend/resume callbacks are special */
	369	ehci_pci_hc_driver.pci_suspend = ehci_suspend;
	370	ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
	371
	372	return pci_register_driver(&ehci_pci_driver);
	373	}
	374	module_init(ehci_pci_init);
	375
	376	static void __exit ehci_pci_cleanup(void)
	377	{
	378	pci_unregister_driver(&ehci_pci_driver);
	379	}
	380	module_exit(ehci_pci_cleanup);
	381
	382	MODULE_DESCRIPTION(DRIVER_DESC);
	383	MODULE_AUTHOR("David Brownell");
	384	MODULE_AUTHOR("Alan Stern");
	385	MODULE_LICENSE("GPL");