Commit | Line | Data |
---|---|---|
7ff71d6a MP |
1 | /* |
2 | * EHCI HCD (Host Controller Driver) PCI Bus Glue. | |
3 | * | |
4 | * Copyright (c) 2000-2004 by David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #ifndef CONFIG_PCI | |
22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." | |
23 | #endif | |
24 | ||
4f683843 DB |
25 | /* defined here to avoid adding to pci_ids.h for single instance use */ |
26 | #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 | |
27 | ||
7ff71d6a MP |
28 | /*-------------------------------------------------------------------------*/ |
29 | ||
18807521 DB |
30 | /* called after powerup, by probe or system-pm "wakeup" */ |
31 | static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) | |
32 | { | |
18807521 | 33 | int retval; |
18807521 | 34 | |
401feafa DB |
35 | /* we expect static quirk code to handle the "extended capabilities" |
36 | * (currently just BIOS handoff) allowed starting with EHCI 0.96 | |
37 | */ | |
18807521 DB |
38 | |
39 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
40 | retval = pci_set_mwi(pdev); | |
41 | if (!retval) | |
42 | ehci_dbg(ehci, "MWI active\n"); | |
43 | ||
18807521 DB |
44 | return 0; |
45 | } | |
46 | ||
8926bfa7 DB |
47 | /* called during probe() after chip reset completes */ |
48 | static int ehci_pci_setup(struct usb_hcd *hcd) | |
7ff71d6a | 49 | { |
abcc9448 DB |
50 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
51 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
b09bc6cb AX |
52 | struct pci_dev *p_smbus; |
53 | u8 rev; | |
7ff71d6a | 54 | u32 temp; |
18807521 | 55 | int retval; |
7ff71d6a | 56 | |
1a49e2ac AS |
57 | ehci->caps = hcd->regs; |
58 | ||
59 | /* | |
60 | * ehci_init() causes memory for DMA transfers to be | |
61 | * allocated. Thus, any vendor-specific workarounds based on | |
62 | * limiting the type of memory used for DMA transfers must | |
63 | * happen before ehci_setup() is called. | |
64 | * | |
65 | * Most other workarounds can be done either before or after | |
66 | * init and reset; they are located here too. | |
67 | */ | |
083522d7 BH |
68 | switch (pdev->vendor) { |
69 | case PCI_VENDOR_ID_TOSHIBA_2: | |
70 | /* celleb's companion chip */ | |
71 | if (pdev->device == 0x01b5) { | |
72 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
73 | ehci->big_endian_mmio = 1; | |
74 | #else | |
75 | ehci_warn(ehci, | |
76 | "unsupported big endian Toshiba quirk\n"); | |
77 | #endif | |
78 | } | |
79 | break; | |
c32ba30f PS |
80 | case PCI_VENDOR_ID_NVIDIA: |
81 | /* NVidia reports that certain chips don't handle | |
82 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
83 | * data buffer, and periodic schedule are normal.) | |
84 | */ | |
85 | switch (pdev->device) { | |
86 | case 0x003c: /* MCP04 */ | |
87 | case 0x005b: /* CK804 */ | |
88 | case 0x00d8: /* CK8 */ | |
89 | case 0x00e8: /* CK8S */ | |
90 | if (pci_set_consistent_dma_mask(pdev, | |
929a22a5 | 91 | DMA_BIT_MASK(31)) < 0) |
c32ba30f PS |
92 | ehci_warn(ehci, "can't enable NVidia " |
93 | "workaround for >2GB RAM\n"); | |
94 | break; | |
7ff71d6a | 95 | |
1a49e2ac AS |
96 | /* Some NForce2 chips have problems with selective suspend; |
97 | * fixed in newer silicon. | |
3d091a6f | 98 | */ |
1a49e2ac AS |
99 | case 0x0068: |
100 | if (pdev->revision < 0xa4) | |
101 | ehci->no_selective_suspend = 1; | |
102 | break; | |
103 | } | |
3681d8f3 | 104 | break; |
403dbd36 | 105 | case PCI_VENDOR_ID_INTEL: |
1a49e2ac | 106 | if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) |
4f683843 | 107 | hcd->has_tt = 1; |
403dbd36 | 108 | break; |
abcc9448 | 109 | case PCI_VENDOR_ID_TDI: |
1a49e2ac | 110 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) |
7329e211 | 111 | hcd->has_tt = 1; |
abcc9448 DB |
112 | break; |
113 | case PCI_VENDOR_ID_AMD: | |
ad93562b AX |
114 | /* AMD PLL quirk */ |
115 | if (usb_amd_find_chipset_info()) | |
116 | ehci->amd_pll_fix = 1; | |
abcc9448 DB |
117 | /* AMD8111 EHCI doesn't work, according to AMD errata */ |
118 | if (pdev->device == 0x7463) { | |
119 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | |
8926bfa7 DB |
120 | retval = -EIO; |
121 | goto done; | |
abcc9448 | 122 | } |
a85b4e7f | 123 | |
1a49e2ac AS |
124 | /* |
125 | * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | |
126 | * read/write memory space which does not belong to it when | |
127 | * there is NULL pointer with T-bit set to 1 in the frame list | |
128 | * table. To avoid the issue, the frame list link pointer | |
129 | * should always contain a valid pointer to a inactive qh. | |
a85b4e7f | 130 | */ |
1a49e2ac AS |
131 | if (pdev->device == 0x7808) { |
132 | ehci->use_dummy_qh = 1; | |
133 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n"); | |
7ff71d6a | 134 | } |
abcc9448 | 135 | break; |
055b93c9 RH |
136 | case PCI_VENDOR_ID_VIA: |
137 | if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { | |
138 | u8 tmp; | |
139 | ||
140 | /* The VT6212 defaults to a 1 usec EHCI sleep time which | |
141 | * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes | |
142 | * that sleep time use the conventional 10 usec. | |
143 | */ | |
144 | pci_read_config_byte(pdev, 0x4b, &tmp); | |
145 | if (tmp & 0x20) | |
146 | break; | |
147 | pci_write_config_byte(pdev, 0x4b, tmp | 0x20); | |
148 | } | |
149 | break; | |
b09bc6cb | 150 | case PCI_VENDOR_ID_ATI: |
ad93562b AX |
151 | /* AMD PLL quirk */ |
152 | if (usb_amd_find_chipset_info()) | |
153 | ehci->amd_pll_fix = 1; | |
1a49e2ac AS |
154 | |
155 | /* | |
156 | * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | |
157 | * read/write memory space which does not belong to it when | |
158 | * there is NULL pointer with T-bit set to 1 in the frame list | |
159 | * table. To avoid the issue, the frame list link pointer | |
160 | * should always contain a valid pointer to a inactive qh. | |
161 | */ | |
162 | if (pdev->device == 0x4396) { | |
163 | ehci->use_dummy_qh = 1; | |
164 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n"); | |
165 | } | |
0a99e8ac | 166 | /* SB600 and old version of SB700 have a bug in EHCI controller, |
b09bc6cb AX |
167 | * which causes usb devices lose response in some cases. |
168 | */ | |
0a99e8ac | 169 | if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { |
b09bc6cb AX |
170 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
171 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
172 | NULL); | |
173 | if (!p_smbus) | |
174 | break; | |
175 | rev = p_smbus->revision; | |
0a99e8ac SH |
176 | if ((pdev->device == 0x4386) || (rev == 0x3a) |
177 | || (rev == 0x3b)) { | |
b09bc6cb | 178 | u8 tmp; |
0a99e8ac SH |
179 | ehci_info(ehci, "applying AMD SB600/SB700 USB " |
180 | "freeze workaround\n"); | |
b09bc6cb AX |
181 | pci_read_config_byte(pdev, 0x53, &tmp); |
182 | pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); | |
183 | } | |
184 | pci_dev_put(p_smbus); | |
185 | } | |
186 | break; | |
68aa95d5 AS |
187 | case PCI_VENDOR_ID_NETMOS: |
188 | /* MosChip frame-index-register bug */ | |
189 | ehci_info(ehci, "applying MosChip frame-index workaround\n"); | |
190 | ehci->frame_index_bug = 1; | |
191 | break; | |
abcc9448 | 192 | } |
7ff71d6a | 193 | |
1a49e2ac AS |
194 | retval = ehci_setup(hcd); |
195 | if (retval) | |
196 | return retval; | |
197 | ||
198 | /* These workarounds need to be applied after ehci_setup() */ | |
199 | switch (pdev->vendor) { | |
200 | case PCI_VENDOR_ID_NEC: | |
201 | ehci->need_io_watchdog = 0; | |
202 | break; | |
203 | case PCI_VENDOR_ID_INTEL: | |
204 | ehci->need_io_watchdog = 0; | |
1a49e2ac AS |
205 | break; |
206 | case PCI_VENDOR_ID_NVIDIA: | |
207 | switch (pdev->device) { | |
208 | /* MCP89 chips on the MacBookAir3,1 give EPROTO when | |
209 | * fetching device descriptors unless LPM is disabled. | |
210 | * There are also intermittent problems enumerating | |
211 | * devices with PPCD enabled. | |
212 | */ | |
213 | case 0x0d9d: | |
4968f951 | 214 | ehci_info(ehci, "disable ppcd for nvidia mcp89\n"); |
1a49e2ac AS |
215 | ehci->has_ppcd = 0; |
216 | ehci->command &= ~CMD_PPCEE; | |
217 | break; | |
218 | } | |
219 | break; | |
220 | } | |
221 | ||
8d053c79 JW |
222 | /* optional debug port, normally in the first BAR */ |
223 | temp = pci_find_capability(pdev, 0x0a); | |
224 | if (temp) { | |
225 | pci_read_config_dword(pdev, temp, &temp); | |
226 | temp >>= 16; | |
227 | if ((temp & (3 << 13)) == (1 << 13)) { | |
228 | temp &= 0x1fff; | |
1a49e2ac | 229 | ehci->debug = hcd->regs + temp; |
8d053c79 JW |
230 | temp = ehci_readl(ehci, &ehci->debug->control); |
231 | ehci_info(ehci, "debug port %d%s\n", | |
232 | HCS_DEBUG_PORT(ehci->hcs_params), | |
233 | (temp & DBGP_ENABLED) | |
234 | ? " IN USE" | |
235 | : ""); | |
236 | if (!(temp & DBGP_ENABLED)) | |
237 | ehci->debug = NULL; | |
238 | } | |
239 | } | |
240 | ||
7ff71d6a MP |
241 | /* at least the Genesys GL880S needs fixup here */ |
242 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
243 | temp &= 0x0f; | |
244 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
abcc9448 | 245 | ehci_dbg(ehci, "bogus port configuration: " |
7ff71d6a MP |
246 | "cc=%d x pcc=%d < ports=%d\n", |
247 | HCS_N_CC(ehci->hcs_params), | |
248 | HCS_N_PCC(ehci->hcs_params), | |
249 | HCS_N_PORTS(ehci->hcs_params)); | |
250 | ||
abcc9448 DB |
251 | switch (pdev->vendor) { |
252 | case 0x17a0: /* GENESYS */ | |
253 | /* GL880S: should be PORTS=2 */ | |
254 | temp |= (ehci->hcs_params & ~0xf); | |
255 | ehci->hcs_params = temp; | |
256 | break; | |
257 | case PCI_VENDOR_ID_NVIDIA: | |
258 | /* NF4: should be PCC=10 */ | |
259 | break; | |
7ff71d6a MP |
260 | } |
261 | } | |
262 | ||
abcc9448 | 263 | /* Serial Bus Release Number is at PCI 0x60 offset */ |
3a0bac06 AR |
264 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO |
265 | && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST) | |
1a49e2ac AS |
266 | ; /* ConneXT has no sbrn register */ |
267 | else | |
268 | pci_read_config_byte(pdev, 0x60, &ehci->sbrn); | |
7ff71d6a | 269 | |
6fd9086a AS |
270 | /* Keep this around for a while just in case some EHCI |
271 | * implementation uses legacy PCI PM support. This test | |
272 | * can be removed on 17 Dec 2009 if the dev_warn() hasn't | |
273 | * been triggered by then. | |
2c1c3c4c DB |
274 | */ |
275 | if (!device_can_wakeup(&pdev->dev)) { | |
276 | u16 port_wake; | |
277 | ||
278 | pci_read_config_word(pdev, 0x62, &port_wake); | |
6fd9086a AS |
279 | if (port_wake & 0x0001) { |
280 | dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); | |
bcca06ef | 281 | device_set_wakeup_capable(&pdev->dev, 1); |
6fd9086a | 282 | } |
2c1c3c4c | 283 | } |
7ff71d6a | 284 | |
f8aeb3bb DB |
285 | #ifdef CONFIG_USB_SUSPEND |
286 | /* REVISIT: the controller works fine for wakeup iff the root hub | |
287 | * itself is "globally" suspended, but usbcore currently doesn't | |
288 | * understand such things. | |
289 | * | |
290 | * System suspend currently expects to be able to suspend the entire | |
291 | * device tree, device-at-a-time. If we failed selective suspend | |
292 | * reports, system suspend would fail; so the root hub code must claim | |
411c9403 | 293 | * success. That's lying to usbcore, and it matters for runtime |
f8aeb3bb DB |
294 | * PM scenarios with selective suspend and remote wakeup... |
295 | */ | |
296 | if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) | |
297 | ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); | |
298 | #endif | |
299 | ||
18807521 | 300 | retval = ehci_pci_reinit(ehci, pdev); |
8926bfa7 DB |
301 | done: |
302 | return retval; | |
7ff71d6a MP |
303 | } |
304 | ||
305 | /*-------------------------------------------------------------------------*/ | |
306 | ||
307 | #ifdef CONFIG_PM | |
308 | ||
309 | /* suspend/resume, section 4.3 */ | |
310 | ||
f03c17fc | 311 | /* These routines rely on the PCI bus glue |
7ff71d6a MP |
312 | * to handle powerdown and wakeup, and currently also on |
313 | * transceivers that don't need any software attention to set up | |
314 | * the right sort of wakeup. | |
f03c17fc | 315 | * Also they depend on separate root hub suspend/resume. |
7ff71d6a MP |
316 | */ |
317 | ||
4147200d | 318 | static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
7ff71d6a | 319 | { |
c5cf9212 | 320 | return ehci_suspend(hcd, do_wakeup); |
7ff71d6a MP |
321 | } |
322 | ||
69e848c2 SS |
323 | static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev) |
324 | { | |
325 | return pdev->class == PCI_CLASS_SERIAL_USB_EHCI && | |
326 | pdev->vendor == PCI_VENDOR_ID_INTEL && | |
1c12443a SS |
327 | (pdev->device == 0x1E26 || |
328 | pdev->device == 0x8C2D || | |
329 | pdev->device == 0x8C26); | |
69e848c2 SS |
330 | } |
331 | ||
332 | static void ehci_enable_xhci_companion(void) | |
333 | { | |
334 | struct pci_dev *companion = NULL; | |
335 | ||
336 | /* The xHCI and EHCI controllers are not on the same PCI slot */ | |
337 | for_each_pci_dev(companion) { | |
338 | if (!usb_is_intel_switchable_xhci(companion)) | |
339 | continue; | |
340 | usb_enable_xhci_ports(companion); | |
341 | return; | |
342 | } | |
343 | } | |
344 | ||
6ec4beb5 | 345 | static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) |
7ff71d6a | 346 | { |
abcc9448 | 347 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
18807521 | 348 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
7ff71d6a | 349 | |
69e848c2 SS |
350 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
351 | * not support xHCI natively. That means that during system resume, it | |
352 | * may switch the ports back to EHCI so that users can use their | |
353 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
354 | * | |
355 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
356 | * enabled before resume, and switch the ports back to xHCI when the | |
357 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
358 | * writers. | |
359 | * | |
360 | * Unconditionally switch the ports back to xHCI after a system resume. | |
361 | * We can't tell whether the EHCI or xHCI controller will be resumed | |
362 | * first, so we have to do the port switchover in both drivers. Writing | |
363 | * a '1' to the port switchover registers should have no effect if the | |
364 | * port was already switched over. | |
365 | */ | |
366 | if (usb_is_intel_switchable_ehci(pdev)) | |
367 | ehci_enable_xhci_companion(); | |
368 | ||
c5cf9212 AS |
369 | if (ehci_resume(hcd, hibernated) != 0) |
370 | (void) ehci_pci_reinit(ehci, pdev); | |
8c03356a | 371 | return 0; |
7ff71d6a MP |
372 | } |
373 | #endif | |
374 | ||
375 | static const struct hc_driver ehci_pci_hc_driver = { | |
376 | .description = hcd_name, | |
377 | .product_desc = "EHCI Host Controller", | |
378 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
379 | ||
380 | /* | |
381 | * generic hardware linkage | |
382 | */ | |
383 | .irq = ehci_irq, | |
384 | .flags = HCD_MEMORY | HCD_USB2, | |
385 | ||
386 | /* | |
387 | * basic lifecycle operations | |
388 | */ | |
8926bfa7 | 389 | .reset = ehci_pci_setup, |
18807521 | 390 | .start = ehci_run, |
7ff71d6a | 391 | #ifdef CONFIG_PM |
7be7d741 AS |
392 | .pci_suspend = ehci_pci_suspend, |
393 | .pci_resume = ehci_pci_resume, | |
7ff71d6a | 394 | #endif |
18807521 | 395 | .stop = ehci_stop, |
64a21d02 | 396 | .shutdown = ehci_shutdown, |
7ff71d6a MP |
397 | |
398 | /* | |
399 | * managing i/o requests and associated device resources | |
400 | */ | |
401 | .urb_enqueue = ehci_urb_enqueue, | |
402 | .urb_dequeue = ehci_urb_dequeue, | |
403 | .endpoint_disable = ehci_endpoint_disable, | |
b18ffd49 | 404 | .endpoint_reset = ehci_endpoint_reset, |
7ff71d6a MP |
405 | |
406 | /* | |
407 | * scheduling support | |
408 | */ | |
409 | .get_frame_number = ehci_get_frame, | |
410 | ||
411 | /* | |
412 | * root hub support | |
413 | */ | |
414 | .hub_status_data = ehci_hub_status_data, | |
415 | .hub_control = ehci_hub_control, | |
0c0382e3 AS |
416 | .bus_suspend = ehci_bus_suspend, |
417 | .bus_resume = ehci_bus_resume, | |
a8e51775 | 418 | .relinquish_port = ehci_relinquish_port, |
3a31155c | 419 | .port_handed_over = ehci_port_handed_over, |
914b7012 AS |
420 | |
421 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, | |
7ff71d6a MP |
422 | }; |
423 | ||
424 | /*-------------------------------------------------------------------------*/ | |
425 | ||
426 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
427 | static const struct pci_device_id pci_ids [] = { { | |
428 | /* handle any USB 2.0 EHCI controller */ | |
c67808ee | 429 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), |
7ff71d6a | 430 | .driver_data = (unsigned long) &ehci_pci_hc_driver, |
3a0bac06 AR |
431 | }, { |
432 | PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST), | |
433 | .driver_data = (unsigned long) &ehci_pci_hc_driver, | |
7ff71d6a MP |
434 | }, |
435 | { /* end: all zeroes */ } | |
436 | }; | |
abcc9448 | 437 | MODULE_DEVICE_TABLE(pci, pci_ids); |
7ff71d6a MP |
438 | |
439 | /* pci driver glue; this is a "new style" PCI driver module */ | |
440 | static struct pci_driver ehci_pci_driver = { | |
441 | .name = (char *) hcd_name, | |
442 | .id_table = pci_ids, | |
443 | ||
444 | .probe = usb_hcd_pci_probe, | |
445 | .remove = usb_hcd_pci_remove, | |
abb30641 | 446 | .shutdown = usb_hcd_pci_shutdown, |
7ff71d6a | 447 | |
abb30641 AS |
448 | #ifdef CONFIG_PM_SLEEP |
449 | .driver = { | |
450 | .pm = &usb_hcd_pci_pm_ops | |
451 | }, | |
7ff71d6a MP |
452 | #endif |
453 | }; |