Commit | Line | Data |
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7ff71d6a MP |
1 | /* |
2 | * EHCI HCD (Host Controller Driver) PCI Bus Glue. | |
3 | * | |
4 | * Copyright (c) 2000-2004 by David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #ifndef CONFIG_PCI | |
22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." | |
23 | #endif | |
24 | ||
4f683843 DB |
25 | /* defined here to avoid adding to pci_ids.h for single instance use */ |
26 | #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 | |
27 | ||
7ff71d6a MP |
28 | /*-------------------------------------------------------------------------*/ |
29 | ||
18807521 DB |
30 | /* called after powerup, by probe or system-pm "wakeup" */ |
31 | static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) | |
32 | { | |
18807521 | 33 | int retval; |
18807521 | 34 | |
401feafa DB |
35 | /* we expect static quirk code to handle the "extended capabilities" |
36 | * (currently just BIOS handoff) allowed starting with EHCI 0.96 | |
37 | */ | |
18807521 DB |
38 | |
39 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
40 | retval = pci_set_mwi(pdev); | |
41 | if (!retval) | |
42 | ehci_dbg(ehci, "MWI active\n"); | |
43 | ||
18807521 DB |
44 | return 0; |
45 | } | |
46 | ||
479b46b5 GKH |
47 | static int ehci_quirk_amd_SB800(struct ehci_hcd *ehci) |
48 | { | |
49 | struct pci_dev *amd_smbus_dev; | |
50 | u8 rev = 0; | |
51 | ||
52 | amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL); | |
53 | if (!amd_smbus_dev) | |
54 | return 0; | |
55 | ||
56 | pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev); | |
57 | if (rev < 0x40) { | |
58 | pci_dev_put(amd_smbus_dev); | |
59 | amd_smbus_dev = NULL; | |
60 | return 0; | |
61 | } | |
62 | ||
63 | if (!amd_nb_dev) | |
64 | amd_nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); | |
65 | if (!amd_nb_dev) | |
66 | ehci_err(ehci, "QUIRK: unable to get AMD NB device\n"); | |
67 | ||
68 | ehci_info(ehci, "QUIRK: Enable AMD SB800 L1 fix\n"); | |
69 | ||
70 | pci_dev_put(amd_smbus_dev); | |
71 | amd_smbus_dev = NULL; | |
72 | ||
73 | return 1; | |
74 | } | |
75 | ||
8926bfa7 DB |
76 | /* called during probe() after chip reset completes */ |
77 | static int ehci_pci_setup(struct usb_hcd *hcd) | |
7ff71d6a | 78 | { |
abcc9448 DB |
79 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
80 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
b09bc6cb AX |
81 | struct pci_dev *p_smbus; |
82 | u8 rev; | |
7ff71d6a | 83 | u32 temp; |
18807521 | 84 | int retval; |
7ff71d6a | 85 | |
083522d7 BH |
86 | switch (pdev->vendor) { |
87 | case PCI_VENDOR_ID_TOSHIBA_2: | |
88 | /* celleb's companion chip */ | |
89 | if (pdev->device == 0x01b5) { | |
90 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
91 | ehci->big_endian_mmio = 1; | |
92 | #else | |
93 | ehci_warn(ehci, | |
94 | "unsupported big endian Toshiba quirk\n"); | |
95 | #endif | |
96 | } | |
97 | break; | |
98 | } | |
99 | ||
7ff71d6a | 100 | ehci->caps = hcd->regs; |
083522d7 BH |
101 | ehci->regs = hcd->regs + |
102 | HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); | |
103 | ||
abcc9448 DB |
104 | dbg_hcs_params(ehci, "reset"); |
105 | dbg_hcc_params(ehci, "reset"); | |
7ff71d6a | 106 | |
c32ba30f PS |
107 | /* ehci_init() causes memory for DMA transfers to be |
108 | * allocated. Thus, any vendor-specific workarounds based on | |
109 | * limiting the type of memory used for DMA transfers must | |
110 | * happen before ehci_init() is called. */ | |
111 | switch (pdev->vendor) { | |
112 | case PCI_VENDOR_ID_NVIDIA: | |
113 | /* NVidia reports that certain chips don't handle | |
114 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
115 | * data buffer, and periodic schedule are normal.) | |
116 | */ | |
117 | switch (pdev->device) { | |
118 | case 0x003c: /* MCP04 */ | |
119 | case 0x005b: /* CK804 */ | |
120 | case 0x00d8: /* CK8 */ | |
121 | case 0x00e8: /* CK8S */ | |
122 | if (pci_set_consistent_dma_mask(pdev, | |
929a22a5 | 123 | DMA_BIT_MASK(31)) < 0) |
c32ba30f PS |
124 | ehci_warn(ehci, "can't enable NVidia " |
125 | "workaround for >2GB RAM\n"); | |
126 | break; | |
127 | } | |
128 | break; | |
129 | } | |
130 | ||
7ff71d6a | 131 | /* cache this readonly data; minimize chip reads */ |
083522d7 | 132 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
7ff71d6a | 133 | |
479b46b5 GKH |
134 | if (ehci_quirk_amd_SB800(ehci)) |
135 | ehci->amd_l1_fix = 1; | |
136 | ||
18807521 DB |
137 | retval = ehci_halt(ehci); |
138 | if (retval) | |
139 | return retval; | |
140 | ||
3d091a6f AX |
141 | if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) || |
142 | (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) { | |
143 | /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | |
144 | * read/write memory space which does not belong to it when | |
145 | * there is NULL pointer with T-bit set to 1 in the frame list | |
146 | * table. To avoid the issue, the frame list link pointer | |
147 | * should always contain a valid pointer to a inactive qh. | |
148 | */ | |
149 | ehci->use_dummy_qh = 1; | |
150 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI " | |
151 | "dummy qh workaround\n"); | |
152 | } | |
153 | ||
8926bfa7 DB |
154 | /* data structure init */ |
155 | retval = ehci_init(hcd); | |
156 | if (retval) | |
157 | return retval; | |
158 | ||
abcc9448 | 159 | switch (pdev->vendor) { |
3681d8f3 DM |
160 | case PCI_VENDOR_ID_NEC: |
161 | ehci->need_io_watchdog = 0; | |
162 | break; | |
403dbd36 AD |
163 | case PCI_VENDOR_ID_INTEL: |
164 | ehci->need_io_watchdog = 0; | |
ae68a83b | 165 | ehci->fs_i_thresh = 1; |
ee4ecb8a ON |
166 | if (pdev->device == 0x27cc) { |
167 | ehci->broken_periodic = 1; | |
168 | ehci_info(ehci, "using broken periodic workaround\n"); | |
169 | } | |
fc928250 AD |
170 | if (pdev->device == 0x0806 || pdev->device == 0x0811 |
171 | || pdev->device == 0x0829) { | |
172 | ehci_info(ehci, "disable lpm for langwell/penwell\n"); | |
173 | ehci->has_lpm = 0; | |
174 | } | |
4f683843 DB |
175 | if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) { |
176 | hcd->has_tt = 1; | |
177 | tdi_reset(ehci); | |
178 | } | |
403dbd36 | 179 | break; |
abcc9448 DB |
180 | case PCI_VENDOR_ID_TDI: |
181 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { | |
7329e211 | 182 | hcd->has_tt = 1; |
abcc9448 DB |
183 | tdi_reset(ehci); |
184 | } | |
185 | break; | |
186 | case PCI_VENDOR_ID_AMD: | |
187 | /* AMD8111 EHCI doesn't work, according to AMD errata */ | |
188 | if (pdev->device == 0x7463) { | |
189 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | |
8926bfa7 DB |
190 | retval = -EIO; |
191 | goto done; | |
abcc9448 DB |
192 | } |
193 | break; | |
194 | case PCI_VENDOR_ID_NVIDIA: | |
f8aeb3bb | 195 | switch (pdev->device) { |
f8aeb3bb DB |
196 | /* Some NForce2 chips have problems with selective suspend; |
197 | * fixed in newer silicon. | |
198 | */ | |
199 | case 0x0068: | |
44c10138 | 200 | if (pdev->revision < 0xa4) |
f8aeb3bb DB |
201 | ehci->no_selective_suspend = 1; |
202 | break; | |
a85b4e7f BT |
203 | |
204 | /* MCP89 chips on the MacBookAir3,1 give EPROTO when | |
205 | * fetching device descriptors unless LPM is disabled. | |
206 | * There are also intermittent problems enumerating | |
207 | * devices with PPCD enabled. | |
208 | */ | |
209 | case 0x0d9d: | |
210 | ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89"); | |
211 | ehci->has_lpm = 0; | |
212 | ehci->has_ppcd = 0; | |
213 | ehci->command &= ~CMD_PPCEE; | |
214 | break; | |
7ff71d6a | 215 | } |
abcc9448 | 216 | break; |
055b93c9 RH |
217 | case PCI_VENDOR_ID_VIA: |
218 | if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { | |
219 | u8 tmp; | |
220 | ||
221 | /* The VT6212 defaults to a 1 usec EHCI sleep time which | |
222 | * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes | |
223 | * that sleep time use the conventional 10 usec. | |
224 | */ | |
225 | pci_read_config_byte(pdev, 0x4b, &tmp); | |
226 | if (tmp & 0x20) | |
227 | break; | |
228 | pci_write_config_byte(pdev, 0x4b, tmp | 0x20); | |
229 | } | |
230 | break; | |
b09bc6cb | 231 | case PCI_VENDOR_ID_ATI: |
0a99e8ac | 232 | /* SB600 and old version of SB700 have a bug in EHCI controller, |
b09bc6cb AX |
233 | * which causes usb devices lose response in some cases. |
234 | */ | |
0a99e8ac | 235 | if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { |
b09bc6cb AX |
236 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
237 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
238 | NULL); | |
239 | if (!p_smbus) | |
240 | break; | |
241 | rev = p_smbus->revision; | |
0a99e8ac SH |
242 | if ((pdev->device == 0x4386) || (rev == 0x3a) |
243 | || (rev == 0x3b)) { | |
b09bc6cb | 244 | u8 tmp; |
0a99e8ac SH |
245 | ehci_info(ehci, "applying AMD SB600/SB700 USB " |
246 | "freeze workaround\n"); | |
b09bc6cb AX |
247 | pci_read_config_byte(pdev, 0x53, &tmp); |
248 | pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); | |
249 | } | |
250 | pci_dev_put(p_smbus); | |
251 | } | |
252 | break; | |
abcc9448 | 253 | } |
7ff71d6a | 254 | |
8d053c79 JW |
255 | /* optional debug port, normally in the first BAR */ |
256 | temp = pci_find_capability(pdev, 0x0a); | |
257 | if (temp) { | |
258 | pci_read_config_dword(pdev, temp, &temp); | |
259 | temp >>= 16; | |
260 | if ((temp & (3 << 13)) == (1 << 13)) { | |
261 | temp &= 0x1fff; | |
262 | ehci->debug = ehci_to_hcd(ehci)->regs + temp; | |
263 | temp = ehci_readl(ehci, &ehci->debug->control); | |
264 | ehci_info(ehci, "debug port %d%s\n", | |
265 | HCS_DEBUG_PORT(ehci->hcs_params), | |
266 | (temp & DBGP_ENABLED) | |
267 | ? " IN USE" | |
268 | : ""); | |
269 | if (!(temp & DBGP_ENABLED)) | |
270 | ehci->debug = NULL; | |
271 | } | |
272 | } | |
273 | ||
af1c51fc | 274 | ehci_reset(ehci); |
7ff71d6a | 275 | |
7ff71d6a MP |
276 | /* at least the Genesys GL880S needs fixup here */ |
277 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
278 | temp &= 0x0f; | |
279 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
abcc9448 | 280 | ehci_dbg(ehci, "bogus port configuration: " |
7ff71d6a MP |
281 | "cc=%d x pcc=%d < ports=%d\n", |
282 | HCS_N_CC(ehci->hcs_params), | |
283 | HCS_N_PCC(ehci->hcs_params), | |
284 | HCS_N_PORTS(ehci->hcs_params)); | |
285 | ||
abcc9448 DB |
286 | switch (pdev->vendor) { |
287 | case 0x17a0: /* GENESYS */ | |
288 | /* GL880S: should be PORTS=2 */ | |
289 | temp |= (ehci->hcs_params & ~0xf); | |
290 | ehci->hcs_params = temp; | |
291 | break; | |
292 | case PCI_VENDOR_ID_NVIDIA: | |
293 | /* NF4: should be PCC=10 */ | |
294 | break; | |
7ff71d6a MP |
295 | } |
296 | } | |
297 | ||
abcc9448 DB |
298 | /* Serial Bus Release Number is at PCI 0x60 offset */ |
299 | pci_read_config_byte(pdev, 0x60, &ehci->sbrn); | |
7ff71d6a | 300 | |
6fd9086a AS |
301 | /* Keep this around for a while just in case some EHCI |
302 | * implementation uses legacy PCI PM support. This test | |
303 | * can be removed on 17 Dec 2009 if the dev_warn() hasn't | |
304 | * been triggered by then. | |
2c1c3c4c DB |
305 | */ |
306 | if (!device_can_wakeup(&pdev->dev)) { | |
307 | u16 port_wake; | |
308 | ||
309 | pci_read_config_word(pdev, 0x62, &port_wake); | |
6fd9086a AS |
310 | if (port_wake & 0x0001) { |
311 | dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); | |
bcca06ef | 312 | device_set_wakeup_capable(&pdev->dev, 1); |
6fd9086a | 313 | } |
2c1c3c4c | 314 | } |
7ff71d6a | 315 | |
f8aeb3bb DB |
316 | #ifdef CONFIG_USB_SUSPEND |
317 | /* REVISIT: the controller works fine for wakeup iff the root hub | |
318 | * itself is "globally" suspended, but usbcore currently doesn't | |
319 | * understand such things. | |
320 | * | |
321 | * System suspend currently expects to be able to suspend the entire | |
322 | * device tree, device-at-a-time. If we failed selective suspend | |
323 | * reports, system suspend would fail; so the root hub code must claim | |
411c9403 | 324 | * success. That's lying to usbcore, and it matters for runtime |
f8aeb3bb DB |
325 | * PM scenarios with selective suspend and remote wakeup... |
326 | */ | |
327 | if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) | |
328 | ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); | |
329 | #endif | |
330 | ||
aff6d18f | 331 | ehci_port_power(ehci, 1); |
18807521 | 332 | retval = ehci_pci_reinit(ehci, pdev); |
8926bfa7 DB |
333 | done: |
334 | return retval; | |
7ff71d6a MP |
335 | } |
336 | ||
337 | /*-------------------------------------------------------------------------*/ | |
338 | ||
339 | #ifdef CONFIG_PM | |
340 | ||
341 | /* suspend/resume, section 4.3 */ | |
342 | ||
f03c17fc | 343 | /* These routines rely on the PCI bus glue |
7ff71d6a MP |
344 | * to handle powerdown and wakeup, and currently also on |
345 | * transceivers that don't need any software attention to set up | |
346 | * the right sort of wakeup. | |
f03c17fc | 347 | * Also they depend on separate root hub suspend/resume. |
7ff71d6a MP |
348 | */ |
349 | ||
4147200d | 350 | static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
7ff71d6a | 351 | { |
abcc9448 | 352 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
8de98402 BH |
353 | unsigned long flags; |
354 | int rc = 0; | |
7ff71d6a | 355 | |
abcc9448 DB |
356 | if (time_before(jiffies, ehci->next_statechange)) |
357 | msleep(10); | |
7ff71d6a | 358 | |
8de98402 | 359 | /* Root hub was already suspended. Disable irq emission and |
16032c4f AS |
360 | * mark HW unaccessible. The PM and USB cores make sure that |
361 | * the root hub is either suspended or stopped. | |
8de98402 BH |
362 | */ |
363 | spin_lock_irqsave (&ehci->lock, flags); | |
4147200d | 364 | ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); |
083522d7 BH |
365 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
366 | (void)ehci_readl(ehci, &ehci->regs->intr_enable); | |
8de98402 BH |
367 | |
368 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
8de98402 BH |
369 | spin_unlock_irqrestore (&ehci->lock, flags); |
370 | ||
f03c17fc | 371 | // could save FLADJ in case of Vaux power loss |
7ff71d6a MP |
372 | // ... we'd only use it to handle clock skew |
373 | ||
8de98402 | 374 | return rc; |
7ff71d6a MP |
375 | } |
376 | ||
6ec4beb5 | 377 | static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) |
7ff71d6a | 378 | { |
abcc9448 | 379 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
18807521 | 380 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
7ff71d6a | 381 | |
f03c17fc | 382 | // maybe restore FLADJ |
7ff71d6a | 383 | |
abcc9448 DB |
384 | if (time_before(jiffies, ehci->next_statechange)) |
385 | msleep(100); | |
7ff71d6a | 386 | |
8de98402 BH |
387 | /* Mark hardware accessible again as we are out of D3 state by now */ |
388 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
389 | ||
6ec4beb5 AS |
390 | /* If CF is still set and we aren't resuming from hibernation |
391 | * then we maintained PCI Vaux power. | |
8c03356a | 392 | * Just undo the effect of ehci_pci_suspend(). |
7ff71d6a | 393 | */ |
6ec4beb5 AS |
394 | if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && |
395 | !hibernated) { | |
8c03356a AS |
396 | int mask = INTR_MASK; |
397 | ||
16032c4f | 398 | ehci_prepare_ports_for_controller_resume(ehci); |
58a97ffe | 399 | if (!hcd->self.root_hub->do_remote_wakeup) |
8c03356a | 400 | mask &= ~STS_PCD; |
083522d7 BH |
401 | ehci_writel(ehci, mask, &ehci->regs->intr_enable); |
402 | ehci_readl(ehci, &ehci->regs->intr_enable); | |
8c03356a | 403 | return 0; |
f03c17fc DB |
404 | } |
405 | ||
1c50c317 | 406 | usb_root_hub_lost_power(hcd->self.root_hub); |
7ff71d6a MP |
407 | |
408 | /* Else reset, to cope with power loss or flush-to-storage | |
f03c17fc | 409 | * style "resume" having let BIOS kick in during reboot. |
7ff71d6a | 410 | */ |
abcc9448 DB |
411 | (void) ehci_halt(ehci); |
412 | (void) ehci_reset(ehci); | |
18807521 | 413 | (void) ehci_pci_reinit(ehci, pdev); |
f03c17fc DB |
414 | |
415 | /* emptying the schedule aborts any urbs */ | |
abcc9448 | 416 | spin_lock_irq(&ehci->lock); |
f03c17fc | 417 | if (ehci->reclaim) |
07d29b63 | 418 | end_unlink_async(ehci); |
7d12e780 | 419 | ehci_work(ehci); |
abcc9448 | 420 | spin_unlock_irq(&ehci->lock); |
f03c17fc | 421 | |
083522d7 BH |
422 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
423 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | |
424 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
8c03356a | 425 | |
383975d7 AS |
426 | /* here we "know" root ports should always stay powered */ |
427 | ehci_port_power(ehci, 1); | |
383975d7 | 428 | |
8c03356a AS |
429 | hcd->state = HC_STATE_SUSPENDED; |
430 | return 0; | |
7ff71d6a MP |
431 | } |
432 | #endif | |
433 | ||
48f24970 AD |
434 | static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
435 | { | |
436 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
437 | int rc = 0; | |
438 | ||
439 | if (!udev->parent) /* udev is root hub itself, impossible */ | |
440 | rc = -1; | |
441 | /* we only support lpm device connected to root hub yet */ | |
442 | if (ehci->has_lpm && !udev->parent->parent) { | |
443 | rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum); | |
444 | if (!rc) | |
445 | rc = ehci_lpm_check(ehci, udev->portnum); | |
446 | } | |
447 | return rc; | |
448 | } | |
449 | ||
7ff71d6a MP |
450 | static const struct hc_driver ehci_pci_hc_driver = { |
451 | .description = hcd_name, | |
452 | .product_desc = "EHCI Host Controller", | |
453 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
454 | ||
455 | /* | |
456 | * generic hardware linkage | |
457 | */ | |
458 | .irq = ehci_irq, | |
459 | .flags = HCD_MEMORY | HCD_USB2, | |
460 | ||
461 | /* | |
462 | * basic lifecycle operations | |
463 | */ | |
8926bfa7 | 464 | .reset = ehci_pci_setup, |
18807521 | 465 | .start = ehci_run, |
7ff71d6a | 466 | #ifdef CONFIG_PM |
7be7d741 AS |
467 | .pci_suspend = ehci_pci_suspend, |
468 | .pci_resume = ehci_pci_resume, | |
7ff71d6a | 469 | #endif |
18807521 | 470 | .stop = ehci_stop, |
64a21d02 | 471 | .shutdown = ehci_shutdown, |
7ff71d6a MP |
472 | |
473 | /* | |
474 | * managing i/o requests and associated device resources | |
475 | */ | |
476 | .urb_enqueue = ehci_urb_enqueue, | |
477 | .urb_dequeue = ehci_urb_dequeue, | |
478 | .endpoint_disable = ehci_endpoint_disable, | |
b18ffd49 | 479 | .endpoint_reset = ehci_endpoint_reset, |
7ff71d6a MP |
480 | |
481 | /* | |
482 | * scheduling support | |
483 | */ | |
484 | .get_frame_number = ehci_get_frame, | |
485 | ||
486 | /* | |
487 | * root hub support | |
488 | */ | |
489 | .hub_status_data = ehci_hub_status_data, | |
490 | .hub_control = ehci_hub_control, | |
0c0382e3 AS |
491 | .bus_suspend = ehci_bus_suspend, |
492 | .bus_resume = ehci_bus_resume, | |
a8e51775 | 493 | .relinquish_port = ehci_relinquish_port, |
3a31155c | 494 | .port_handed_over = ehci_port_handed_over, |
914b7012 | 495 | |
48f24970 AD |
496 | /* |
497 | * call back when device connected and addressed | |
498 | */ | |
499 | .update_device = ehci_update_device, | |
500 | ||
914b7012 | 501 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, |
7ff71d6a MP |
502 | }; |
503 | ||
504 | /*-------------------------------------------------------------------------*/ | |
505 | ||
506 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
507 | static const struct pci_device_id pci_ids [] = { { | |
508 | /* handle any USB 2.0 EHCI controller */ | |
c67808ee | 509 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), |
7ff71d6a MP |
510 | .driver_data = (unsigned long) &ehci_pci_hc_driver, |
511 | }, | |
512 | { /* end: all zeroes */ } | |
513 | }; | |
abcc9448 | 514 | MODULE_DEVICE_TABLE(pci, pci_ids); |
7ff71d6a MP |
515 | |
516 | /* pci driver glue; this is a "new style" PCI driver module */ | |
517 | static struct pci_driver ehci_pci_driver = { | |
518 | .name = (char *) hcd_name, | |
519 | .id_table = pci_ids, | |
520 | ||
521 | .probe = usb_hcd_pci_probe, | |
522 | .remove = usb_hcd_pci_remove, | |
abb30641 | 523 | .shutdown = usb_hcd_pci_shutdown, |
7ff71d6a | 524 | |
abb30641 AS |
525 | #ifdef CONFIG_PM_SLEEP |
526 | .driver = { | |
527 | .pm = &usb_hcd_pci_pm_ops | |
528 | }, | |
7ff71d6a MP |
529 | #endif |
530 | }; |