Commit | Line | Data |
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7ff71d6a MP |
1 | /* |
2 | * EHCI HCD (Host Controller Driver) PCI Bus Glue. | |
3 | * | |
4 | * Copyright (c) 2000-2004 by David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #ifndef CONFIG_PCI | |
22 | #error "This file is PCI bus glue. CONFIG_PCI must be defined." | |
23 | #endif | |
24 | ||
4f683843 DB |
25 | /* defined here to avoid adding to pci_ids.h for single instance use */ |
26 | #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 | |
27 | ||
7ff71d6a MP |
28 | /*-------------------------------------------------------------------------*/ |
29 | ||
18807521 DB |
30 | /* called after powerup, by probe or system-pm "wakeup" */ |
31 | static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) | |
32 | { | |
18807521 | 33 | int retval; |
18807521 | 34 | |
401feafa DB |
35 | /* we expect static quirk code to handle the "extended capabilities" |
36 | * (currently just BIOS handoff) allowed starting with EHCI 0.96 | |
37 | */ | |
18807521 DB |
38 | |
39 | /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ | |
40 | retval = pci_set_mwi(pdev); | |
41 | if (!retval) | |
42 | ehci_dbg(ehci, "MWI active\n"); | |
43 | ||
18807521 DB |
44 | return 0; |
45 | } | |
46 | ||
8926bfa7 DB |
47 | /* called during probe() after chip reset completes */ |
48 | static int ehci_pci_setup(struct usb_hcd *hcd) | |
7ff71d6a | 49 | { |
abcc9448 DB |
50 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
51 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
b09bc6cb AX |
52 | struct pci_dev *p_smbus; |
53 | u8 rev; | |
7ff71d6a | 54 | u32 temp; |
18807521 | 55 | int retval; |
7ff71d6a | 56 | |
083522d7 BH |
57 | switch (pdev->vendor) { |
58 | case PCI_VENDOR_ID_TOSHIBA_2: | |
59 | /* celleb's companion chip */ | |
60 | if (pdev->device == 0x01b5) { | |
61 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
62 | ehci->big_endian_mmio = 1; | |
63 | #else | |
64 | ehci_warn(ehci, | |
65 | "unsupported big endian Toshiba quirk\n"); | |
66 | #endif | |
67 | } | |
68 | break; | |
69 | } | |
70 | ||
7ff71d6a | 71 | ehci->caps = hcd->regs; |
083522d7 | 72 | ehci->regs = hcd->regs + |
c430131a | 73 | HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); |
083522d7 | 74 | |
abcc9448 DB |
75 | dbg_hcs_params(ehci, "reset"); |
76 | dbg_hcc_params(ehci, "reset"); | |
7ff71d6a | 77 | |
c32ba30f PS |
78 | /* ehci_init() causes memory for DMA transfers to be |
79 | * allocated. Thus, any vendor-specific workarounds based on | |
80 | * limiting the type of memory used for DMA transfers must | |
81 | * happen before ehci_init() is called. */ | |
82 | switch (pdev->vendor) { | |
83 | case PCI_VENDOR_ID_NVIDIA: | |
84 | /* NVidia reports that certain chips don't handle | |
85 | * QH, ITD, or SITD addresses above 2GB. (But TD, | |
86 | * data buffer, and periodic schedule are normal.) | |
87 | */ | |
88 | switch (pdev->device) { | |
89 | case 0x003c: /* MCP04 */ | |
90 | case 0x005b: /* CK804 */ | |
91 | case 0x00d8: /* CK8 */ | |
92 | case 0x00e8: /* CK8S */ | |
93 | if (pci_set_consistent_dma_mask(pdev, | |
929a22a5 | 94 | DMA_BIT_MASK(31)) < 0) |
c32ba30f PS |
95 | ehci_warn(ehci, "can't enable NVidia " |
96 | "workaround for >2GB RAM\n"); | |
97 | break; | |
98 | } | |
99 | break; | |
100 | } | |
101 | ||
7ff71d6a | 102 | /* cache this readonly data; minimize chip reads */ |
083522d7 | 103 | ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); |
7ff71d6a | 104 | |
18807521 DB |
105 | retval = ehci_halt(ehci); |
106 | if (retval) | |
107 | return retval; | |
108 | ||
3d091a6f AX |
109 | if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) || |
110 | (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) { | |
111 | /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may | |
112 | * read/write memory space which does not belong to it when | |
113 | * there is NULL pointer with T-bit set to 1 in the frame list | |
114 | * table. To avoid the issue, the frame list link pointer | |
115 | * should always contain a valid pointer to a inactive qh. | |
116 | */ | |
117 | ehci->use_dummy_qh = 1; | |
118 | ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI " | |
119 | "dummy qh workaround\n"); | |
120 | } | |
121 | ||
8926bfa7 DB |
122 | /* data structure init */ |
123 | retval = ehci_init(hcd); | |
124 | if (retval) | |
125 | return retval; | |
126 | ||
abcc9448 | 127 | switch (pdev->vendor) { |
3681d8f3 DM |
128 | case PCI_VENDOR_ID_NEC: |
129 | ehci->need_io_watchdog = 0; | |
130 | break; | |
403dbd36 AD |
131 | case PCI_VENDOR_ID_INTEL: |
132 | ehci->need_io_watchdog = 0; | |
ae68a83b | 133 | ehci->fs_i_thresh = 1; |
ee4ecb8a ON |
134 | if (pdev->device == 0x27cc) { |
135 | ehci->broken_periodic = 1; | |
136 | ehci_info(ehci, "using broken periodic workaround\n"); | |
137 | } | |
fc928250 AD |
138 | if (pdev->device == 0x0806 || pdev->device == 0x0811 |
139 | || pdev->device == 0x0829) { | |
140 | ehci_info(ehci, "disable lpm for langwell/penwell\n"); | |
141 | ehci->has_lpm = 0; | |
142 | } | |
4f683843 DB |
143 | if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) { |
144 | hcd->has_tt = 1; | |
145 | tdi_reset(ehci); | |
146 | } | |
403dbd36 | 147 | break; |
abcc9448 DB |
148 | case PCI_VENDOR_ID_TDI: |
149 | if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { | |
7329e211 | 150 | hcd->has_tt = 1; |
abcc9448 DB |
151 | tdi_reset(ehci); |
152 | } | |
153 | break; | |
154 | case PCI_VENDOR_ID_AMD: | |
ad93562b AX |
155 | /* AMD PLL quirk */ |
156 | if (usb_amd_find_chipset_info()) | |
157 | ehci->amd_pll_fix = 1; | |
abcc9448 DB |
158 | /* AMD8111 EHCI doesn't work, according to AMD errata */ |
159 | if (pdev->device == 0x7463) { | |
160 | ehci_info(ehci, "ignoring AMD8111 (errata)\n"); | |
8926bfa7 DB |
161 | retval = -EIO; |
162 | goto done; | |
abcc9448 DB |
163 | } |
164 | break; | |
165 | case PCI_VENDOR_ID_NVIDIA: | |
f8aeb3bb | 166 | switch (pdev->device) { |
f8aeb3bb DB |
167 | /* Some NForce2 chips have problems with selective suspend; |
168 | * fixed in newer silicon. | |
169 | */ | |
170 | case 0x0068: | |
44c10138 | 171 | if (pdev->revision < 0xa4) |
f8aeb3bb DB |
172 | ehci->no_selective_suspend = 1; |
173 | break; | |
a85b4e7f BT |
174 | |
175 | /* MCP89 chips on the MacBookAir3,1 give EPROTO when | |
176 | * fetching device descriptors unless LPM is disabled. | |
177 | * There are also intermittent problems enumerating | |
178 | * devices with PPCD enabled. | |
179 | */ | |
180 | case 0x0d9d: | |
181 | ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89"); | |
182 | ehci->has_lpm = 0; | |
183 | ehci->has_ppcd = 0; | |
184 | ehci->command &= ~CMD_PPCEE; | |
185 | break; | |
7ff71d6a | 186 | } |
abcc9448 | 187 | break; |
055b93c9 RH |
188 | case PCI_VENDOR_ID_VIA: |
189 | if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { | |
190 | u8 tmp; | |
191 | ||
192 | /* The VT6212 defaults to a 1 usec EHCI sleep time which | |
193 | * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes | |
194 | * that sleep time use the conventional 10 usec. | |
195 | */ | |
196 | pci_read_config_byte(pdev, 0x4b, &tmp); | |
197 | if (tmp & 0x20) | |
198 | break; | |
199 | pci_write_config_byte(pdev, 0x4b, tmp | 0x20); | |
200 | } | |
201 | break; | |
b09bc6cb | 202 | case PCI_VENDOR_ID_ATI: |
ad93562b AX |
203 | /* AMD PLL quirk */ |
204 | if (usb_amd_find_chipset_info()) | |
205 | ehci->amd_pll_fix = 1; | |
0a99e8ac | 206 | /* SB600 and old version of SB700 have a bug in EHCI controller, |
b09bc6cb AX |
207 | * which causes usb devices lose response in some cases. |
208 | */ | |
0a99e8ac | 209 | if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { |
b09bc6cb AX |
210 | p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, |
211 | PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
212 | NULL); | |
213 | if (!p_smbus) | |
214 | break; | |
215 | rev = p_smbus->revision; | |
0a99e8ac SH |
216 | if ((pdev->device == 0x4386) || (rev == 0x3a) |
217 | || (rev == 0x3b)) { | |
b09bc6cb | 218 | u8 tmp; |
0a99e8ac SH |
219 | ehci_info(ehci, "applying AMD SB600/SB700 USB " |
220 | "freeze workaround\n"); | |
b09bc6cb AX |
221 | pci_read_config_byte(pdev, 0x53, &tmp); |
222 | pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); | |
223 | } | |
224 | pci_dev_put(p_smbus); | |
225 | } | |
226 | break; | |
68aa95d5 AS |
227 | case PCI_VENDOR_ID_NETMOS: |
228 | /* MosChip frame-index-register bug */ | |
229 | ehci_info(ehci, "applying MosChip frame-index workaround\n"); | |
230 | ehci->frame_index_bug = 1; | |
231 | break; | |
abcc9448 | 232 | } |
7ff71d6a | 233 | |
8d053c79 JW |
234 | /* optional debug port, normally in the first BAR */ |
235 | temp = pci_find_capability(pdev, 0x0a); | |
236 | if (temp) { | |
237 | pci_read_config_dword(pdev, temp, &temp); | |
238 | temp >>= 16; | |
239 | if ((temp & (3 << 13)) == (1 << 13)) { | |
240 | temp &= 0x1fff; | |
241 | ehci->debug = ehci_to_hcd(ehci)->regs + temp; | |
242 | temp = ehci_readl(ehci, &ehci->debug->control); | |
243 | ehci_info(ehci, "debug port %d%s\n", | |
244 | HCS_DEBUG_PORT(ehci->hcs_params), | |
245 | (temp & DBGP_ENABLED) | |
246 | ? " IN USE" | |
247 | : ""); | |
248 | if (!(temp & DBGP_ENABLED)) | |
249 | ehci->debug = NULL; | |
250 | } | |
251 | } | |
252 | ||
af1c51fc | 253 | ehci_reset(ehci); |
7ff71d6a | 254 | |
7ff71d6a MP |
255 | /* at least the Genesys GL880S needs fixup here */ |
256 | temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); | |
257 | temp &= 0x0f; | |
258 | if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { | |
abcc9448 | 259 | ehci_dbg(ehci, "bogus port configuration: " |
7ff71d6a MP |
260 | "cc=%d x pcc=%d < ports=%d\n", |
261 | HCS_N_CC(ehci->hcs_params), | |
262 | HCS_N_PCC(ehci->hcs_params), | |
263 | HCS_N_PORTS(ehci->hcs_params)); | |
264 | ||
abcc9448 DB |
265 | switch (pdev->vendor) { |
266 | case 0x17a0: /* GENESYS */ | |
267 | /* GL880S: should be PORTS=2 */ | |
268 | temp |= (ehci->hcs_params & ~0xf); | |
269 | ehci->hcs_params = temp; | |
270 | break; | |
271 | case PCI_VENDOR_ID_NVIDIA: | |
272 | /* NF4: should be PCC=10 */ | |
273 | break; | |
7ff71d6a MP |
274 | } |
275 | } | |
276 | ||
abcc9448 DB |
277 | /* Serial Bus Release Number is at PCI 0x60 offset */ |
278 | pci_read_config_byte(pdev, 0x60, &ehci->sbrn); | |
3a0bac06 AR |
279 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO |
280 | && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST) | |
281 | ehci->sbrn = 0x20; /* ConneXT has no sbrn register */ | |
7ff71d6a | 282 | |
6fd9086a AS |
283 | /* Keep this around for a while just in case some EHCI |
284 | * implementation uses legacy PCI PM support. This test | |
285 | * can be removed on 17 Dec 2009 if the dev_warn() hasn't | |
286 | * been triggered by then. | |
2c1c3c4c DB |
287 | */ |
288 | if (!device_can_wakeup(&pdev->dev)) { | |
289 | u16 port_wake; | |
290 | ||
291 | pci_read_config_word(pdev, 0x62, &port_wake); | |
6fd9086a AS |
292 | if (port_wake & 0x0001) { |
293 | dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); | |
bcca06ef | 294 | device_set_wakeup_capable(&pdev->dev, 1); |
6fd9086a | 295 | } |
2c1c3c4c | 296 | } |
7ff71d6a | 297 | |
f8aeb3bb DB |
298 | #ifdef CONFIG_USB_SUSPEND |
299 | /* REVISIT: the controller works fine for wakeup iff the root hub | |
300 | * itself is "globally" suspended, but usbcore currently doesn't | |
301 | * understand such things. | |
302 | * | |
303 | * System suspend currently expects to be able to suspend the entire | |
304 | * device tree, device-at-a-time. If we failed selective suspend | |
305 | * reports, system suspend would fail; so the root hub code must claim | |
411c9403 | 306 | * success. That's lying to usbcore, and it matters for runtime |
f8aeb3bb DB |
307 | * PM scenarios with selective suspend and remote wakeup... |
308 | */ | |
309 | if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) | |
310 | ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); | |
311 | #endif | |
312 | ||
aff6d18f | 313 | ehci_port_power(ehci, 1); |
18807521 | 314 | retval = ehci_pci_reinit(ehci, pdev); |
8926bfa7 DB |
315 | done: |
316 | return retval; | |
7ff71d6a MP |
317 | } |
318 | ||
319 | /*-------------------------------------------------------------------------*/ | |
320 | ||
321 | #ifdef CONFIG_PM | |
322 | ||
323 | /* suspend/resume, section 4.3 */ | |
324 | ||
f03c17fc | 325 | /* These routines rely on the PCI bus glue |
7ff71d6a MP |
326 | * to handle powerdown and wakeup, and currently also on |
327 | * transceivers that don't need any software attention to set up | |
328 | * the right sort of wakeup. | |
f03c17fc | 329 | * Also they depend on separate root hub suspend/resume. |
7ff71d6a MP |
330 | */ |
331 | ||
4147200d | 332 | static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
7ff71d6a | 333 | { |
abcc9448 | 334 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
8de98402 BH |
335 | unsigned long flags; |
336 | int rc = 0; | |
7ff71d6a | 337 | |
abcc9448 DB |
338 | if (time_before(jiffies, ehci->next_statechange)) |
339 | msleep(10); | |
7ff71d6a | 340 | |
8de98402 | 341 | /* Root hub was already suspended. Disable irq emission and |
16032c4f AS |
342 | * mark HW unaccessible. The PM and USB cores make sure that |
343 | * the root hub is either suspended or stopped. | |
8de98402 | 344 | */ |
4147200d | 345 | ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); |
148fc55f | 346 | spin_lock_irqsave (&ehci->lock, flags); |
083522d7 BH |
347 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); |
348 | (void)ehci_readl(ehci, &ehci->regs->intr_enable); | |
8de98402 BH |
349 | |
350 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
8de98402 BH |
351 | spin_unlock_irqrestore (&ehci->lock, flags); |
352 | ||
f03c17fc | 353 | // could save FLADJ in case of Vaux power loss |
7ff71d6a MP |
354 | // ... we'd only use it to handle clock skew |
355 | ||
8de98402 | 356 | return rc; |
7ff71d6a MP |
357 | } |
358 | ||
69e848c2 SS |
359 | static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev) |
360 | { | |
361 | return pdev->class == PCI_CLASS_SERIAL_USB_EHCI && | |
362 | pdev->vendor == PCI_VENDOR_ID_INTEL && | |
1c12443a SS |
363 | (pdev->device == 0x1E26 || |
364 | pdev->device == 0x8C2D || | |
365 | pdev->device == 0x8C26); | |
69e848c2 SS |
366 | } |
367 | ||
368 | static void ehci_enable_xhci_companion(void) | |
369 | { | |
370 | struct pci_dev *companion = NULL; | |
371 | ||
372 | /* The xHCI and EHCI controllers are not on the same PCI slot */ | |
373 | for_each_pci_dev(companion) { | |
374 | if (!usb_is_intel_switchable_xhci(companion)) | |
375 | continue; | |
376 | usb_enable_xhci_ports(companion); | |
377 | return; | |
378 | } | |
379 | } | |
380 | ||
6ec4beb5 | 381 | static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) |
7ff71d6a | 382 | { |
abcc9448 | 383 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); |
18807521 | 384 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); |
7ff71d6a | 385 | |
69e848c2 SS |
386 | /* The BIOS on systems with the Intel Panther Point chipset may or may |
387 | * not support xHCI natively. That means that during system resume, it | |
388 | * may switch the ports back to EHCI so that users can use their | |
389 | * keyboard to select a kernel from GRUB after resume from hibernate. | |
390 | * | |
391 | * The BIOS is supposed to remember whether the OS had xHCI ports | |
392 | * enabled before resume, and switch the ports back to xHCI when the | |
393 | * BIOS/OS semaphore is written, but we all know we can't trust BIOS | |
394 | * writers. | |
395 | * | |
396 | * Unconditionally switch the ports back to xHCI after a system resume. | |
397 | * We can't tell whether the EHCI or xHCI controller will be resumed | |
398 | * first, so we have to do the port switchover in both drivers. Writing | |
399 | * a '1' to the port switchover registers should have no effect if the | |
400 | * port was already switched over. | |
401 | */ | |
402 | if (usb_is_intel_switchable_ehci(pdev)) | |
403 | ehci_enable_xhci_companion(); | |
404 | ||
f03c17fc | 405 | // maybe restore FLADJ |
7ff71d6a | 406 | |
abcc9448 DB |
407 | if (time_before(jiffies, ehci->next_statechange)) |
408 | msleep(100); | |
7ff71d6a | 409 | |
8de98402 BH |
410 | /* Mark hardware accessible again as we are out of D3 state by now */ |
411 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
412 | ||
6ec4beb5 AS |
413 | /* If CF is still set and we aren't resuming from hibernation |
414 | * then we maintained PCI Vaux power. | |
8c03356a | 415 | * Just undo the effect of ehci_pci_suspend(). |
7ff71d6a | 416 | */ |
6ec4beb5 AS |
417 | if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && |
418 | !hibernated) { | |
8c03356a AS |
419 | int mask = INTR_MASK; |
420 | ||
16032c4f | 421 | ehci_prepare_ports_for_controller_resume(ehci); |
58a97ffe | 422 | if (!hcd->self.root_hub->do_remote_wakeup) |
8c03356a | 423 | mask &= ~STS_PCD; |
083522d7 BH |
424 | ehci_writel(ehci, mask, &ehci->regs->intr_enable); |
425 | ehci_readl(ehci, &ehci->regs->intr_enable); | |
8c03356a | 426 | return 0; |
f03c17fc DB |
427 | } |
428 | ||
1c50c317 | 429 | usb_root_hub_lost_power(hcd->self.root_hub); |
7ff71d6a MP |
430 | |
431 | /* Else reset, to cope with power loss or flush-to-storage | |
f03c17fc | 432 | * style "resume" having let BIOS kick in during reboot. |
7ff71d6a | 433 | */ |
abcc9448 DB |
434 | (void) ehci_halt(ehci); |
435 | (void) ehci_reset(ehci); | |
18807521 | 436 | (void) ehci_pci_reinit(ehci, pdev); |
f03c17fc DB |
437 | |
438 | /* emptying the schedule aborts any urbs */ | |
abcc9448 | 439 | spin_lock_irq(&ehci->lock); |
f03c17fc | 440 | if (ehci->reclaim) |
07d29b63 | 441 | end_unlink_async(ehci); |
7d12e780 | 442 | ehci_work(ehci); |
abcc9448 | 443 | spin_unlock_irq(&ehci->lock); |
f03c17fc | 444 | |
083522d7 BH |
445 | ehci_writel(ehci, ehci->command, &ehci->regs->command); |
446 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | |
447 | ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ | |
8c03356a | 448 | |
383975d7 AS |
449 | /* here we "know" root ports should always stay powered */ |
450 | ehci_port_power(ehci, 1); | |
383975d7 | 451 | |
e8799906 | 452 | ehci->rh_state = EHCI_RH_SUSPENDED; |
8c03356a | 453 | return 0; |
7ff71d6a MP |
454 | } |
455 | #endif | |
456 | ||
48f24970 AD |
457 | static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
458 | { | |
459 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
460 | int rc = 0; | |
461 | ||
462 | if (!udev->parent) /* udev is root hub itself, impossible */ | |
463 | rc = -1; | |
464 | /* we only support lpm device connected to root hub yet */ | |
465 | if (ehci->has_lpm && !udev->parent->parent) { | |
466 | rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum); | |
467 | if (!rc) | |
468 | rc = ehci_lpm_check(ehci, udev->portnum); | |
469 | } | |
470 | return rc; | |
471 | } | |
472 | ||
7ff71d6a MP |
473 | static const struct hc_driver ehci_pci_hc_driver = { |
474 | .description = hcd_name, | |
475 | .product_desc = "EHCI Host Controller", | |
476 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
477 | ||
478 | /* | |
479 | * generic hardware linkage | |
480 | */ | |
481 | .irq = ehci_irq, | |
482 | .flags = HCD_MEMORY | HCD_USB2, | |
483 | ||
484 | /* | |
485 | * basic lifecycle operations | |
486 | */ | |
8926bfa7 | 487 | .reset = ehci_pci_setup, |
18807521 | 488 | .start = ehci_run, |
7ff71d6a | 489 | #ifdef CONFIG_PM |
7be7d741 AS |
490 | .pci_suspend = ehci_pci_suspend, |
491 | .pci_resume = ehci_pci_resume, | |
7ff71d6a | 492 | #endif |
18807521 | 493 | .stop = ehci_stop, |
64a21d02 | 494 | .shutdown = ehci_shutdown, |
7ff71d6a MP |
495 | |
496 | /* | |
497 | * managing i/o requests and associated device resources | |
498 | */ | |
499 | .urb_enqueue = ehci_urb_enqueue, | |
500 | .urb_dequeue = ehci_urb_dequeue, | |
501 | .endpoint_disable = ehci_endpoint_disable, | |
b18ffd49 | 502 | .endpoint_reset = ehci_endpoint_reset, |
7ff71d6a MP |
503 | |
504 | /* | |
505 | * scheduling support | |
506 | */ | |
507 | .get_frame_number = ehci_get_frame, | |
508 | ||
509 | /* | |
510 | * root hub support | |
511 | */ | |
512 | .hub_status_data = ehci_hub_status_data, | |
513 | .hub_control = ehci_hub_control, | |
0c0382e3 AS |
514 | .bus_suspend = ehci_bus_suspend, |
515 | .bus_resume = ehci_bus_resume, | |
a8e51775 | 516 | .relinquish_port = ehci_relinquish_port, |
3a31155c | 517 | .port_handed_over = ehci_port_handed_over, |
914b7012 | 518 | |
48f24970 AD |
519 | /* |
520 | * call back when device connected and addressed | |
521 | */ | |
522 | .update_device = ehci_update_device, | |
523 | ||
914b7012 | 524 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, |
7ff71d6a MP |
525 | }; |
526 | ||
527 | /*-------------------------------------------------------------------------*/ | |
528 | ||
529 | /* PCI driver selection metadata; PCI hotplugging uses this */ | |
530 | static const struct pci_device_id pci_ids [] = { { | |
531 | /* handle any USB 2.0 EHCI controller */ | |
c67808ee | 532 | PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), |
7ff71d6a | 533 | .driver_data = (unsigned long) &ehci_pci_hc_driver, |
3a0bac06 AR |
534 | }, { |
535 | PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST), | |
536 | .driver_data = (unsigned long) &ehci_pci_hc_driver, | |
7ff71d6a MP |
537 | }, |
538 | { /* end: all zeroes */ } | |
539 | }; | |
abcc9448 | 540 | MODULE_DEVICE_TABLE(pci, pci_ids); |
7ff71d6a MP |
541 | |
542 | /* pci driver glue; this is a "new style" PCI driver module */ | |
543 | static struct pci_driver ehci_pci_driver = { | |
544 | .name = (char *) hcd_name, | |
545 | .id_table = pci_ids, | |
546 | ||
547 | .probe = usb_hcd_pci_probe, | |
548 | .remove = usb_hcd_pci_remove, | |
abb30641 | 549 | .shutdown = usb_hcd_pci_shutdown, |
7ff71d6a | 550 | |
abb30641 AS |
551 | #ifdef CONFIG_PM_SLEEP |
552 | .driver = { | |
553 | .pm = &usb_hcd_pci_pm_ops | |
554 | }, | |
7ff71d6a MP |
555 | #endif |
556 | }; |