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xHCI: Clear PLC for USB2 root hub ports
[deliverable/linux.git] / drivers / usb / host / ehci-sched.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
53bd6a60 4 *
1da177e4
LT		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20/* this file is part of ehci-hcd.c */
21
22/*-------------------------------------------------------------------------*/
23
24/*
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
27 *
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
31 *
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
35 */
36
37static int ehci_get_frame (struct usb_hcd *hcd);
38
39/*-------------------------------------------------------------------------*/
40
41/*
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
45 */
46static union ehci_shadow *
6dbd682b
SR		 47periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
1da177e4 49{
6dbd682b 50 switch (hc32_to_cpu(ehci, tag)) {
1da177e4
LT		 51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
60 }
61}
62
3807e26d
AD		 63static __hc32 *
64shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
65 __hc32 tag)
66{
67 switch (hc32_to_cpu(ehci, tag)) {
68 /* our ehci_shadow.qh is actually software part */
69 case Q_TYPE_QH:
70 return &periodic->qh->hw->hw_next;
71 /* others are hw parts */
72 default:
73 return periodic->hw_next;
74 }
75}
76
1da177e4
LT		 77/* caller must hold ehci->lock */
78static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
79{
6dbd682b
SR		 80 union ehci_shadow *prev_p = &ehci->pshadow[frame];
81 __hc32 *hw_p = &ehci->periodic[frame];
1da177e4
LT		 82 union ehci_shadow here = *prev_p;
83
84 /* find predecessor of "ptr"; hw and shadow lists are in sync */
85 while (here.ptr && here.ptr != ptr) {
6dbd682b
SR		 86 prev_p = periodic_next_shadow(ehci, prev_p,
87 Q_NEXT_TYPE(ehci, *hw_p));
3807e26d
AD		 88 hw_p = shadow_next_periodic(ehci, &here,
89 Q_NEXT_TYPE(ehci, *hw_p));
1da177e4
LT		 90 here = *prev_p;
91 }
92 /* an interrupt entry (at list end) could have been shared */
93 if (!here.ptr)
94 return;
95
96 /* update shadow and hardware lists ... the old "next" pointers
97 * from ptr may still be in use, the caller updates them.
98 */
6dbd682b
SR		 99 *prev_p = *periodic_next_shadow(ehci, &here,
100 Q_NEXT_TYPE(ehci, *hw_p));
3d091a6f
AX		 101
102 if (!ehci->use_dummy_qh ||
103 *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p))
104 != EHCI_LIST_END(ehci))
105 *hw_p = *shadow_next_periodic(ehci, &here,
106 Q_NEXT_TYPE(ehci, *hw_p));
107 else
108 *hw_p = ehci->dummy->qh_dma;
1da177e4
LT		 109}
110
111/* how many of the uframe's 125 usecs are allocated? */
112static unsigned short
113periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
114{
6dbd682b 115 __hc32 *hw_p = &ehci->periodic [frame];
1da177e4
LT		 116 union ehci_shadow *q = &ehci->pshadow [frame];
117 unsigned usecs = 0;
3807e26d 118 struct ehci_qh_hw *hw;
1da177e4
LT		 119
120 while (q->ptr) {
6dbd682b 121 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
1da177e4 122 case Q_TYPE_QH:
3807e26d 123 hw = q->qh->hw;
1da177e4 124 /* is it in the S-mask? */
3807e26d 125 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
1da177e4
LT		 126 usecs += q->qh->usecs;
127 /* ... or C-mask? */
3807e26d 128 if (hw->hw_info2 & cpu_to_hc32(ehci,
6dbd682b 129 1 << (8 + uframe)))
1da177e4 130 usecs += q->qh->c_usecs;
3807e26d 131 hw_p = &hw->hw_next;
1da177e4
LT		 132 q = &q->qh->qh_next;
133 break;
134 // case Q_TYPE_FSTN:
135 default:
136 /* for "save place" FSTNs, count the relevant INTR
137 * bandwidth from the previous frame
138 */
6dbd682b 139 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
1da177e4
LT		 140 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
141 }
142 hw_p = &q->fstn->hw_next;
143 q = &q->fstn->fstn_next;
144 break;
145 case Q_TYPE_ITD:
3b6fcfd0
KW		 146 if (q->itd->hw_transaction[uframe])
147 usecs += q->itd->stream->usecs;
1da177e4
LT		 148 hw_p = &q->itd->hw_next;
149 q = &q->itd->itd_next;
150 break;
151 case Q_TYPE_SITD:
152 /* is it in the S-mask? (count SPLIT, DATA) */
6dbd682b
SR		 153 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
154 1 << uframe)) {
1da177e4 155 if (q->sitd->hw_fullspeed_ep &
6dbd682b 156 cpu_to_hc32(ehci, 1<<31))
1da177e4
LT		 157 usecs += q->sitd->stream->usecs;
158 else /* worst case for OUT start-split */
159 usecs += HS_USECS_ISO (188);
160 }
161
162 /* ... C-mask? (count CSPLIT, DATA) */
163 if (q->sitd->hw_uframe &
6dbd682b 164 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
1da177e4
LT		 165 /* worst case for IN complete-split */
166 usecs += q->sitd->stream->c_usecs;
167 }
168
169 hw_p = &q->sitd->hw_next;
170 q = &q->sitd->sitd_next;
171 break;
172 }
173 }
174#ifdef DEBUG
cc62a7eb 175 if (usecs > ehci->uframe_periodic_max)
1da177e4
LT		 176 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
177 frame * 8 + uframe, usecs);
178#endif
179 return usecs;
180}
181
182/*-------------------------------------------------------------------------*/
183
184static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
185{
186 if (!dev1->tt || !dev2->tt)
187 return 0;
188 if (dev1->tt != dev2->tt)
189 return 0;
190 if (dev1->tt->multi)
191 return dev1->ttport == dev2->ttport;
192 else
193 return 1;
194}
195
ba47f66b
DS		 196#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
197
198/* Which uframe does the low/fullspeed transfer start in?
199 *
200 * The parameter is the mask of ssplits in "H-frame" terms
201 * and this returns the transfer start uframe in "B-frame" terms,
202 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
203 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
204 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
205 */
6dbd682b 206static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
ba47f66b 207{
6dbd682b 208 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
ba47f66b
DS		 209 if (!smask) {
210 ehci_err(ehci, "invalid empty smask!\n");
211 /* uframe 7 can't have bw so this will indicate failure */
212 return 7;
213 }
214 return ffs(smask) - 1;
215}
216
217static const unsigned char
218max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
219
220/* carryover low/fullspeed bandwidth that crosses uframe boundries */
221static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
222{
223 int i;
224 for (i=0; i<7; i++) {
225 if (max_tt_usecs[i] < tt_usecs[i]) {
226 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
227 tt_usecs[i] = max_tt_usecs[i];
228 }
229 }
230}
231
232/* How many of the tt's periodic downstream 1000 usecs are allocated?
233 *
234 * While this measures the bandwidth in terms of usecs/uframe,
235 * the low/fullspeed bus has no notion of uframes, so any particular
236 * low/fullspeed transfer can "carry over" from one uframe to the next,
237 * since the TT just performs downstream transfers in sequence.
238 *
dc0d5c1e 239 * For example two separate 100 usec transfers can start in the same uframe,
ba47f66b
DS		 240 * and the second one would "carry over" 75 usecs into the next uframe.
241 */
242static void
243periodic_tt_usecs (
244 struct ehci_hcd *ehci,
245 struct usb_device *dev,
246 unsigned frame,
247 unsigned short tt_usecs[8]
248)
249{
6dbd682b 250 __hc32 *hw_p = &ehci->periodic [frame];
ba47f66b
DS		 251 union ehci_shadow *q = &ehci->pshadow [frame];
252 unsigned char uf;
253
254 memset(tt_usecs, 0, 16);
255
256 while (q->ptr) {
6dbd682b 257 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
ba47f66b
DS		 258 case Q_TYPE_ITD:
259 hw_p = &q->itd->hw_next;
260 q = &q->itd->itd_next;
261 continue;
262 case Q_TYPE_QH:
263 if (same_tt(dev, q->qh->dev)) {
3807e26d 264 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
ba47f66b
DS		 265 tt_usecs[uf] += q->qh->tt_usecs;
266 }
3807e26d 267 hw_p = &q->qh->hw->hw_next;
ba47f66b
DS		 268 q = &q->qh->qh_next;
269 continue;
270 case Q_TYPE_SITD:
271 if (same_tt(dev, q->sitd->urb->dev)) {
272 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
273 tt_usecs[uf] += q->sitd->stream->tt_usecs;
274 }
275 hw_p = &q->sitd->hw_next;
276 q = &q->sitd->sitd_next;
277 continue;
278 // case Q_TYPE_FSTN:
279 default:
6dbd682b
SR		 280 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
281 frame);
ba47f66b
DS		 282 hw_p = &q->fstn->hw_next;
283 q = &q->fstn->fstn_next;
284 }
285 }
286
287 carryover_tt_bandwidth(tt_usecs);
288
289 if (max_tt_usecs[7] < tt_usecs[7])
290 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
291 frame, tt_usecs[7] - max_tt_usecs[7]);
292}
293
294/*
295 * Return true if the device's tt's downstream bus is available for a
296 * periodic transfer of the specified length (usecs), starting at the
297 * specified frame/uframe. Note that (as summarized in section 11.19
298 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
299 * uframe.
300 *
301 * The uframe parameter is when the fullspeed/lowspeed transfer
302 * should be executed in "B-frame" terms, which is the same as the
303 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
304 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
305 * See the EHCI spec sec 4.5 and fig 4.7.
306 *
307 * This checks if the full/lowspeed bus, at the specified starting uframe,
308 * has the specified bandwidth available, according to rules listed
309 * in USB 2.0 spec section 11.18.1 fig 11-60.
310 *
311 * This does not check if the transfer would exceed the max ssplit
312 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
313 * since proper scheduling limits ssplits to less than 16 per uframe.
314 */
315static int tt_available (
316 struct ehci_hcd *ehci,
317 unsigned period,
318 struct usb_device *dev,
319 unsigned frame,
320 unsigned uframe,
321 u16 usecs
322)
323{
324 if ((period == 0) || (uframe >= 7)) /* error */
325 return 0;
326
327 for (; frame < ehci->periodic_size; frame += period) {
328 unsigned short tt_usecs[8];
329
330 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
331
332 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
333 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
334 frame, usecs, uframe,
335 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
336 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
337
338 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
339 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
340 frame, uframe);
341 return 0;
342 }
343
344 /* special case for isoc transfers larger than 125us:
345 * the first and each subsequent fully used uframe
346 * must be empty, so as to not illegally delay
347 * already scheduled transactions
348 */
349 if (125 < usecs) {
c065c60e 350 int ufs = (usecs / 125);
ba47f66b
DS		 351 int i;
352 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
353 if (0 < tt_usecs[i]) {
354 ehci_vdbg(ehci,
355 "multi-uframe xfer can't fit "
356 "in frame %d uframe %d\n",
357 frame, i);
358 return 0;
359 }
360 }
361
362 tt_usecs[uframe] += usecs;
363
364 carryover_tt_bandwidth(tt_usecs);
365
366 /* fail if the carryover pushed bw past the last uframe's limit */
367 if (max_tt_usecs[7] < tt_usecs[7]) {
368 ehci_vdbg(ehci,
369 "tt unavailable usecs %d frame %d uframe %d\n",
370 usecs, frame, uframe);
371 return 0;
372 }
373 }
374
375 return 1;
376}
377
378#else
379
1da177e4
LT		 380/* return true iff the device's transaction translator is available
381 * for a periodic transfer starting at the specified frame, using
382 * all the uframes in the mask.
383 */
384static int tt_no_collision (
385 struct ehci_hcd *ehci,
386 unsigned period,
387 struct usb_device *dev,
388 unsigned frame,
389 u32 uf_mask
390)
391{
392 if (period == 0) /* error */
393 return 0;
394
395 /* note bandwidth wastage: split never follows csplit
396 * (different dev or endpoint) until the next uframe.
397 * calling convention doesn't make that distinction.
398 */
399 for (; frame < ehci->periodic_size; frame += period) {
400 union ehci_shadow here;
6dbd682b 401 __hc32 type;
3807e26d 402 struct ehci_qh_hw *hw;
1da177e4
LT		 403
404 here = ehci->pshadow [frame];
6dbd682b 405 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
1da177e4 406 while (here.ptr) {
6dbd682b 407 switch (hc32_to_cpu(ehci, type)) {
1da177e4 408 case Q_TYPE_ITD:
6dbd682b 409 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
1da177e4
LT		 410 here = here.itd->itd_next;
411 continue;
412 case Q_TYPE_QH:
3807e26d 413 hw = here.qh->hw;
1da177e4
LT		 414 if (same_tt (dev, here.qh->dev)) {
415 u32 mask;
416
6dbd682b 417 mask = hc32_to_cpu(ehci,
3807e26d 418 hw->hw_info2);
1da177e4
LT		 419 /* "knows" no gap is needed */
420 mask |= mask >> 8;
421 if (mask & uf_mask)
422 break;
423 }
3807e26d 424 type = Q_NEXT_TYPE(ehci, hw->hw_next);
1da177e4
LT		 425 here = here.qh->qh_next;
426 continue;
427 case Q_TYPE_SITD:
428 if (same_tt (dev, here.sitd->urb->dev)) {
429 u16 mask;
430
6dbd682b 431 mask = hc32_to_cpu(ehci, here.sitd
1da177e4
LT		 432 ->hw_uframe);
433 /* FIXME assumes no gap for IN! */
434 mask |= mask >> 8;
435 if (mask & uf_mask)
436 break;
437 }
6dbd682b 438 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
1da177e4
LT		 439 here = here.sitd->sitd_next;
440 continue;
441 // case Q_TYPE_FSTN:
442 default:
443 ehci_dbg (ehci,
444 "periodic frame %d bogus type %d\n",
445 frame, type);
446 }
447
448 /* collision or error */
449 return 0;
450 }
451 }
452
453 /* no collision */
454 return 1;
455}
456
ba47f66b
DS		 457#endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
458
1da177e4
LT		 459/*-------------------------------------------------------------------------*/
460
461static int enable_periodic (struct ehci_hcd *ehci)
462{
463 u32 cmd;
464 int status;
465
01c17142
DB		 466 if (ehci->periodic_sched++)
467 return 0;
468
1da177e4
LT		 469 /* did clearing PSE did take effect yet?
470 * takes effect only at frame boundaries...
471 */
c765d4ca
KW		 472 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
473 STS_PSS, 0, 9 * 125);
69fff59d
AS		 474 if (status) {
475 usb_hc_died(ehci_to_hcd(ehci));
1da177e4 476 return status;
69fff59d 477 }
1da177e4 478
083522d7
BH		 479 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
480 ehci_writel(ehci, cmd, &ehci->regs->command);
1da177e4 481 /* posted write ... PSS happens later */
1da177e4
LT		 482
483 /* make sure ehci_work scans these */
083522d7
BH		 484 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
485 % (ehci->periodic_size << 3);
ee4ecb8a
ON		 486 if (unlikely(ehci->broken_periodic))
487 ehci->last_periodic_enable = ktime_get_real();
1da177e4
LT		 488 return 0;
489}
490
491static int disable_periodic (struct ehci_hcd *ehci)
492{
493 u32 cmd;
494 int status;
495
01c17142
DB		 496 if (--ehci->periodic_sched)
497 return 0;
498
ee4ecb8a
ON		 499 if (unlikely(ehci->broken_periodic)) {
500 /* delay experimentally determined */
501 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
502 ktime_t now = ktime_get_real();
503 s64 delay = ktime_us_delta(safe, now);
504
505 if (unlikely(delay > 0))
506 udelay(delay);
507 }
508
1da177e4
LT		 509 /* did setting PSE not take effect yet?
510 * takes effect only at frame boundaries...
511 */
c765d4ca
KW		 512 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
513 STS_PSS, STS_PSS, 9 * 125);
69fff59d
AS		 514 if (status) {
515 usb_hc_died(ehci_to_hcd(ehci));
1da177e4 516 return status;
69fff59d 517 }
1da177e4 518
083522d7
BH		 519 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
520 ehci_writel(ehci, cmd, &ehci->regs->command);
1da177e4
LT		 521 /* posted write ... */
522
0e5f231b 523 free_cached_lists(ehci);
d63c66d2 524
1da177e4
LT		 525 ehci->next_uframe = -1;
526 return 0;
527}
528
529/*-------------------------------------------------------------------------*/
530
531/* periodic schedule slots have iso tds (normal or split) first, then a
532 * sparse tree for active interrupt transfers.
533 *
534 * this just links in a qh; caller guarantees uframe masks are set right.
535 * no FSTN support (yet; ehci 0.96+)
536 */
537static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
538{
539 unsigned i;
540 unsigned period = qh->period;
541
542 dev_dbg (&qh->dev->dev,
543 "link qh%d-%04x/%p start %d [%d/%d us]\n",
3807e26d
AD		 544 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
545 & (QH_CMASK | QH_SMASK),
1da177e4
LT		 546 qh, qh->start, qh->usecs, qh->c_usecs);
547
548 /* high bandwidth, or otherwise every microframe */
549 if (period == 0)
550 period = 1;
551
552 for (i = qh->start; i < ehci->periodic_size; i += period) {
6dbd682b
SR		 553 union ehci_shadow *prev = &ehci->pshadow[i];
554 __hc32 *hw_p = &ehci->periodic[i];
1da177e4 555 union ehci_shadow here = *prev;
6dbd682b 556 __hc32 type = 0;
1da177e4
LT		 557
558 /* skip the iso nodes at list head */
559 while (here.ptr) {
6dbd682b
SR		 560 type = Q_NEXT_TYPE(ehci, *hw_p);
561 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1da177e4 562 break;
6dbd682b 563 prev = periodic_next_shadow(ehci, prev, type);
3807e26d 564 hw_p = shadow_next_periodic(ehci, &here, type);
1da177e4
LT		 565 here = *prev;
566 }
567
568 /* sorting each branch by period (slow-->fast)
569 * enables sharing interior tree nodes
570 */
571 while (here.ptr && qh != here.qh) {
572 if (qh->period > here.qh->period)
573 break;
574 prev = &here.qh->qh_next;
3807e26d 575 hw_p = &here.qh->hw->hw_next;
1da177e4
LT		 576 here = *prev;
577 }
578 /* link in this qh, unless some earlier pass did that */
579 if (qh != here.qh) {
580 qh->qh_next = here;
581 if (here.qh)
3807e26d 582 qh->hw->hw_next = *hw_p;
1da177e4
LT		 583 wmb ();
584 prev->qh = qh;
6dbd682b 585 *hw_p = QH_NEXT (ehci, qh->qh_dma);
1da177e4
LT		 586 }
587 }
588 qh->qh_state = QH_STATE_LINKED;
ef4638f9 589 qh->xacterrs = 0;
1da177e4
LT		 590 qh_get (qh);
591
592 /* update per-qh bandwidth for usbfs */
593 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
594 ? ((qh->usecs + qh->c_usecs) / qh->period)
595 : (qh->usecs * 8);
596
597 /* maybe enable periodic schedule processing */
01c17142 598 return enable_periodic(ehci);
1da177e4
LT		 599}
600
01c17142 601static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
1da177e4
LT		 602{
603 unsigned i;
604 unsigned period;
605
606 // FIXME:
607 // IF this isn't high speed
608 // and this qh is active in the current uframe
609 // (and overlay token SplitXstate is false?)
610 // THEN
551509d2 611 // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
1da177e4
LT		 612
613 /* high bandwidth, or otherwise part of every microframe */
614 if ((period = qh->period) == 0)
615 period = 1;
616
617 for (i = qh->start; i < ehci->periodic_size; i += period)
618 periodic_unlink (ehci, i, qh);
619
620 /* update per-qh bandwidth for usbfs */
621 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
622 ? ((qh->usecs + qh->c_usecs) / qh->period)
623 : (qh->usecs * 8);
624
625 dev_dbg (&qh->dev->dev,
626 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
7dedacf4 627 qh->period,
3807e26d 628 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
1da177e4
LT		 629 qh, qh->start, qh->usecs, qh->c_usecs);
630
631 /* qh->qh_next still "live" to HC */
632 qh->qh_state = QH_STATE_UNLINK;
633 qh->qh_next.ptr = NULL;
634 qh_put (qh);
635
636 /* maybe turn off periodic schedule */
01c17142 637 return disable_periodic(ehci);
1da177e4
LT		 638}
639
640static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
641{
a448c9d8
AS		 642 unsigned wait;
643 struct ehci_qh_hw *hw = qh->hw;
644 int rc;
645
646 /* If the QH isn't linked then there's nothing we can do
647 * unless we were called during a giveback, in which case
648 * qh_completions() has to deal with it.
649 */
650 if (qh->qh_state != QH_STATE_LINKED) {
651 if (qh->qh_state == QH_STATE_COMPLETING)
652 qh->needs_rescan = 1;
653 return;
654 }
1da177e4
LT		 655
656 qh_unlink_periodic (ehci, qh);
657
658 /* simple/paranoid: always delay, expecting the HC needs to read
659 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
660 * expect khubd to clean up after any CSPLITs we won't issue.
661 * active high speed queues may need bigger delays...
662 */
663 if (list_empty (&qh->qtd_list)
6dbd682b 664 || (cpu_to_hc32(ehci, QH_CMASK)
3807e26d 665 & hw->hw_info2) != 0)
1da177e4
LT		 666 wait = 2;
667 else
668 wait = 55; /* worst case: 3 * 1024 */
669
670 udelay (wait);
671 qh->qh_state = QH_STATE_IDLE;
3807e26d 672 hw->hw_next = EHCI_LIST_END(ehci);
1da177e4 673 wmb ();
a448c9d8
AS		 674
675 qh_completions(ehci, qh);
676
677 /* reschedule QH iff another request is queued */
678 if (!list_empty(&qh->qtd_list) &&
e8799906 679 ehci->rh_state == EHCI_RH_RUNNING) {
a448c9d8
AS		 680 rc = qh_schedule(ehci, qh);
681
682 /* An error here likely indicates handshake failure
683 * or no space left in the schedule. Neither fault
684 * should happen often ...
685 *
686 * FIXME kill the now-dysfunctional queued urbs
687 */
688 if (rc != 0)
689 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
690 qh, rc);
691 }
1da177e4
LT		 692}
693
694/*-------------------------------------------------------------------------*/
695
696static int check_period (
53bd6a60 697 struct ehci_hcd *ehci,
1da177e4
LT		 698 unsigned frame,
699 unsigned uframe,
700 unsigned period,
701 unsigned usecs
702) {
703 int claimed;
704
705 /* complete split running into next frame?
706 * given FSTN support, we could sometimes check...
707 */
708 if (uframe >= 8)
709 return 0;
710
cc62a7eb
KS		 711 /* convert "usecs we need" to "max already claimed" */
712 usecs = ehci->uframe_periodic_max - usecs;
1da177e4
LT		 713
714 /* we "know" 2 and 4 uframe intervals were rejected; so
715 * for period 0, check _every_ microframe in the schedule.
716 */
717 if (unlikely (period == 0)) {
718 do {
719 for (uframe = 0; uframe < 7; uframe++) {
720 claimed = periodic_usecs (ehci, frame, uframe);
721 if (claimed > usecs)
722 return 0;
723 }
724 } while ((frame += 1) < ehci->periodic_size);
725
726 /* just check the specified uframe, at that period */
727 } else {
728 do {
729 claimed = periodic_usecs (ehci, frame, uframe);
730 if (claimed > usecs)
731 return 0;
732 } while ((frame += period) < ehci->periodic_size);
733 }
734
735 // success!
736 return 1;
737}
738
739static int check_intr_schedule (
53bd6a60 740 struct ehci_hcd *ehci,
1da177e4
LT		 741 unsigned frame,
742 unsigned uframe,
743 const struct ehci_qh *qh,
6dbd682b 744 __hc32 *c_maskp
1da177e4
LT		 745)
746{
53bd6a60 747 int retval = -ENOSPC;
ba47f66b 748 u8 mask = 0;
1da177e4
LT		 749
750 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
751 goto done;
752
753 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
754 goto done;
755 if (!qh->c_usecs) {
756 retval = 0;
757 *c_maskp = 0;
758 goto done;
759 }
760
ba47f66b
DS		 761#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
762 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
763 qh->tt_usecs)) {
764 unsigned i;
765
766 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
767 for (i=uframe+1; i<8 && i<uframe+4; i++)
768 if (!check_period (ehci, frame, i,
769 qh->period, qh->c_usecs))
770 goto done;
771 else
772 mask |= 1 << i;
773
774 retval = 0;
775
6dbd682b 776 *c_maskp = cpu_to_hc32(ehci, mask << 8);
ba47f66b
DS		 777 }
778#else
1da177e4
LT		 779 /* Make sure this tt's buffer is also available for CSPLITs.
780 * We pessimize a bit; probably the typical full speed case
781 * doesn't need the second CSPLIT.
53bd6a60 782 *
1da177e4
LT		 783 * NOTE: both SPLIT and CSPLIT could be checked in just
784 * one smart pass...
785 */
786 mask = 0x03 << (uframe + qh->gap_uf);
6dbd682b 787 *c_maskp = cpu_to_hc32(ehci, mask << 8);
1da177e4
LT		 788
789 mask |= 1 << uframe;
790 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
791 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
792 qh->period, qh->c_usecs))
793 goto done;
794 if (!check_period (ehci, frame, uframe + qh->gap_uf,
795 qh->period, qh->c_usecs))
796 goto done;
797 retval = 0;
798 }
ba47f66b 799#endif
1da177e4
LT		 800done:
801 return retval;
802}
803
804/* "first fit" scheduling policy used the first time through,
805 * or when the previous schedule slot can't be re-used.
806 */
6dbd682b 807static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
1da177e4 808{
53bd6a60 809 int status;
1da177e4 810 unsigned uframe;
6dbd682b 811 __hc32 c_mask;
1da177e4 812 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
3807e26d 813 struct ehci_qh_hw *hw = qh->hw;
1da177e4
LT		 814
815 qh_refresh(ehci, qh);
3807e26d 816 hw->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 817 frame = qh->start;
818
819 /* reuse the previous schedule slots, if we can */
820 if (frame < qh->period) {
3807e26d 821 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
1da177e4
LT		 822 status = check_intr_schedule (ehci, frame, --uframe,
823 qh, &c_mask);
824 } else {
825 uframe = 0;
826 c_mask = 0;
827 status = -ENOSPC;
828 }
829
830 /* else scan the schedule to find a group of slots such that all
831 * uframes have enough periodic bandwidth available.
832 */
833 if (status) {
834 /* "normal" case, uframing flexible except with splits */
835 if (qh->period) {
68335e81
AS		 836 int i;
837
838 for (i = qh->period; status && i > 0; --i) {
839 frame = ++ehci->random_frame % qh->period;
1da177e4
LT		 840 for (uframe = 0; uframe < 8; uframe++) {
841 status = check_intr_schedule (ehci,
842 frame, uframe, qh,
843 &c_mask);
844 if (status == 0)
845 break;
846 }
68335e81 847 }
1da177e4
LT		 848
849 /* qh->period == 0 means every uframe */
850 } else {
851 frame = 0;
852 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
853 }
854 if (status)
855 goto done;
856 qh->start = frame;
857
858 /* reset S-frame and (maybe) C-frame masks */
3807e26d
AD		 859 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
860 hw->hw_info2 |= qh->period
6dbd682b
SR		 861 ? cpu_to_hc32(ehci, 1 << uframe)
862 : cpu_to_hc32(ehci, QH_SMASK);
3807e26d 863 hw->hw_info2 |= c_mask;
1da177e4
LT		 864 } else
865 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
866
867 /* stuff into the periodic schedule */
53bd6a60 868 status = qh_link_periodic (ehci, qh);
1da177e4
LT		 869done:
870 return status;
871}
872
873static int intr_submit (
874 struct ehci_hcd *ehci,
1da177e4
LT		 875 struct urb *urb,
876 struct list_head *qtd_list,
55016f10 877 gfp_t mem_flags
1da177e4
LT		 878) {
879 unsigned epnum;
880 unsigned long flags;
881 struct ehci_qh *qh;
e9df41c5 882 int status;
1da177e4
LT		 883 struct list_head empty;
884
885 /* get endpoint and transfer/schedule data */
e9df41c5 886 epnum = urb->ep->desc.bEndpointAddress;
1da177e4
LT		 887
888 spin_lock_irqsave (&ehci->lock, flags);
889
541c7d43 890 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
8de98402 891 status = -ESHUTDOWN;
e9df41c5 892 goto done_not_linked;
8de98402 893 }
e9df41c5
AS		 894 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
895 if (unlikely(status))
896 goto done_not_linked;
8de98402 897
1da177e4
LT		 898 /* get qh and force any scheduling errors */
899 INIT_LIST_HEAD (&empty);
e9df41c5 900 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
1da177e4
LT		 901 if (qh == NULL) {
902 status = -ENOMEM;
903 goto done;
904 }
905 if (qh->qh_state == QH_STATE_IDLE) {
906 if ((status = qh_schedule (ehci, qh)) != 0)
907 goto done;
908 }
909
910 /* then queue the urb's tds to the qh */
e9df41c5 911 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
1da177e4
LT		 912 BUG_ON (qh == NULL);
913
914 /* ... update usbfs periodic stats */
915 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
916
917done:
e9df41c5
AS		 918 if (unlikely(status))
919 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
920done_not_linked:
1da177e4
LT		 921 spin_unlock_irqrestore (&ehci->lock, flags);
922 if (status)
923 qtd_list_free (ehci, urb, qtd_list);
924
925 return status;
926}
927
928/*-------------------------------------------------------------------------*/
929
930/* ehci_iso_stream ops work with both ITD and SITD */
931
932static struct ehci_iso_stream *
55016f10 933iso_stream_alloc (gfp_t mem_flags)
1da177e4
LT		 934{
935 struct ehci_iso_stream *stream;
936
7b842b6e 937 stream = kzalloc(sizeof *stream, mem_flags);
1da177e4 938 if (likely (stream != NULL)) {
1da177e4
LT		 939 INIT_LIST_HEAD(&stream->td_list);
940 INIT_LIST_HEAD(&stream->free_list);
941 stream->next_uframe = -1;
942 stream->refcount = 1;
943 }
944 return stream;
945}
946
947static void
948iso_stream_init (
949 struct ehci_hcd *ehci,
950 struct ehci_iso_stream *stream,
951 struct usb_device *dev,
952 int pipe,
953 unsigned interval
954)
955{
956 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
957
958 u32 buf1;
959 unsigned epnum, maxp;
960 int is_input;
961 long bandwidth;
962
963 /*
964 * this might be a "high bandwidth" highspeed endpoint,
965 * as encoded in the ep descriptor's wMaxPacket field
966 */
967 epnum = usb_pipeendpoint (pipe);
968 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
969 maxp = usb_maxpacket(dev, pipe, !is_input);
970 if (is_input) {
971 buf1 = (1 << 11);
972 } else {
973 buf1 = 0;
974 }
975
976 /* knows about ITD vs SITD */
977 if (dev->speed == USB_SPEED_HIGH) {
978 unsigned multi = hb_mult(maxp);
979
980 stream->highspeed = 1;
981
982 maxp = max_packet(maxp);
983 buf1 |= maxp;
984 maxp *= multi;
985
6dbd682b
SR		 986 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
987 stream->buf1 = cpu_to_hc32(ehci, buf1);
988 stream->buf2 = cpu_to_hc32(ehci, multi);
1da177e4
LT		 989
990 /* usbfs wants to report the average usecs per frame tied up
991 * when transfers on this endpoint are scheduled ...
992 */
993 stream->usecs = HS_USECS_ISO (maxp);
994 bandwidth = stream->usecs * 8;
372dd6e8 995 bandwidth /= interval;
1da177e4
LT		 996
997 } else {
998 u32 addr;
d0384200 999 int think_time;
469d0229 1000 int hs_transfers;
1da177e4
LT		 1001
1002 addr = dev->ttport << 24;
1003 if (!ehci_is_TDI(ehci)
1004 || (dev->tt->hub !=
1005 ehci_to_hcd(ehci)->self.root_hub))
1006 addr |= dev->tt->hub->devnum << 16;
1007 addr |= epnum << 8;
1008 addr |= dev->devnum;
1009 stream->usecs = HS_USECS_ISO (maxp);
d0384200 1010 think_time = dev->tt ? dev->tt->think_time : 0;
1011 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1012 dev->speed, is_input, 1, maxp));
469d0229 1013 hs_transfers = max (1u, (maxp + 187) / 188);
1da177e4
LT		 1014 if (is_input) {
1015 u32 tmp;
1016
1017 addr |= 1 << 31;
1018 stream->c_usecs = stream->usecs;
1019 stream->usecs = HS_USECS_ISO (1);
1020 stream->raw_mask = 1;
1021
469d0229
CL		 1022 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1023 tmp = (1 << (hs_transfers + 2)) - 1;
1024 stream->raw_mask |= tmp << (8 + 2);
1da177e4 1025 } else
469d0229 1026 stream->raw_mask = smask_out [hs_transfers - 1];
1da177e4 1027 bandwidth = stream->usecs + stream->c_usecs;
372dd6e8 1028 bandwidth /= interval << 3;
1da177e4
LT		 1029
1030 /* stream->splits gets created from raw_mask later */
6dbd682b 1031 stream->address = cpu_to_hc32(ehci, addr);
1da177e4
LT		 1032 }
1033 stream->bandwidth = bandwidth;
1034
1035 stream->udev = dev;
1036
1037 stream->bEndpointAddress = is_input | epnum;
1038 stream->interval = interval;
1039 stream->maxp = maxp;
1040}
1041
1042static void
1043iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1044{
1045 stream->refcount--;
1046
1047 /* free whenever just a dev->ep reference remains.
1048 * not like a QH -- no persistent state (toggle, halt)
1049 */
1050 if (stream->refcount == 1) {
1da177e4
LT		 1051 // BUG_ON (!list_empty(&stream->td_list));
1052
1053 while (!list_empty (&stream->free_list)) {
1054 struct list_head *entry;
1055
1056 entry = stream->free_list.next;
1057 list_del (entry);
1058
1059 /* knows about ITD vs SITD */
1060 if (stream->highspeed) {
1061 struct ehci_itd *itd;
1062
1063 itd = list_entry (entry, struct ehci_itd,
1064 itd_list);
1065 dma_pool_free (ehci->itd_pool, itd,
1066 itd->itd_dma);
1067 } else {
1068 struct ehci_sitd *sitd;
1069
1070 sitd = list_entry (entry, struct ehci_sitd,
1071 sitd_list);
1072 dma_pool_free (ehci->sitd_pool, sitd,
1073 sitd->sitd_dma);
1074 }
1075 }
1076
1da177e4 1077 stream->bEndpointAddress &= 0x0f;
9aa09d2f
KW		 1078 if (stream->ep)
1079 stream->ep->hcpriv = NULL;
1da177e4 1080
1da177e4
LT		 1081 kfree(stream);
1082 }
1083}
1084
1085static inline struct ehci_iso_stream *
1086iso_stream_get (struct ehci_iso_stream *stream)
1087{
1088 if (likely (stream != NULL))
1089 stream->refcount++;
1090 return stream;
1091}
1092
1093static struct ehci_iso_stream *
1094iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1095{
1096 unsigned epnum;
1097 struct ehci_iso_stream *stream;
1098 struct usb_host_endpoint *ep;
1099 unsigned long flags;
1100
1101 epnum = usb_pipeendpoint (urb->pipe);
1102 if (usb_pipein(urb->pipe))
1103 ep = urb->dev->ep_in[epnum];
1104 else
1105 ep = urb->dev->ep_out[epnum];
1106
1107 spin_lock_irqsave (&ehci->lock, flags);
1108 stream = ep->hcpriv;
1109
1110 if (unlikely (stream == NULL)) {
1111 stream = iso_stream_alloc(GFP_ATOMIC);
1112 if (likely (stream != NULL)) {
1113 /* dev->ep owns the initial refcount */
1114 ep->hcpriv = stream;
1115 stream->ep = ep;
1116 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1117 urb->interval);
1118 }
1119
1082f57a
CL		 1120 /* if dev->ep [epnum] is a QH, hw is set */
1121 } else if (unlikely (stream->hw != NULL)) {
1da177e4
LT		 1122 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1123 urb->dev->devpath, epnum,
1124 usb_pipein(urb->pipe) ? "in" : "out");
1125 stream = NULL;
1126 }
1127
1128 /* caller guarantees an eventual matching iso_stream_put */
1129 stream = iso_stream_get (stream);
1130
1131 spin_unlock_irqrestore (&ehci->lock, flags);
1132 return stream;
1133}
1134
1135/*-------------------------------------------------------------------------*/
1136
1137/* ehci_iso_sched ops can be ITD-only or SITD-only */
1138
1139static struct ehci_iso_sched *
55016f10 1140iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1da177e4
LT		 1141{
1142 struct ehci_iso_sched *iso_sched;
1143 int size = sizeof *iso_sched;
1144
1145 size += packets * sizeof (struct ehci_iso_packet);
80b6ca48 1146 iso_sched = kzalloc(size, mem_flags);
1da177e4 1147 if (likely (iso_sched != NULL)) {
1da177e4
LT		 1148 INIT_LIST_HEAD (&iso_sched->td_list);
1149 }
1150 return iso_sched;
1151}
1152
1153static inline void
6dbd682b
SR		 1154itd_sched_init(
1155 struct ehci_hcd *ehci,
1da177e4
LT		 1156 struct ehci_iso_sched *iso_sched,
1157 struct ehci_iso_stream *stream,
1158 struct urb *urb
1159)
1160{
1161 unsigned i;
1162 dma_addr_t dma = urb->transfer_dma;
1163
1164 /* how many uframes are needed for these transfers */
1165 iso_sched->span = urb->number_of_packets * stream->interval;
1166
1167 /* figure out per-uframe itd fields that we'll need later
1168 * when we fit new itds into the schedule.
1169 */
1170 for (i = 0; i < urb->number_of_packets; i++) {
1171 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1172 unsigned length;
1173 dma_addr_t buf;
1174 u32 trans;
1175
1176 length = urb->iso_frame_desc [i].length;
1177 buf = dma + urb->iso_frame_desc [i].offset;
1178
1179 trans = EHCI_ISOC_ACTIVE;
1180 trans |= buf & 0x0fff;
1181 if (unlikely (((i + 1) == urb->number_of_packets))
1182 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1183 trans |= EHCI_ITD_IOC;
1184 trans |= length << 16;
6dbd682b 1185 uframe->transaction = cpu_to_hc32(ehci, trans);
1da177e4 1186
77078570 1187 /* might need to cross a buffer page within a uframe */
1da177e4
LT		 1188 uframe->bufp = (buf & ~(u64)0x0fff);
1189 buf += length;
1190 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1191 uframe->cross = 1;
1192 }
1193}
1194
1195static void
1196iso_sched_free (
1197 struct ehci_iso_stream *stream,
1198 struct ehci_iso_sched *iso_sched
1199)
1200{
1201 if (!iso_sched)
1202 return;
1203 // caller must hold ehci->lock!
1204 list_splice (&iso_sched->td_list, &stream->free_list);
1205 kfree (iso_sched);
1206}
1207
1208static int
1209itd_urb_transaction (
1210 struct ehci_iso_stream *stream,
1211 struct ehci_hcd *ehci,
1212 struct urb *urb,
55016f10 1213 gfp_t mem_flags
1da177e4
LT		 1214)
1215{
1216 struct ehci_itd *itd;
1217 dma_addr_t itd_dma;
1218 int i;
1219 unsigned num_itds;
1220 struct ehci_iso_sched *sched;
1221 unsigned long flags;
1222
1223 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1224 if (unlikely (sched == NULL))
1225 return -ENOMEM;
1226
6dbd682b 1227 itd_sched_init(ehci, sched, stream, urb);
1da177e4
LT		 1228
1229 if (urb->interval < 8)
1230 num_itds = 1 + (sched->span + 7) / 8;
1231 else
1232 num_itds = urb->number_of_packets;
1233
1234 /* allocate/init ITDs */
1235 spin_lock_irqsave (&ehci->lock, flags);
1236 for (i = 0; i < num_itds; i++) {
1237
1238 /* free_list.next might be cache-hot ... but maybe
1239 * the HC caches it too. avoid that issue for now.
1240 */
1241
1242 /* prefer previously-allocated itds */
1243 if (likely (!list_empty(&stream->free_list))) {
1244 itd = list_entry (stream->free_list.prev,
6dbd682b 1245 struct ehci_itd, itd_list);
1da177e4
LT		 1246 list_del (&itd->itd_list);
1247 itd_dma = itd->itd_dma;
3d01f0fe 1248 } else {
1da177e4
LT		 1249 spin_unlock_irqrestore (&ehci->lock, flags);
1250 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1251 &itd_dma);
1252 spin_lock_irqsave (&ehci->lock, flags);
3d01f0fe
KW		 1253 if (!itd) {
1254 iso_sched_free(stream, sched);
1255 spin_unlock_irqrestore(&ehci->lock, flags);
1256 return -ENOMEM;
1257 }
1da177e4
LT		 1258 }
1259
1da177e4
LT		 1260 memset (itd, 0, sizeof *itd);
1261 itd->itd_dma = itd_dma;
1262 list_add (&itd->itd_list, &sched->td_list);
1263 }
1264 spin_unlock_irqrestore (&ehci->lock, flags);
1265
1266 /* temporarily store schedule info in hcpriv */
1267 urb->hcpriv = sched;
1268 urb->error_count = 0;
1269 return 0;
1270}
1271
1272/*-------------------------------------------------------------------------*/
1273
1274static inline int
1275itd_slot_ok (
1276 struct ehci_hcd *ehci,
1277 u32 mod,
1278 u32 uframe,
1279 u8 usecs,
1280 u32 period
1281)
1282{
1283 uframe %= period;
1284 do {
cc62a7eb 1285 /* can't commit more than uframe_periodic_max usec */
1da177e4 1286 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
cc62a7eb 1287 > (ehci->uframe_periodic_max - usecs))
1da177e4
LT		 1288 return 0;
1289
1290 /* we know urb->interval is 2^N uframes */
1291 uframe += period;
1292 } while (uframe < mod);
1293 return 1;
1294}
1295
1296static inline int
1297sitd_slot_ok (
1298 struct ehci_hcd *ehci,
1299 u32 mod,
1300 struct ehci_iso_stream *stream,
1301 u32 uframe,
1302 struct ehci_iso_sched *sched,
1303 u32 period_uframes
1304)
1305{
1306 u32 mask, tmp;
1307 u32 frame, uf;
1308
1309 mask = stream->raw_mask << (uframe & 7);
1310
1311 /* for IN, don't wrap CSPLIT into the next frame */
1312 if (mask & ~0xffff)
1313 return 0;
1314
1315 /* this multi-pass logic is simple, but performance may
1316 * suffer when the schedule data isn't cached.
1317 */
1318
1319 /* check bandwidth */
1320 uframe %= period_uframes;
1321 do {
1322 u32 max_used;
1323
1324 frame = uframe >> 3;
1325 uf = uframe & 7;
1326
ba47f66b
DS		 1327#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1328 /* The tt's fullspeed bus bandwidth must be available.
1329 * tt_available scheduling guarantees 10+% for control/bulk.
1330 */
1331 if (!tt_available (ehci, period_uframes << 3,
1332 stream->udev, frame, uf, stream->tt_usecs))
1333 return 0;
1334#else
1da177e4
LT		 1335 /* tt must be idle for start(s), any gap, and csplit.
1336 * assume scheduling slop leaves 10+% for control/bulk.
1337 */
1338 if (!tt_no_collision (ehci, period_uframes << 3,
1339 stream->udev, frame, mask))
1340 return 0;
ba47f66b 1341#endif
1da177e4
LT		 1342
1343 /* check starts (OUT uses more than one) */
cc62a7eb 1344 max_used = ehci->uframe_periodic_max - stream->usecs;
1da177e4
LT		 1345 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1346 if (periodic_usecs (ehci, frame, uf) > max_used)
1347 return 0;
1348 }
1349
1350 /* for IN, check CSPLIT */
1351 if (stream->c_usecs) {
0c734622 1352 uf = uframe & 7;
cc62a7eb 1353 max_used = ehci->uframe_periodic_max - stream->c_usecs;
1da177e4
LT		 1354 do {
1355 tmp = 1 << uf;
1356 tmp <<= 8;
1357 if ((stream->raw_mask & tmp) == 0)
1358 continue;
1359 if (periodic_usecs (ehci, frame, uf)
1360 > max_used)
1361 return 0;
1362 } while (++uf < 8);
1363 }
1364
1365 /* we know urb->interval is 2^N uframes */
1366 uframe += period_uframes;
1367 } while (uframe < mod);
1368
6dbd682b 1369 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1da177e4
LT		 1370 return 1;
1371}
1372
1373/*
1374 * This scheduler plans almost as far into the future as it has actual
1375 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1376 * "as small as possible" to be cache-friendlier.) That limits the size
1377 * transfers you can stream reliably; avoid more than 64 msec per urb.
1378 * Also avoid queue depths of less than ehci's worst irq latency (affected
1379 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1380 * and other factors); or more than about 230 msec total (for portability,
1381 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1382 */
1383
d7e055f1 1384#define SCHEDULE_SLOP 80 /* microframes */
1da177e4
LT		 1385
1386static int
1387iso_stream_schedule (
1388 struct ehci_hcd *ehci,
1389 struct urb *urb,
1390 struct ehci_iso_stream *stream
1391)
1392{
ffda0803 1393 u32 now, next, start, period, span;
1da177e4
LT		 1394 int status;
1395 unsigned mod = ehci->periodic_size << 3;
1396 struct ehci_iso_sched *sched = urb->hcpriv;
1397
ffda0803
AS		 1398 period = urb->interval;
1399 span = sched->span;
1400 if (!stream->highspeed) {
1401 period <<= 3;
1402 span <<= 3;
1403 }
1404
1405 if (span > mod - SCHEDULE_SLOP) {
1da177e4
LT		 1406 ehci_dbg (ehci, "iso request %p too long\n", urb);
1407 status = -EFBIG;
1408 goto fail;
1409 }
1410
bccbefaa 1411 now = ehci_readl(ehci, &ehci->regs->frame_index) & (mod - 1);
1da177e4 1412
b40e43fc
AS		 1413 /* Typical case: reuse current schedule, stream is still active.
1414 * Hopefully there are no gaps from the host falling behind
1415 * (irq delays etc), but if there are we'll take the next
1416 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1da177e4
LT		 1417 */
1418 if (likely (!list_empty (&stream->td_list))) {
1fb2e055 1419 u32 excess;
dccd574c
SS		 1420
1421 /* For high speed devices, allow scheduling within the
ae68a83b
AS		 1422 * isochronous scheduling threshold. For full speed devices
1423 * and Intel PCI-based controllers, don't (work around for
1424 * Intel ICH9 bug).
dccd574c 1425 */
ae68a83b 1426 if (!stream->highspeed && ehci->fs_i_thresh)
dccd574c
SS		 1427 next = now + ehci->i_thresh;
1428 else
1429 next = now;
b40e43fc 1430
1fb2e055
AS		 1431 /* Fell behind (by up to twice the slop amount)?
1432 * We decide based on the time of the last currently-scheduled
1433 * slot, not the time of the next available slot.
1434 */
1435 excess = (stream->next_uframe - period - next) & (mod - 1);
1436 if (excess >= mod - 2 * SCHEDULE_SLOP)
1437 start = next + excess - mod + period *
1438 DIV_ROUND_UP(mod - excess, period);
1439 else
1440 start = next + excess + period;
1441 if (start - now >= mod) {
1442 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1443 urb, start - now - period, period,
1444 mod);
b40e43fc
AS		 1445 status = -EFBIG;
1446 goto fail;
1447 }
1da177e4
LT		 1448 }
1449
1450 /* need to schedule; when's the next (u)frame we could start?
1451 * this is bigger than ehci->i_thresh allows; scheduling itself
1452 * isn't free, the slop should handle reasonably slow cpus. it
1453 * can also help high bandwidth if the dma and irq loads don't
1454 * jump until after the queue is primed.
1455 */
1fb2e055
AS		 1456 else {
1457 start = SCHEDULE_SLOP + (now & ~0x07);
1458
1459 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1460
1461 /* find a uframe slot with enough bandwidth */
1462 next = start + period;
1463 for (; start < next; start++) {
1464
1465 /* check schedule: enough space? */
1466 if (stream->highspeed) {
1467 if (itd_slot_ok(ehci, mod, start,
1468 stream->usecs, period))
1469 break;
1470 } else {
1471 if ((start % 8) >= 6)
1472 continue;
1473 if (sitd_slot_ok(ehci, mod, stream,
1474 start, sched, period))
1475 break;
1476 }
1da177e4
LT		 1477 }
1478
1fb2e055
AS		 1479 /* no room in the schedule */
1480 if (start == next) {
1481 ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n",
1482 urb, now, now + mod);
1483 status = -ENOSPC;
1484 goto fail;
1da177e4
LT		 1485 }
1486 }
1487
1fb2e055
AS		 1488 /* Tried to schedule too far into the future? */
1489 if (unlikely(start - now + span - period
1490 >= mod - 2 * SCHEDULE_SLOP)) {
1491 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1492 urb, start - now, span - period,
1493 mod - 2 * SCHEDULE_SLOP);
1494 status = -EFBIG;
1495 goto fail;
1496 }
1da177e4 1497
1fb2e055 1498 stream->next_uframe = start & (mod - 1);
1da177e4 1499
1da177e4
LT		 1500 /* report high speed start in uframes; full speed, in frames */
1501 urb->start_frame = stream->next_uframe;
1502 if (!stream->highspeed)
1503 urb->start_frame >>= 3;
1504 return 0;
1fb2e055
AS		 1505
1506 fail:
1507 iso_sched_free(stream, sched);
1508 urb->hcpriv = NULL;
1509 return status;
1da177e4
LT		 1510}
1511
1512/*-------------------------------------------------------------------------*/
1513
1514static inline void
6dbd682b
SR		 1515itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1516 struct ehci_itd *itd)
1da177e4
LT		 1517{
1518 int i;
1519
77078570 1520 /* it's been recently zeroed */
6dbd682b 1521 itd->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 1522 itd->hw_bufp [0] = stream->buf0;
1523 itd->hw_bufp [1] = stream->buf1;
1524 itd->hw_bufp [2] = stream->buf2;
1525
1526 for (i = 0; i < 8; i++)
1527 itd->index[i] = -1;
1528
1529 /* All other fields are filled when scheduling */
1530}
1531
1532static inline void
6dbd682b
SR		 1533itd_patch(
1534 struct ehci_hcd *ehci,
1da177e4
LT		 1535 struct ehci_itd *itd,
1536 struct ehci_iso_sched *iso_sched,
1537 unsigned index,
77078570 1538 u16 uframe
1da177e4
LT		 1539)
1540{
1541 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1542 unsigned pg = itd->pg;
1543
1544 // BUG_ON (pg == 6 && uf->cross);
1545
1546 uframe &= 0x07;
1547 itd->index [uframe] = index;
1548
6dbd682b
SR		 1549 itd->hw_transaction[uframe] = uf->transaction;
1550 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1551 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1552 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1da177e4
LT		 1553
1554 /* iso_frame_desc[].offset must be strictly increasing */
77078570 1555 if (unlikely (uf->cross)) {
1da177e4 1556 u64 bufp = uf->bufp + 4096;
6dbd682b 1557
1da177e4 1558 itd->pg = ++pg;
6dbd682b
SR		 1559 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1560 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1da177e4
LT		 1561 }
1562}
1563
1564static inline void
1565itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1566{
92bc3648
CL		 1567 union ehci_shadow *prev = &ehci->pshadow[frame];
1568 __hc32 *hw_p = &ehci->periodic[frame];
1569 union ehci_shadow here = *prev;
1570 __hc32 type = 0;
1571
1572 /* skip any iso nodes which might belong to previous microframes */
1573 while (here.ptr) {
1574 type = Q_NEXT_TYPE(ehci, *hw_p);
1575 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1576 break;
1577 prev = periodic_next_shadow(ehci, prev, type);
1578 hw_p = shadow_next_periodic(ehci, &here, type);
1579 here = *prev;
1580 }
1581
1582 itd->itd_next = here;
1583 itd->hw_next = *hw_p;
1584 prev->itd = itd;
1da177e4
LT		 1585 itd->frame = frame;
1586 wmb ();
92bc3648 1587 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1da177e4
LT		 1588}
1589
1590/* fit urb's itds into the selected schedule slot; activate as needed */
1591static int
1592itd_link_urb (
1593 struct ehci_hcd *ehci,
1594 struct urb *urb,
1595 unsigned mod,
1596 struct ehci_iso_stream *stream
1597)
1598{
77078570 1599 int packet;
1da177e4
LT		 1600 unsigned next_uframe, uframe, frame;
1601 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1602 struct ehci_itd *itd;
1603
bccbefaa 1604 next_uframe = stream->next_uframe & (mod - 1);
1da177e4
LT		 1605
1606 if (unlikely (list_empty(&stream->td_list))) {
1607 ehci_to_hcd(ehci)->self.bandwidth_allocated
1608 += stream->bandwidth;
1609 ehci_vdbg (ehci,
1610 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1611 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1612 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1613 urb->interval,
1614 next_uframe >> 3, next_uframe & 0x7);
1da177e4 1615 }
05570297
AH		 1616
1617 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
ad93562b
AX		 1618 if (ehci->amd_pll_fix == 1)
1619 usb_amd_quirk_pll_disable();
05570297
AH		 1620 }
1621
1da177e4
LT		 1622 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1623
1624 /* fill iTDs uframe by uframe */
1625 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1626 if (itd == NULL) {
1627 /* ASSERT: we have all necessary itds */
1628 // BUG_ON (list_empty (&iso_sched->td_list));
1629
1630 /* ASSERT: no itds for this endpoint in this uframe */
1631
1632 itd = list_entry (iso_sched->td_list.next,
1633 struct ehci_itd, itd_list);
1634 list_move_tail (&itd->itd_list, &stream->td_list);
1635 itd->stream = iso_stream_get (stream);
508db8c9 1636 itd->urb = urb;
6dbd682b 1637 itd_init (ehci, stream, itd);
1da177e4
LT		 1638 }
1639
1640 uframe = next_uframe & 0x07;
1641 frame = next_uframe >> 3;
1642
6dbd682b 1643 itd_patch(ehci, itd, iso_sched, packet, uframe);
1da177e4
LT		 1644
1645 next_uframe += stream->interval;
bccbefaa 1646 next_uframe &= mod - 1;
1da177e4
LT		 1647 packet++;
1648
1649 /* link completed itds into the schedule */
1650 if (((next_uframe >> 3) != frame)
1651 || packet == urb->number_of_packets) {
bccbefaa 1652 itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1da177e4
LT		 1653 itd = NULL;
1654 }
1655 }
1656 stream->next_uframe = next_uframe;
1657
1658 /* don't need that schedule data any more */
1659 iso_sched_free (stream, iso_sched);
1660 urb->hcpriv = NULL;
1661
1662 timer_action (ehci, TIMER_IO_WATCHDOG);
01c17142 1663 return enable_periodic(ehci);
1da177e4
LT		 1664}
1665
1666#define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1667
30bf54e6
DB		 1668/* Process and recycle a completed ITD. Return true iff its urb completed,
1669 * and hence its completion callback probably added things to the hardware
1670 * schedule.
1671 *
1672 * Note that we carefully avoid recycling this descriptor until after any
1673 * completion callback runs, so that it won't be reused quickly. That is,
1674 * assuming (a) no more than two urbs per frame on this endpoint, and also
1675 * (b) only this endpoint's completions submit URBs. It seems some silicon
1676 * corrupts things if you reuse completed descriptors very quickly...
1677 */
1da177e4
LT		 1678static unsigned
1679itd_complete (
1680 struct ehci_hcd *ehci,
7d12e780 1681 struct ehci_itd *itd
1da177e4
LT		 1682) {
1683 struct urb *urb = itd->urb;
1684 struct usb_iso_packet_descriptor *desc;
1685 u32 t;
1686 unsigned uframe;
1687 int urb_index = -1;
1688 struct ehci_iso_stream *stream = itd->stream;
1689 struct usb_device *dev;
30bf54e6 1690 unsigned retval = false;
1da177e4
LT		 1691
1692 /* for each uframe with a packet */
1693 for (uframe = 0; uframe < 8; uframe++) {
1694 if (likely (itd->index[uframe] == -1))
1695 continue;
1696 urb_index = itd->index[uframe];
1697 desc = &urb->iso_frame_desc [urb_index];
1698
6dbd682b 1699 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1da177e4 1700 itd->hw_transaction [uframe] = 0;
1da177e4
LT		 1701
1702 /* report transfer status */
1703 if (unlikely (t & ISO_ERRS)) {
1704 urb->error_count++;
1705 if (t & EHCI_ISOC_BUF_ERR)
1706 desc->status = usb_pipein (urb->pipe)
1707 ? -ENOSR /* hc couldn't read */
1708 : -ECOMM; /* hc couldn't write */
1709 else if (t & EHCI_ISOC_BABBLE)
1710 desc->status = -EOVERFLOW;
1711 else /* (t & EHCI_ISOC_XACTERR) */
1712 desc->status = -EPROTO;
1713
1714 /* HC need not update length with this error */
ec6d67e3
AS		 1715 if (!(t & EHCI_ISOC_BABBLE)) {
1716 desc->actual_length = EHCI_ITD_LENGTH(t);
1717 urb->actual_length += desc->actual_length;
1718 }
1da177e4
LT		 1719 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1720 desc->status = 0;
ec6d67e3
AS		 1721 desc->actual_length = EHCI_ITD_LENGTH(t);
1722 urb->actual_length += desc->actual_length;
b40e43fc
AS		 1723 } else {
1724 /* URB was too late */
1725 desc->status = -EXDEV;
1da177e4
LT		 1726 }
1727 }
1728
1da177e4
LT		 1729 /* handle completion now? */
1730 if (likely ((urb_index + 1) != urb->number_of_packets))
30bf54e6 1731 goto done;
1da177e4
LT		 1732
1733 /* ASSERT: it's really the last itd for this urb
1734 list_for_each_entry (itd, &stream->td_list, itd_list)
1735 BUG_ON (itd->urb == urb);
1736 */
1737
aa16ca30 1738 /* give urb back to the driver; completion often (re)submits */
6a8e87b2 1739 dev = urb->dev;
14c04c0f 1740 ehci_urb_done(ehci, urb, 0);
30bf54e6 1741 retval = true;
1da177e4 1742 urb = NULL;
01c17142 1743 (void) disable_periodic(ehci);
1da177e4
LT		 1744 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1745
05570297 1746 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
ad93562b
AX		 1747 if (ehci->amd_pll_fix == 1)
1748 usb_amd_quirk_pll_enable();
05570297
AH		 1749 }
1750
508db8c9 1751 if (unlikely(list_is_singular(&stream->td_list))) {
1da177e4
LT		 1752 ehci_to_hcd(ehci)->self.bandwidth_allocated
1753 -= stream->bandwidth;
1754 ehci_vdbg (ehci,
1755 "deschedule devp %s ep%d%s-iso\n",
1756 dev->devpath, stream->bEndpointAddress & 0x0f,
1757 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1758 }
1759 iso_stream_put (ehci, stream);
9aa09d2f 1760
30bf54e6 1761done:
30bf54e6 1762 itd->urb = NULL;
9aa09d2f
KW		 1763 if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1764 /* OK to recycle this ITD now. */
1765 itd->stream = NULL;
1766 list_move(&itd->itd_list, &stream->free_list);
1767 iso_stream_put(ehci, stream);
1768 } else {
1769 /* HW might remember this ITD, so we can't recycle it yet.
1770 * Move it to a safe place until a new frame starts.
1771 */
1772 list_move(&itd->itd_list, &ehci->cached_itd_list);
1773 if (stream->refcount == 2) {
1774 /* If iso_stream_put() were called here, stream
1775 * would be freed. Instead, just prevent reuse.
1776 */
1777 stream->ep->hcpriv = NULL;
1778 stream->ep = NULL;
1779 }
1780 }
30bf54e6 1781 return retval;
1da177e4
LT		 1782}
1783
1784/*-------------------------------------------------------------------------*/
1785
5db539e4 1786static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
55016f10 1787 gfp_t mem_flags)
1da177e4
LT		 1788{
1789 int status = -EINVAL;
1790 unsigned long flags;
1791 struct ehci_iso_stream *stream;
1792
1793 /* Get iso_stream head */
1794 stream = iso_stream_find (ehci, urb);
1795 if (unlikely (stream == NULL)) {
1796 ehci_dbg (ehci, "can't get iso stream\n");
1797 return -ENOMEM;
1798 }
1799 if (unlikely (urb->interval != stream->interval)) {
1800 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1801 stream->interval, urb->interval);
1802 goto done;
1803 }
1804
1805#ifdef EHCI_URB_TRACE
1806 ehci_dbg (ehci,
1807 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
441b62c1 1808 __func__, urb->dev->devpath, urb,
1da177e4
LT		 1809 usb_pipeendpoint (urb->pipe),
1810 usb_pipein (urb->pipe) ? "in" : "out",
1811 urb->transfer_buffer_length,
1812 urb->number_of_packets, urb->interval,
1813 stream);
1814#endif
1815
1816 /* allocate ITDs w/o locking anything */
1817 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1818 if (unlikely (status < 0)) {
1819 ehci_dbg (ehci, "can't init itds\n");
1820 goto done;
1821 }
1822
1823 /* schedule ... need to lock */
1824 spin_lock_irqsave (&ehci->lock, flags);
541c7d43 1825 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
8de98402 1826 status = -ESHUTDOWN;
e9df41c5
AS		 1827 goto done_not_linked;
1828 }
1829 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1830 if (unlikely(status))
1831 goto done_not_linked;
1832 status = iso_stream_schedule(ehci, urb, stream);
53bd6a60 1833 if (likely (status == 0))
1da177e4 1834 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
e9df41c5
AS		 1835 else
1836 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1837done_not_linked:
1da177e4
LT		 1838 spin_unlock_irqrestore (&ehci->lock, flags);
1839
1840done:
1841 if (unlikely (status < 0))
1842 iso_stream_put (ehci, stream);
1843 return status;
1844}
1845
1da177e4
LT		 1846/*-------------------------------------------------------------------------*/
1847
1848/*
1849 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1850 * TTs in USB 2.0 hubs. These need microframe scheduling.
1851 */
1852
1853static inline void
6dbd682b
SR		 1854sitd_sched_init(
1855 struct ehci_hcd *ehci,
1da177e4
LT		 1856 struct ehci_iso_sched *iso_sched,
1857 struct ehci_iso_stream *stream,
1858 struct urb *urb
1859)
1860{
1861 unsigned i;
1862 dma_addr_t dma = urb->transfer_dma;
1863
1864 /* how many frames are needed for these transfers */
1865 iso_sched->span = urb->number_of_packets * stream->interval;
1866
1867 /* figure out per-frame sitd fields that we'll need later
1868 * when we fit new sitds into the schedule.
1869 */
1870 for (i = 0; i < urb->number_of_packets; i++) {
1871 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1872 unsigned length;
1873 dma_addr_t buf;
1874 u32 trans;
1875
1876 length = urb->iso_frame_desc [i].length & 0x03ff;
1877 buf = dma + urb->iso_frame_desc [i].offset;
1878
1879 trans = SITD_STS_ACTIVE;
1880 if (((i + 1) == urb->number_of_packets)
1881 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1882 trans |= SITD_IOC;
1883 trans |= length << 16;
6dbd682b 1884 packet->transaction = cpu_to_hc32(ehci, trans);
1da177e4
LT		 1885
1886 /* might need to cross a buffer page within a td */
1887 packet->bufp = buf;
1888 packet->buf1 = (buf + length) & ~0x0fff;
1889 if (packet->buf1 != (buf & ~(u64)0x0fff))
1890 packet->cross = 1;
1891
53bd6a60 1892 /* OUT uses multiple start-splits */
1da177e4
LT		 1893 if (stream->bEndpointAddress & USB_DIR_IN)
1894 continue;
1895 length = (length + 187) / 188;
1896 if (length > 1) /* BEGIN vs ALL */
1897 length |= 1 << 3;
1898 packet->buf1 |= length;
1899 }
1900}
1901
1902static int
1903sitd_urb_transaction (
1904 struct ehci_iso_stream *stream,
1905 struct ehci_hcd *ehci,
1906 struct urb *urb,
55016f10 1907 gfp_t mem_flags
1da177e4
LT		 1908)
1909{
1910 struct ehci_sitd *sitd;
1911 dma_addr_t sitd_dma;
1912 int i;
1913 struct ehci_iso_sched *iso_sched;
1914 unsigned long flags;
1915
1916 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1917 if (iso_sched == NULL)
1918 return -ENOMEM;
1919
6dbd682b 1920 sitd_sched_init(ehci, iso_sched, stream, urb);
1da177e4
LT		 1921
1922 /* allocate/init sITDs */
1923 spin_lock_irqsave (&ehci->lock, flags);
1924 for (i = 0; i < urb->number_of_packets; i++) {
1925
1926 /* NOTE: for now, we don't try to handle wraparound cases
1927 * for IN (using sitd->hw_backpointer, like a FSTN), which
1928 * means we never need two sitds for full speed packets.
1929 */
1930
1931 /* free_list.next might be cache-hot ... but maybe
1932 * the HC caches it too. avoid that issue for now.
1933 */
1934
1935 /* prefer previously-allocated sitds */
1936 if (!list_empty(&stream->free_list)) {
1937 sitd = list_entry (stream->free_list.prev,
1938 struct ehci_sitd, sitd_list);
1939 list_del (&sitd->sitd_list);
1940 sitd_dma = sitd->sitd_dma;
3d01f0fe 1941 } else {
1da177e4
LT		 1942 spin_unlock_irqrestore (&ehci->lock, flags);
1943 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1944 &sitd_dma);
1945 spin_lock_irqsave (&ehci->lock, flags);
3d01f0fe
KW		 1946 if (!sitd) {
1947 iso_sched_free(stream, iso_sched);
1948 spin_unlock_irqrestore(&ehci->lock, flags);
1949 return -ENOMEM;
1950 }
1da177e4
LT		 1951 }
1952
1da177e4
LT		 1953 memset (sitd, 0, sizeof *sitd);
1954 sitd->sitd_dma = sitd_dma;
1955 list_add (&sitd->sitd_list, &iso_sched->td_list);
1956 }
1957
1958 /* temporarily store schedule info in hcpriv */
1959 urb->hcpriv = iso_sched;
1960 urb->error_count = 0;
1961
1962 spin_unlock_irqrestore (&ehci->lock, flags);
1963 return 0;
1964}
1965
1966/*-------------------------------------------------------------------------*/
1967
1968static inline void
6dbd682b
SR		 1969sitd_patch(
1970 struct ehci_hcd *ehci,
1da177e4
LT		 1971 struct ehci_iso_stream *stream,
1972 struct ehci_sitd *sitd,
1973 struct ehci_iso_sched *iso_sched,
1974 unsigned index
1975)
1976{
1977 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1978 u64 bufp = uf->bufp;
1979
6dbd682b 1980 sitd->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 1981 sitd->hw_fullspeed_ep = stream->address;
1982 sitd->hw_uframe = stream->splits;
1983 sitd->hw_results = uf->transaction;
6dbd682b 1984 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1da177e4
LT		 1985
1986 bufp = uf->bufp;
6dbd682b
SR		 1987 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1988 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1da177e4 1989
6dbd682b 1990 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1da177e4
LT		 1991 if (uf->cross)
1992 bufp += 4096;
6dbd682b 1993 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1da177e4
LT		 1994 sitd->index = index;
1995}
1996
1997static inline void
1998sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1999{
2000 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
2001 sitd->sitd_next = ehci->pshadow [frame];
2002 sitd->hw_next = ehci->periodic [frame];
2003 ehci->pshadow [frame].sitd = sitd;
2004 sitd->frame = frame;
2005 wmb ();
6dbd682b 2006 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1da177e4
LT		 2007}
2008
2009/* fit urb's sitds into the selected schedule slot; activate as needed */
2010static int
2011sitd_link_urb (
2012 struct ehci_hcd *ehci,
2013 struct urb *urb,
2014 unsigned mod,
2015 struct ehci_iso_stream *stream
2016)
2017{
2018 int packet;
2019 unsigned next_uframe;
2020 struct ehci_iso_sched *sched = urb->hcpriv;
2021 struct ehci_sitd *sitd;
2022
2023 next_uframe = stream->next_uframe;
2024
2025 if (list_empty(&stream->td_list)) {
2026 /* usbfs ignores TT bandwidth */
2027 ehci_to_hcd(ehci)->self.bandwidth_allocated
2028 += stream->bandwidth;
2029 ehci_vdbg (ehci,
2030 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2031 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2032 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
bccbefaa 2033 (next_uframe >> 3) & (ehci->periodic_size - 1),
6dbd682b 2034 stream->interval, hc32_to_cpu(ehci, stream->splits));
1da177e4 2035 }
05570297
AH		 2036
2037 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
ad93562b
AX		 2038 if (ehci->amd_pll_fix == 1)
2039 usb_amd_quirk_pll_disable();
05570297
AH		 2040 }
2041
1da177e4
LT		 2042 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2043
2044 /* fill sITDs frame by frame */
2045 for (packet = 0, sitd = NULL;
2046 packet < urb->number_of_packets;
2047 packet++) {
2048
2049 /* ASSERT: we have all necessary sitds */
2050 BUG_ON (list_empty (&sched->td_list));
2051
2052 /* ASSERT: no itds for this endpoint in this frame */
2053
2054 sitd = list_entry (sched->td_list.next,
2055 struct ehci_sitd, sitd_list);
2056 list_move_tail (&sitd->sitd_list, &stream->td_list);
2057 sitd->stream = iso_stream_get (stream);
508db8c9 2058 sitd->urb = urb;
1da177e4 2059
6dbd682b 2060 sitd_patch(ehci, stream, sitd, sched, packet);
bccbefaa 2061 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
1da177e4
LT		 2062 sitd);
2063
2064 next_uframe += stream->interval << 3;
1da177e4 2065 }
bccbefaa 2066 stream->next_uframe = next_uframe & (mod - 1);
1da177e4
LT		 2067
2068 /* don't need that schedule data any more */
2069 iso_sched_free (stream, sched);
2070 urb->hcpriv = NULL;
2071
2072 timer_action (ehci, TIMER_IO_WATCHDOG);
01c17142 2073 return enable_periodic(ehci);
1da177e4
LT		 2074}
2075
2076/*-------------------------------------------------------------------------*/
2077
2078#define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
53bd6a60 2079 | SITD_STS_XACT | SITD_STS_MMF)
1da177e4 2080
30bf54e6
DB		 2081/* Process and recycle a completed SITD. Return true iff its urb completed,
2082 * and hence its completion callback probably added things to the hardware
2083 * schedule.
2084 *
2085 * Note that we carefully avoid recycling this descriptor until after any
2086 * completion callback runs, so that it won't be reused quickly. That is,
2087 * assuming (a) no more than two urbs per frame on this endpoint, and also
2088 * (b) only this endpoint's completions submit URBs. It seems some silicon
2089 * corrupts things if you reuse completed descriptors very quickly...
2090 */
1da177e4
LT		 2091static unsigned
2092sitd_complete (
2093 struct ehci_hcd *ehci,
7d12e780 2094 struct ehci_sitd *sitd
1da177e4
LT		 2095) {
2096 struct urb *urb = sitd->urb;
2097 struct usb_iso_packet_descriptor *desc;
2098 u32 t;
2099 int urb_index = -1;
2100 struct ehci_iso_stream *stream = sitd->stream;
2101 struct usb_device *dev;
30bf54e6 2102 unsigned retval = false;
1da177e4
LT		 2103
2104 urb_index = sitd->index;
2105 desc = &urb->iso_frame_desc [urb_index];
6dbd682b 2106 t = hc32_to_cpup(ehci, &sitd->hw_results);
1da177e4
LT		 2107
2108 /* report transfer status */
2109 if (t & SITD_ERRS) {
2110 urb->error_count++;
2111 if (t & SITD_STS_DBE)
2112 desc->status = usb_pipein (urb->pipe)
2113 ? -ENOSR /* hc couldn't read */
2114 : -ECOMM; /* hc couldn't write */
2115 else if (t & SITD_STS_BABBLE)
2116 desc->status = -EOVERFLOW;
2117 else /* XACT, MMF, etc */
2118 desc->status = -EPROTO;
2119 } else {
2120 desc->status = 0;
ec6d67e3
AS		 2121 desc->actual_length = desc->length - SITD_LENGTH(t);
2122 urb->actual_length += desc->actual_length;
1da177e4 2123 }
1da177e4
LT		 2124
2125 /* handle completion now? */
2126 if ((urb_index + 1) != urb->number_of_packets)
30bf54e6 2127 goto done;
1da177e4
LT		 2128
2129 /* ASSERT: it's really the last sitd for this urb
2130 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2131 BUG_ON (sitd->urb == urb);
2132 */
2133
aa16ca30 2134 /* give urb back to the driver; completion often (re)submits */
6a8e87b2 2135 dev = urb->dev;
14c04c0f 2136 ehci_urb_done(ehci, urb, 0);
30bf54e6 2137 retval = true;
1da177e4 2138 urb = NULL;
01c17142 2139 (void) disable_periodic(ehci);
1da177e4
LT		 2140 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2141
05570297 2142 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) {
ad93562b
AX		 2143 if (ehci->amd_pll_fix == 1)
2144 usb_amd_quirk_pll_enable();
05570297
AH		 2145 }
2146
508db8c9 2147 if (list_is_singular(&stream->td_list)) {
1da177e4
LT		 2148 ehci_to_hcd(ehci)->self.bandwidth_allocated
2149 -= stream->bandwidth;
2150 ehci_vdbg (ehci,
2151 "deschedule devp %s ep%d%s-iso\n",
2152 dev->devpath, stream->bEndpointAddress & 0x0f,
2153 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2154 }
2155 iso_stream_put (ehci, stream);
0e5f231b 2156
30bf54e6 2157done:
30bf54e6 2158 sitd->urb = NULL;
0e5f231b
AS		 2159 if (ehci->clock_frame != sitd->frame) {
2160 /* OK to recycle this SITD now. */
2161 sitd->stream = NULL;
2162 list_move(&sitd->sitd_list, &stream->free_list);
2163 iso_stream_put(ehci, stream);
2164 } else {
2165 /* HW might remember this SITD, so we can't recycle it yet.
2166 * Move it to a safe place until a new frame starts.
2167 */
2168 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2169 if (stream->refcount == 2) {
2170 /* If iso_stream_put() were called here, stream
2171 * would be freed. Instead, just prevent reuse.
2172 */
2173 stream->ep->hcpriv = NULL;
2174 stream->ep = NULL;
2175 }
2176 }
30bf54e6 2177 return retval;
1da177e4
LT		 2178}
2179
2180
5db539e4 2181static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
55016f10 2182 gfp_t mem_flags)
1da177e4
LT		 2183{
2184 int status = -EINVAL;
2185 unsigned long flags;
2186 struct ehci_iso_stream *stream;
2187
2188 /* Get iso_stream head */
2189 stream = iso_stream_find (ehci, urb);
2190 if (stream == NULL) {
2191 ehci_dbg (ehci, "can't get iso stream\n");
2192 return -ENOMEM;
2193 }
2194 if (urb->interval != stream->interval) {
2195 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2196 stream->interval, urb->interval);
2197 goto done;
2198 }
2199
2200#ifdef EHCI_URB_TRACE
2201 ehci_dbg (ehci,
2202 "submit %p dev%s ep%d%s-iso len %d\n",
2203 urb, urb->dev->devpath,
2204 usb_pipeendpoint (urb->pipe),
2205 usb_pipein (urb->pipe) ? "in" : "out",
2206 urb->transfer_buffer_length);
2207#endif
2208
2209 /* allocate SITDs */
2210 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2211 if (status < 0) {
2212 ehci_dbg (ehci, "can't init sitds\n");
2213 goto done;
2214 }
2215
2216 /* schedule ... need to lock */
2217 spin_lock_irqsave (&ehci->lock, flags);
541c7d43 2218 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
8de98402 2219 status = -ESHUTDOWN;
e9df41c5
AS		 2220 goto done_not_linked;
2221 }
2222 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2223 if (unlikely(status))
2224 goto done_not_linked;
2225 status = iso_stream_schedule(ehci, urb, stream);
53bd6a60 2226 if (status == 0)
1da177e4 2227 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
e9df41c5
AS		 2228 else
2229 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2230done_not_linked:
1da177e4
LT		 2231 spin_unlock_irqrestore (&ehci->lock, flags);
2232
2233done:
2234 if (status < 0)
2235 iso_stream_put (ehci, stream);
2236 return status;
2237}
2238
1da177e4
LT		 2239/*-------------------------------------------------------------------------*/
2240
0e5f231b 2241static void free_cached_lists(struct ehci_hcd *ehci)
9aa09d2f
KW		 2242{
2243 struct ehci_itd *itd, *n;
0e5f231b 2244 struct ehci_sitd *sitd, *sn;
9aa09d2f
KW		 2245
2246 list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2247 struct ehci_iso_stream *stream = itd->stream;
2248 itd->stream = NULL;
2249 list_move(&itd->itd_list, &stream->free_list);
2250 iso_stream_put(ehci, stream);
2251 }
0e5f231b
AS		 2252
2253 list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2254 struct ehci_iso_stream *stream = sitd->stream;
2255 sitd->stream = NULL;
2256 list_move(&sitd->sitd_list, &stream->free_list);
2257 iso_stream_put(ehci, stream);
2258 }
9aa09d2f
KW		 2259}
2260
2261/*-------------------------------------------------------------------------*/
2262
1da177e4 2263static void
7d12e780 2264scan_periodic (struct ehci_hcd *ehci)
1da177e4 2265{
b40e43fc 2266 unsigned now_uframe, frame, clock, clock_frame, mod;
1da177e4
LT		 2267 unsigned modified;
2268
2269 mod = ehci->periodic_size << 3;
2270
2271 /*
2272 * When running, scan from last scan point up to "now"
2273 * else clean up by scanning everything that's left.
2274 * Touches as few pages as possible: cache-friendly.
2275 */
2276 now_uframe = ehci->next_uframe;
e8799906 2277 if (ehci->rh_state == EHCI_RH_RUNNING) {
083522d7 2278 clock = ehci_readl(ehci, &ehci->regs->frame_index);
bccbefaa 2279 clock_frame = (clock >> 3) & (ehci->periodic_size - 1);
9aa09d2f 2280 } else {
1da177e4 2281 clock = now_uframe + mod - 1;
9aa09d2f
KW		 2282 clock_frame = -1;
2283 }
2284 if (ehci->clock_frame != clock_frame) {
0e5f231b 2285 free_cached_lists(ehci);
9aa09d2f
KW		 2286 ehci->clock_frame = clock_frame;
2287 }
bccbefaa 2288 clock &= mod - 1;
b40e43fc 2289 clock_frame = clock >> 3;
1e12c910 2290 ++ehci->periodic_stamp;
1da177e4
LT		 2291
2292 for (;;) {
2293 union ehci_shadow q, *q_p;
6dbd682b 2294 __hc32 type, *hw_p;
79592b72 2295 unsigned incomplete = false;
1da177e4 2296
1da177e4 2297 frame = now_uframe >> 3;
1da177e4
LT		 2298
2299restart:
2300 /* scan each element in frame's queue for completions */
2301 q_p = &ehci->pshadow [frame];
2302 hw_p = &ehci->periodic [frame];
2303 q.ptr = q_p->ptr;
6dbd682b 2304 type = Q_NEXT_TYPE(ehci, *hw_p);
1da177e4
LT		 2305 modified = 0;
2306
2307 while (q.ptr != NULL) {
2308 unsigned uf;
2309 union ehci_shadow temp;
2310 int live;
2311
e8799906 2312 live = (ehci->rh_state == EHCI_RH_RUNNING);
6dbd682b 2313 switch (hc32_to_cpu(ehci, type)) {
1da177e4
LT		 2314 case Q_TYPE_QH:
2315 /* handle any completions */
2316 temp.qh = qh_get (q.qh);
3807e26d 2317 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
1da177e4 2318 q = q.qh->qh_next;
1e12c910
AS		 2319 if (temp.qh->stamp != ehci->periodic_stamp) {
2320 modified = qh_completions(ehci, temp.qh);
2321 if (!modified)
2322 temp.qh->stamp = ehci->periodic_stamp;
2323 if (unlikely(list_empty(&temp.qh->qtd_list) ||
2324 temp.qh->needs_rescan))
2325 intr_deschedule(ehci, temp.qh);
2326 }
1da177e4
LT		 2327 qh_put (temp.qh);
2328 break;
2329 case Q_TYPE_FSTN:
2330 /* for "save place" FSTNs, look at QH entries
2331 * in the previous frame for completions.
2332 */
6dbd682b 2333 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
1da177e4
LT		 2334 dbg ("ignoring completions from FSTNs");
2335 }
6dbd682b 2336 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
1da177e4
LT		 2337 q = q.fstn->fstn_next;
2338 break;
2339 case Q_TYPE_ITD:
79592b72
DB		 2340 /* If this ITD is still active, leave it for
2341 * later processing ... check the next entry.
b40e43fc
AS		 2342 * No need to check for activity unless the
2343 * frame is current.
79592b72 2344 */
b40e43fc
AS		 2345 if (frame == clock_frame && live) {
2346 rmb();
2347 for (uf = 0; uf < 8; uf++) {
2348 if (q.itd->hw_transaction[uf] &
2349 ITD_ACTIVE(ehci))
2350 break;
2351 }
2352 if (uf < 8) {
2353 incomplete = true;
2354 q_p = &q.itd->itd_next;
2355 hw_p = &q.itd->hw_next;
2356 type = Q_NEXT_TYPE(ehci,
6dbd682b 2357 q.itd->hw_next);
b40e43fc
AS		 2358 q = *q_p;
2359 break;
2360 }
1da177e4 2361 }
1da177e4 2362
79592b72
DB		 2363 /* Take finished ITDs out of the schedule
2364 * and process them: recycle, maybe report
2365 * URB completion. HC won't cache the
1da177e4
LT		 2366 * pointer for much longer, if at all.
2367 */
2368 *q_p = q.itd->itd_next;
3d091a6f
AX		 2369 if (!ehci->use_dummy_qh ||
2370 q.itd->hw_next != EHCI_LIST_END(ehci))
2371 *hw_p = q.itd->hw_next;
2372 else
2373 *hw_p = ehci->dummy->qh_dma;
6dbd682b 2374 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
1da177e4 2375 wmb();
7d12e780 2376 modified = itd_complete (ehci, q.itd);
1da177e4
LT		 2377 q = *q_p;
2378 break;
2379 case Q_TYPE_SITD:
79592b72
DB		 2380 /* If this SITD is still active, leave it for
2381 * later processing ... check the next entry.
b40e43fc
AS		 2382 * No need to check for activity unless the
2383 * frame is current.
79592b72 2384 */
22e18694 2385 if (((frame == clock_frame) ||
bccbefaa 2386 (((frame + 1) & (ehci->periodic_size - 1))
22e18694
DE		 2387 == clock_frame))
2388 && live
2389 && (q.sitd->hw_results &
2390 SITD_ACTIVE(ehci))) {
2391
79592b72 2392 incomplete = true;
1da177e4
LT		 2393 q_p = &q.sitd->sitd_next;
2394 hw_p = &q.sitd->hw_next;
6dbd682b
SR		 2395 type = Q_NEXT_TYPE(ehci,
2396 q.sitd->hw_next);
1da177e4
LT		 2397 q = *q_p;
2398 break;
2399 }
79592b72
DB		 2400
2401 /* Take finished SITDs out of the schedule
2402 * and process them: recycle, maybe report
2403 * URB completion.
2404 */
1da177e4 2405 *q_p = q.sitd->sitd_next;
3d091a6f
AX		 2406 if (!ehci->use_dummy_qh ||
2407 q.sitd->hw_next != EHCI_LIST_END(ehci))
2408 *hw_p = q.sitd->hw_next;
2409 else
2410 *hw_p = ehci->dummy->qh_dma;
6dbd682b 2411 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
1da177e4 2412 wmb();
7d12e780 2413 modified = sitd_complete (ehci, q.sitd);
1da177e4
LT		 2414 q = *q_p;
2415 break;
2416 default:
2417 dbg ("corrupt type %d frame %d shadow %p",
2418 type, frame, q.ptr);
2419 // BUG ();
2420 q.ptr = NULL;
2421 }
2422
2423 /* assume completion callbacks modify the queue */
aa16ca30
DB		 2424 if (unlikely (modified)) {
2425 if (likely(ehci->periodic_sched > 0))
2426 goto restart;
01c17142 2427 /* short-circuit this scan */
aa16ca30
DB		 2428 now_uframe = clock;
2429 break;
2430 }
1da177e4
LT		 2431 }
2432
79592b72
DB		 2433 /* If we can tell we caught up to the hardware, stop now.
2434 * We can't advance our scan without collecting the ISO
2435 * transfers that are still pending in this frame.
2436 */
e8799906 2437 if (incomplete && ehci->rh_state == EHCI_RH_RUNNING) {
79592b72
DB		 2438 ehci->next_uframe = now_uframe;
2439 break;
2440 }
1da177e4
LT		 2441
2442 // FIXME: this assumes we won't get lapped when
2443 // latencies climb; that should be rare, but...
2444 // detect it, and just go all the way around.
2445 // FLR might help detect this case, so long as latencies
2446 // don't exceed periodic_size msec (default 1.024 sec).
2447
2448 // FIXME: likewise assumes HC doesn't halt mid-scan
2449
2450 if (now_uframe == clock) {
2451 unsigned now;
2452
e8799906 2453 if (ehci->rh_state != EHCI_RH_RUNNING
aa16ca30 2454 || ehci->periodic_sched == 0)
1da177e4
LT		 2455 break;
2456 ehci->next_uframe = now_uframe;
bccbefaa
AS		 2457 now = ehci_readl(ehci, &ehci->regs->frame_index) &
2458 (mod - 1);
1da177e4
LT		 2459 if (now_uframe == now)
2460 break;
2461
2462 /* rescan the rest of this frame, then ... */
2463 clock = now;
b40e43fc 2464 clock_frame = clock >> 3;
9aa09d2f 2465 if (ehci->clock_frame != clock_frame) {
0e5f231b 2466 free_cached_lists(ehci);
9aa09d2f 2467 ehci->clock_frame = clock_frame;
1e12c910 2468 ++ehci->periodic_stamp;
9aa09d2f 2469 }
1da177e4
LT		 2470 } else {
2471 now_uframe++;
bccbefaa 2472 now_uframe &= mod - 1;
1da177e4 2473 }
53bd6a60 2474 }
1da177e4 2475}
Linux kernel - Deliverables
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