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Merge commit 'v2.6.35' into kbuild/kconfig
[deliverable/linux.git] / drivers / usb / host / ehci-sched.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
53bd6a60 4 *
1da177e4
LT		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20/* this file is part of ehci-hcd.c */
21
22/*-------------------------------------------------------------------------*/
23
24/*
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
27 *
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
31 *
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
35 */
36
37static int ehci_get_frame (struct usb_hcd *hcd);
38
39/*-------------------------------------------------------------------------*/
40
41/*
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
45 */
46static union ehci_shadow *
6dbd682b
SR		 47periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
1da177e4 49{
6dbd682b 50 switch (hc32_to_cpu(ehci, tag)) {
1da177e4
LT		 51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
60 }
61}
62
3807e26d
AD		 63static __hc32 *
64shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
65 __hc32 tag)
66{
67 switch (hc32_to_cpu(ehci, tag)) {
68 /* our ehci_shadow.qh is actually software part */
69 case Q_TYPE_QH:
70 return &periodic->qh->hw->hw_next;
71 /* others are hw parts */
72 default:
73 return periodic->hw_next;
74 }
75}
76
1da177e4
LT		 77/* caller must hold ehci->lock */
78static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
79{
6dbd682b
SR		 80 union ehci_shadow *prev_p = &ehci->pshadow[frame];
81 __hc32 *hw_p = &ehci->periodic[frame];
1da177e4
LT		 82 union ehci_shadow here = *prev_p;
83
84 /* find predecessor of "ptr"; hw and shadow lists are in sync */
85 while (here.ptr && here.ptr != ptr) {
6dbd682b
SR		 86 prev_p = periodic_next_shadow(ehci, prev_p,
87 Q_NEXT_TYPE(ehci, *hw_p));
3807e26d
AD		 88 hw_p = shadow_next_periodic(ehci, &here,
89 Q_NEXT_TYPE(ehci, *hw_p));
1da177e4
LT		 90 here = *prev_p;
91 }
92 /* an interrupt entry (at list end) could have been shared */
93 if (!here.ptr)
94 return;
95
96 /* update shadow and hardware lists ... the old "next" pointers
97 * from ptr may still be in use, the caller updates them.
98 */
6dbd682b
SR		 99 *prev_p = *periodic_next_shadow(ehci, &here,
100 Q_NEXT_TYPE(ehci, *hw_p));
3807e26d 101 *hw_p = *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p));
1da177e4
LT		 102}
103
104/* how many of the uframe's 125 usecs are allocated? */
105static unsigned short
106periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
107{
6dbd682b 108 __hc32 *hw_p = &ehci->periodic [frame];
1da177e4
LT		 109 union ehci_shadow *q = &ehci->pshadow [frame];
110 unsigned usecs = 0;
3807e26d 111 struct ehci_qh_hw *hw;
1da177e4
LT		 112
113 while (q->ptr) {
6dbd682b 114 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
1da177e4 115 case Q_TYPE_QH:
3807e26d 116 hw = q->qh->hw;
1da177e4 117 /* is it in the S-mask? */
3807e26d 118 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
1da177e4
LT		 119 usecs += q->qh->usecs;
120 /* ... or C-mask? */
3807e26d 121 if (hw->hw_info2 & cpu_to_hc32(ehci,
6dbd682b 122 1 << (8 + uframe)))
1da177e4 123 usecs += q->qh->c_usecs;
3807e26d 124 hw_p = &hw->hw_next;
1da177e4
LT		 125 q = &q->qh->qh_next;
126 break;
127 // case Q_TYPE_FSTN:
128 default:
129 /* for "save place" FSTNs, count the relevant INTR
130 * bandwidth from the previous frame
131 */
6dbd682b 132 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
1da177e4
LT		 133 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
134 }
135 hw_p = &q->fstn->hw_next;
136 q = &q->fstn->fstn_next;
137 break;
138 case Q_TYPE_ITD:
3b6fcfd0
KW		 139 if (q->itd->hw_transaction[uframe])
140 usecs += q->itd->stream->usecs;
1da177e4
LT		 141 hw_p = &q->itd->hw_next;
142 q = &q->itd->itd_next;
143 break;
144 case Q_TYPE_SITD:
145 /* is it in the S-mask? (count SPLIT, DATA) */
6dbd682b
SR		 146 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
147 1 << uframe)) {
1da177e4 148 if (q->sitd->hw_fullspeed_ep &
6dbd682b 149 cpu_to_hc32(ehci, 1<<31))
1da177e4
LT		 150 usecs += q->sitd->stream->usecs;
151 else /* worst case for OUT start-split */
152 usecs += HS_USECS_ISO (188);
153 }
154
155 /* ... C-mask? (count CSPLIT, DATA) */
156 if (q->sitd->hw_uframe &
6dbd682b 157 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
1da177e4
LT		 158 /* worst case for IN complete-split */
159 usecs += q->sitd->stream->c_usecs;
160 }
161
162 hw_p = &q->sitd->hw_next;
163 q = &q->sitd->sitd_next;
164 break;
165 }
166 }
167#ifdef DEBUG
168 if (usecs > 100)
169 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
170 frame * 8 + uframe, usecs);
171#endif
172 return usecs;
173}
174
175/*-------------------------------------------------------------------------*/
176
177static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
178{
179 if (!dev1->tt || !dev2->tt)
180 return 0;
181 if (dev1->tt != dev2->tt)
182 return 0;
183 if (dev1->tt->multi)
184 return dev1->ttport == dev2->ttport;
185 else
186 return 1;
187}
188
ba47f66b
DS		 189#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
190
191/* Which uframe does the low/fullspeed transfer start in?
192 *
193 * The parameter is the mask of ssplits in "H-frame" terms
194 * and this returns the transfer start uframe in "B-frame" terms,
195 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
196 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
197 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
198 */
6dbd682b 199static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
ba47f66b 200{
6dbd682b 201 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
ba47f66b
DS		 202 if (!smask) {
203 ehci_err(ehci, "invalid empty smask!\n");
204 /* uframe 7 can't have bw so this will indicate failure */
205 return 7;
206 }
207 return ffs(smask) - 1;
208}
209
210static const unsigned char
211max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
212
213/* carryover low/fullspeed bandwidth that crosses uframe boundries */
214static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
215{
216 int i;
217 for (i=0; i<7; i++) {
218 if (max_tt_usecs[i] < tt_usecs[i]) {
219 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
220 tt_usecs[i] = max_tt_usecs[i];
221 }
222 }
223}
224
225/* How many of the tt's periodic downstream 1000 usecs are allocated?
226 *
227 * While this measures the bandwidth in terms of usecs/uframe,
228 * the low/fullspeed bus has no notion of uframes, so any particular
229 * low/fullspeed transfer can "carry over" from one uframe to the next,
230 * since the TT just performs downstream transfers in sequence.
231 *
dc0d5c1e 232 * For example two separate 100 usec transfers can start in the same uframe,
ba47f66b
DS		 233 * and the second one would "carry over" 75 usecs into the next uframe.
234 */
235static void
236periodic_tt_usecs (
237 struct ehci_hcd *ehci,
238 struct usb_device *dev,
239 unsigned frame,
240 unsigned short tt_usecs[8]
241)
242{
6dbd682b 243 __hc32 *hw_p = &ehci->periodic [frame];
ba47f66b
DS		 244 union ehci_shadow *q = &ehci->pshadow [frame];
245 unsigned char uf;
246
247 memset(tt_usecs, 0, 16);
248
249 while (q->ptr) {
6dbd682b 250 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
ba47f66b
DS		 251 case Q_TYPE_ITD:
252 hw_p = &q->itd->hw_next;
253 q = &q->itd->itd_next;
254 continue;
255 case Q_TYPE_QH:
256 if (same_tt(dev, q->qh->dev)) {
3807e26d 257 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
ba47f66b
DS		 258 tt_usecs[uf] += q->qh->tt_usecs;
259 }
3807e26d 260 hw_p = &q->qh->hw->hw_next;
ba47f66b
DS		 261 q = &q->qh->qh_next;
262 continue;
263 case Q_TYPE_SITD:
264 if (same_tt(dev, q->sitd->urb->dev)) {
265 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
266 tt_usecs[uf] += q->sitd->stream->tt_usecs;
267 }
268 hw_p = &q->sitd->hw_next;
269 q = &q->sitd->sitd_next;
270 continue;
271 // case Q_TYPE_FSTN:
272 default:
6dbd682b
SR		 273 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
274 frame);
ba47f66b
DS		 275 hw_p = &q->fstn->hw_next;
276 q = &q->fstn->fstn_next;
277 }
278 }
279
280 carryover_tt_bandwidth(tt_usecs);
281
282 if (max_tt_usecs[7] < tt_usecs[7])
283 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
284 frame, tt_usecs[7] - max_tt_usecs[7]);
285}
286
287/*
288 * Return true if the device's tt's downstream bus is available for a
289 * periodic transfer of the specified length (usecs), starting at the
290 * specified frame/uframe. Note that (as summarized in section 11.19
291 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
292 * uframe.
293 *
294 * The uframe parameter is when the fullspeed/lowspeed transfer
295 * should be executed in "B-frame" terms, which is the same as the
296 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
297 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
298 * See the EHCI spec sec 4.5 and fig 4.7.
299 *
300 * This checks if the full/lowspeed bus, at the specified starting uframe,
301 * has the specified bandwidth available, according to rules listed
302 * in USB 2.0 spec section 11.18.1 fig 11-60.
303 *
304 * This does not check if the transfer would exceed the max ssplit
305 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
306 * since proper scheduling limits ssplits to less than 16 per uframe.
307 */
308static int tt_available (
309 struct ehci_hcd *ehci,
310 unsigned period,
311 struct usb_device *dev,
312 unsigned frame,
313 unsigned uframe,
314 u16 usecs
315)
316{
317 if ((period == 0) || (uframe >= 7)) /* error */
318 return 0;
319
320 for (; frame < ehci->periodic_size; frame += period) {
321 unsigned short tt_usecs[8];
322
323 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
324
325 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
326 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
327 frame, usecs, uframe,
328 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
329 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
330
331 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
332 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
333 frame, uframe);
334 return 0;
335 }
336
337 /* special case for isoc transfers larger than 125us:
338 * the first and each subsequent fully used uframe
339 * must be empty, so as to not illegally delay
340 * already scheduled transactions
341 */
342 if (125 < usecs) {
c065c60e 343 int ufs = (usecs / 125);
ba47f66b
DS		 344 int i;
345 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
346 if (0 < tt_usecs[i]) {
347 ehci_vdbg(ehci,
348 "multi-uframe xfer can't fit "
349 "in frame %d uframe %d\n",
350 frame, i);
351 return 0;
352 }
353 }
354
355 tt_usecs[uframe] += usecs;
356
357 carryover_tt_bandwidth(tt_usecs);
358
359 /* fail if the carryover pushed bw past the last uframe's limit */
360 if (max_tt_usecs[7] < tt_usecs[7]) {
361 ehci_vdbg(ehci,
362 "tt unavailable usecs %d frame %d uframe %d\n",
363 usecs, frame, uframe);
364 return 0;
365 }
366 }
367
368 return 1;
369}
370
371#else
372
1da177e4
LT		 373/* return true iff the device's transaction translator is available
374 * for a periodic transfer starting at the specified frame, using
375 * all the uframes in the mask.
376 */
377static int tt_no_collision (
378 struct ehci_hcd *ehci,
379 unsigned period,
380 struct usb_device *dev,
381 unsigned frame,
382 u32 uf_mask
383)
384{
385 if (period == 0) /* error */
386 return 0;
387
388 /* note bandwidth wastage: split never follows csplit
389 * (different dev or endpoint) until the next uframe.
390 * calling convention doesn't make that distinction.
391 */
392 for (; frame < ehci->periodic_size; frame += period) {
393 union ehci_shadow here;
6dbd682b 394 __hc32 type;
3807e26d 395 struct ehci_qh_hw *hw;
1da177e4
LT		 396
397 here = ehci->pshadow [frame];
6dbd682b 398 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
1da177e4 399 while (here.ptr) {
6dbd682b 400 switch (hc32_to_cpu(ehci, type)) {
1da177e4 401 case Q_TYPE_ITD:
6dbd682b 402 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
1da177e4
LT		 403 here = here.itd->itd_next;
404 continue;
405 case Q_TYPE_QH:
3807e26d 406 hw = here.qh->hw;
1da177e4
LT		 407 if (same_tt (dev, here.qh->dev)) {
408 u32 mask;
409
6dbd682b 410 mask = hc32_to_cpu(ehci,
3807e26d 411 hw->hw_info2);
1da177e4
LT		 412 /* "knows" no gap is needed */
413 mask |= mask >> 8;
414 if (mask & uf_mask)
415 break;
416 }
3807e26d 417 type = Q_NEXT_TYPE(ehci, hw->hw_next);
1da177e4
LT		 418 here = here.qh->qh_next;
419 continue;
420 case Q_TYPE_SITD:
421 if (same_tt (dev, here.sitd->urb->dev)) {
422 u16 mask;
423
6dbd682b 424 mask = hc32_to_cpu(ehci, here.sitd
1da177e4
LT		 425 ->hw_uframe);
426 /* FIXME assumes no gap for IN! */
427 mask |= mask >> 8;
428 if (mask & uf_mask)
429 break;
430 }
6dbd682b 431 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
1da177e4
LT		 432 here = here.sitd->sitd_next;
433 continue;
434 // case Q_TYPE_FSTN:
435 default:
436 ehci_dbg (ehci,
437 "periodic frame %d bogus type %d\n",
438 frame, type);
439 }
440
441 /* collision or error */
442 return 0;
443 }
444 }
445
446 /* no collision */
447 return 1;
448}
449
ba47f66b
DS		 450#endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
451
1da177e4
LT		 452/*-------------------------------------------------------------------------*/
453
454static int enable_periodic (struct ehci_hcd *ehci)
455{
456 u32 cmd;
457 int status;
458
01c17142
DB		 459 if (ehci->periodic_sched++)
460 return 0;
461
1da177e4
LT		 462 /* did clearing PSE did take effect yet?
463 * takes effect only at frame boundaries...
464 */
c765d4ca
KW		 465 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
466 STS_PSS, 0, 9 * 125);
467 if (status)
1da177e4 468 return status;
1da177e4 469
083522d7
BH		 470 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
471 ehci_writel(ehci, cmd, &ehci->regs->command);
1da177e4
LT		 472 /* posted write ... PSS happens later */
473 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
474
475 /* make sure ehci_work scans these */
083522d7
BH		 476 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
477 % (ehci->periodic_size << 3);
ee4ecb8a
ON		 478 if (unlikely(ehci->broken_periodic))
479 ehci->last_periodic_enable = ktime_get_real();
1da177e4
LT		 480 return 0;
481}
482
483static int disable_periodic (struct ehci_hcd *ehci)
484{
485 u32 cmd;
486 int status;
487
01c17142
DB		 488 if (--ehci->periodic_sched)
489 return 0;
490
ee4ecb8a
ON		 491 if (unlikely(ehci->broken_periodic)) {
492 /* delay experimentally determined */
493 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
494 ktime_t now = ktime_get_real();
495 s64 delay = ktime_us_delta(safe, now);
496
497 if (unlikely(delay > 0))
498 udelay(delay);
499 }
500
1da177e4
LT		 501 /* did setting PSE not take effect yet?
502 * takes effect only at frame boundaries...
503 */
c765d4ca
KW		 504 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
505 STS_PSS, STS_PSS, 9 * 125);
506 if (status)
1da177e4 507 return status;
1da177e4 508
083522d7
BH		 509 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
510 ehci_writel(ehci, cmd, &ehci->regs->command);
1da177e4
LT		 511 /* posted write ... */
512
0e5f231b 513 free_cached_lists(ehci);
d63c66d2 514
1da177e4
LT		 515 ehci->next_uframe = -1;
516 return 0;
517}
518
519/*-------------------------------------------------------------------------*/
520
521/* periodic schedule slots have iso tds (normal or split) first, then a
522 * sparse tree for active interrupt transfers.
523 *
524 * this just links in a qh; caller guarantees uframe masks are set right.
525 * no FSTN support (yet; ehci 0.96+)
526 */
527static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
528{
529 unsigned i;
530 unsigned period = qh->period;
531
532 dev_dbg (&qh->dev->dev,
533 "link qh%d-%04x/%p start %d [%d/%d us]\n",
3807e26d
AD		 534 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
535 & (QH_CMASK | QH_SMASK),
1da177e4
LT		 536 qh, qh->start, qh->usecs, qh->c_usecs);
537
538 /* high bandwidth, or otherwise every microframe */
539 if (period == 0)
540 period = 1;
541
542 for (i = qh->start; i < ehci->periodic_size; i += period) {
6dbd682b
SR		 543 union ehci_shadow *prev = &ehci->pshadow[i];
544 __hc32 *hw_p = &ehci->periodic[i];
1da177e4 545 union ehci_shadow here = *prev;
6dbd682b 546 __hc32 type = 0;
1da177e4
LT		 547
548 /* skip the iso nodes at list head */
549 while (here.ptr) {
6dbd682b
SR		 550 type = Q_NEXT_TYPE(ehci, *hw_p);
551 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1da177e4 552 break;
6dbd682b 553 prev = periodic_next_shadow(ehci, prev, type);
3807e26d 554 hw_p = shadow_next_periodic(ehci, &here, type);
1da177e4
LT		 555 here = *prev;
556 }
557
558 /* sorting each branch by period (slow-->fast)
559 * enables sharing interior tree nodes
560 */
561 while (here.ptr && qh != here.qh) {
562 if (qh->period > here.qh->period)
563 break;
564 prev = &here.qh->qh_next;
3807e26d 565 hw_p = &here.qh->hw->hw_next;
1da177e4
LT		 566 here = *prev;
567 }
568 /* link in this qh, unless some earlier pass did that */
569 if (qh != here.qh) {
570 qh->qh_next = here;
571 if (here.qh)
3807e26d 572 qh->hw->hw_next = *hw_p;
1da177e4
LT		 573 wmb ();
574 prev->qh = qh;
6dbd682b 575 *hw_p = QH_NEXT (ehci, qh->qh_dma);
1da177e4
LT		 576 }
577 }
578 qh->qh_state = QH_STATE_LINKED;
ef4638f9 579 qh->xacterrs = 0;
1da177e4
LT		 580 qh_get (qh);
581
582 /* update per-qh bandwidth for usbfs */
583 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
584 ? ((qh->usecs + qh->c_usecs) / qh->period)
585 : (qh->usecs * 8);
586
587 /* maybe enable periodic schedule processing */
01c17142 588 return enable_periodic(ehci);
1da177e4
LT		 589}
590
01c17142 591static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
1da177e4
LT		 592{
593 unsigned i;
594 unsigned period;
595
596 // FIXME:
597 // IF this isn't high speed
598 // and this qh is active in the current uframe
599 // (and overlay token SplitXstate is false?)
600 // THEN
551509d2 601 // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
1da177e4
LT		 602
603 /* high bandwidth, or otherwise part of every microframe */
604 if ((period = qh->period) == 0)
605 period = 1;
606
607 for (i = qh->start; i < ehci->periodic_size; i += period)
608 periodic_unlink (ehci, i, qh);
609
610 /* update per-qh bandwidth for usbfs */
611 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
612 ? ((qh->usecs + qh->c_usecs) / qh->period)
613 : (qh->usecs * 8);
614
615 dev_dbg (&qh->dev->dev,
616 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
7dedacf4 617 qh->period,
3807e26d 618 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
1da177e4
LT		 619 qh, qh->start, qh->usecs, qh->c_usecs);
620
621 /* qh->qh_next still "live" to HC */
622 qh->qh_state = QH_STATE_UNLINK;
623 qh->qh_next.ptr = NULL;
624 qh_put (qh);
625
626 /* maybe turn off periodic schedule */
01c17142 627 return disable_periodic(ehci);
1da177e4
LT		 628}
629
630static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
631{
a448c9d8
AS		 632 unsigned wait;
633 struct ehci_qh_hw *hw = qh->hw;
634 int rc;
635
636 /* If the QH isn't linked then there's nothing we can do
637 * unless we were called during a giveback, in which case
638 * qh_completions() has to deal with it.
639 */
640 if (qh->qh_state != QH_STATE_LINKED) {
641 if (qh->qh_state == QH_STATE_COMPLETING)
642 qh->needs_rescan = 1;
643 return;
644 }
1da177e4
LT		 645
646 qh_unlink_periodic (ehci, qh);
647
648 /* simple/paranoid: always delay, expecting the HC needs to read
649 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
650 * expect khubd to clean up after any CSPLITs we won't issue.
651 * active high speed queues may need bigger delays...
652 */
653 if (list_empty (&qh->qtd_list)
6dbd682b 654 || (cpu_to_hc32(ehci, QH_CMASK)
3807e26d 655 & hw->hw_info2) != 0)
1da177e4
LT		 656 wait = 2;
657 else
658 wait = 55; /* worst case: 3 * 1024 */
659
660 udelay (wait);
661 qh->qh_state = QH_STATE_IDLE;
3807e26d 662 hw->hw_next = EHCI_LIST_END(ehci);
1da177e4 663 wmb ();
a448c9d8
AS		 664
665 qh_completions(ehci, qh);
666
667 /* reschedule QH iff another request is queued */
668 if (!list_empty(&qh->qtd_list) &&
669 HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
670 rc = qh_schedule(ehci, qh);
671
672 /* An error here likely indicates handshake failure
673 * or no space left in the schedule. Neither fault
674 * should happen often ...
675 *
676 * FIXME kill the now-dysfunctional queued urbs
677 */
678 if (rc != 0)
679 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
680 qh, rc);
681 }
1da177e4
LT		 682}
683
684/*-------------------------------------------------------------------------*/
685
686static int check_period (
53bd6a60 687 struct ehci_hcd *ehci,
1da177e4
LT		 688 unsigned frame,
689 unsigned uframe,
690 unsigned period,
691 unsigned usecs
692) {
693 int claimed;
694
695 /* complete split running into next frame?
696 * given FSTN support, we could sometimes check...
697 */
698 if (uframe >= 8)
699 return 0;
700
701 /*
702 * 80% periodic == 100 usec/uframe available
53bd6a60 703 * convert "usecs we need" to "max already claimed"
1da177e4
LT		 704 */
705 usecs = 100 - usecs;
706
707 /* we "know" 2 and 4 uframe intervals were rejected; so
708 * for period 0, check _every_ microframe in the schedule.
709 */
710 if (unlikely (period == 0)) {
711 do {
712 for (uframe = 0; uframe < 7; uframe++) {
713 claimed = periodic_usecs (ehci, frame, uframe);
714 if (claimed > usecs)
715 return 0;
716 }
717 } while ((frame += 1) < ehci->periodic_size);
718
719 /* just check the specified uframe, at that period */
720 } else {
721 do {
722 claimed = periodic_usecs (ehci, frame, uframe);
723 if (claimed > usecs)
724 return 0;
725 } while ((frame += period) < ehci->periodic_size);
726 }
727
728 // success!
729 return 1;
730}
731
732static int check_intr_schedule (
53bd6a60 733 struct ehci_hcd *ehci,
1da177e4
LT		 734 unsigned frame,
735 unsigned uframe,
736 const struct ehci_qh *qh,
6dbd682b 737 __hc32 *c_maskp
1da177e4
LT		 738)
739{
53bd6a60 740 int retval = -ENOSPC;
ba47f66b 741 u8 mask = 0;
1da177e4
LT		 742
743 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
744 goto done;
745
746 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
747 goto done;
748 if (!qh->c_usecs) {
749 retval = 0;
750 *c_maskp = 0;
751 goto done;
752 }
753
ba47f66b
DS		 754#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
755 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
756 qh->tt_usecs)) {
757 unsigned i;
758
759 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
760 for (i=uframe+1; i<8 && i<uframe+4; i++)
761 if (!check_period (ehci, frame, i,
762 qh->period, qh->c_usecs))
763 goto done;
764 else
765 mask |= 1 << i;
766
767 retval = 0;
768
6dbd682b 769 *c_maskp = cpu_to_hc32(ehci, mask << 8);
ba47f66b
DS		 770 }
771#else
1da177e4
LT		 772 /* Make sure this tt's buffer is also available for CSPLITs.
773 * We pessimize a bit; probably the typical full speed case
774 * doesn't need the second CSPLIT.
53bd6a60 775 *
1da177e4
LT		 776 * NOTE: both SPLIT and CSPLIT could be checked in just
777 * one smart pass...
778 */
779 mask = 0x03 << (uframe + qh->gap_uf);
6dbd682b 780 *c_maskp = cpu_to_hc32(ehci, mask << 8);
1da177e4
LT		 781
782 mask |= 1 << uframe;
783 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
784 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
785 qh->period, qh->c_usecs))
786 goto done;
787 if (!check_period (ehci, frame, uframe + qh->gap_uf,
788 qh->period, qh->c_usecs))
789 goto done;
790 retval = 0;
791 }
ba47f66b 792#endif
1da177e4
LT		 793done:
794 return retval;
795}
796
797/* "first fit" scheduling policy used the first time through,
798 * or when the previous schedule slot can't be re-used.
799 */
6dbd682b 800static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
1da177e4 801{
53bd6a60 802 int status;
1da177e4 803 unsigned uframe;
6dbd682b 804 __hc32 c_mask;
1da177e4 805 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
3807e26d 806 struct ehci_qh_hw *hw = qh->hw;
1da177e4
LT		 807
808 qh_refresh(ehci, qh);
3807e26d 809 hw->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 810 frame = qh->start;
811
812 /* reuse the previous schedule slots, if we can */
813 if (frame < qh->period) {
3807e26d 814 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
1da177e4
LT		 815 status = check_intr_schedule (ehci, frame, --uframe,
816 qh, &c_mask);
817 } else {
818 uframe = 0;
819 c_mask = 0;
820 status = -ENOSPC;
821 }
822
823 /* else scan the schedule to find a group of slots such that all
824 * uframes have enough periodic bandwidth available.
825 */
826 if (status) {
827 /* "normal" case, uframing flexible except with splits */
828 if (qh->period) {
68335e81
AS		 829 int i;
830
831 for (i = qh->period; status && i > 0; --i) {
832 frame = ++ehci->random_frame % qh->period;
1da177e4
LT		 833 for (uframe = 0; uframe < 8; uframe++) {
834 status = check_intr_schedule (ehci,
835 frame, uframe, qh,
836 &c_mask);
837 if (status == 0)
838 break;
839 }
68335e81 840 }
1da177e4
LT		 841
842 /* qh->period == 0 means every uframe */
843 } else {
844 frame = 0;
845 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
846 }
847 if (status)
848 goto done;
849 qh->start = frame;
850
851 /* reset S-frame and (maybe) C-frame masks */
3807e26d
AD		 852 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
853 hw->hw_info2 |= qh->period
6dbd682b
SR		 854 ? cpu_to_hc32(ehci, 1 << uframe)
855 : cpu_to_hc32(ehci, QH_SMASK);
3807e26d 856 hw->hw_info2 |= c_mask;
1da177e4
LT		 857 } else
858 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
859
860 /* stuff into the periodic schedule */
53bd6a60 861 status = qh_link_periodic (ehci, qh);
1da177e4
LT		 862done:
863 return status;
864}
865
866static int intr_submit (
867 struct ehci_hcd *ehci,
1da177e4
LT		 868 struct urb *urb,
869 struct list_head *qtd_list,
55016f10 870 gfp_t mem_flags
1da177e4
LT		 871) {
872 unsigned epnum;
873 unsigned long flags;
874 struct ehci_qh *qh;
e9df41c5 875 int status;
1da177e4
LT		 876 struct list_head empty;
877
878 /* get endpoint and transfer/schedule data */
e9df41c5 879 epnum = urb->ep->desc.bEndpointAddress;
1da177e4
LT		 880
881 spin_lock_irqsave (&ehci->lock, flags);
882
8de98402 883 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
6dbd682b 884 &ehci_to_hcd(ehci)->flags))) {
8de98402 885 status = -ESHUTDOWN;
e9df41c5 886 goto done_not_linked;
8de98402 887 }
e9df41c5
AS		 888 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
889 if (unlikely(status))
890 goto done_not_linked;
8de98402 891
1da177e4
LT		 892 /* get qh and force any scheduling errors */
893 INIT_LIST_HEAD (&empty);
e9df41c5 894 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
1da177e4
LT		 895 if (qh == NULL) {
896 status = -ENOMEM;
897 goto done;
898 }
899 if (qh->qh_state == QH_STATE_IDLE) {
900 if ((status = qh_schedule (ehci, qh)) != 0)
901 goto done;
902 }
903
904 /* then queue the urb's tds to the qh */
e9df41c5 905 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
1da177e4
LT		 906 BUG_ON (qh == NULL);
907
908 /* ... update usbfs periodic stats */
909 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
910
911done:
e9df41c5
AS		 912 if (unlikely(status))
913 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
914done_not_linked:
1da177e4
LT		 915 spin_unlock_irqrestore (&ehci->lock, flags);
916 if (status)
917 qtd_list_free (ehci, urb, qtd_list);
918
919 return status;
920}
921
922/*-------------------------------------------------------------------------*/
923
924/* ehci_iso_stream ops work with both ITD and SITD */
925
926static struct ehci_iso_stream *
55016f10 927iso_stream_alloc (gfp_t mem_flags)
1da177e4
LT		 928{
929 struct ehci_iso_stream *stream;
930
7b842b6e 931 stream = kzalloc(sizeof *stream, mem_flags);
1da177e4 932 if (likely (stream != NULL)) {
1da177e4
LT		 933 INIT_LIST_HEAD(&stream->td_list);
934 INIT_LIST_HEAD(&stream->free_list);
935 stream->next_uframe = -1;
936 stream->refcount = 1;
937 }
938 return stream;
939}
940
941static void
942iso_stream_init (
943 struct ehci_hcd *ehci,
944 struct ehci_iso_stream *stream,
945 struct usb_device *dev,
946 int pipe,
947 unsigned interval
948)
949{
950 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
951
952 u32 buf1;
953 unsigned epnum, maxp;
954 int is_input;
955 long bandwidth;
956
957 /*
958 * this might be a "high bandwidth" highspeed endpoint,
959 * as encoded in the ep descriptor's wMaxPacket field
960 */
961 epnum = usb_pipeendpoint (pipe);
962 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
963 maxp = usb_maxpacket(dev, pipe, !is_input);
964 if (is_input) {
965 buf1 = (1 << 11);
966 } else {
967 buf1 = 0;
968 }
969
970 /* knows about ITD vs SITD */
971 if (dev->speed == USB_SPEED_HIGH) {
972 unsigned multi = hb_mult(maxp);
973
974 stream->highspeed = 1;
975
976 maxp = max_packet(maxp);
977 buf1 |= maxp;
978 maxp *= multi;
979
6dbd682b
SR		 980 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
981 stream->buf1 = cpu_to_hc32(ehci, buf1);
982 stream->buf2 = cpu_to_hc32(ehci, multi);
1da177e4
LT		 983
984 /* usbfs wants to report the average usecs per frame tied up
985 * when transfers on this endpoint are scheduled ...
986 */
987 stream->usecs = HS_USECS_ISO (maxp);
988 bandwidth = stream->usecs * 8;
372dd6e8 989 bandwidth /= interval;
1da177e4
LT		 990
991 } else {
992 u32 addr;
d0384200 993 int think_time;
469d0229 994 int hs_transfers;
1da177e4
LT		 995
996 addr = dev->ttport << 24;
997 if (!ehci_is_TDI(ehci)
998 || (dev->tt->hub !=
999 ehci_to_hcd(ehci)->self.root_hub))
1000 addr |= dev->tt->hub->devnum << 16;
1001 addr |= epnum << 8;
1002 addr |= dev->devnum;
1003 stream->usecs = HS_USECS_ISO (maxp);
d0384200 1004 think_time = dev->tt ? dev->tt->think_time : 0;
1005 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1006 dev->speed, is_input, 1, maxp));
469d0229 1007 hs_transfers = max (1u, (maxp + 187) / 188);
1da177e4
LT		 1008 if (is_input) {
1009 u32 tmp;
1010
1011 addr |= 1 << 31;
1012 stream->c_usecs = stream->usecs;
1013 stream->usecs = HS_USECS_ISO (1);
1014 stream->raw_mask = 1;
1015
469d0229
CL		 1016 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1017 tmp = (1 << (hs_transfers + 2)) - 1;
1018 stream->raw_mask |= tmp << (8 + 2);
1da177e4 1019 } else
469d0229 1020 stream->raw_mask = smask_out [hs_transfers - 1];
1da177e4 1021 bandwidth = stream->usecs + stream->c_usecs;
372dd6e8 1022 bandwidth /= interval << 3;
1da177e4
LT		 1023
1024 /* stream->splits gets created from raw_mask later */
6dbd682b 1025 stream->address = cpu_to_hc32(ehci, addr);
1da177e4
LT		 1026 }
1027 stream->bandwidth = bandwidth;
1028
1029 stream->udev = dev;
1030
1031 stream->bEndpointAddress = is_input | epnum;
1032 stream->interval = interval;
1033 stream->maxp = maxp;
1034}
1035
1036static void
1037iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1038{
1039 stream->refcount--;
1040
1041 /* free whenever just a dev->ep reference remains.
1042 * not like a QH -- no persistent state (toggle, halt)
1043 */
1044 if (stream->refcount == 1) {
1045 int is_in;
1046
1047 // BUG_ON (!list_empty(&stream->td_list));
1048
1049 while (!list_empty (&stream->free_list)) {
1050 struct list_head *entry;
1051
1052 entry = stream->free_list.next;
1053 list_del (entry);
1054
1055 /* knows about ITD vs SITD */
1056 if (stream->highspeed) {
1057 struct ehci_itd *itd;
1058
1059 itd = list_entry (entry, struct ehci_itd,
1060 itd_list);
1061 dma_pool_free (ehci->itd_pool, itd,
1062 itd->itd_dma);
1063 } else {
1064 struct ehci_sitd *sitd;
1065
1066 sitd = list_entry (entry, struct ehci_sitd,
1067 sitd_list);
1068 dma_pool_free (ehci->sitd_pool, sitd,
1069 sitd->sitd_dma);
1070 }
1071 }
1072
1073 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1074 stream->bEndpointAddress &= 0x0f;
9aa09d2f
KW		 1075 if (stream->ep)
1076 stream->ep->hcpriv = NULL;
1da177e4
LT		 1077
1078 if (stream->rescheduled) {
1079 ehci_info (ehci, "ep%d%s-iso rescheduled "
1080 "%lu times in %lu seconds\n",
1081 stream->bEndpointAddress, is_in ? "in" : "out",
1082 stream->rescheduled,
1083 ((jiffies - stream->start)/HZ)
1084 );
1085 }
1086
1087 kfree(stream);
1088 }
1089}
1090
1091static inline struct ehci_iso_stream *
1092iso_stream_get (struct ehci_iso_stream *stream)
1093{
1094 if (likely (stream != NULL))
1095 stream->refcount++;
1096 return stream;
1097}
1098
1099static struct ehci_iso_stream *
1100iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1101{
1102 unsigned epnum;
1103 struct ehci_iso_stream *stream;
1104 struct usb_host_endpoint *ep;
1105 unsigned long flags;
1106
1107 epnum = usb_pipeendpoint (urb->pipe);
1108 if (usb_pipein(urb->pipe))
1109 ep = urb->dev->ep_in[epnum];
1110 else
1111 ep = urb->dev->ep_out[epnum];
1112
1113 spin_lock_irqsave (&ehci->lock, flags);
1114 stream = ep->hcpriv;
1115
1116 if (unlikely (stream == NULL)) {
1117 stream = iso_stream_alloc(GFP_ATOMIC);
1118 if (likely (stream != NULL)) {
1119 /* dev->ep owns the initial refcount */
1120 ep->hcpriv = stream;
1121 stream->ep = ep;
1122 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1123 urb->interval);
1124 }
1125
1082f57a
CL		 1126 /* if dev->ep [epnum] is a QH, hw is set */
1127 } else if (unlikely (stream->hw != NULL)) {
1da177e4
LT		 1128 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1129 urb->dev->devpath, epnum,
1130 usb_pipein(urb->pipe) ? "in" : "out");
1131 stream = NULL;
1132 }
1133
1134 /* caller guarantees an eventual matching iso_stream_put */
1135 stream = iso_stream_get (stream);
1136
1137 spin_unlock_irqrestore (&ehci->lock, flags);
1138 return stream;
1139}
1140
1141/*-------------------------------------------------------------------------*/
1142
1143/* ehci_iso_sched ops can be ITD-only or SITD-only */
1144
1145static struct ehci_iso_sched *
55016f10 1146iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1da177e4
LT		 1147{
1148 struct ehci_iso_sched *iso_sched;
1149 int size = sizeof *iso_sched;
1150
1151 size += packets * sizeof (struct ehci_iso_packet);
80b6ca48 1152 iso_sched = kzalloc(size, mem_flags);
1da177e4 1153 if (likely (iso_sched != NULL)) {
1da177e4
LT		 1154 INIT_LIST_HEAD (&iso_sched->td_list);
1155 }
1156 return iso_sched;
1157}
1158
1159static inline void
6dbd682b
SR		 1160itd_sched_init(
1161 struct ehci_hcd *ehci,
1da177e4
LT		 1162 struct ehci_iso_sched *iso_sched,
1163 struct ehci_iso_stream *stream,
1164 struct urb *urb
1165)
1166{
1167 unsigned i;
1168 dma_addr_t dma = urb->transfer_dma;
1169
1170 /* how many uframes are needed for these transfers */
1171 iso_sched->span = urb->number_of_packets * stream->interval;
1172
1173 /* figure out per-uframe itd fields that we'll need later
1174 * when we fit new itds into the schedule.
1175 */
1176 for (i = 0; i < urb->number_of_packets; i++) {
1177 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1178 unsigned length;
1179 dma_addr_t buf;
1180 u32 trans;
1181
1182 length = urb->iso_frame_desc [i].length;
1183 buf = dma + urb->iso_frame_desc [i].offset;
1184
1185 trans = EHCI_ISOC_ACTIVE;
1186 trans |= buf & 0x0fff;
1187 if (unlikely (((i + 1) == urb->number_of_packets))
1188 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1189 trans |= EHCI_ITD_IOC;
1190 trans |= length << 16;
6dbd682b 1191 uframe->transaction = cpu_to_hc32(ehci, trans);
1da177e4 1192
77078570 1193 /* might need to cross a buffer page within a uframe */
1da177e4
LT		 1194 uframe->bufp = (buf & ~(u64)0x0fff);
1195 buf += length;
1196 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1197 uframe->cross = 1;
1198 }
1199}
1200
1201static void
1202iso_sched_free (
1203 struct ehci_iso_stream *stream,
1204 struct ehci_iso_sched *iso_sched
1205)
1206{
1207 if (!iso_sched)
1208 return;
1209 // caller must hold ehci->lock!
1210 list_splice (&iso_sched->td_list, &stream->free_list);
1211 kfree (iso_sched);
1212}
1213
1214static int
1215itd_urb_transaction (
1216 struct ehci_iso_stream *stream,
1217 struct ehci_hcd *ehci,
1218 struct urb *urb,
55016f10 1219 gfp_t mem_flags
1da177e4
LT		 1220)
1221{
1222 struct ehci_itd *itd;
1223 dma_addr_t itd_dma;
1224 int i;
1225 unsigned num_itds;
1226 struct ehci_iso_sched *sched;
1227 unsigned long flags;
1228
1229 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1230 if (unlikely (sched == NULL))
1231 return -ENOMEM;
1232
6dbd682b 1233 itd_sched_init(ehci, sched, stream, urb);
1da177e4
LT		 1234
1235 if (urb->interval < 8)
1236 num_itds = 1 + (sched->span + 7) / 8;
1237 else
1238 num_itds = urb->number_of_packets;
1239
1240 /* allocate/init ITDs */
1241 spin_lock_irqsave (&ehci->lock, flags);
1242 for (i = 0; i < num_itds; i++) {
1243
1244 /* free_list.next might be cache-hot ... but maybe
1245 * the HC caches it too. avoid that issue for now.
1246 */
1247
1248 /* prefer previously-allocated itds */
1249 if (likely (!list_empty(&stream->free_list))) {
1250 itd = list_entry (stream->free_list.prev,
6dbd682b 1251 struct ehci_itd, itd_list);
1da177e4
LT		 1252 list_del (&itd->itd_list);
1253 itd_dma = itd->itd_dma;
3d01f0fe 1254 } else {
1da177e4
LT		 1255 spin_unlock_irqrestore (&ehci->lock, flags);
1256 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1257 &itd_dma);
1258 spin_lock_irqsave (&ehci->lock, flags);
3d01f0fe
KW		 1259 if (!itd) {
1260 iso_sched_free(stream, sched);
1261 spin_unlock_irqrestore(&ehci->lock, flags);
1262 return -ENOMEM;
1263 }
1da177e4
LT		 1264 }
1265
1da177e4
LT		 1266 memset (itd, 0, sizeof *itd);
1267 itd->itd_dma = itd_dma;
1268 list_add (&itd->itd_list, &sched->td_list);
1269 }
1270 spin_unlock_irqrestore (&ehci->lock, flags);
1271
1272 /* temporarily store schedule info in hcpriv */
1273 urb->hcpriv = sched;
1274 urb->error_count = 0;
1275 return 0;
1276}
1277
1278/*-------------------------------------------------------------------------*/
1279
1280static inline int
1281itd_slot_ok (
1282 struct ehci_hcd *ehci,
1283 u32 mod,
1284 u32 uframe,
1285 u8 usecs,
1286 u32 period
1287)
1288{
1289 uframe %= period;
1290 do {
1291 /* can't commit more than 80% periodic == 100 usec */
1292 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1293 > (100 - usecs))
1294 return 0;
1295
1296 /* we know urb->interval is 2^N uframes */
1297 uframe += period;
1298 } while (uframe < mod);
1299 return 1;
1300}
1301
1302static inline int
1303sitd_slot_ok (
1304 struct ehci_hcd *ehci,
1305 u32 mod,
1306 struct ehci_iso_stream *stream,
1307 u32 uframe,
1308 struct ehci_iso_sched *sched,
1309 u32 period_uframes
1310)
1311{
1312 u32 mask, tmp;
1313 u32 frame, uf;
1314
1315 mask = stream->raw_mask << (uframe & 7);
1316
1317 /* for IN, don't wrap CSPLIT into the next frame */
1318 if (mask & ~0xffff)
1319 return 0;
1320
1321 /* this multi-pass logic is simple, but performance may
1322 * suffer when the schedule data isn't cached.
1323 */
1324
1325 /* check bandwidth */
1326 uframe %= period_uframes;
1327 do {
1328 u32 max_used;
1329
1330 frame = uframe >> 3;
1331 uf = uframe & 7;
1332
ba47f66b
DS		 1333#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1334 /* The tt's fullspeed bus bandwidth must be available.
1335 * tt_available scheduling guarantees 10+% for control/bulk.
1336 */
1337 if (!tt_available (ehci, period_uframes << 3,
1338 stream->udev, frame, uf, stream->tt_usecs))
1339 return 0;
1340#else
1da177e4
LT		 1341 /* tt must be idle for start(s), any gap, and csplit.
1342 * assume scheduling slop leaves 10+% for control/bulk.
1343 */
1344 if (!tt_no_collision (ehci, period_uframes << 3,
1345 stream->udev, frame, mask))
1346 return 0;
ba47f66b 1347#endif
1da177e4
LT		 1348
1349 /* check starts (OUT uses more than one) */
1350 max_used = 100 - stream->usecs;
1351 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1352 if (periodic_usecs (ehci, frame, uf) > max_used)
1353 return 0;
1354 }
1355
1356 /* for IN, check CSPLIT */
1357 if (stream->c_usecs) {
0c734622 1358 uf = uframe & 7;
1da177e4
LT		 1359 max_used = 100 - stream->c_usecs;
1360 do {
1361 tmp = 1 << uf;
1362 tmp <<= 8;
1363 if ((stream->raw_mask & tmp) == 0)
1364 continue;
1365 if (periodic_usecs (ehci, frame, uf)
1366 > max_used)
1367 return 0;
1368 } while (++uf < 8);
1369 }
1370
1371 /* we know urb->interval is 2^N uframes */
1372 uframe += period_uframes;
1373 } while (uframe < mod);
1374
6dbd682b 1375 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1da177e4
LT		 1376 return 1;
1377}
1378
1379/*
1380 * This scheduler plans almost as far into the future as it has actual
1381 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1382 * "as small as possible" to be cache-friendlier.) That limits the size
1383 * transfers you can stream reliably; avoid more than 64 msec per urb.
1384 * Also avoid queue depths of less than ehci's worst irq latency (affected
1385 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1386 * and other factors); or more than about 230 msec total (for portability,
1387 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1388 */
1389
d7e055f1 1390#define SCHEDULE_SLOP 80 /* microframes */
1da177e4
LT		 1391
1392static int
1393iso_stream_schedule (
1394 struct ehci_hcd *ehci,
1395 struct urb *urb,
1396 struct ehci_iso_stream *stream
1397)
1398{
dccd574c 1399 u32 now, next, start, period;
1da177e4
LT		 1400 int status;
1401 unsigned mod = ehci->periodic_size << 3;
1402 struct ehci_iso_sched *sched = urb->hcpriv;
dccd574c 1403 struct pci_dev *pdev;
1da177e4 1404
d7e055f1 1405 if (sched->span > (mod - SCHEDULE_SLOP)) {
1da177e4
LT		 1406 ehci_dbg (ehci, "iso request %p too long\n", urb);
1407 status = -EFBIG;
1408 goto fail;
1409 }
1410
1411 if ((stream->depth + sched->span) > mod) {
1412 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1413 urb, stream->depth, sched->span, mod);
1414 status = -EFBIG;
1415 goto fail;
1416 }
1417
36f21329
SS		 1418 period = urb->interval;
1419 if (!stream->highspeed)
1420 period <<= 3;
1421
083522d7 1422 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1da177e4 1423
b40e43fc
AS		 1424 /* Typical case: reuse current schedule, stream is still active.
1425 * Hopefully there are no gaps from the host falling behind
1426 * (irq delays etc), but if there are we'll take the next
1427 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1da177e4
LT		 1428 */
1429 if (likely (!list_empty (&stream->td_list))) {
dccd574c 1430 pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
1da177e4 1431 start = stream->next_uframe;
dccd574c
SS		 1432
1433 /* For high speed devices, allow scheduling within the
1434 * isochronous scheduling threshold. For full speed devices,
1435 * don't. (Work around for Intel ICH9 bug.)
1436 */
1437 if (!stream->highspeed &&
1438 pdev->vendor == PCI_VENDOR_ID_INTEL)
1439 next = now + ehci->i_thresh;
1440 else
1441 next = now;
b40e43fc
AS		 1442
1443 /* Fell behind (by up to twice the slop amount)? */
dccd574c
SS		 1444 if (((start - next) & (mod - 1)) >=
1445 mod - 2 * SCHEDULE_SLOP)
36f21329 1446 start += period * DIV_ROUND_UP(
dccd574c
SS		 1447 (next - start) & (mod - 1),
1448 period);
b40e43fc
AS		 1449
1450 /* Tried to schedule too far into the future? */
dccd574c
SS		 1451 if (unlikely(((start - now) & (mod - 1)) + sched->span
1452 >= mod - 2 * SCHEDULE_SLOP)) {
b40e43fc
AS		 1453 status = -EFBIG;
1454 goto fail;
1455 }
d5550094 1456 stream->next_uframe = start;
b40e43fc 1457 goto ready;
1da177e4
LT		 1458 }
1459
1460 /* need to schedule; when's the next (u)frame we could start?
1461 * this is bigger than ehci->i_thresh allows; scheduling itself
1462 * isn't free, the slop should handle reasonably slow cpus. it
1463 * can also help high bandwidth if the dma and irq loads don't
1464 * jump until after the queue is primed.
1465 */
d7e055f1 1466 start = SCHEDULE_SLOP + (now & ~0x07);
1da177e4
LT		 1467 start %= mod;
1468 stream->next_uframe = start;
1469
1470 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1471
1da177e4
LT		 1472 /* find a uframe slot with enough bandwidth */
1473 for (; start < (stream->next_uframe + period); start++) {
1474 int enough_space;
1475
1476 /* check schedule: enough space? */
1477 if (stream->highspeed)
1478 enough_space = itd_slot_ok (ehci, mod, start,
1479 stream->usecs, period);
1480 else {
1481 if ((start % 8) >= 6)
1482 continue;
1483 enough_space = sitd_slot_ok (ehci, mod, stream,
1484 start, sched, period);
1485 }
1486
1487 /* schedule it here if there's enough bandwidth */
1488 if (enough_space) {
1489 stream->next_uframe = start % mod;
1490 goto ready;
1491 }
1492 }
1493
1494 /* no room in the schedule */
1495 ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1496 list_empty (&stream->td_list) ? "" : "re",
dccd574c 1497 urb, now, now + mod);
1da177e4
LT		 1498 status = -ENOSPC;
1499
1500fail:
1501 iso_sched_free (stream, sched);
1502 urb->hcpriv = NULL;
1503 return status;
1504
1505ready:
1506 /* report high speed start in uframes; full speed, in frames */
1507 urb->start_frame = stream->next_uframe;
1508 if (!stream->highspeed)
1509 urb->start_frame >>= 3;
1510 return 0;
1511}
1512
1513/*-------------------------------------------------------------------------*/
1514
1515static inline void
6dbd682b
SR		 1516itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1517 struct ehci_itd *itd)
1da177e4
LT		 1518{
1519 int i;
1520
77078570 1521 /* it's been recently zeroed */
6dbd682b 1522 itd->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 1523 itd->hw_bufp [0] = stream->buf0;
1524 itd->hw_bufp [1] = stream->buf1;
1525 itd->hw_bufp [2] = stream->buf2;
1526
1527 for (i = 0; i < 8; i++)
1528 itd->index[i] = -1;
1529
1530 /* All other fields are filled when scheduling */
1531}
1532
1533static inline void
6dbd682b
SR		 1534itd_patch(
1535 struct ehci_hcd *ehci,
1da177e4
LT		 1536 struct ehci_itd *itd,
1537 struct ehci_iso_sched *iso_sched,
1538 unsigned index,
77078570 1539 u16 uframe
1da177e4
LT		 1540)
1541{
1542 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1543 unsigned pg = itd->pg;
1544
1545 // BUG_ON (pg == 6 && uf->cross);
1546
1547 uframe &= 0x07;
1548 itd->index [uframe] = index;
1549
6dbd682b
SR		 1550 itd->hw_transaction[uframe] = uf->transaction;
1551 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1552 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1553 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1da177e4
LT		 1554
1555 /* iso_frame_desc[].offset must be strictly increasing */
77078570 1556 if (unlikely (uf->cross)) {
1da177e4 1557 u64 bufp = uf->bufp + 4096;
6dbd682b 1558
1da177e4 1559 itd->pg = ++pg;
6dbd682b
SR		 1560 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1561 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1da177e4
LT		 1562 }
1563}
1564
1565static inline void
1566itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1567{
92bc3648
CL		 1568 union ehci_shadow *prev = &ehci->pshadow[frame];
1569 __hc32 *hw_p = &ehci->periodic[frame];
1570 union ehci_shadow here = *prev;
1571 __hc32 type = 0;
1572
1573 /* skip any iso nodes which might belong to previous microframes */
1574 while (here.ptr) {
1575 type = Q_NEXT_TYPE(ehci, *hw_p);
1576 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1577 break;
1578 prev = periodic_next_shadow(ehci, prev, type);
1579 hw_p = shadow_next_periodic(ehci, &here, type);
1580 here = *prev;
1581 }
1582
1583 itd->itd_next = here;
1584 itd->hw_next = *hw_p;
1585 prev->itd = itd;
1da177e4
LT		 1586 itd->frame = frame;
1587 wmb ();
92bc3648 1588 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1da177e4
LT		 1589}
1590
1591/* fit urb's itds into the selected schedule slot; activate as needed */
1592static int
1593itd_link_urb (
1594 struct ehci_hcd *ehci,
1595 struct urb *urb,
1596 unsigned mod,
1597 struct ehci_iso_stream *stream
1598)
1599{
77078570 1600 int packet;
1da177e4
LT		 1601 unsigned next_uframe, uframe, frame;
1602 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1603 struct ehci_itd *itd;
1604
1605 next_uframe = stream->next_uframe % mod;
1606
1607 if (unlikely (list_empty(&stream->td_list))) {
1608 ehci_to_hcd(ehci)->self.bandwidth_allocated
1609 += stream->bandwidth;
1610 ehci_vdbg (ehci,
1611 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1612 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1613 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1614 urb->interval,
1615 next_uframe >> 3, next_uframe & 0x7);
1616 stream->start = jiffies;
1617 }
1618 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1619
1620 /* fill iTDs uframe by uframe */
1621 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1622 if (itd == NULL) {
1623 /* ASSERT: we have all necessary itds */
1624 // BUG_ON (list_empty (&iso_sched->td_list));
1625
1626 /* ASSERT: no itds for this endpoint in this uframe */
1627
1628 itd = list_entry (iso_sched->td_list.next,
1629 struct ehci_itd, itd_list);
1630 list_move_tail (&itd->itd_list, &stream->td_list);
1631 itd->stream = iso_stream_get (stream);
508db8c9 1632 itd->urb = urb;
6dbd682b 1633 itd_init (ehci, stream, itd);
1da177e4
LT		 1634 }
1635
1636 uframe = next_uframe & 0x07;
1637 frame = next_uframe >> 3;
1638
6dbd682b 1639 itd_patch(ehci, itd, iso_sched, packet, uframe);
1da177e4
LT		 1640
1641 next_uframe += stream->interval;
1642 stream->depth += stream->interval;
1643 next_uframe %= mod;
1644 packet++;
1645
1646 /* link completed itds into the schedule */
1647 if (((next_uframe >> 3) != frame)
1648 || packet == urb->number_of_packets) {
1649 itd_link (ehci, frame % ehci->periodic_size, itd);
1650 itd = NULL;
1651 }
1652 }
1653 stream->next_uframe = next_uframe;
1654
1655 /* don't need that schedule data any more */
1656 iso_sched_free (stream, iso_sched);
1657 urb->hcpriv = NULL;
1658
1659 timer_action (ehci, TIMER_IO_WATCHDOG);
01c17142 1660 return enable_periodic(ehci);
1da177e4
LT		 1661}
1662
1663#define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1664
30bf54e6
DB		 1665/* Process and recycle a completed ITD. Return true iff its urb completed,
1666 * and hence its completion callback probably added things to the hardware
1667 * schedule.
1668 *
1669 * Note that we carefully avoid recycling this descriptor until after any
1670 * completion callback runs, so that it won't be reused quickly. That is,
1671 * assuming (a) no more than two urbs per frame on this endpoint, and also
1672 * (b) only this endpoint's completions submit URBs. It seems some silicon
1673 * corrupts things if you reuse completed descriptors very quickly...
1674 */
1da177e4
LT		 1675static unsigned
1676itd_complete (
1677 struct ehci_hcd *ehci,
7d12e780 1678 struct ehci_itd *itd
1da177e4
LT		 1679) {
1680 struct urb *urb = itd->urb;
1681 struct usb_iso_packet_descriptor *desc;
1682 u32 t;
1683 unsigned uframe;
1684 int urb_index = -1;
1685 struct ehci_iso_stream *stream = itd->stream;
1686 struct usb_device *dev;
30bf54e6 1687 unsigned retval = false;
1da177e4
LT		 1688
1689 /* for each uframe with a packet */
1690 for (uframe = 0; uframe < 8; uframe++) {
1691 if (likely (itd->index[uframe] == -1))
1692 continue;
1693 urb_index = itd->index[uframe];
1694 desc = &urb->iso_frame_desc [urb_index];
1695
6dbd682b 1696 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1da177e4
LT		 1697 itd->hw_transaction [uframe] = 0;
1698 stream->depth -= stream->interval;
1699
1700 /* report transfer status */
1701 if (unlikely (t & ISO_ERRS)) {
1702 urb->error_count++;
1703 if (t & EHCI_ISOC_BUF_ERR)
1704 desc->status = usb_pipein (urb->pipe)
1705 ? -ENOSR /* hc couldn't read */
1706 : -ECOMM; /* hc couldn't write */
1707 else if (t & EHCI_ISOC_BABBLE)
1708 desc->status = -EOVERFLOW;
1709 else /* (t & EHCI_ISOC_XACTERR) */
1710 desc->status = -EPROTO;
1711
1712 /* HC need not update length with this error */
ec6d67e3
AS		 1713 if (!(t & EHCI_ISOC_BABBLE)) {
1714 desc->actual_length = EHCI_ITD_LENGTH(t);
1715 urb->actual_length += desc->actual_length;
1716 }
1da177e4
LT		 1717 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1718 desc->status = 0;
ec6d67e3
AS		 1719 desc->actual_length = EHCI_ITD_LENGTH(t);
1720 urb->actual_length += desc->actual_length;
b40e43fc
AS		 1721 } else {
1722 /* URB was too late */
1723 desc->status = -EXDEV;
1da177e4
LT		 1724 }
1725 }
1726
1da177e4
LT		 1727 /* handle completion now? */
1728 if (likely ((urb_index + 1) != urb->number_of_packets))
30bf54e6 1729 goto done;
1da177e4
LT		 1730
1731 /* ASSERT: it's really the last itd for this urb
1732 list_for_each_entry (itd, &stream->td_list, itd_list)
1733 BUG_ON (itd->urb == urb);
1734 */
1735
aa16ca30 1736 /* give urb back to the driver; completion often (re)submits */
6a8e87b2 1737 dev = urb->dev;
14c04c0f 1738 ehci_urb_done(ehci, urb, 0);
30bf54e6 1739 retval = true;
1da177e4 1740 urb = NULL;
01c17142 1741 (void) disable_periodic(ehci);
1da177e4
LT		 1742 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1743
508db8c9 1744 if (unlikely(list_is_singular(&stream->td_list))) {
1da177e4
LT		 1745 ehci_to_hcd(ehci)->self.bandwidth_allocated
1746 -= stream->bandwidth;
1747 ehci_vdbg (ehci,
1748 "deschedule devp %s ep%d%s-iso\n",
1749 dev->devpath, stream->bEndpointAddress & 0x0f,
1750 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1751 }
1752 iso_stream_put (ehci, stream);
9aa09d2f 1753
30bf54e6 1754done:
30bf54e6 1755 itd->urb = NULL;
9aa09d2f
KW		 1756 if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1757 /* OK to recycle this ITD now. */
1758 itd->stream = NULL;
1759 list_move(&itd->itd_list, &stream->free_list);
1760 iso_stream_put(ehci, stream);
1761 } else {
1762 /* HW might remember this ITD, so we can't recycle it yet.
1763 * Move it to a safe place until a new frame starts.
1764 */
1765 list_move(&itd->itd_list, &ehci->cached_itd_list);
1766 if (stream->refcount == 2) {
1767 /* If iso_stream_put() were called here, stream
1768 * would be freed. Instead, just prevent reuse.
1769 */
1770 stream->ep->hcpriv = NULL;
1771 stream->ep = NULL;
1772 }
1773 }
30bf54e6 1774 return retval;
1da177e4
LT		 1775}
1776
1777/*-------------------------------------------------------------------------*/
1778
5db539e4 1779static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
55016f10 1780 gfp_t mem_flags)
1da177e4
LT		 1781{
1782 int status = -EINVAL;
1783 unsigned long flags;
1784 struct ehci_iso_stream *stream;
1785
1786 /* Get iso_stream head */
1787 stream = iso_stream_find (ehci, urb);
1788 if (unlikely (stream == NULL)) {
1789 ehci_dbg (ehci, "can't get iso stream\n");
1790 return -ENOMEM;
1791 }
1792 if (unlikely (urb->interval != stream->interval)) {
1793 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1794 stream->interval, urb->interval);
1795 goto done;
1796 }
1797
1798#ifdef EHCI_URB_TRACE
1799 ehci_dbg (ehci,
1800 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
441b62c1 1801 __func__, urb->dev->devpath, urb,
1da177e4
LT		 1802 usb_pipeendpoint (urb->pipe),
1803 usb_pipein (urb->pipe) ? "in" : "out",
1804 urb->transfer_buffer_length,
1805 urb->number_of_packets, urb->interval,
1806 stream);
1807#endif
1808
1809 /* allocate ITDs w/o locking anything */
1810 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1811 if (unlikely (status < 0)) {
1812 ehci_dbg (ehci, "can't init itds\n");
1813 goto done;
1814 }
1815
1816 /* schedule ... need to lock */
1817 spin_lock_irqsave (&ehci->lock, flags);
8de98402 1818 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
e9df41c5 1819 &ehci_to_hcd(ehci)->flags))) {
8de98402 1820 status = -ESHUTDOWN;
e9df41c5
AS		 1821 goto done_not_linked;
1822 }
1823 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1824 if (unlikely(status))
1825 goto done_not_linked;
1826 status = iso_stream_schedule(ehci, urb, stream);
53bd6a60 1827 if (likely (status == 0))
1da177e4 1828 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
e9df41c5
AS		 1829 else
1830 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1831done_not_linked:
1da177e4
LT		 1832 spin_unlock_irqrestore (&ehci->lock, flags);
1833
1834done:
1835 if (unlikely (status < 0))
1836 iso_stream_put (ehci, stream);
1837 return status;
1838}
1839
1da177e4
LT		 1840/*-------------------------------------------------------------------------*/
1841
1842/*
1843 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1844 * TTs in USB 2.0 hubs. These need microframe scheduling.
1845 */
1846
1847static inline void
6dbd682b
SR		 1848sitd_sched_init(
1849 struct ehci_hcd *ehci,
1da177e4
LT		 1850 struct ehci_iso_sched *iso_sched,
1851 struct ehci_iso_stream *stream,
1852 struct urb *urb
1853)
1854{
1855 unsigned i;
1856 dma_addr_t dma = urb->transfer_dma;
1857
1858 /* how many frames are needed for these transfers */
1859 iso_sched->span = urb->number_of_packets * stream->interval;
1860
1861 /* figure out per-frame sitd fields that we'll need later
1862 * when we fit new sitds into the schedule.
1863 */
1864 for (i = 0; i < urb->number_of_packets; i++) {
1865 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1866 unsigned length;
1867 dma_addr_t buf;
1868 u32 trans;
1869
1870 length = urb->iso_frame_desc [i].length & 0x03ff;
1871 buf = dma + urb->iso_frame_desc [i].offset;
1872
1873 trans = SITD_STS_ACTIVE;
1874 if (((i + 1) == urb->number_of_packets)
1875 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1876 trans |= SITD_IOC;
1877 trans |= length << 16;
6dbd682b 1878 packet->transaction = cpu_to_hc32(ehci, trans);
1da177e4
LT		 1879
1880 /* might need to cross a buffer page within a td */
1881 packet->bufp = buf;
1882 packet->buf1 = (buf + length) & ~0x0fff;
1883 if (packet->buf1 != (buf & ~(u64)0x0fff))
1884 packet->cross = 1;
1885
53bd6a60 1886 /* OUT uses multiple start-splits */
1da177e4
LT		 1887 if (stream->bEndpointAddress & USB_DIR_IN)
1888 continue;
1889 length = (length + 187) / 188;
1890 if (length > 1) /* BEGIN vs ALL */
1891 length |= 1 << 3;
1892 packet->buf1 |= length;
1893 }
1894}
1895
1896static int
1897sitd_urb_transaction (
1898 struct ehci_iso_stream *stream,
1899 struct ehci_hcd *ehci,
1900 struct urb *urb,
55016f10 1901 gfp_t mem_flags
1da177e4
LT		 1902)
1903{
1904 struct ehci_sitd *sitd;
1905 dma_addr_t sitd_dma;
1906 int i;
1907 struct ehci_iso_sched *iso_sched;
1908 unsigned long flags;
1909
1910 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1911 if (iso_sched == NULL)
1912 return -ENOMEM;
1913
6dbd682b 1914 sitd_sched_init(ehci, iso_sched, stream, urb);
1da177e4
LT		 1915
1916 /* allocate/init sITDs */
1917 spin_lock_irqsave (&ehci->lock, flags);
1918 for (i = 0; i < urb->number_of_packets; i++) {
1919
1920 /* NOTE: for now, we don't try to handle wraparound cases
1921 * for IN (using sitd->hw_backpointer, like a FSTN), which
1922 * means we never need two sitds for full speed packets.
1923 */
1924
1925 /* free_list.next might be cache-hot ... but maybe
1926 * the HC caches it too. avoid that issue for now.
1927 */
1928
1929 /* prefer previously-allocated sitds */
1930 if (!list_empty(&stream->free_list)) {
1931 sitd = list_entry (stream->free_list.prev,
1932 struct ehci_sitd, sitd_list);
1933 list_del (&sitd->sitd_list);
1934 sitd_dma = sitd->sitd_dma;
3d01f0fe 1935 } else {
1da177e4
LT		 1936 spin_unlock_irqrestore (&ehci->lock, flags);
1937 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1938 &sitd_dma);
1939 spin_lock_irqsave (&ehci->lock, flags);
3d01f0fe
KW		 1940 if (!sitd) {
1941 iso_sched_free(stream, iso_sched);
1942 spin_unlock_irqrestore(&ehci->lock, flags);
1943 return -ENOMEM;
1944 }
1da177e4
LT		 1945 }
1946
1da177e4
LT		 1947 memset (sitd, 0, sizeof *sitd);
1948 sitd->sitd_dma = sitd_dma;
1949 list_add (&sitd->sitd_list, &iso_sched->td_list);
1950 }
1951
1952 /* temporarily store schedule info in hcpriv */
1953 urb->hcpriv = iso_sched;
1954 urb->error_count = 0;
1955
1956 spin_unlock_irqrestore (&ehci->lock, flags);
1957 return 0;
1958}
1959
1960/*-------------------------------------------------------------------------*/
1961
1962static inline void
6dbd682b
SR		 1963sitd_patch(
1964 struct ehci_hcd *ehci,
1da177e4
LT		 1965 struct ehci_iso_stream *stream,
1966 struct ehci_sitd *sitd,
1967 struct ehci_iso_sched *iso_sched,
1968 unsigned index
1969)
1970{
1971 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1972 u64 bufp = uf->bufp;
1973
6dbd682b 1974 sitd->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 1975 sitd->hw_fullspeed_ep = stream->address;
1976 sitd->hw_uframe = stream->splits;
1977 sitd->hw_results = uf->transaction;
6dbd682b 1978 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1da177e4
LT		 1979
1980 bufp = uf->bufp;
6dbd682b
SR		 1981 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1982 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1da177e4 1983
6dbd682b 1984 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1da177e4
LT		 1985 if (uf->cross)
1986 bufp += 4096;
6dbd682b 1987 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1da177e4
LT		 1988 sitd->index = index;
1989}
1990
1991static inline void
1992sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1993{
1994 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1995 sitd->sitd_next = ehci->pshadow [frame];
1996 sitd->hw_next = ehci->periodic [frame];
1997 ehci->pshadow [frame].sitd = sitd;
1998 sitd->frame = frame;
1999 wmb ();
6dbd682b 2000 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1da177e4
LT		 2001}
2002
2003/* fit urb's sitds into the selected schedule slot; activate as needed */
2004static int
2005sitd_link_urb (
2006 struct ehci_hcd *ehci,
2007 struct urb *urb,
2008 unsigned mod,
2009 struct ehci_iso_stream *stream
2010)
2011{
2012 int packet;
2013 unsigned next_uframe;
2014 struct ehci_iso_sched *sched = urb->hcpriv;
2015 struct ehci_sitd *sitd;
2016
2017 next_uframe = stream->next_uframe;
2018
2019 if (list_empty(&stream->td_list)) {
2020 /* usbfs ignores TT bandwidth */
2021 ehci_to_hcd(ehci)->self.bandwidth_allocated
2022 += stream->bandwidth;
2023 ehci_vdbg (ehci,
2024 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2025 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2026 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2027 (next_uframe >> 3) % ehci->periodic_size,
6dbd682b 2028 stream->interval, hc32_to_cpu(ehci, stream->splits));
1da177e4
LT		 2029 stream->start = jiffies;
2030 }
2031 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2032
2033 /* fill sITDs frame by frame */
2034 for (packet = 0, sitd = NULL;
2035 packet < urb->number_of_packets;
2036 packet++) {
2037
2038 /* ASSERT: we have all necessary sitds */
2039 BUG_ON (list_empty (&sched->td_list));
2040
2041 /* ASSERT: no itds for this endpoint in this frame */
2042
2043 sitd = list_entry (sched->td_list.next,
2044 struct ehci_sitd, sitd_list);
2045 list_move_tail (&sitd->sitd_list, &stream->td_list);
2046 sitd->stream = iso_stream_get (stream);
508db8c9 2047 sitd->urb = urb;
1da177e4 2048
6dbd682b 2049 sitd_patch(ehci, stream, sitd, sched, packet);
1da177e4
LT		 2050 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
2051 sitd);
2052
2053 next_uframe += stream->interval << 3;
2054 stream->depth += stream->interval << 3;
2055 }
2056 stream->next_uframe = next_uframe % mod;
2057
2058 /* don't need that schedule data any more */
2059 iso_sched_free (stream, sched);
2060 urb->hcpriv = NULL;
2061
2062 timer_action (ehci, TIMER_IO_WATCHDOG);
01c17142 2063 return enable_periodic(ehci);
1da177e4
LT		 2064}
2065
2066/*-------------------------------------------------------------------------*/
2067
2068#define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
53bd6a60 2069 | SITD_STS_XACT | SITD_STS_MMF)
1da177e4 2070
30bf54e6
DB		 2071/* Process and recycle a completed SITD. Return true iff its urb completed,
2072 * and hence its completion callback probably added things to the hardware
2073 * schedule.
2074 *
2075 * Note that we carefully avoid recycling this descriptor until after any
2076 * completion callback runs, so that it won't be reused quickly. That is,
2077 * assuming (a) no more than two urbs per frame on this endpoint, and also
2078 * (b) only this endpoint's completions submit URBs. It seems some silicon
2079 * corrupts things if you reuse completed descriptors very quickly...
2080 */
1da177e4
LT		 2081static unsigned
2082sitd_complete (
2083 struct ehci_hcd *ehci,
7d12e780 2084 struct ehci_sitd *sitd
1da177e4
LT		 2085) {
2086 struct urb *urb = sitd->urb;
2087 struct usb_iso_packet_descriptor *desc;
2088 u32 t;
2089 int urb_index = -1;
2090 struct ehci_iso_stream *stream = sitd->stream;
2091 struct usb_device *dev;
30bf54e6 2092 unsigned retval = false;
1da177e4
LT		 2093
2094 urb_index = sitd->index;
2095 desc = &urb->iso_frame_desc [urb_index];
6dbd682b 2096 t = hc32_to_cpup(ehci, &sitd->hw_results);
1da177e4
LT		 2097
2098 /* report transfer status */
2099 if (t & SITD_ERRS) {
2100 urb->error_count++;
2101 if (t & SITD_STS_DBE)
2102 desc->status = usb_pipein (urb->pipe)
2103 ? -ENOSR /* hc couldn't read */
2104 : -ECOMM; /* hc couldn't write */
2105 else if (t & SITD_STS_BABBLE)
2106 desc->status = -EOVERFLOW;
2107 else /* XACT, MMF, etc */
2108 desc->status = -EPROTO;
2109 } else {
2110 desc->status = 0;
ec6d67e3
AS		 2111 desc->actual_length = desc->length - SITD_LENGTH(t);
2112 urb->actual_length += desc->actual_length;
1da177e4 2113 }
1da177e4 2114 stream->depth -= stream->interval << 3;
1da177e4
LT		 2115
2116 /* handle completion now? */
2117 if ((urb_index + 1) != urb->number_of_packets)
30bf54e6 2118 goto done;
1da177e4
LT		 2119
2120 /* ASSERT: it's really the last sitd for this urb
2121 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2122 BUG_ON (sitd->urb == urb);
2123 */
2124
aa16ca30 2125 /* give urb back to the driver; completion often (re)submits */
6a8e87b2 2126 dev = urb->dev;
14c04c0f 2127 ehci_urb_done(ehci, urb, 0);
30bf54e6 2128 retval = true;
1da177e4 2129 urb = NULL;
01c17142 2130 (void) disable_periodic(ehci);
1da177e4
LT		 2131 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2132
508db8c9 2133 if (list_is_singular(&stream->td_list)) {
1da177e4
LT		 2134 ehci_to_hcd(ehci)->self.bandwidth_allocated
2135 -= stream->bandwidth;
2136 ehci_vdbg (ehci,
2137 "deschedule devp %s ep%d%s-iso\n",
2138 dev->devpath, stream->bEndpointAddress & 0x0f,
2139 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2140 }
2141 iso_stream_put (ehci, stream);
0e5f231b 2142
30bf54e6 2143done:
30bf54e6 2144 sitd->urb = NULL;
0e5f231b
AS		 2145 if (ehci->clock_frame != sitd->frame) {
2146 /* OK to recycle this SITD now. */
2147 sitd->stream = NULL;
2148 list_move(&sitd->sitd_list, &stream->free_list);
2149 iso_stream_put(ehci, stream);
2150 } else {
2151 /* HW might remember this SITD, so we can't recycle it yet.
2152 * Move it to a safe place until a new frame starts.
2153 */
2154 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2155 if (stream->refcount == 2) {
2156 /* If iso_stream_put() were called here, stream
2157 * would be freed. Instead, just prevent reuse.
2158 */
2159 stream->ep->hcpriv = NULL;
2160 stream->ep = NULL;
2161 }
2162 }
30bf54e6 2163 return retval;
1da177e4
LT		 2164}
2165
2166
5db539e4 2167static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
55016f10 2168 gfp_t mem_flags)
1da177e4
LT		 2169{
2170 int status = -EINVAL;
2171 unsigned long flags;
2172 struct ehci_iso_stream *stream;
2173
2174 /* Get iso_stream head */
2175 stream = iso_stream_find (ehci, urb);
2176 if (stream == NULL) {
2177 ehci_dbg (ehci, "can't get iso stream\n");
2178 return -ENOMEM;
2179 }
2180 if (urb->interval != stream->interval) {
2181 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2182 stream->interval, urb->interval);
2183 goto done;
2184 }
2185
2186#ifdef EHCI_URB_TRACE
2187 ehci_dbg (ehci,
2188 "submit %p dev%s ep%d%s-iso len %d\n",
2189 urb, urb->dev->devpath,
2190 usb_pipeendpoint (urb->pipe),
2191 usb_pipein (urb->pipe) ? "in" : "out",
2192 urb->transfer_buffer_length);
2193#endif
2194
2195 /* allocate SITDs */
2196 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2197 if (status < 0) {
2198 ehci_dbg (ehci, "can't init sitds\n");
2199 goto done;
2200 }
2201
2202 /* schedule ... need to lock */
2203 spin_lock_irqsave (&ehci->lock, flags);
8de98402 2204 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
e9df41c5 2205 &ehci_to_hcd(ehci)->flags))) {
8de98402 2206 status = -ESHUTDOWN;
e9df41c5
AS		 2207 goto done_not_linked;
2208 }
2209 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2210 if (unlikely(status))
2211 goto done_not_linked;
2212 status = iso_stream_schedule(ehci, urb, stream);
53bd6a60 2213 if (status == 0)
1da177e4 2214 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
e9df41c5
AS		 2215 else
2216 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2217done_not_linked:
1da177e4
LT		 2218 spin_unlock_irqrestore (&ehci->lock, flags);
2219
2220done:
2221 if (status < 0)
2222 iso_stream_put (ehci, stream);
2223 return status;
2224}
2225
1da177e4
LT		 2226/*-------------------------------------------------------------------------*/
2227
0e5f231b 2228static void free_cached_lists(struct ehci_hcd *ehci)
9aa09d2f
KW		 2229{
2230 struct ehci_itd *itd, *n;
0e5f231b 2231 struct ehci_sitd *sitd, *sn;
9aa09d2f
KW		 2232
2233 list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2234 struct ehci_iso_stream *stream = itd->stream;
2235 itd->stream = NULL;
2236 list_move(&itd->itd_list, &stream->free_list);
2237 iso_stream_put(ehci, stream);
2238 }
0e5f231b
AS		 2239
2240 list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2241 struct ehci_iso_stream *stream = sitd->stream;
2242 sitd->stream = NULL;
2243 list_move(&sitd->sitd_list, &stream->free_list);
2244 iso_stream_put(ehci, stream);
2245 }
9aa09d2f
KW		 2246}
2247
2248/*-------------------------------------------------------------------------*/
2249
1da177e4 2250static void
7d12e780 2251scan_periodic (struct ehci_hcd *ehci)
1da177e4 2252{
b40e43fc 2253 unsigned now_uframe, frame, clock, clock_frame, mod;
1da177e4
LT		 2254 unsigned modified;
2255
2256 mod = ehci->periodic_size << 3;
2257
2258 /*
2259 * When running, scan from last scan point up to "now"
2260 * else clean up by scanning everything that's left.
2261 * Touches as few pages as possible: cache-friendly.
2262 */
2263 now_uframe = ehci->next_uframe;
9aa09d2f 2264 if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
083522d7 2265 clock = ehci_readl(ehci, &ehci->regs->frame_index);
9aa09d2f
KW		 2266 clock_frame = (clock >> 3) % ehci->periodic_size;
2267 } else {
1da177e4 2268 clock = now_uframe + mod - 1;
9aa09d2f
KW		 2269 clock_frame = -1;
2270 }
2271 if (ehci->clock_frame != clock_frame) {
0e5f231b 2272 free_cached_lists(ehci);
9aa09d2f
KW		 2273 ehci->clock_frame = clock_frame;
2274 }
1da177e4 2275 clock %= mod;
b40e43fc 2276 clock_frame = clock >> 3;
1da177e4
LT		 2277
2278 for (;;) {
2279 union ehci_shadow q, *q_p;
6dbd682b 2280 __hc32 type, *hw_p;
79592b72 2281 unsigned incomplete = false;
1da177e4 2282
1da177e4 2283 frame = now_uframe >> 3;
1da177e4
LT		 2284
2285restart:
2286 /* scan each element in frame's queue for completions */
2287 q_p = &ehci->pshadow [frame];
2288 hw_p = &ehci->periodic [frame];
2289 q.ptr = q_p->ptr;
6dbd682b 2290 type = Q_NEXT_TYPE(ehci, *hw_p);
1da177e4
LT		 2291 modified = 0;
2292
2293 while (q.ptr != NULL) {
2294 unsigned uf;
2295 union ehci_shadow temp;
2296 int live;
2297
2298 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
6dbd682b 2299 switch (hc32_to_cpu(ehci, type)) {
1da177e4
LT		 2300 case Q_TYPE_QH:
2301 /* handle any completions */
2302 temp.qh = qh_get (q.qh);
3807e26d 2303 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
1da177e4 2304 q = q.qh->qh_next;
7d12e780 2305 modified = qh_completions (ehci, temp.qh);
a448c9d8
AS		 2306 if (unlikely(list_empty(&temp.qh->qtd_list) ||
2307 temp.qh->needs_rescan))
1da177e4
LT		 2308 intr_deschedule (ehci, temp.qh);
2309 qh_put (temp.qh);
2310 break;
2311 case Q_TYPE_FSTN:
2312 /* for "save place" FSTNs, look at QH entries
2313 * in the previous frame for completions.
2314 */
6dbd682b 2315 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
1da177e4
LT		 2316 dbg ("ignoring completions from FSTNs");
2317 }
6dbd682b 2318 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
1da177e4
LT		 2319 q = q.fstn->fstn_next;
2320 break;
2321 case Q_TYPE_ITD:
79592b72
DB		 2322 /* If this ITD is still active, leave it for
2323 * later processing ... check the next entry.
b40e43fc
AS		 2324 * No need to check for activity unless the
2325 * frame is current.
79592b72 2326 */
b40e43fc
AS		 2327 if (frame == clock_frame && live) {
2328 rmb();
2329 for (uf = 0; uf < 8; uf++) {
2330 if (q.itd->hw_transaction[uf] &
2331 ITD_ACTIVE(ehci))
2332 break;
2333 }
2334 if (uf < 8) {
2335 incomplete = true;
2336 q_p = &q.itd->itd_next;
2337 hw_p = &q.itd->hw_next;
2338 type = Q_NEXT_TYPE(ehci,
6dbd682b 2339 q.itd->hw_next);
b40e43fc
AS		 2340 q = *q_p;
2341 break;
2342 }
1da177e4 2343 }
1da177e4 2344
79592b72
DB		 2345 /* Take finished ITDs out of the schedule
2346 * and process them: recycle, maybe report
2347 * URB completion. HC won't cache the
1da177e4
LT		 2348 * pointer for much longer, if at all.
2349 */
2350 *q_p = q.itd->itd_next;
2351 *hw_p = q.itd->hw_next;
6dbd682b 2352 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
1da177e4 2353 wmb();
7d12e780 2354 modified = itd_complete (ehci, q.itd);
1da177e4
LT		 2355 q = *q_p;
2356 break;
2357 case Q_TYPE_SITD:
79592b72
DB		 2358 /* If this SITD is still active, leave it for
2359 * later processing ... check the next entry.
b40e43fc
AS		 2360 * No need to check for activity unless the
2361 * frame is current.
79592b72 2362 */
22e18694
DE		 2363 if (((frame == clock_frame) ||
2364 (((frame + 1) % ehci->periodic_size)
2365 == clock_frame))
2366 && live
2367 && (q.sitd->hw_results &
2368 SITD_ACTIVE(ehci))) {
2369
79592b72 2370 incomplete = true;
1da177e4
LT		 2371 q_p = &q.sitd->sitd_next;
2372 hw_p = &q.sitd->hw_next;
6dbd682b
SR		 2373 type = Q_NEXT_TYPE(ehci,
2374 q.sitd->hw_next);
1da177e4
LT		 2375 q = *q_p;
2376 break;
2377 }
79592b72
DB		 2378
2379 /* Take finished SITDs out of the schedule
2380 * and process them: recycle, maybe report
2381 * URB completion.
2382 */
1da177e4
LT		 2383 *q_p = q.sitd->sitd_next;
2384 *hw_p = q.sitd->hw_next;
6dbd682b 2385 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
1da177e4 2386 wmb();
7d12e780 2387 modified = sitd_complete (ehci, q.sitd);
1da177e4
LT		 2388 q = *q_p;
2389 break;
2390 default:
2391 dbg ("corrupt type %d frame %d shadow %p",
2392 type, frame, q.ptr);
2393 // BUG ();
2394 q.ptr = NULL;
2395 }
2396
2397 /* assume completion callbacks modify the queue */
aa16ca30
DB		 2398 if (unlikely (modified)) {
2399 if (likely(ehci->periodic_sched > 0))
2400 goto restart;
01c17142 2401 /* short-circuit this scan */
aa16ca30
DB		 2402 now_uframe = clock;
2403 break;
2404 }
1da177e4
LT		 2405 }
2406
79592b72
DB		 2407 /* If we can tell we caught up to the hardware, stop now.
2408 * We can't advance our scan without collecting the ISO
2409 * transfers that are still pending in this frame.
2410 */
2411 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2412 ehci->next_uframe = now_uframe;
2413 break;
2414 }
1da177e4
LT		 2415
2416 // FIXME: this assumes we won't get lapped when
2417 // latencies climb; that should be rare, but...
2418 // detect it, and just go all the way around.
2419 // FLR might help detect this case, so long as latencies
2420 // don't exceed periodic_size msec (default 1.024 sec).
2421
2422 // FIXME: likewise assumes HC doesn't halt mid-scan
2423
2424 if (now_uframe == clock) {
2425 unsigned now;
2426
aa16ca30
DB		 2427 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2428 || ehci->periodic_sched == 0)
1da177e4
LT		 2429 break;
2430 ehci->next_uframe = now_uframe;
083522d7 2431 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1da177e4
LT		 2432 if (now_uframe == now)
2433 break;
2434
2435 /* rescan the rest of this frame, then ... */
2436 clock = now;
b40e43fc 2437 clock_frame = clock >> 3;
9aa09d2f 2438 if (ehci->clock_frame != clock_frame) {
0e5f231b 2439 free_cached_lists(ehci);
9aa09d2f
KW		 2440 ehci->clock_frame = clock_frame;
2441 }
1da177e4
LT		 2442 } else {
2443 now_uframe++;
2444 now_uframe %= mod;
2445 }
53bd6a60 2446 }
1da177e4 2447}
Linux kernel - Deliverables
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