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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2001-2004 by David Brownell | |
3 | * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers | |
53bd6a60 | 4 | * |
1da177e4 LT |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software Foundation, | |
17 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | /* this file is part of ehci-hcd.c */ | |
21 | ||
22 | /*-------------------------------------------------------------------------*/ | |
23 | ||
24 | /* | |
25 | * EHCI scheduled transaction support: interrupt, iso, split iso | |
26 | * These are called "periodic" transactions in the EHCI spec. | |
27 | * | |
28 | * Note that for interrupt transfers, the QH/QTD manipulation is shared | |
29 | * with the "asynchronous" transaction support (control/bulk transfers). | |
30 | * The only real difference is in how interrupt transfers are scheduled. | |
31 | * | |
32 | * For ISO, we make an "iso_stream" head to serve the same role as a QH. | |
33 | * It keeps track of every ITD (or SITD) that's linked, and holds enough | |
34 | * pre-calculated schedule data to make appending to the queue be quick. | |
35 | */ | |
36 | ||
37 | static int ehci_get_frame (struct usb_hcd *hcd); | |
38 | ||
39 | /*-------------------------------------------------------------------------*/ | |
40 | ||
41 | /* | |
42 | * periodic_next_shadow - return "next" pointer on shadow list | |
43 | * @periodic: host pointer to qh/itd/sitd | |
44 | * @tag: hardware tag for type of this record | |
45 | */ | |
46 | static union ehci_shadow * | |
6dbd682b SR |
47 | periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic, |
48 | __hc32 tag) | |
1da177e4 | 49 | { |
6dbd682b | 50 | switch (hc32_to_cpu(ehci, tag)) { |
1da177e4 LT |
51 | case Q_TYPE_QH: |
52 | return &periodic->qh->qh_next; | |
53 | case Q_TYPE_FSTN: | |
54 | return &periodic->fstn->fstn_next; | |
55 | case Q_TYPE_ITD: | |
56 | return &periodic->itd->itd_next; | |
57 | // case Q_TYPE_SITD: | |
58 | default: | |
59 | return &periodic->sitd->sitd_next; | |
60 | } | |
61 | } | |
62 | ||
3807e26d AD |
63 | static __hc32 * |
64 | shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic, | |
65 | __hc32 tag) | |
66 | { | |
67 | switch (hc32_to_cpu(ehci, tag)) { | |
68 | /* our ehci_shadow.qh is actually software part */ | |
69 | case Q_TYPE_QH: | |
70 | return &periodic->qh->hw->hw_next; | |
71 | /* others are hw parts */ | |
72 | default: | |
73 | return periodic->hw_next; | |
74 | } | |
75 | } | |
76 | ||
1da177e4 LT |
77 | /* caller must hold ehci->lock */ |
78 | static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr) | |
79 | { | |
6dbd682b SR |
80 | union ehci_shadow *prev_p = &ehci->pshadow[frame]; |
81 | __hc32 *hw_p = &ehci->periodic[frame]; | |
1da177e4 LT |
82 | union ehci_shadow here = *prev_p; |
83 | ||
84 | /* find predecessor of "ptr"; hw and shadow lists are in sync */ | |
85 | while (here.ptr && here.ptr != ptr) { | |
6dbd682b SR |
86 | prev_p = periodic_next_shadow(ehci, prev_p, |
87 | Q_NEXT_TYPE(ehci, *hw_p)); | |
3807e26d AD |
88 | hw_p = shadow_next_periodic(ehci, &here, |
89 | Q_NEXT_TYPE(ehci, *hw_p)); | |
1da177e4 LT |
90 | here = *prev_p; |
91 | } | |
92 | /* an interrupt entry (at list end) could have been shared */ | |
93 | if (!here.ptr) | |
94 | return; | |
95 | ||
96 | /* update shadow and hardware lists ... the old "next" pointers | |
97 | * from ptr may still be in use, the caller updates them. | |
98 | */ | |
6dbd682b SR |
99 | *prev_p = *periodic_next_shadow(ehci, &here, |
100 | Q_NEXT_TYPE(ehci, *hw_p)); | |
3d091a6f AX |
101 | |
102 | if (!ehci->use_dummy_qh || | |
103 | *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p)) | |
104 | != EHCI_LIST_END(ehci)) | |
105 | *hw_p = *shadow_next_periodic(ehci, &here, | |
106 | Q_NEXT_TYPE(ehci, *hw_p)); | |
107 | else | |
108 | *hw_p = ehci->dummy->qh_dma; | |
1da177e4 LT |
109 | } |
110 | ||
111 | /* how many of the uframe's 125 usecs are allocated? */ | |
112 | static unsigned short | |
113 | periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe) | |
114 | { | |
6dbd682b | 115 | __hc32 *hw_p = &ehci->periodic [frame]; |
1da177e4 LT |
116 | union ehci_shadow *q = &ehci->pshadow [frame]; |
117 | unsigned usecs = 0; | |
3807e26d | 118 | struct ehci_qh_hw *hw; |
1da177e4 LT |
119 | |
120 | while (q->ptr) { | |
6dbd682b | 121 | switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) { |
1da177e4 | 122 | case Q_TYPE_QH: |
3807e26d | 123 | hw = q->qh->hw; |
1da177e4 | 124 | /* is it in the S-mask? */ |
3807e26d | 125 | if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe)) |
1da177e4 LT |
126 | usecs += q->qh->usecs; |
127 | /* ... or C-mask? */ | |
3807e26d | 128 | if (hw->hw_info2 & cpu_to_hc32(ehci, |
6dbd682b | 129 | 1 << (8 + uframe))) |
1da177e4 | 130 | usecs += q->qh->c_usecs; |
3807e26d | 131 | hw_p = &hw->hw_next; |
1da177e4 LT |
132 | q = &q->qh->qh_next; |
133 | break; | |
134 | // case Q_TYPE_FSTN: | |
135 | default: | |
136 | /* for "save place" FSTNs, count the relevant INTR | |
137 | * bandwidth from the previous frame | |
138 | */ | |
6dbd682b | 139 | if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) { |
1da177e4 LT |
140 | ehci_dbg (ehci, "ignoring FSTN cost ...\n"); |
141 | } | |
142 | hw_p = &q->fstn->hw_next; | |
143 | q = &q->fstn->fstn_next; | |
144 | break; | |
145 | case Q_TYPE_ITD: | |
3b6fcfd0 KW |
146 | if (q->itd->hw_transaction[uframe]) |
147 | usecs += q->itd->stream->usecs; | |
1da177e4 LT |
148 | hw_p = &q->itd->hw_next; |
149 | q = &q->itd->itd_next; | |
150 | break; | |
151 | case Q_TYPE_SITD: | |
152 | /* is it in the S-mask? (count SPLIT, DATA) */ | |
6dbd682b SR |
153 | if (q->sitd->hw_uframe & cpu_to_hc32(ehci, |
154 | 1 << uframe)) { | |
1da177e4 | 155 | if (q->sitd->hw_fullspeed_ep & |
6dbd682b | 156 | cpu_to_hc32(ehci, 1<<31)) |
1da177e4 LT |
157 | usecs += q->sitd->stream->usecs; |
158 | else /* worst case for OUT start-split */ | |
159 | usecs += HS_USECS_ISO (188); | |
160 | } | |
161 | ||
162 | /* ... C-mask? (count CSPLIT, DATA) */ | |
163 | if (q->sitd->hw_uframe & | |
6dbd682b | 164 | cpu_to_hc32(ehci, 1 << (8 + uframe))) { |
1da177e4 LT |
165 | /* worst case for IN complete-split */ |
166 | usecs += q->sitd->stream->c_usecs; | |
167 | } | |
168 | ||
169 | hw_p = &q->sitd->hw_next; | |
170 | q = &q->sitd->sitd_next; | |
171 | break; | |
172 | } | |
173 | } | |
174 | #ifdef DEBUG | |
175 | if (usecs > 100) | |
176 | ehci_err (ehci, "uframe %d sched overrun: %d usecs\n", | |
177 | frame * 8 + uframe, usecs); | |
178 | #endif | |
179 | return usecs; | |
180 | } | |
181 | ||
182 | /*-------------------------------------------------------------------------*/ | |
183 | ||
184 | static int same_tt (struct usb_device *dev1, struct usb_device *dev2) | |
185 | { | |
186 | if (!dev1->tt || !dev2->tt) | |
187 | return 0; | |
188 | if (dev1->tt != dev2->tt) | |
189 | return 0; | |
190 | if (dev1->tt->multi) | |
191 | return dev1->ttport == dev2->ttport; | |
192 | else | |
193 | return 1; | |
194 | } | |
195 | ||
ba47f66b DS |
196 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED |
197 | ||
198 | /* Which uframe does the low/fullspeed transfer start in? | |
199 | * | |
200 | * The parameter is the mask of ssplits in "H-frame" terms | |
201 | * and this returns the transfer start uframe in "B-frame" terms, | |
202 | * which allows both to match, e.g. a ssplit in "H-frame" uframe 0 | |
203 | * will cause a transfer in "B-frame" uframe 0. "B-frames" lag | |
204 | * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7. | |
205 | */ | |
6dbd682b | 206 | static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask) |
ba47f66b | 207 | { |
6dbd682b | 208 | unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask); |
ba47f66b DS |
209 | if (!smask) { |
210 | ehci_err(ehci, "invalid empty smask!\n"); | |
211 | /* uframe 7 can't have bw so this will indicate failure */ | |
212 | return 7; | |
213 | } | |
214 | return ffs(smask) - 1; | |
215 | } | |
216 | ||
217 | static const unsigned char | |
218 | max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 }; | |
219 | ||
220 | /* carryover low/fullspeed bandwidth that crosses uframe boundries */ | |
221 | static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8]) | |
222 | { | |
223 | int i; | |
224 | for (i=0; i<7; i++) { | |
225 | if (max_tt_usecs[i] < tt_usecs[i]) { | |
226 | tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i]; | |
227 | tt_usecs[i] = max_tt_usecs[i]; | |
228 | } | |
229 | } | |
230 | } | |
231 | ||
232 | /* How many of the tt's periodic downstream 1000 usecs are allocated? | |
233 | * | |
234 | * While this measures the bandwidth in terms of usecs/uframe, | |
235 | * the low/fullspeed bus has no notion of uframes, so any particular | |
236 | * low/fullspeed transfer can "carry over" from one uframe to the next, | |
237 | * since the TT just performs downstream transfers in sequence. | |
238 | * | |
dc0d5c1e | 239 | * For example two separate 100 usec transfers can start in the same uframe, |
ba47f66b DS |
240 | * and the second one would "carry over" 75 usecs into the next uframe. |
241 | */ | |
242 | static void | |
243 | periodic_tt_usecs ( | |
244 | struct ehci_hcd *ehci, | |
245 | struct usb_device *dev, | |
246 | unsigned frame, | |
247 | unsigned short tt_usecs[8] | |
248 | ) | |
249 | { | |
6dbd682b | 250 | __hc32 *hw_p = &ehci->periodic [frame]; |
ba47f66b DS |
251 | union ehci_shadow *q = &ehci->pshadow [frame]; |
252 | unsigned char uf; | |
253 | ||
254 | memset(tt_usecs, 0, 16); | |
255 | ||
256 | while (q->ptr) { | |
6dbd682b | 257 | switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) { |
ba47f66b DS |
258 | case Q_TYPE_ITD: |
259 | hw_p = &q->itd->hw_next; | |
260 | q = &q->itd->itd_next; | |
261 | continue; | |
262 | case Q_TYPE_QH: | |
263 | if (same_tt(dev, q->qh->dev)) { | |
3807e26d | 264 | uf = tt_start_uframe(ehci, q->qh->hw->hw_info2); |
ba47f66b DS |
265 | tt_usecs[uf] += q->qh->tt_usecs; |
266 | } | |
3807e26d | 267 | hw_p = &q->qh->hw->hw_next; |
ba47f66b DS |
268 | q = &q->qh->qh_next; |
269 | continue; | |
270 | case Q_TYPE_SITD: | |
271 | if (same_tt(dev, q->sitd->urb->dev)) { | |
272 | uf = tt_start_uframe(ehci, q->sitd->hw_uframe); | |
273 | tt_usecs[uf] += q->sitd->stream->tt_usecs; | |
274 | } | |
275 | hw_p = &q->sitd->hw_next; | |
276 | q = &q->sitd->sitd_next; | |
277 | continue; | |
278 | // case Q_TYPE_FSTN: | |
279 | default: | |
6dbd682b SR |
280 | ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n", |
281 | frame); | |
ba47f66b DS |
282 | hw_p = &q->fstn->hw_next; |
283 | q = &q->fstn->fstn_next; | |
284 | } | |
285 | } | |
286 | ||
287 | carryover_tt_bandwidth(tt_usecs); | |
288 | ||
289 | if (max_tt_usecs[7] < tt_usecs[7]) | |
290 | ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n", | |
291 | frame, tt_usecs[7] - max_tt_usecs[7]); | |
292 | } | |
293 | ||
294 | /* | |
295 | * Return true if the device's tt's downstream bus is available for a | |
296 | * periodic transfer of the specified length (usecs), starting at the | |
297 | * specified frame/uframe. Note that (as summarized in section 11.19 | |
298 | * of the usb 2.0 spec) TTs can buffer multiple transactions for each | |
299 | * uframe. | |
300 | * | |
301 | * The uframe parameter is when the fullspeed/lowspeed transfer | |
302 | * should be executed in "B-frame" terms, which is the same as the | |
303 | * highspeed ssplit's uframe (which is in "H-frame" terms). For example | |
304 | * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0. | |
305 | * See the EHCI spec sec 4.5 and fig 4.7. | |
306 | * | |
307 | * This checks if the full/lowspeed bus, at the specified starting uframe, | |
308 | * has the specified bandwidth available, according to rules listed | |
309 | * in USB 2.0 spec section 11.18.1 fig 11-60. | |
310 | * | |
311 | * This does not check if the transfer would exceed the max ssplit | |
312 | * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4, | |
313 | * since proper scheduling limits ssplits to less than 16 per uframe. | |
314 | */ | |
315 | static int tt_available ( | |
316 | struct ehci_hcd *ehci, | |
317 | unsigned period, | |
318 | struct usb_device *dev, | |
319 | unsigned frame, | |
320 | unsigned uframe, | |
321 | u16 usecs | |
322 | ) | |
323 | { | |
324 | if ((period == 0) || (uframe >= 7)) /* error */ | |
325 | return 0; | |
326 | ||
327 | for (; frame < ehci->periodic_size; frame += period) { | |
328 | unsigned short tt_usecs[8]; | |
329 | ||
330 | periodic_tt_usecs (ehci, dev, frame, tt_usecs); | |
331 | ||
332 | ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in" | |
333 | " schedule %d/%d/%d/%d/%d/%d/%d/%d\n", | |
334 | frame, usecs, uframe, | |
335 | tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3], | |
336 | tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]); | |
337 | ||
338 | if (max_tt_usecs[uframe] <= tt_usecs[uframe]) { | |
339 | ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n", | |
340 | frame, uframe); | |
341 | return 0; | |
342 | } | |
343 | ||
344 | /* special case for isoc transfers larger than 125us: | |
345 | * the first and each subsequent fully used uframe | |
346 | * must be empty, so as to not illegally delay | |
347 | * already scheduled transactions | |
348 | */ | |
349 | if (125 < usecs) { | |
c065c60e | 350 | int ufs = (usecs / 125); |
ba47f66b DS |
351 | int i; |
352 | for (i = uframe; i < (uframe + ufs) && i < 8; i++) | |
353 | if (0 < tt_usecs[i]) { | |
354 | ehci_vdbg(ehci, | |
355 | "multi-uframe xfer can't fit " | |
356 | "in frame %d uframe %d\n", | |
357 | frame, i); | |
358 | return 0; | |
359 | } | |
360 | } | |
361 | ||
362 | tt_usecs[uframe] += usecs; | |
363 | ||
364 | carryover_tt_bandwidth(tt_usecs); | |
365 | ||
366 | /* fail if the carryover pushed bw past the last uframe's limit */ | |
367 | if (max_tt_usecs[7] < tt_usecs[7]) { | |
368 | ehci_vdbg(ehci, | |
369 | "tt unavailable usecs %d frame %d uframe %d\n", | |
370 | usecs, frame, uframe); | |
371 | return 0; | |
372 | } | |
373 | } | |
374 | ||
375 | return 1; | |
376 | } | |
377 | ||
378 | #else | |
379 | ||
1da177e4 LT |
380 | /* return true iff the device's transaction translator is available |
381 | * for a periodic transfer starting at the specified frame, using | |
382 | * all the uframes in the mask. | |
383 | */ | |
384 | static int tt_no_collision ( | |
385 | struct ehci_hcd *ehci, | |
386 | unsigned period, | |
387 | struct usb_device *dev, | |
388 | unsigned frame, | |
389 | u32 uf_mask | |
390 | ) | |
391 | { | |
392 | if (period == 0) /* error */ | |
393 | return 0; | |
394 | ||
395 | /* note bandwidth wastage: split never follows csplit | |
396 | * (different dev or endpoint) until the next uframe. | |
397 | * calling convention doesn't make that distinction. | |
398 | */ | |
399 | for (; frame < ehci->periodic_size; frame += period) { | |
400 | union ehci_shadow here; | |
6dbd682b | 401 | __hc32 type; |
3807e26d | 402 | struct ehci_qh_hw *hw; |
1da177e4 LT |
403 | |
404 | here = ehci->pshadow [frame]; | |
6dbd682b | 405 | type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]); |
1da177e4 | 406 | while (here.ptr) { |
6dbd682b | 407 | switch (hc32_to_cpu(ehci, type)) { |
1da177e4 | 408 | case Q_TYPE_ITD: |
6dbd682b | 409 | type = Q_NEXT_TYPE(ehci, here.itd->hw_next); |
1da177e4 LT |
410 | here = here.itd->itd_next; |
411 | continue; | |
412 | case Q_TYPE_QH: | |
3807e26d | 413 | hw = here.qh->hw; |
1da177e4 LT |
414 | if (same_tt (dev, here.qh->dev)) { |
415 | u32 mask; | |
416 | ||
6dbd682b | 417 | mask = hc32_to_cpu(ehci, |
3807e26d | 418 | hw->hw_info2); |
1da177e4 LT |
419 | /* "knows" no gap is needed */ |
420 | mask |= mask >> 8; | |
421 | if (mask & uf_mask) | |
422 | break; | |
423 | } | |
3807e26d | 424 | type = Q_NEXT_TYPE(ehci, hw->hw_next); |
1da177e4 LT |
425 | here = here.qh->qh_next; |
426 | continue; | |
427 | case Q_TYPE_SITD: | |
428 | if (same_tt (dev, here.sitd->urb->dev)) { | |
429 | u16 mask; | |
430 | ||
6dbd682b | 431 | mask = hc32_to_cpu(ehci, here.sitd |
1da177e4 LT |
432 | ->hw_uframe); |
433 | /* FIXME assumes no gap for IN! */ | |
434 | mask |= mask >> 8; | |
435 | if (mask & uf_mask) | |
436 | break; | |
437 | } | |
6dbd682b | 438 | type = Q_NEXT_TYPE(ehci, here.sitd->hw_next); |
1da177e4 LT |
439 | here = here.sitd->sitd_next; |
440 | continue; | |
441 | // case Q_TYPE_FSTN: | |
442 | default: | |
443 | ehci_dbg (ehci, | |
444 | "periodic frame %d bogus type %d\n", | |
445 | frame, type); | |
446 | } | |
447 | ||
448 | /* collision or error */ | |
449 | return 0; | |
450 | } | |
451 | } | |
452 | ||
453 | /* no collision */ | |
454 | return 1; | |
455 | } | |
456 | ||
ba47f66b DS |
457 | #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */ |
458 | ||
1da177e4 LT |
459 | /*-------------------------------------------------------------------------*/ |
460 | ||
461 | static int enable_periodic (struct ehci_hcd *ehci) | |
462 | { | |
463 | u32 cmd; | |
464 | int status; | |
465 | ||
01c17142 DB |
466 | if (ehci->periodic_sched++) |
467 | return 0; | |
468 | ||
1da177e4 LT |
469 | /* did clearing PSE did take effect yet? |
470 | * takes effect only at frame boundaries... | |
471 | */ | |
c765d4ca KW |
472 | status = handshake_on_error_set_halt(ehci, &ehci->regs->status, |
473 | STS_PSS, 0, 9 * 125); | |
69fff59d AS |
474 | if (status) { |
475 | usb_hc_died(ehci_to_hcd(ehci)); | |
1da177e4 | 476 | return status; |
69fff59d | 477 | } |
1da177e4 | 478 | |
083522d7 BH |
479 | cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE; |
480 | ehci_writel(ehci, cmd, &ehci->regs->command); | |
1da177e4 LT |
481 | /* posted write ... PSS happens later */ |
482 | ehci_to_hcd(ehci)->state = HC_STATE_RUNNING; | |
483 | ||
484 | /* make sure ehci_work scans these */ | |
083522d7 BH |
485 | ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index) |
486 | % (ehci->periodic_size << 3); | |
ee4ecb8a ON |
487 | if (unlikely(ehci->broken_periodic)) |
488 | ehci->last_periodic_enable = ktime_get_real(); | |
1da177e4 LT |
489 | return 0; |
490 | } | |
491 | ||
492 | static int disable_periodic (struct ehci_hcd *ehci) | |
493 | { | |
494 | u32 cmd; | |
495 | int status; | |
496 | ||
01c17142 DB |
497 | if (--ehci->periodic_sched) |
498 | return 0; | |
499 | ||
ee4ecb8a ON |
500 | if (unlikely(ehci->broken_periodic)) { |
501 | /* delay experimentally determined */ | |
502 | ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000); | |
503 | ktime_t now = ktime_get_real(); | |
504 | s64 delay = ktime_us_delta(safe, now); | |
505 | ||
506 | if (unlikely(delay > 0)) | |
507 | udelay(delay); | |
508 | } | |
509 | ||
1da177e4 LT |
510 | /* did setting PSE not take effect yet? |
511 | * takes effect only at frame boundaries... | |
512 | */ | |
c765d4ca KW |
513 | status = handshake_on_error_set_halt(ehci, &ehci->regs->status, |
514 | STS_PSS, STS_PSS, 9 * 125); | |
69fff59d AS |
515 | if (status) { |
516 | usb_hc_died(ehci_to_hcd(ehci)); | |
1da177e4 | 517 | return status; |
69fff59d | 518 | } |
1da177e4 | 519 | |
083522d7 BH |
520 | cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE; |
521 | ehci_writel(ehci, cmd, &ehci->regs->command); | |
1da177e4 LT |
522 | /* posted write ... */ |
523 | ||
0e5f231b | 524 | free_cached_lists(ehci); |
d63c66d2 | 525 | |
1da177e4 LT |
526 | ehci->next_uframe = -1; |
527 | return 0; | |
528 | } | |
529 | ||
530 | /*-------------------------------------------------------------------------*/ | |
531 | ||
532 | /* periodic schedule slots have iso tds (normal or split) first, then a | |
533 | * sparse tree for active interrupt transfers. | |
534 | * | |
535 | * this just links in a qh; caller guarantees uframe masks are set right. | |
536 | * no FSTN support (yet; ehci 0.96+) | |
537 | */ | |
538 | static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
539 | { | |
540 | unsigned i; | |
541 | unsigned period = qh->period; | |
542 | ||
543 | dev_dbg (&qh->dev->dev, | |
544 | "link qh%d-%04x/%p start %d [%d/%d us]\n", | |
3807e26d AD |
545 | period, hc32_to_cpup(ehci, &qh->hw->hw_info2) |
546 | & (QH_CMASK | QH_SMASK), | |
1da177e4 LT |
547 | qh, qh->start, qh->usecs, qh->c_usecs); |
548 | ||
549 | /* high bandwidth, or otherwise every microframe */ | |
550 | if (period == 0) | |
551 | period = 1; | |
552 | ||
553 | for (i = qh->start; i < ehci->periodic_size; i += period) { | |
6dbd682b SR |
554 | union ehci_shadow *prev = &ehci->pshadow[i]; |
555 | __hc32 *hw_p = &ehci->periodic[i]; | |
1da177e4 | 556 | union ehci_shadow here = *prev; |
6dbd682b | 557 | __hc32 type = 0; |
1da177e4 LT |
558 | |
559 | /* skip the iso nodes at list head */ | |
560 | while (here.ptr) { | |
6dbd682b SR |
561 | type = Q_NEXT_TYPE(ehci, *hw_p); |
562 | if (type == cpu_to_hc32(ehci, Q_TYPE_QH)) | |
1da177e4 | 563 | break; |
6dbd682b | 564 | prev = periodic_next_shadow(ehci, prev, type); |
3807e26d | 565 | hw_p = shadow_next_periodic(ehci, &here, type); |
1da177e4 LT |
566 | here = *prev; |
567 | } | |
568 | ||
569 | /* sorting each branch by period (slow-->fast) | |
570 | * enables sharing interior tree nodes | |
571 | */ | |
572 | while (here.ptr && qh != here.qh) { | |
573 | if (qh->period > here.qh->period) | |
574 | break; | |
575 | prev = &here.qh->qh_next; | |
3807e26d | 576 | hw_p = &here.qh->hw->hw_next; |
1da177e4 LT |
577 | here = *prev; |
578 | } | |
579 | /* link in this qh, unless some earlier pass did that */ | |
580 | if (qh != here.qh) { | |
581 | qh->qh_next = here; | |
582 | if (here.qh) | |
3807e26d | 583 | qh->hw->hw_next = *hw_p; |
1da177e4 LT |
584 | wmb (); |
585 | prev->qh = qh; | |
6dbd682b | 586 | *hw_p = QH_NEXT (ehci, qh->qh_dma); |
1da177e4 LT |
587 | } |
588 | } | |
589 | qh->qh_state = QH_STATE_LINKED; | |
ef4638f9 | 590 | qh->xacterrs = 0; |
1da177e4 LT |
591 | qh_get (qh); |
592 | ||
593 | /* update per-qh bandwidth for usbfs */ | |
594 | ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period | |
595 | ? ((qh->usecs + qh->c_usecs) / qh->period) | |
596 | : (qh->usecs * 8); | |
597 | ||
598 | /* maybe enable periodic schedule processing */ | |
01c17142 | 599 | return enable_periodic(ehci); |
1da177e4 LT |
600 | } |
601 | ||
01c17142 | 602 | static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 LT |
603 | { |
604 | unsigned i; | |
605 | unsigned period; | |
606 | ||
607 | // FIXME: | |
608 | // IF this isn't high speed | |
609 | // and this qh is active in the current uframe | |
610 | // (and overlay token SplitXstate is false?) | |
611 | // THEN | |
551509d2 | 612 | // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */); |
1da177e4 LT |
613 | |
614 | /* high bandwidth, or otherwise part of every microframe */ | |
615 | if ((period = qh->period) == 0) | |
616 | period = 1; | |
617 | ||
618 | for (i = qh->start; i < ehci->periodic_size; i += period) | |
619 | periodic_unlink (ehci, i, qh); | |
620 | ||
621 | /* update per-qh bandwidth for usbfs */ | |
622 | ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period | |
623 | ? ((qh->usecs + qh->c_usecs) / qh->period) | |
624 | : (qh->usecs * 8); | |
625 | ||
626 | dev_dbg (&qh->dev->dev, | |
627 | "unlink qh%d-%04x/%p start %d [%d/%d us]\n", | |
7dedacf4 | 628 | qh->period, |
3807e26d | 629 | hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK), |
1da177e4 LT |
630 | qh, qh->start, qh->usecs, qh->c_usecs); |
631 | ||
632 | /* qh->qh_next still "live" to HC */ | |
633 | qh->qh_state = QH_STATE_UNLINK; | |
634 | qh->qh_next.ptr = NULL; | |
635 | qh_put (qh); | |
636 | ||
637 | /* maybe turn off periodic schedule */ | |
01c17142 | 638 | return disable_periodic(ehci); |
1da177e4 LT |
639 | } |
640 | ||
641 | static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh) | |
642 | { | |
a448c9d8 AS |
643 | unsigned wait; |
644 | struct ehci_qh_hw *hw = qh->hw; | |
645 | int rc; | |
646 | ||
647 | /* If the QH isn't linked then there's nothing we can do | |
648 | * unless we were called during a giveback, in which case | |
649 | * qh_completions() has to deal with it. | |
650 | */ | |
651 | if (qh->qh_state != QH_STATE_LINKED) { | |
652 | if (qh->qh_state == QH_STATE_COMPLETING) | |
653 | qh->needs_rescan = 1; | |
654 | return; | |
655 | } | |
1da177e4 LT |
656 | |
657 | qh_unlink_periodic (ehci, qh); | |
658 | ||
659 | /* simple/paranoid: always delay, expecting the HC needs to read | |
660 | * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and | |
661 | * expect khubd to clean up after any CSPLITs we won't issue. | |
662 | * active high speed queues may need bigger delays... | |
663 | */ | |
664 | if (list_empty (&qh->qtd_list) | |
6dbd682b | 665 | || (cpu_to_hc32(ehci, QH_CMASK) |
3807e26d | 666 | & hw->hw_info2) != 0) |
1da177e4 LT |
667 | wait = 2; |
668 | else | |
669 | wait = 55; /* worst case: 3 * 1024 */ | |
670 | ||
671 | udelay (wait); | |
672 | qh->qh_state = QH_STATE_IDLE; | |
3807e26d | 673 | hw->hw_next = EHCI_LIST_END(ehci); |
1da177e4 | 674 | wmb (); |
a448c9d8 AS |
675 | |
676 | qh_completions(ehci, qh); | |
677 | ||
678 | /* reschedule QH iff another request is queued */ | |
679 | if (!list_empty(&qh->qtd_list) && | |
680 | HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { | |
681 | rc = qh_schedule(ehci, qh); | |
682 | ||
683 | /* An error here likely indicates handshake failure | |
684 | * or no space left in the schedule. Neither fault | |
685 | * should happen often ... | |
686 | * | |
687 | * FIXME kill the now-dysfunctional queued urbs | |
688 | */ | |
689 | if (rc != 0) | |
690 | ehci_err(ehci, "can't reschedule qh %p, err %d\n", | |
691 | qh, rc); | |
692 | } | |
1da177e4 LT |
693 | } |
694 | ||
695 | /*-------------------------------------------------------------------------*/ | |
696 | ||
697 | static int check_period ( | |
53bd6a60 | 698 | struct ehci_hcd *ehci, |
1da177e4 LT |
699 | unsigned frame, |
700 | unsigned uframe, | |
701 | unsigned period, | |
702 | unsigned usecs | |
703 | ) { | |
704 | int claimed; | |
705 | ||
706 | /* complete split running into next frame? | |
707 | * given FSTN support, we could sometimes check... | |
708 | */ | |
709 | if (uframe >= 8) | |
710 | return 0; | |
711 | ||
712 | /* | |
713 | * 80% periodic == 100 usec/uframe available | |
53bd6a60 | 714 | * convert "usecs we need" to "max already claimed" |
1da177e4 LT |
715 | */ |
716 | usecs = 100 - usecs; | |
717 | ||
718 | /* we "know" 2 and 4 uframe intervals were rejected; so | |
719 | * for period 0, check _every_ microframe in the schedule. | |
720 | */ | |
721 | if (unlikely (period == 0)) { | |
722 | do { | |
723 | for (uframe = 0; uframe < 7; uframe++) { | |
724 | claimed = periodic_usecs (ehci, frame, uframe); | |
725 | if (claimed > usecs) | |
726 | return 0; | |
727 | } | |
728 | } while ((frame += 1) < ehci->periodic_size); | |
729 | ||
730 | /* just check the specified uframe, at that period */ | |
731 | } else { | |
732 | do { | |
733 | claimed = periodic_usecs (ehci, frame, uframe); | |
734 | if (claimed > usecs) | |
735 | return 0; | |
736 | } while ((frame += period) < ehci->periodic_size); | |
737 | } | |
738 | ||
739 | // success! | |
740 | return 1; | |
741 | } | |
742 | ||
743 | static int check_intr_schedule ( | |
53bd6a60 | 744 | struct ehci_hcd *ehci, |
1da177e4 LT |
745 | unsigned frame, |
746 | unsigned uframe, | |
747 | const struct ehci_qh *qh, | |
6dbd682b | 748 | __hc32 *c_maskp |
1da177e4 LT |
749 | ) |
750 | { | |
53bd6a60 | 751 | int retval = -ENOSPC; |
ba47f66b | 752 | u8 mask = 0; |
1da177e4 LT |
753 | |
754 | if (qh->c_usecs && uframe >= 6) /* FSTN territory? */ | |
755 | goto done; | |
756 | ||
757 | if (!check_period (ehci, frame, uframe, qh->period, qh->usecs)) | |
758 | goto done; | |
759 | if (!qh->c_usecs) { | |
760 | retval = 0; | |
761 | *c_maskp = 0; | |
762 | goto done; | |
763 | } | |
764 | ||
ba47f66b DS |
765 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED |
766 | if (tt_available (ehci, qh->period, qh->dev, frame, uframe, | |
767 | qh->tt_usecs)) { | |
768 | unsigned i; | |
769 | ||
770 | /* TODO : this may need FSTN for SSPLIT in uframe 5. */ | |
771 | for (i=uframe+1; i<8 && i<uframe+4; i++) | |
772 | if (!check_period (ehci, frame, i, | |
773 | qh->period, qh->c_usecs)) | |
774 | goto done; | |
775 | else | |
776 | mask |= 1 << i; | |
777 | ||
778 | retval = 0; | |
779 | ||
6dbd682b | 780 | *c_maskp = cpu_to_hc32(ehci, mask << 8); |
ba47f66b DS |
781 | } |
782 | #else | |
1da177e4 LT |
783 | /* Make sure this tt's buffer is also available for CSPLITs. |
784 | * We pessimize a bit; probably the typical full speed case | |
785 | * doesn't need the second CSPLIT. | |
53bd6a60 | 786 | * |
1da177e4 LT |
787 | * NOTE: both SPLIT and CSPLIT could be checked in just |
788 | * one smart pass... | |
789 | */ | |
790 | mask = 0x03 << (uframe + qh->gap_uf); | |
6dbd682b | 791 | *c_maskp = cpu_to_hc32(ehci, mask << 8); |
1da177e4 LT |
792 | |
793 | mask |= 1 << uframe; | |
794 | if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) { | |
795 | if (!check_period (ehci, frame, uframe + qh->gap_uf + 1, | |
796 | qh->period, qh->c_usecs)) | |
797 | goto done; | |
798 | if (!check_period (ehci, frame, uframe + qh->gap_uf, | |
799 | qh->period, qh->c_usecs)) | |
800 | goto done; | |
801 | retval = 0; | |
802 | } | |
ba47f66b | 803 | #endif |
1da177e4 LT |
804 | done: |
805 | return retval; | |
806 | } | |
807 | ||
808 | /* "first fit" scheduling policy used the first time through, | |
809 | * or when the previous schedule slot can't be re-used. | |
810 | */ | |
6dbd682b | 811 | static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 | 812 | { |
53bd6a60 | 813 | int status; |
1da177e4 | 814 | unsigned uframe; |
6dbd682b | 815 | __hc32 c_mask; |
1da177e4 | 816 | unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */ |
3807e26d | 817 | struct ehci_qh_hw *hw = qh->hw; |
1da177e4 LT |
818 | |
819 | qh_refresh(ehci, qh); | |
3807e26d | 820 | hw->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
821 | frame = qh->start; |
822 | ||
823 | /* reuse the previous schedule slots, if we can */ | |
824 | if (frame < qh->period) { | |
3807e26d | 825 | uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK); |
1da177e4 LT |
826 | status = check_intr_schedule (ehci, frame, --uframe, |
827 | qh, &c_mask); | |
828 | } else { | |
829 | uframe = 0; | |
830 | c_mask = 0; | |
831 | status = -ENOSPC; | |
832 | } | |
833 | ||
834 | /* else scan the schedule to find a group of slots such that all | |
835 | * uframes have enough periodic bandwidth available. | |
836 | */ | |
837 | if (status) { | |
838 | /* "normal" case, uframing flexible except with splits */ | |
839 | if (qh->period) { | |
68335e81 AS |
840 | int i; |
841 | ||
842 | for (i = qh->period; status && i > 0; --i) { | |
843 | frame = ++ehci->random_frame % qh->period; | |
1da177e4 LT |
844 | for (uframe = 0; uframe < 8; uframe++) { |
845 | status = check_intr_schedule (ehci, | |
846 | frame, uframe, qh, | |
847 | &c_mask); | |
848 | if (status == 0) | |
849 | break; | |
850 | } | |
68335e81 | 851 | } |
1da177e4 LT |
852 | |
853 | /* qh->period == 0 means every uframe */ | |
854 | } else { | |
855 | frame = 0; | |
856 | status = check_intr_schedule (ehci, 0, 0, qh, &c_mask); | |
857 | } | |
858 | if (status) | |
859 | goto done; | |
860 | qh->start = frame; | |
861 | ||
862 | /* reset S-frame and (maybe) C-frame masks */ | |
3807e26d AD |
863 | hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK)); |
864 | hw->hw_info2 |= qh->period | |
6dbd682b SR |
865 | ? cpu_to_hc32(ehci, 1 << uframe) |
866 | : cpu_to_hc32(ehci, QH_SMASK); | |
3807e26d | 867 | hw->hw_info2 |= c_mask; |
1da177e4 LT |
868 | } else |
869 | ehci_dbg (ehci, "reused qh %p schedule\n", qh); | |
870 | ||
871 | /* stuff into the periodic schedule */ | |
53bd6a60 | 872 | status = qh_link_periodic (ehci, qh); |
1da177e4 LT |
873 | done: |
874 | return status; | |
875 | } | |
876 | ||
877 | static int intr_submit ( | |
878 | struct ehci_hcd *ehci, | |
1da177e4 LT |
879 | struct urb *urb, |
880 | struct list_head *qtd_list, | |
55016f10 | 881 | gfp_t mem_flags |
1da177e4 LT |
882 | ) { |
883 | unsigned epnum; | |
884 | unsigned long flags; | |
885 | struct ehci_qh *qh; | |
e9df41c5 | 886 | int status; |
1da177e4 LT |
887 | struct list_head empty; |
888 | ||
889 | /* get endpoint and transfer/schedule data */ | |
e9df41c5 | 890 | epnum = urb->ep->desc.bEndpointAddress; |
1da177e4 LT |
891 | |
892 | spin_lock_irqsave (&ehci->lock, flags); | |
893 | ||
541c7d43 | 894 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 895 | status = -ESHUTDOWN; |
e9df41c5 | 896 | goto done_not_linked; |
8de98402 | 897 | } |
e9df41c5 AS |
898 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); |
899 | if (unlikely(status)) | |
900 | goto done_not_linked; | |
8de98402 | 901 | |
1da177e4 LT |
902 | /* get qh and force any scheduling errors */ |
903 | INIT_LIST_HEAD (&empty); | |
e9df41c5 | 904 | qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv); |
1da177e4 LT |
905 | if (qh == NULL) { |
906 | status = -ENOMEM; | |
907 | goto done; | |
908 | } | |
909 | if (qh->qh_state == QH_STATE_IDLE) { | |
910 | if ((status = qh_schedule (ehci, qh)) != 0) | |
911 | goto done; | |
912 | } | |
913 | ||
914 | /* then queue the urb's tds to the qh */ | |
e9df41c5 | 915 | qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); |
1da177e4 LT |
916 | BUG_ON (qh == NULL); |
917 | ||
918 | /* ... update usbfs periodic stats */ | |
919 | ehci_to_hcd(ehci)->self.bandwidth_int_reqs++; | |
920 | ||
921 | done: | |
e9df41c5 AS |
922 | if (unlikely(status)) |
923 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
924 | done_not_linked: | |
1da177e4 LT |
925 | spin_unlock_irqrestore (&ehci->lock, flags); |
926 | if (status) | |
927 | qtd_list_free (ehci, urb, qtd_list); | |
928 | ||
929 | return status; | |
930 | } | |
931 | ||
932 | /*-------------------------------------------------------------------------*/ | |
933 | ||
934 | /* ehci_iso_stream ops work with both ITD and SITD */ | |
935 | ||
936 | static struct ehci_iso_stream * | |
55016f10 | 937 | iso_stream_alloc (gfp_t mem_flags) |
1da177e4 LT |
938 | { |
939 | struct ehci_iso_stream *stream; | |
940 | ||
7b842b6e | 941 | stream = kzalloc(sizeof *stream, mem_flags); |
1da177e4 | 942 | if (likely (stream != NULL)) { |
1da177e4 LT |
943 | INIT_LIST_HEAD(&stream->td_list); |
944 | INIT_LIST_HEAD(&stream->free_list); | |
945 | stream->next_uframe = -1; | |
946 | stream->refcount = 1; | |
947 | } | |
948 | return stream; | |
949 | } | |
950 | ||
951 | static void | |
952 | iso_stream_init ( | |
953 | struct ehci_hcd *ehci, | |
954 | struct ehci_iso_stream *stream, | |
955 | struct usb_device *dev, | |
956 | int pipe, | |
957 | unsigned interval | |
958 | ) | |
959 | { | |
960 | static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f }; | |
961 | ||
962 | u32 buf1; | |
963 | unsigned epnum, maxp; | |
964 | int is_input; | |
965 | long bandwidth; | |
966 | ||
967 | /* | |
968 | * this might be a "high bandwidth" highspeed endpoint, | |
969 | * as encoded in the ep descriptor's wMaxPacket field | |
970 | */ | |
971 | epnum = usb_pipeendpoint (pipe); | |
972 | is_input = usb_pipein (pipe) ? USB_DIR_IN : 0; | |
973 | maxp = usb_maxpacket(dev, pipe, !is_input); | |
974 | if (is_input) { | |
975 | buf1 = (1 << 11); | |
976 | } else { | |
977 | buf1 = 0; | |
978 | } | |
979 | ||
980 | /* knows about ITD vs SITD */ | |
981 | if (dev->speed == USB_SPEED_HIGH) { | |
982 | unsigned multi = hb_mult(maxp); | |
983 | ||
984 | stream->highspeed = 1; | |
985 | ||
986 | maxp = max_packet(maxp); | |
987 | buf1 |= maxp; | |
988 | maxp *= multi; | |
989 | ||
6dbd682b SR |
990 | stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum); |
991 | stream->buf1 = cpu_to_hc32(ehci, buf1); | |
992 | stream->buf2 = cpu_to_hc32(ehci, multi); | |
1da177e4 LT |
993 | |
994 | /* usbfs wants to report the average usecs per frame tied up | |
995 | * when transfers on this endpoint are scheduled ... | |
996 | */ | |
997 | stream->usecs = HS_USECS_ISO (maxp); | |
998 | bandwidth = stream->usecs * 8; | |
372dd6e8 | 999 | bandwidth /= interval; |
1da177e4 LT |
1000 | |
1001 | } else { | |
1002 | u32 addr; | |
d0384200 | 1003 | int think_time; |
469d0229 | 1004 | int hs_transfers; |
1da177e4 LT |
1005 | |
1006 | addr = dev->ttport << 24; | |
1007 | if (!ehci_is_TDI(ehci) | |
1008 | || (dev->tt->hub != | |
1009 | ehci_to_hcd(ehci)->self.root_hub)) | |
1010 | addr |= dev->tt->hub->devnum << 16; | |
1011 | addr |= epnum << 8; | |
1012 | addr |= dev->devnum; | |
1013 | stream->usecs = HS_USECS_ISO (maxp); | |
d0384200 | 1014 | think_time = dev->tt ? dev->tt->think_time : 0; |
1015 | stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time ( | |
1016 | dev->speed, is_input, 1, maxp)); | |
469d0229 | 1017 | hs_transfers = max (1u, (maxp + 187) / 188); |
1da177e4 LT |
1018 | if (is_input) { |
1019 | u32 tmp; | |
1020 | ||
1021 | addr |= 1 << 31; | |
1022 | stream->c_usecs = stream->usecs; | |
1023 | stream->usecs = HS_USECS_ISO (1); | |
1024 | stream->raw_mask = 1; | |
1025 | ||
469d0229 CL |
1026 | /* c-mask as specified in USB 2.0 11.18.4 3.c */ |
1027 | tmp = (1 << (hs_transfers + 2)) - 1; | |
1028 | stream->raw_mask |= tmp << (8 + 2); | |
1da177e4 | 1029 | } else |
469d0229 | 1030 | stream->raw_mask = smask_out [hs_transfers - 1]; |
1da177e4 | 1031 | bandwidth = stream->usecs + stream->c_usecs; |
372dd6e8 | 1032 | bandwidth /= interval << 3; |
1da177e4 LT |
1033 | |
1034 | /* stream->splits gets created from raw_mask later */ | |
6dbd682b | 1035 | stream->address = cpu_to_hc32(ehci, addr); |
1da177e4 LT |
1036 | } |
1037 | stream->bandwidth = bandwidth; | |
1038 | ||
1039 | stream->udev = dev; | |
1040 | ||
1041 | stream->bEndpointAddress = is_input | epnum; | |
1042 | stream->interval = interval; | |
1043 | stream->maxp = maxp; | |
1044 | } | |
1045 | ||
1046 | static void | |
1047 | iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream) | |
1048 | { | |
1049 | stream->refcount--; | |
1050 | ||
1051 | /* free whenever just a dev->ep reference remains. | |
1052 | * not like a QH -- no persistent state (toggle, halt) | |
1053 | */ | |
1054 | if (stream->refcount == 1) { | |
1da177e4 LT |
1055 | // BUG_ON (!list_empty(&stream->td_list)); |
1056 | ||
1057 | while (!list_empty (&stream->free_list)) { | |
1058 | struct list_head *entry; | |
1059 | ||
1060 | entry = stream->free_list.next; | |
1061 | list_del (entry); | |
1062 | ||
1063 | /* knows about ITD vs SITD */ | |
1064 | if (stream->highspeed) { | |
1065 | struct ehci_itd *itd; | |
1066 | ||
1067 | itd = list_entry (entry, struct ehci_itd, | |
1068 | itd_list); | |
1069 | dma_pool_free (ehci->itd_pool, itd, | |
1070 | itd->itd_dma); | |
1071 | } else { | |
1072 | struct ehci_sitd *sitd; | |
1073 | ||
1074 | sitd = list_entry (entry, struct ehci_sitd, | |
1075 | sitd_list); | |
1076 | dma_pool_free (ehci->sitd_pool, sitd, | |
1077 | sitd->sitd_dma); | |
1078 | } | |
1079 | } | |
1080 | ||
1da177e4 | 1081 | stream->bEndpointAddress &= 0x0f; |
9aa09d2f KW |
1082 | if (stream->ep) |
1083 | stream->ep->hcpriv = NULL; | |
1da177e4 | 1084 | |
1da177e4 LT |
1085 | kfree(stream); |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static inline struct ehci_iso_stream * | |
1090 | iso_stream_get (struct ehci_iso_stream *stream) | |
1091 | { | |
1092 | if (likely (stream != NULL)) | |
1093 | stream->refcount++; | |
1094 | return stream; | |
1095 | } | |
1096 | ||
1097 | static struct ehci_iso_stream * | |
1098 | iso_stream_find (struct ehci_hcd *ehci, struct urb *urb) | |
1099 | { | |
1100 | unsigned epnum; | |
1101 | struct ehci_iso_stream *stream; | |
1102 | struct usb_host_endpoint *ep; | |
1103 | unsigned long flags; | |
1104 | ||
1105 | epnum = usb_pipeendpoint (urb->pipe); | |
1106 | if (usb_pipein(urb->pipe)) | |
1107 | ep = urb->dev->ep_in[epnum]; | |
1108 | else | |
1109 | ep = urb->dev->ep_out[epnum]; | |
1110 | ||
1111 | spin_lock_irqsave (&ehci->lock, flags); | |
1112 | stream = ep->hcpriv; | |
1113 | ||
1114 | if (unlikely (stream == NULL)) { | |
1115 | stream = iso_stream_alloc(GFP_ATOMIC); | |
1116 | if (likely (stream != NULL)) { | |
1117 | /* dev->ep owns the initial refcount */ | |
1118 | ep->hcpriv = stream; | |
1119 | stream->ep = ep; | |
1120 | iso_stream_init(ehci, stream, urb->dev, urb->pipe, | |
1121 | urb->interval); | |
1122 | } | |
1123 | ||
1082f57a CL |
1124 | /* if dev->ep [epnum] is a QH, hw is set */ |
1125 | } else if (unlikely (stream->hw != NULL)) { | |
1da177e4 LT |
1126 | ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n", |
1127 | urb->dev->devpath, epnum, | |
1128 | usb_pipein(urb->pipe) ? "in" : "out"); | |
1129 | stream = NULL; | |
1130 | } | |
1131 | ||
1132 | /* caller guarantees an eventual matching iso_stream_put */ | |
1133 | stream = iso_stream_get (stream); | |
1134 | ||
1135 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1136 | return stream; | |
1137 | } | |
1138 | ||
1139 | /*-------------------------------------------------------------------------*/ | |
1140 | ||
1141 | /* ehci_iso_sched ops can be ITD-only or SITD-only */ | |
1142 | ||
1143 | static struct ehci_iso_sched * | |
55016f10 | 1144 | iso_sched_alloc (unsigned packets, gfp_t mem_flags) |
1da177e4 LT |
1145 | { |
1146 | struct ehci_iso_sched *iso_sched; | |
1147 | int size = sizeof *iso_sched; | |
1148 | ||
1149 | size += packets * sizeof (struct ehci_iso_packet); | |
80b6ca48 | 1150 | iso_sched = kzalloc(size, mem_flags); |
1da177e4 | 1151 | if (likely (iso_sched != NULL)) { |
1da177e4 LT |
1152 | INIT_LIST_HEAD (&iso_sched->td_list); |
1153 | } | |
1154 | return iso_sched; | |
1155 | } | |
1156 | ||
1157 | static inline void | |
6dbd682b SR |
1158 | itd_sched_init( |
1159 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1160 | struct ehci_iso_sched *iso_sched, |
1161 | struct ehci_iso_stream *stream, | |
1162 | struct urb *urb | |
1163 | ) | |
1164 | { | |
1165 | unsigned i; | |
1166 | dma_addr_t dma = urb->transfer_dma; | |
1167 | ||
1168 | /* how many uframes are needed for these transfers */ | |
1169 | iso_sched->span = urb->number_of_packets * stream->interval; | |
1170 | ||
1171 | /* figure out per-uframe itd fields that we'll need later | |
1172 | * when we fit new itds into the schedule. | |
1173 | */ | |
1174 | for (i = 0; i < urb->number_of_packets; i++) { | |
1175 | struct ehci_iso_packet *uframe = &iso_sched->packet [i]; | |
1176 | unsigned length; | |
1177 | dma_addr_t buf; | |
1178 | u32 trans; | |
1179 | ||
1180 | length = urb->iso_frame_desc [i].length; | |
1181 | buf = dma + urb->iso_frame_desc [i].offset; | |
1182 | ||
1183 | trans = EHCI_ISOC_ACTIVE; | |
1184 | trans |= buf & 0x0fff; | |
1185 | if (unlikely (((i + 1) == urb->number_of_packets)) | |
1186 | && !(urb->transfer_flags & URB_NO_INTERRUPT)) | |
1187 | trans |= EHCI_ITD_IOC; | |
1188 | trans |= length << 16; | |
6dbd682b | 1189 | uframe->transaction = cpu_to_hc32(ehci, trans); |
1da177e4 | 1190 | |
77078570 | 1191 | /* might need to cross a buffer page within a uframe */ |
1da177e4 LT |
1192 | uframe->bufp = (buf & ~(u64)0x0fff); |
1193 | buf += length; | |
1194 | if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff)))) | |
1195 | uframe->cross = 1; | |
1196 | } | |
1197 | } | |
1198 | ||
1199 | static void | |
1200 | iso_sched_free ( | |
1201 | struct ehci_iso_stream *stream, | |
1202 | struct ehci_iso_sched *iso_sched | |
1203 | ) | |
1204 | { | |
1205 | if (!iso_sched) | |
1206 | return; | |
1207 | // caller must hold ehci->lock! | |
1208 | list_splice (&iso_sched->td_list, &stream->free_list); | |
1209 | kfree (iso_sched); | |
1210 | } | |
1211 | ||
1212 | static int | |
1213 | itd_urb_transaction ( | |
1214 | struct ehci_iso_stream *stream, | |
1215 | struct ehci_hcd *ehci, | |
1216 | struct urb *urb, | |
55016f10 | 1217 | gfp_t mem_flags |
1da177e4 LT |
1218 | ) |
1219 | { | |
1220 | struct ehci_itd *itd; | |
1221 | dma_addr_t itd_dma; | |
1222 | int i; | |
1223 | unsigned num_itds; | |
1224 | struct ehci_iso_sched *sched; | |
1225 | unsigned long flags; | |
1226 | ||
1227 | sched = iso_sched_alloc (urb->number_of_packets, mem_flags); | |
1228 | if (unlikely (sched == NULL)) | |
1229 | return -ENOMEM; | |
1230 | ||
6dbd682b | 1231 | itd_sched_init(ehci, sched, stream, urb); |
1da177e4 LT |
1232 | |
1233 | if (urb->interval < 8) | |
1234 | num_itds = 1 + (sched->span + 7) / 8; | |
1235 | else | |
1236 | num_itds = urb->number_of_packets; | |
1237 | ||
1238 | /* allocate/init ITDs */ | |
1239 | spin_lock_irqsave (&ehci->lock, flags); | |
1240 | for (i = 0; i < num_itds; i++) { | |
1241 | ||
1242 | /* free_list.next might be cache-hot ... but maybe | |
1243 | * the HC caches it too. avoid that issue for now. | |
1244 | */ | |
1245 | ||
1246 | /* prefer previously-allocated itds */ | |
1247 | if (likely (!list_empty(&stream->free_list))) { | |
1248 | itd = list_entry (stream->free_list.prev, | |
6dbd682b | 1249 | struct ehci_itd, itd_list); |
1da177e4 LT |
1250 | list_del (&itd->itd_list); |
1251 | itd_dma = itd->itd_dma; | |
3d01f0fe | 1252 | } else { |
1da177e4 LT |
1253 | spin_unlock_irqrestore (&ehci->lock, flags); |
1254 | itd = dma_pool_alloc (ehci->itd_pool, mem_flags, | |
1255 | &itd_dma); | |
1256 | spin_lock_irqsave (&ehci->lock, flags); | |
3d01f0fe KW |
1257 | if (!itd) { |
1258 | iso_sched_free(stream, sched); | |
1259 | spin_unlock_irqrestore(&ehci->lock, flags); | |
1260 | return -ENOMEM; | |
1261 | } | |
1da177e4 LT |
1262 | } |
1263 | ||
1da177e4 LT |
1264 | memset (itd, 0, sizeof *itd); |
1265 | itd->itd_dma = itd_dma; | |
1266 | list_add (&itd->itd_list, &sched->td_list); | |
1267 | } | |
1268 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1269 | ||
1270 | /* temporarily store schedule info in hcpriv */ | |
1271 | urb->hcpriv = sched; | |
1272 | urb->error_count = 0; | |
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | /*-------------------------------------------------------------------------*/ | |
1277 | ||
1278 | static inline int | |
1279 | itd_slot_ok ( | |
1280 | struct ehci_hcd *ehci, | |
1281 | u32 mod, | |
1282 | u32 uframe, | |
1283 | u8 usecs, | |
1284 | u32 period | |
1285 | ) | |
1286 | { | |
1287 | uframe %= period; | |
1288 | do { | |
1289 | /* can't commit more than 80% periodic == 100 usec */ | |
1290 | if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7) | |
1291 | > (100 - usecs)) | |
1292 | return 0; | |
1293 | ||
1294 | /* we know urb->interval is 2^N uframes */ | |
1295 | uframe += period; | |
1296 | } while (uframe < mod); | |
1297 | return 1; | |
1298 | } | |
1299 | ||
1300 | static inline int | |
1301 | sitd_slot_ok ( | |
1302 | struct ehci_hcd *ehci, | |
1303 | u32 mod, | |
1304 | struct ehci_iso_stream *stream, | |
1305 | u32 uframe, | |
1306 | struct ehci_iso_sched *sched, | |
1307 | u32 period_uframes | |
1308 | ) | |
1309 | { | |
1310 | u32 mask, tmp; | |
1311 | u32 frame, uf; | |
1312 | ||
1313 | mask = stream->raw_mask << (uframe & 7); | |
1314 | ||
1315 | /* for IN, don't wrap CSPLIT into the next frame */ | |
1316 | if (mask & ~0xffff) | |
1317 | return 0; | |
1318 | ||
1319 | /* this multi-pass logic is simple, but performance may | |
1320 | * suffer when the schedule data isn't cached. | |
1321 | */ | |
1322 | ||
1323 | /* check bandwidth */ | |
1324 | uframe %= period_uframes; | |
1325 | do { | |
1326 | u32 max_used; | |
1327 | ||
1328 | frame = uframe >> 3; | |
1329 | uf = uframe & 7; | |
1330 | ||
ba47f66b DS |
1331 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED |
1332 | /* The tt's fullspeed bus bandwidth must be available. | |
1333 | * tt_available scheduling guarantees 10+% for control/bulk. | |
1334 | */ | |
1335 | if (!tt_available (ehci, period_uframes << 3, | |
1336 | stream->udev, frame, uf, stream->tt_usecs)) | |
1337 | return 0; | |
1338 | #else | |
1da177e4 LT |
1339 | /* tt must be idle for start(s), any gap, and csplit. |
1340 | * assume scheduling slop leaves 10+% for control/bulk. | |
1341 | */ | |
1342 | if (!tt_no_collision (ehci, period_uframes << 3, | |
1343 | stream->udev, frame, mask)) | |
1344 | return 0; | |
ba47f66b | 1345 | #endif |
1da177e4 LT |
1346 | |
1347 | /* check starts (OUT uses more than one) */ | |
1348 | max_used = 100 - stream->usecs; | |
1349 | for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) { | |
1350 | if (periodic_usecs (ehci, frame, uf) > max_used) | |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | /* for IN, check CSPLIT */ | |
1355 | if (stream->c_usecs) { | |
0c734622 | 1356 | uf = uframe & 7; |
1da177e4 LT |
1357 | max_used = 100 - stream->c_usecs; |
1358 | do { | |
1359 | tmp = 1 << uf; | |
1360 | tmp <<= 8; | |
1361 | if ((stream->raw_mask & tmp) == 0) | |
1362 | continue; | |
1363 | if (periodic_usecs (ehci, frame, uf) | |
1364 | > max_used) | |
1365 | return 0; | |
1366 | } while (++uf < 8); | |
1367 | } | |
1368 | ||
1369 | /* we know urb->interval is 2^N uframes */ | |
1370 | uframe += period_uframes; | |
1371 | } while (uframe < mod); | |
1372 | ||
6dbd682b | 1373 | stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7)); |
1da177e4 LT |
1374 | return 1; |
1375 | } | |
1376 | ||
1377 | /* | |
1378 | * This scheduler plans almost as far into the future as it has actual | |
1379 | * periodic schedule slots. (Affected by TUNE_FLS, which defaults to | |
1380 | * "as small as possible" to be cache-friendlier.) That limits the size | |
1381 | * transfers you can stream reliably; avoid more than 64 msec per urb. | |
1382 | * Also avoid queue depths of less than ehci's worst irq latency (affected | |
1383 | * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter, | |
1384 | * and other factors); or more than about 230 msec total (for portability, | |
1385 | * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler! | |
1386 | */ | |
1387 | ||
d7e055f1 | 1388 | #define SCHEDULE_SLOP 80 /* microframes */ |
1da177e4 LT |
1389 | |
1390 | static int | |
1391 | iso_stream_schedule ( | |
1392 | struct ehci_hcd *ehci, | |
1393 | struct urb *urb, | |
1394 | struct ehci_iso_stream *stream | |
1395 | ) | |
1396 | { | |
ffda0803 | 1397 | u32 now, next, start, period, span; |
1da177e4 LT |
1398 | int status; |
1399 | unsigned mod = ehci->periodic_size << 3; | |
1400 | struct ehci_iso_sched *sched = urb->hcpriv; | |
1401 | ||
ffda0803 AS |
1402 | period = urb->interval; |
1403 | span = sched->span; | |
1404 | if (!stream->highspeed) { | |
1405 | period <<= 3; | |
1406 | span <<= 3; | |
1407 | } | |
1408 | ||
1409 | if (span > mod - SCHEDULE_SLOP) { | |
1da177e4 LT |
1410 | ehci_dbg (ehci, "iso request %p too long\n", urb); |
1411 | status = -EFBIG; | |
1412 | goto fail; | |
1413 | } | |
1414 | ||
bccbefaa | 1415 | now = ehci_readl(ehci, &ehci->regs->frame_index) & (mod - 1); |
1da177e4 | 1416 | |
b40e43fc AS |
1417 | /* Typical case: reuse current schedule, stream is still active. |
1418 | * Hopefully there are no gaps from the host falling behind | |
1419 | * (irq delays etc), but if there are we'll take the next | |
1420 | * slot in the schedule, implicitly assuming URB_ISO_ASAP. | |
1da177e4 LT |
1421 | */ |
1422 | if (likely (!list_empty (&stream->td_list))) { | |
1fb2e055 | 1423 | u32 excess; |
dccd574c SS |
1424 | |
1425 | /* For high speed devices, allow scheduling within the | |
ae68a83b AS |
1426 | * isochronous scheduling threshold. For full speed devices |
1427 | * and Intel PCI-based controllers, don't (work around for | |
1428 | * Intel ICH9 bug). | |
dccd574c | 1429 | */ |
ae68a83b | 1430 | if (!stream->highspeed && ehci->fs_i_thresh) |
dccd574c SS |
1431 | next = now + ehci->i_thresh; |
1432 | else | |
1433 | next = now; | |
b40e43fc | 1434 | |
1fb2e055 AS |
1435 | /* Fell behind (by up to twice the slop amount)? |
1436 | * We decide based on the time of the last currently-scheduled | |
1437 | * slot, not the time of the next available slot. | |
1438 | */ | |
1439 | excess = (stream->next_uframe - period - next) & (mod - 1); | |
1440 | if (excess >= mod - 2 * SCHEDULE_SLOP) | |
1441 | start = next + excess - mod + period * | |
1442 | DIV_ROUND_UP(mod - excess, period); | |
1443 | else | |
1444 | start = next + excess + period; | |
1445 | if (start - now >= mod) { | |
1446 | ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n", | |
1447 | urb, start - now - period, period, | |
1448 | mod); | |
b40e43fc AS |
1449 | status = -EFBIG; |
1450 | goto fail; | |
1451 | } | |
1da177e4 LT |
1452 | } |
1453 | ||
1454 | /* need to schedule; when's the next (u)frame we could start? | |
1455 | * this is bigger than ehci->i_thresh allows; scheduling itself | |
1456 | * isn't free, the slop should handle reasonably slow cpus. it | |
1457 | * can also help high bandwidth if the dma and irq loads don't | |
1458 | * jump until after the queue is primed. | |
1459 | */ | |
1fb2e055 AS |
1460 | else { |
1461 | start = SCHEDULE_SLOP + (now & ~0x07); | |
1462 | ||
1463 | /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */ | |
1464 | ||
1465 | /* find a uframe slot with enough bandwidth */ | |
1466 | next = start + period; | |
1467 | for (; start < next; start++) { | |
1468 | ||
1469 | /* check schedule: enough space? */ | |
1470 | if (stream->highspeed) { | |
1471 | if (itd_slot_ok(ehci, mod, start, | |
1472 | stream->usecs, period)) | |
1473 | break; | |
1474 | } else { | |
1475 | if ((start % 8) >= 6) | |
1476 | continue; | |
1477 | if (sitd_slot_ok(ehci, mod, stream, | |
1478 | start, sched, period)) | |
1479 | break; | |
1480 | } | |
1da177e4 LT |
1481 | } |
1482 | ||
1fb2e055 AS |
1483 | /* no room in the schedule */ |
1484 | if (start == next) { | |
1485 | ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n", | |
1486 | urb, now, now + mod); | |
1487 | status = -ENOSPC; | |
1488 | goto fail; | |
1da177e4 LT |
1489 | } |
1490 | } | |
1491 | ||
1fb2e055 AS |
1492 | /* Tried to schedule too far into the future? */ |
1493 | if (unlikely(start - now + span - period | |
1494 | >= mod - 2 * SCHEDULE_SLOP)) { | |
1495 | ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n", | |
1496 | urb, start - now, span - period, | |
1497 | mod - 2 * SCHEDULE_SLOP); | |
1498 | status = -EFBIG; | |
1499 | goto fail; | |
1500 | } | |
1da177e4 | 1501 | |
1fb2e055 | 1502 | stream->next_uframe = start & (mod - 1); |
1da177e4 | 1503 | |
1da177e4 LT |
1504 | /* report high speed start in uframes; full speed, in frames */ |
1505 | urb->start_frame = stream->next_uframe; | |
1506 | if (!stream->highspeed) | |
1507 | urb->start_frame >>= 3; | |
1508 | return 0; | |
1fb2e055 AS |
1509 | |
1510 | fail: | |
1511 | iso_sched_free(stream, sched); | |
1512 | urb->hcpriv = NULL; | |
1513 | return status; | |
1da177e4 LT |
1514 | } |
1515 | ||
1516 | /*-------------------------------------------------------------------------*/ | |
1517 | ||
1518 | static inline void | |
6dbd682b SR |
1519 | itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream, |
1520 | struct ehci_itd *itd) | |
1da177e4 LT |
1521 | { |
1522 | int i; | |
1523 | ||
77078570 | 1524 | /* it's been recently zeroed */ |
6dbd682b | 1525 | itd->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
1526 | itd->hw_bufp [0] = stream->buf0; |
1527 | itd->hw_bufp [1] = stream->buf1; | |
1528 | itd->hw_bufp [2] = stream->buf2; | |
1529 | ||
1530 | for (i = 0; i < 8; i++) | |
1531 | itd->index[i] = -1; | |
1532 | ||
1533 | /* All other fields are filled when scheduling */ | |
1534 | } | |
1535 | ||
1536 | static inline void | |
6dbd682b SR |
1537 | itd_patch( |
1538 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1539 | struct ehci_itd *itd, |
1540 | struct ehci_iso_sched *iso_sched, | |
1541 | unsigned index, | |
77078570 | 1542 | u16 uframe |
1da177e4 LT |
1543 | ) |
1544 | { | |
1545 | struct ehci_iso_packet *uf = &iso_sched->packet [index]; | |
1546 | unsigned pg = itd->pg; | |
1547 | ||
1548 | // BUG_ON (pg == 6 && uf->cross); | |
1549 | ||
1550 | uframe &= 0x07; | |
1551 | itd->index [uframe] = index; | |
1552 | ||
6dbd682b SR |
1553 | itd->hw_transaction[uframe] = uf->transaction; |
1554 | itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12); | |
1555 | itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0); | |
1556 | itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32)); | |
1da177e4 LT |
1557 | |
1558 | /* iso_frame_desc[].offset must be strictly increasing */ | |
77078570 | 1559 | if (unlikely (uf->cross)) { |
1da177e4 | 1560 | u64 bufp = uf->bufp + 4096; |
6dbd682b | 1561 | |
1da177e4 | 1562 | itd->pg = ++pg; |
6dbd682b SR |
1563 | itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0); |
1564 | itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32)); | |
1da177e4 LT |
1565 | } |
1566 | } | |
1567 | ||
1568 | static inline void | |
1569 | itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd) | |
1570 | { | |
92bc3648 CL |
1571 | union ehci_shadow *prev = &ehci->pshadow[frame]; |
1572 | __hc32 *hw_p = &ehci->periodic[frame]; | |
1573 | union ehci_shadow here = *prev; | |
1574 | __hc32 type = 0; | |
1575 | ||
1576 | /* skip any iso nodes which might belong to previous microframes */ | |
1577 | while (here.ptr) { | |
1578 | type = Q_NEXT_TYPE(ehci, *hw_p); | |
1579 | if (type == cpu_to_hc32(ehci, Q_TYPE_QH)) | |
1580 | break; | |
1581 | prev = periodic_next_shadow(ehci, prev, type); | |
1582 | hw_p = shadow_next_periodic(ehci, &here, type); | |
1583 | here = *prev; | |
1584 | } | |
1585 | ||
1586 | itd->itd_next = here; | |
1587 | itd->hw_next = *hw_p; | |
1588 | prev->itd = itd; | |
1da177e4 LT |
1589 | itd->frame = frame; |
1590 | wmb (); | |
92bc3648 | 1591 | *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD); |
1da177e4 LT |
1592 | } |
1593 | ||
1594 | /* fit urb's itds into the selected schedule slot; activate as needed */ | |
1595 | static int | |
1596 | itd_link_urb ( | |
1597 | struct ehci_hcd *ehci, | |
1598 | struct urb *urb, | |
1599 | unsigned mod, | |
1600 | struct ehci_iso_stream *stream | |
1601 | ) | |
1602 | { | |
77078570 | 1603 | int packet; |
1da177e4 LT |
1604 | unsigned next_uframe, uframe, frame; |
1605 | struct ehci_iso_sched *iso_sched = urb->hcpriv; | |
1606 | struct ehci_itd *itd; | |
1607 | ||
bccbefaa | 1608 | next_uframe = stream->next_uframe & (mod - 1); |
1da177e4 LT |
1609 | |
1610 | if (unlikely (list_empty(&stream->td_list))) { | |
1611 | ehci_to_hcd(ehci)->self.bandwidth_allocated | |
1612 | += stream->bandwidth; | |
1613 | ehci_vdbg (ehci, | |
1614 | "schedule devp %s ep%d%s-iso period %d start %d.%d\n", | |
1615 | urb->dev->devpath, stream->bEndpointAddress & 0x0f, | |
1616 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out", | |
1617 | urb->interval, | |
1618 | next_uframe >> 3, next_uframe & 0x7); | |
1da177e4 | 1619 | } |
05570297 AH |
1620 | |
1621 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | |
ad93562b AX |
1622 | if (ehci->amd_pll_fix == 1) |
1623 | usb_amd_quirk_pll_disable(); | |
05570297 AH |
1624 | } |
1625 | ||
1da177e4 LT |
1626 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; |
1627 | ||
1628 | /* fill iTDs uframe by uframe */ | |
1629 | for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) { | |
1630 | if (itd == NULL) { | |
1631 | /* ASSERT: we have all necessary itds */ | |
1632 | // BUG_ON (list_empty (&iso_sched->td_list)); | |
1633 | ||
1634 | /* ASSERT: no itds for this endpoint in this uframe */ | |
1635 | ||
1636 | itd = list_entry (iso_sched->td_list.next, | |
1637 | struct ehci_itd, itd_list); | |
1638 | list_move_tail (&itd->itd_list, &stream->td_list); | |
1639 | itd->stream = iso_stream_get (stream); | |
508db8c9 | 1640 | itd->urb = urb; |
6dbd682b | 1641 | itd_init (ehci, stream, itd); |
1da177e4 LT |
1642 | } |
1643 | ||
1644 | uframe = next_uframe & 0x07; | |
1645 | frame = next_uframe >> 3; | |
1646 | ||
6dbd682b | 1647 | itd_patch(ehci, itd, iso_sched, packet, uframe); |
1da177e4 LT |
1648 | |
1649 | next_uframe += stream->interval; | |
bccbefaa | 1650 | next_uframe &= mod - 1; |
1da177e4 LT |
1651 | packet++; |
1652 | ||
1653 | /* link completed itds into the schedule */ | |
1654 | if (((next_uframe >> 3) != frame) | |
1655 | || packet == urb->number_of_packets) { | |
bccbefaa | 1656 | itd_link(ehci, frame & (ehci->periodic_size - 1), itd); |
1da177e4 LT |
1657 | itd = NULL; |
1658 | } | |
1659 | } | |
1660 | stream->next_uframe = next_uframe; | |
1661 | ||
1662 | /* don't need that schedule data any more */ | |
1663 | iso_sched_free (stream, iso_sched); | |
1664 | urb->hcpriv = NULL; | |
1665 | ||
1666 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
01c17142 | 1667 | return enable_periodic(ehci); |
1da177e4 LT |
1668 | } |
1669 | ||
1670 | #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR) | |
1671 | ||
30bf54e6 DB |
1672 | /* Process and recycle a completed ITD. Return true iff its urb completed, |
1673 | * and hence its completion callback probably added things to the hardware | |
1674 | * schedule. | |
1675 | * | |
1676 | * Note that we carefully avoid recycling this descriptor until after any | |
1677 | * completion callback runs, so that it won't be reused quickly. That is, | |
1678 | * assuming (a) no more than two urbs per frame on this endpoint, and also | |
1679 | * (b) only this endpoint's completions submit URBs. It seems some silicon | |
1680 | * corrupts things if you reuse completed descriptors very quickly... | |
1681 | */ | |
1da177e4 LT |
1682 | static unsigned |
1683 | itd_complete ( | |
1684 | struct ehci_hcd *ehci, | |
7d12e780 | 1685 | struct ehci_itd *itd |
1da177e4 LT |
1686 | ) { |
1687 | struct urb *urb = itd->urb; | |
1688 | struct usb_iso_packet_descriptor *desc; | |
1689 | u32 t; | |
1690 | unsigned uframe; | |
1691 | int urb_index = -1; | |
1692 | struct ehci_iso_stream *stream = itd->stream; | |
1693 | struct usb_device *dev; | |
30bf54e6 | 1694 | unsigned retval = false; |
1da177e4 LT |
1695 | |
1696 | /* for each uframe with a packet */ | |
1697 | for (uframe = 0; uframe < 8; uframe++) { | |
1698 | if (likely (itd->index[uframe] == -1)) | |
1699 | continue; | |
1700 | urb_index = itd->index[uframe]; | |
1701 | desc = &urb->iso_frame_desc [urb_index]; | |
1702 | ||
6dbd682b | 1703 | t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]); |
1da177e4 | 1704 | itd->hw_transaction [uframe] = 0; |
1da177e4 LT |
1705 | |
1706 | /* report transfer status */ | |
1707 | if (unlikely (t & ISO_ERRS)) { | |
1708 | urb->error_count++; | |
1709 | if (t & EHCI_ISOC_BUF_ERR) | |
1710 | desc->status = usb_pipein (urb->pipe) | |
1711 | ? -ENOSR /* hc couldn't read */ | |
1712 | : -ECOMM; /* hc couldn't write */ | |
1713 | else if (t & EHCI_ISOC_BABBLE) | |
1714 | desc->status = -EOVERFLOW; | |
1715 | else /* (t & EHCI_ISOC_XACTERR) */ | |
1716 | desc->status = -EPROTO; | |
1717 | ||
1718 | /* HC need not update length with this error */ | |
ec6d67e3 AS |
1719 | if (!(t & EHCI_ISOC_BABBLE)) { |
1720 | desc->actual_length = EHCI_ITD_LENGTH(t); | |
1721 | urb->actual_length += desc->actual_length; | |
1722 | } | |
1da177e4 LT |
1723 | } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) { |
1724 | desc->status = 0; | |
ec6d67e3 AS |
1725 | desc->actual_length = EHCI_ITD_LENGTH(t); |
1726 | urb->actual_length += desc->actual_length; | |
b40e43fc AS |
1727 | } else { |
1728 | /* URB was too late */ | |
1729 | desc->status = -EXDEV; | |
1da177e4 LT |
1730 | } |
1731 | } | |
1732 | ||
1da177e4 LT |
1733 | /* handle completion now? */ |
1734 | if (likely ((urb_index + 1) != urb->number_of_packets)) | |
30bf54e6 | 1735 | goto done; |
1da177e4 LT |
1736 | |
1737 | /* ASSERT: it's really the last itd for this urb | |
1738 | list_for_each_entry (itd, &stream->td_list, itd_list) | |
1739 | BUG_ON (itd->urb == urb); | |
1740 | */ | |
1741 | ||
aa16ca30 | 1742 | /* give urb back to the driver; completion often (re)submits */ |
6a8e87b2 | 1743 | dev = urb->dev; |
14c04c0f | 1744 | ehci_urb_done(ehci, urb, 0); |
30bf54e6 | 1745 | retval = true; |
1da177e4 | 1746 | urb = NULL; |
01c17142 | 1747 | (void) disable_periodic(ehci); |
1da177e4 LT |
1748 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
1749 | ||
05570297 | 1750 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { |
ad93562b AX |
1751 | if (ehci->amd_pll_fix == 1) |
1752 | usb_amd_quirk_pll_enable(); | |
05570297 AH |
1753 | } |
1754 | ||
508db8c9 | 1755 | if (unlikely(list_is_singular(&stream->td_list))) { |
1da177e4 LT |
1756 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
1757 | -= stream->bandwidth; | |
1758 | ehci_vdbg (ehci, | |
1759 | "deschedule devp %s ep%d%s-iso\n", | |
1760 | dev->devpath, stream->bEndpointAddress & 0x0f, | |
1761 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out"); | |
1762 | } | |
1763 | iso_stream_put (ehci, stream); | |
9aa09d2f | 1764 | |
30bf54e6 | 1765 | done: |
30bf54e6 | 1766 | itd->urb = NULL; |
9aa09d2f KW |
1767 | if (ehci->clock_frame != itd->frame || itd->index[7] != -1) { |
1768 | /* OK to recycle this ITD now. */ | |
1769 | itd->stream = NULL; | |
1770 | list_move(&itd->itd_list, &stream->free_list); | |
1771 | iso_stream_put(ehci, stream); | |
1772 | } else { | |
1773 | /* HW might remember this ITD, so we can't recycle it yet. | |
1774 | * Move it to a safe place until a new frame starts. | |
1775 | */ | |
1776 | list_move(&itd->itd_list, &ehci->cached_itd_list); | |
1777 | if (stream->refcount == 2) { | |
1778 | /* If iso_stream_put() were called here, stream | |
1779 | * would be freed. Instead, just prevent reuse. | |
1780 | */ | |
1781 | stream->ep->hcpriv = NULL; | |
1782 | stream->ep = NULL; | |
1783 | } | |
1784 | } | |
30bf54e6 | 1785 | return retval; |
1da177e4 LT |
1786 | } |
1787 | ||
1788 | /*-------------------------------------------------------------------------*/ | |
1789 | ||
5db539e4 | 1790 | static int itd_submit (struct ehci_hcd *ehci, struct urb *urb, |
55016f10 | 1791 | gfp_t mem_flags) |
1da177e4 LT |
1792 | { |
1793 | int status = -EINVAL; | |
1794 | unsigned long flags; | |
1795 | struct ehci_iso_stream *stream; | |
1796 | ||
1797 | /* Get iso_stream head */ | |
1798 | stream = iso_stream_find (ehci, urb); | |
1799 | if (unlikely (stream == NULL)) { | |
1800 | ehci_dbg (ehci, "can't get iso stream\n"); | |
1801 | return -ENOMEM; | |
1802 | } | |
1803 | if (unlikely (urb->interval != stream->interval)) { | |
1804 | ehci_dbg (ehci, "can't change iso interval %d --> %d\n", | |
1805 | stream->interval, urb->interval); | |
1806 | goto done; | |
1807 | } | |
1808 | ||
1809 | #ifdef EHCI_URB_TRACE | |
1810 | ehci_dbg (ehci, | |
1811 | "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n", | |
441b62c1 | 1812 | __func__, urb->dev->devpath, urb, |
1da177e4 LT |
1813 | usb_pipeendpoint (urb->pipe), |
1814 | usb_pipein (urb->pipe) ? "in" : "out", | |
1815 | urb->transfer_buffer_length, | |
1816 | urb->number_of_packets, urb->interval, | |
1817 | stream); | |
1818 | #endif | |
1819 | ||
1820 | /* allocate ITDs w/o locking anything */ | |
1821 | status = itd_urb_transaction (stream, ehci, urb, mem_flags); | |
1822 | if (unlikely (status < 0)) { | |
1823 | ehci_dbg (ehci, "can't init itds\n"); | |
1824 | goto done; | |
1825 | } | |
1826 | ||
1827 | /* schedule ... need to lock */ | |
1828 | spin_lock_irqsave (&ehci->lock, flags); | |
541c7d43 | 1829 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 1830 | status = -ESHUTDOWN; |
e9df41c5 AS |
1831 | goto done_not_linked; |
1832 | } | |
1833 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); | |
1834 | if (unlikely(status)) | |
1835 | goto done_not_linked; | |
1836 | status = iso_stream_schedule(ehci, urb, stream); | |
53bd6a60 | 1837 | if (likely (status == 0)) |
1da177e4 | 1838 | itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream); |
e9df41c5 AS |
1839 | else |
1840 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
1841 | done_not_linked: | |
1da177e4 LT |
1842 | spin_unlock_irqrestore (&ehci->lock, flags); |
1843 | ||
1844 | done: | |
1845 | if (unlikely (status < 0)) | |
1846 | iso_stream_put (ehci, stream); | |
1847 | return status; | |
1848 | } | |
1849 | ||
1da177e4 LT |
1850 | /*-------------------------------------------------------------------------*/ |
1851 | ||
1852 | /* | |
1853 | * "Split ISO TDs" ... used for USB 1.1 devices going through the | |
1854 | * TTs in USB 2.0 hubs. These need microframe scheduling. | |
1855 | */ | |
1856 | ||
1857 | static inline void | |
6dbd682b SR |
1858 | sitd_sched_init( |
1859 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1860 | struct ehci_iso_sched *iso_sched, |
1861 | struct ehci_iso_stream *stream, | |
1862 | struct urb *urb | |
1863 | ) | |
1864 | { | |
1865 | unsigned i; | |
1866 | dma_addr_t dma = urb->transfer_dma; | |
1867 | ||
1868 | /* how many frames are needed for these transfers */ | |
1869 | iso_sched->span = urb->number_of_packets * stream->interval; | |
1870 | ||
1871 | /* figure out per-frame sitd fields that we'll need later | |
1872 | * when we fit new sitds into the schedule. | |
1873 | */ | |
1874 | for (i = 0; i < urb->number_of_packets; i++) { | |
1875 | struct ehci_iso_packet *packet = &iso_sched->packet [i]; | |
1876 | unsigned length; | |
1877 | dma_addr_t buf; | |
1878 | u32 trans; | |
1879 | ||
1880 | length = urb->iso_frame_desc [i].length & 0x03ff; | |
1881 | buf = dma + urb->iso_frame_desc [i].offset; | |
1882 | ||
1883 | trans = SITD_STS_ACTIVE; | |
1884 | if (((i + 1) == urb->number_of_packets) | |
1885 | && !(urb->transfer_flags & URB_NO_INTERRUPT)) | |
1886 | trans |= SITD_IOC; | |
1887 | trans |= length << 16; | |
6dbd682b | 1888 | packet->transaction = cpu_to_hc32(ehci, trans); |
1da177e4 LT |
1889 | |
1890 | /* might need to cross a buffer page within a td */ | |
1891 | packet->bufp = buf; | |
1892 | packet->buf1 = (buf + length) & ~0x0fff; | |
1893 | if (packet->buf1 != (buf & ~(u64)0x0fff)) | |
1894 | packet->cross = 1; | |
1895 | ||
53bd6a60 | 1896 | /* OUT uses multiple start-splits */ |
1da177e4 LT |
1897 | if (stream->bEndpointAddress & USB_DIR_IN) |
1898 | continue; | |
1899 | length = (length + 187) / 188; | |
1900 | if (length > 1) /* BEGIN vs ALL */ | |
1901 | length |= 1 << 3; | |
1902 | packet->buf1 |= length; | |
1903 | } | |
1904 | } | |
1905 | ||
1906 | static int | |
1907 | sitd_urb_transaction ( | |
1908 | struct ehci_iso_stream *stream, | |
1909 | struct ehci_hcd *ehci, | |
1910 | struct urb *urb, | |
55016f10 | 1911 | gfp_t mem_flags |
1da177e4 LT |
1912 | ) |
1913 | { | |
1914 | struct ehci_sitd *sitd; | |
1915 | dma_addr_t sitd_dma; | |
1916 | int i; | |
1917 | struct ehci_iso_sched *iso_sched; | |
1918 | unsigned long flags; | |
1919 | ||
1920 | iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags); | |
1921 | if (iso_sched == NULL) | |
1922 | return -ENOMEM; | |
1923 | ||
6dbd682b | 1924 | sitd_sched_init(ehci, iso_sched, stream, urb); |
1da177e4 LT |
1925 | |
1926 | /* allocate/init sITDs */ | |
1927 | spin_lock_irqsave (&ehci->lock, flags); | |
1928 | for (i = 0; i < urb->number_of_packets; i++) { | |
1929 | ||
1930 | /* NOTE: for now, we don't try to handle wraparound cases | |
1931 | * for IN (using sitd->hw_backpointer, like a FSTN), which | |
1932 | * means we never need two sitds for full speed packets. | |
1933 | */ | |
1934 | ||
1935 | /* free_list.next might be cache-hot ... but maybe | |
1936 | * the HC caches it too. avoid that issue for now. | |
1937 | */ | |
1938 | ||
1939 | /* prefer previously-allocated sitds */ | |
1940 | if (!list_empty(&stream->free_list)) { | |
1941 | sitd = list_entry (stream->free_list.prev, | |
1942 | struct ehci_sitd, sitd_list); | |
1943 | list_del (&sitd->sitd_list); | |
1944 | sitd_dma = sitd->sitd_dma; | |
3d01f0fe | 1945 | } else { |
1da177e4 LT |
1946 | spin_unlock_irqrestore (&ehci->lock, flags); |
1947 | sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags, | |
1948 | &sitd_dma); | |
1949 | spin_lock_irqsave (&ehci->lock, flags); | |
3d01f0fe KW |
1950 | if (!sitd) { |
1951 | iso_sched_free(stream, iso_sched); | |
1952 | spin_unlock_irqrestore(&ehci->lock, flags); | |
1953 | return -ENOMEM; | |
1954 | } | |
1da177e4 LT |
1955 | } |
1956 | ||
1da177e4 LT |
1957 | memset (sitd, 0, sizeof *sitd); |
1958 | sitd->sitd_dma = sitd_dma; | |
1959 | list_add (&sitd->sitd_list, &iso_sched->td_list); | |
1960 | } | |
1961 | ||
1962 | /* temporarily store schedule info in hcpriv */ | |
1963 | urb->hcpriv = iso_sched; | |
1964 | urb->error_count = 0; | |
1965 | ||
1966 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1967 | return 0; | |
1968 | } | |
1969 | ||
1970 | /*-------------------------------------------------------------------------*/ | |
1971 | ||
1972 | static inline void | |
6dbd682b SR |
1973 | sitd_patch( |
1974 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1975 | struct ehci_iso_stream *stream, |
1976 | struct ehci_sitd *sitd, | |
1977 | struct ehci_iso_sched *iso_sched, | |
1978 | unsigned index | |
1979 | ) | |
1980 | { | |
1981 | struct ehci_iso_packet *uf = &iso_sched->packet [index]; | |
1982 | u64 bufp = uf->bufp; | |
1983 | ||
6dbd682b | 1984 | sitd->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
1985 | sitd->hw_fullspeed_ep = stream->address; |
1986 | sitd->hw_uframe = stream->splits; | |
1987 | sitd->hw_results = uf->transaction; | |
6dbd682b | 1988 | sitd->hw_backpointer = EHCI_LIST_END(ehci); |
1da177e4 LT |
1989 | |
1990 | bufp = uf->bufp; | |
6dbd682b SR |
1991 | sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp); |
1992 | sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32); | |
1da177e4 | 1993 | |
6dbd682b | 1994 | sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1); |
1da177e4 LT |
1995 | if (uf->cross) |
1996 | bufp += 4096; | |
6dbd682b | 1997 | sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32); |
1da177e4 LT |
1998 | sitd->index = index; |
1999 | } | |
2000 | ||
2001 | static inline void | |
2002 | sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd) | |
2003 | { | |
2004 | /* note: sitd ordering could matter (CSPLIT then SSPLIT) */ | |
2005 | sitd->sitd_next = ehci->pshadow [frame]; | |
2006 | sitd->hw_next = ehci->periodic [frame]; | |
2007 | ehci->pshadow [frame].sitd = sitd; | |
2008 | sitd->frame = frame; | |
2009 | wmb (); | |
6dbd682b | 2010 | ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD); |
1da177e4 LT |
2011 | } |
2012 | ||
2013 | /* fit urb's sitds into the selected schedule slot; activate as needed */ | |
2014 | static int | |
2015 | sitd_link_urb ( | |
2016 | struct ehci_hcd *ehci, | |
2017 | struct urb *urb, | |
2018 | unsigned mod, | |
2019 | struct ehci_iso_stream *stream | |
2020 | ) | |
2021 | { | |
2022 | int packet; | |
2023 | unsigned next_uframe; | |
2024 | struct ehci_iso_sched *sched = urb->hcpriv; | |
2025 | struct ehci_sitd *sitd; | |
2026 | ||
2027 | next_uframe = stream->next_uframe; | |
2028 | ||
2029 | if (list_empty(&stream->td_list)) { | |
2030 | /* usbfs ignores TT bandwidth */ | |
2031 | ehci_to_hcd(ehci)->self.bandwidth_allocated | |
2032 | += stream->bandwidth; | |
2033 | ehci_vdbg (ehci, | |
2034 | "sched devp %s ep%d%s-iso [%d] %dms/%04x\n", | |
2035 | urb->dev->devpath, stream->bEndpointAddress & 0x0f, | |
2036 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out", | |
bccbefaa | 2037 | (next_uframe >> 3) & (ehci->periodic_size - 1), |
6dbd682b | 2038 | stream->interval, hc32_to_cpu(ehci, stream->splits)); |
1da177e4 | 2039 | } |
05570297 AH |
2040 | |
2041 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | |
ad93562b AX |
2042 | if (ehci->amd_pll_fix == 1) |
2043 | usb_amd_quirk_pll_disable(); | |
05570297 AH |
2044 | } |
2045 | ||
1da177e4 LT |
2046 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; |
2047 | ||
2048 | /* fill sITDs frame by frame */ | |
2049 | for (packet = 0, sitd = NULL; | |
2050 | packet < urb->number_of_packets; | |
2051 | packet++) { | |
2052 | ||
2053 | /* ASSERT: we have all necessary sitds */ | |
2054 | BUG_ON (list_empty (&sched->td_list)); | |
2055 | ||
2056 | /* ASSERT: no itds for this endpoint in this frame */ | |
2057 | ||
2058 | sitd = list_entry (sched->td_list.next, | |
2059 | struct ehci_sitd, sitd_list); | |
2060 | list_move_tail (&sitd->sitd_list, &stream->td_list); | |
2061 | sitd->stream = iso_stream_get (stream); | |
508db8c9 | 2062 | sitd->urb = urb; |
1da177e4 | 2063 | |
6dbd682b | 2064 | sitd_patch(ehci, stream, sitd, sched, packet); |
bccbefaa | 2065 | sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1), |
1da177e4 LT |
2066 | sitd); |
2067 | ||
2068 | next_uframe += stream->interval << 3; | |
1da177e4 | 2069 | } |
bccbefaa | 2070 | stream->next_uframe = next_uframe & (mod - 1); |
1da177e4 LT |
2071 | |
2072 | /* don't need that schedule data any more */ | |
2073 | iso_sched_free (stream, sched); | |
2074 | urb->hcpriv = NULL; | |
2075 | ||
2076 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
01c17142 | 2077 | return enable_periodic(ehci); |
1da177e4 LT |
2078 | } |
2079 | ||
2080 | /*-------------------------------------------------------------------------*/ | |
2081 | ||
2082 | #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \ | |
53bd6a60 | 2083 | | SITD_STS_XACT | SITD_STS_MMF) |
1da177e4 | 2084 | |
30bf54e6 DB |
2085 | /* Process and recycle a completed SITD. Return true iff its urb completed, |
2086 | * and hence its completion callback probably added things to the hardware | |
2087 | * schedule. | |
2088 | * | |
2089 | * Note that we carefully avoid recycling this descriptor until after any | |
2090 | * completion callback runs, so that it won't be reused quickly. That is, | |
2091 | * assuming (a) no more than two urbs per frame on this endpoint, and also | |
2092 | * (b) only this endpoint's completions submit URBs. It seems some silicon | |
2093 | * corrupts things if you reuse completed descriptors very quickly... | |
2094 | */ | |
1da177e4 LT |
2095 | static unsigned |
2096 | sitd_complete ( | |
2097 | struct ehci_hcd *ehci, | |
7d12e780 | 2098 | struct ehci_sitd *sitd |
1da177e4 LT |
2099 | ) { |
2100 | struct urb *urb = sitd->urb; | |
2101 | struct usb_iso_packet_descriptor *desc; | |
2102 | u32 t; | |
2103 | int urb_index = -1; | |
2104 | struct ehci_iso_stream *stream = sitd->stream; | |
2105 | struct usb_device *dev; | |
30bf54e6 | 2106 | unsigned retval = false; |
1da177e4 LT |
2107 | |
2108 | urb_index = sitd->index; | |
2109 | desc = &urb->iso_frame_desc [urb_index]; | |
6dbd682b | 2110 | t = hc32_to_cpup(ehci, &sitd->hw_results); |
1da177e4 LT |
2111 | |
2112 | /* report transfer status */ | |
2113 | if (t & SITD_ERRS) { | |
2114 | urb->error_count++; | |
2115 | if (t & SITD_STS_DBE) | |
2116 | desc->status = usb_pipein (urb->pipe) | |
2117 | ? -ENOSR /* hc couldn't read */ | |
2118 | : -ECOMM; /* hc couldn't write */ | |
2119 | else if (t & SITD_STS_BABBLE) | |
2120 | desc->status = -EOVERFLOW; | |
2121 | else /* XACT, MMF, etc */ | |
2122 | desc->status = -EPROTO; | |
2123 | } else { | |
2124 | desc->status = 0; | |
ec6d67e3 AS |
2125 | desc->actual_length = desc->length - SITD_LENGTH(t); |
2126 | urb->actual_length += desc->actual_length; | |
1da177e4 | 2127 | } |
1da177e4 LT |
2128 | |
2129 | /* handle completion now? */ | |
2130 | if ((urb_index + 1) != urb->number_of_packets) | |
30bf54e6 | 2131 | goto done; |
1da177e4 LT |
2132 | |
2133 | /* ASSERT: it's really the last sitd for this urb | |
2134 | list_for_each_entry (sitd, &stream->td_list, sitd_list) | |
2135 | BUG_ON (sitd->urb == urb); | |
2136 | */ | |
2137 | ||
aa16ca30 | 2138 | /* give urb back to the driver; completion often (re)submits */ |
6a8e87b2 | 2139 | dev = urb->dev; |
14c04c0f | 2140 | ehci_urb_done(ehci, urb, 0); |
30bf54e6 | 2141 | retval = true; |
1da177e4 | 2142 | urb = NULL; |
01c17142 | 2143 | (void) disable_periodic(ehci); |
1da177e4 LT |
2144 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
2145 | ||
05570297 | 2146 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { |
ad93562b AX |
2147 | if (ehci->amd_pll_fix == 1) |
2148 | usb_amd_quirk_pll_enable(); | |
05570297 AH |
2149 | } |
2150 | ||
508db8c9 | 2151 | if (list_is_singular(&stream->td_list)) { |
1da177e4 LT |
2152 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
2153 | -= stream->bandwidth; | |
2154 | ehci_vdbg (ehci, | |
2155 | "deschedule devp %s ep%d%s-iso\n", | |
2156 | dev->devpath, stream->bEndpointAddress & 0x0f, | |
2157 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out"); | |
2158 | } | |
2159 | iso_stream_put (ehci, stream); | |
0e5f231b | 2160 | |
30bf54e6 | 2161 | done: |
30bf54e6 | 2162 | sitd->urb = NULL; |
0e5f231b AS |
2163 | if (ehci->clock_frame != sitd->frame) { |
2164 | /* OK to recycle this SITD now. */ | |
2165 | sitd->stream = NULL; | |
2166 | list_move(&sitd->sitd_list, &stream->free_list); | |
2167 | iso_stream_put(ehci, stream); | |
2168 | } else { | |
2169 | /* HW might remember this SITD, so we can't recycle it yet. | |
2170 | * Move it to a safe place until a new frame starts. | |
2171 | */ | |
2172 | list_move(&sitd->sitd_list, &ehci->cached_sitd_list); | |
2173 | if (stream->refcount == 2) { | |
2174 | /* If iso_stream_put() were called here, stream | |
2175 | * would be freed. Instead, just prevent reuse. | |
2176 | */ | |
2177 | stream->ep->hcpriv = NULL; | |
2178 | stream->ep = NULL; | |
2179 | } | |
2180 | } | |
30bf54e6 | 2181 | return retval; |
1da177e4 LT |
2182 | } |
2183 | ||
2184 | ||
5db539e4 | 2185 | static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb, |
55016f10 | 2186 | gfp_t mem_flags) |
1da177e4 LT |
2187 | { |
2188 | int status = -EINVAL; | |
2189 | unsigned long flags; | |
2190 | struct ehci_iso_stream *stream; | |
2191 | ||
2192 | /* Get iso_stream head */ | |
2193 | stream = iso_stream_find (ehci, urb); | |
2194 | if (stream == NULL) { | |
2195 | ehci_dbg (ehci, "can't get iso stream\n"); | |
2196 | return -ENOMEM; | |
2197 | } | |
2198 | if (urb->interval != stream->interval) { | |
2199 | ehci_dbg (ehci, "can't change iso interval %d --> %d\n", | |
2200 | stream->interval, urb->interval); | |
2201 | goto done; | |
2202 | } | |
2203 | ||
2204 | #ifdef EHCI_URB_TRACE | |
2205 | ehci_dbg (ehci, | |
2206 | "submit %p dev%s ep%d%s-iso len %d\n", | |
2207 | urb, urb->dev->devpath, | |
2208 | usb_pipeendpoint (urb->pipe), | |
2209 | usb_pipein (urb->pipe) ? "in" : "out", | |
2210 | urb->transfer_buffer_length); | |
2211 | #endif | |
2212 | ||
2213 | /* allocate SITDs */ | |
2214 | status = sitd_urb_transaction (stream, ehci, urb, mem_flags); | |
2215 | if (status < 0) { | |
2216 | ehci_dbg (ehci, "can't init sitds\n"); | |
2217 | goto done; | |
2218 | } | |
2219 | ||
2220 | /* schedule ... need to lock */ | |
2221 | spin_lock_irqsave (&ehci->lock, flags); | |
541c7d43 | 2222 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 2223 | status = -ESHUTDOWN; |
e9df41c5 AS |
2224 | goto done_not_linked; |
2225 | } | |
2226 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); | |
2227 | if (unlikely(status)) | |
2228 | goto done_not_linked; | |
2229 | status = iso_stream_schedule(ehci, urb, stream); | |
53bd6a60 | 2230 | if (status == 0) |
1da177e4 | 2231 | sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream); |
e9df41c5 AS |
2232 | else |
2233 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
2234 | done_not_linked: | |
1da177e4 LT |
2235 | spin_unlock_irqrestore (&ehci->lock, flags); |
2236 | ||
2237 | done: | |
2238 | if (status < 0) | |
2239 | iso_stream_put (ehci, stream); | |
2240 | return status; | |
2241 | } | |
2242 | ||
1da177e4 LT |
2243 | /*-------------------------------------------------------------------------*/ |
2244 | ||
0e5f231b | 2245 | static void free_cached_lists(struct ehci_hcd *ehci) |
9aa09d2f KW |
2246 | { |
2247 | struct ehci_itd *itd, *n; | |
0e5f231b | 2248 | struct ehci_sitd *sitd, *sn; |
9aa09d2f KW |
2249 | |
2250 | list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) { | |
2251 | struct ehci_iso_stream *stream = itd->stream; | |
2252 | itd->stream = NULL; | |
2253 | list_move(&itd->itd_list, &stream->free_list); | |
2254 | iso_stream_put(ehci, stream); | |
2255 | } | |
0e5f231b AS |
2256 | |
2257 | list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) { | |
2258 | struct ehci_iso_stream *stream = sitd->stream; | |
2259 | sitd->stream = NULL; | |
2260 | list_move(&sitd->sitd_list, &stream->free_list); | |
2261 | iso_stream_put(ehci, stream); | |
2262 | } | |
9aa09d2f KW |
2263 | } |
2264 | ||
2265 | /*-------------------------------------------------------------------------*/ | |
2266 | ||
1da177e4 | 2267 | static void |
7d12e780 | 2268 | scan_periodic (struct ehci_hcd *ehci) |
1da177e4 | 2269 | { |
b40e43fc | 2270 | unsigned now_uframe, frame, clock, clock_frame, mod; |
1da177e4 LT |
2271 | unsigned modified; |
2272 | ||
2273 | mod = ehci->periodic_size << 3; | |
2274 | ||
2275 | /* | |
2276 | * When running, scan from last scan point up to "now" | |
2277 | * else clean up by scanning everything that's left. | |
2278 | * Touches as few pages as possible: cache-friendly. | |
2279 | */ | |
2280 | now_uframe = ehci->next_uframe; | |
9aa09d2f | 2281 | if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { |
083522d7 | 2282 | clock = ehci_readl(ehci, &ehci->regs->frame_index); |
bccbefaa | 2283 | clock_frame = (clock >> 3) & (ehci->periodic_size - 1); |
9aa09d2f | 2284 | } else { |
1da177e4 | 2285 | clock = now_uframe + mod - 1; |
9aa09d2f KW |
2286 | clock_frame = -1; |
2287 | } | |
2288 | if (ehci->clock_frame != clock_frame) { | |
0e5f231b | 2289 | free_cached_lists(ehci); |
9aa09d2f KW |
2290 | ehci->clock_frame = clock_frame; |
2291 | } | |
bccbefaa | 2292 | clock &= mod - 1; |
b40e43fc | 2293 | clock_frame = clock >> 3; |
1e12c910 | 2294 | ++ehci->periodic_stamp; |
1da177e4 LT |
2295 | |
2296 | for (;;) { | |
2297 | union ehci_shadow q, *q_p; | |
6dbd682b | 2298 | __hc32 type, *hw_p; |
79592b72 | 2299 | unsigned incomplete = false; |
1da177e4 | 2300 | |
1da177e4 | 2301 | frame = now_uframe >> 3; |
1da177e4 LT |
2302 | |
2303 | restart: | |
2304 | /* scan each element in frame's queue for completions */ | |
2305 | q_p = &ehci->pshadow [frame]; | |
2306 | hw_p = &ehci->periodic [frame]; | |
2307 | q.ptr = q_p->ptr; | |
6dbd682b | 2308 | type = Q_NEXT_TYPE(ehci, *hw_p); |
1da177e4 LT |
2309 | modified = 0; |
2310 | ||
2311 | while (q.ptr != NULL) { | |
2312 | unsigned uf; | |
2313 | union ehci_shadow temp; | |
2314 | int live; | |
2315 | ||
2316 | live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state); | |
6dbd682b | 2317 | switch (hc32_to_cpu(ehci, type)) { |
1da177e4 LT |
2318 | case Q_TYPE_QH: |
2319 | /* handle any completions */ | |
2320 | temp.qh = qh_get (q.qh); | |
3807e26d | 2321 | type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next); |
1da177e4 | 2322 | q = q.qh->qh_next; |
1e12c910 AS |
2323 | if (temp.qh->stamp != ehci->periodic_stamp) { |
2324 | modified = qh_completions(ehci, temp.qh); | |
2325 | if (!modified) | |
2326 | temp.qh->stamp = ehci->periodic_stamp; | |
2327 | if (unlikely(list_empty(&temp.qh->qtd_list) || | |
2328 | temp.qh->needs_rescan)) | |
2329 | intr_deschedule(ehci, temp.qh); | |
2330 | } | |
1da177e4 LT |
2331 | qh_put (temp.qh); |
2332 | break; | |
2333 | case Q_TYPE_FSTN: | |
2334 | /* for "save place" FSTNs, look at QH entries | |
2335 | * in the previous frame for completions. | |
2336 | */ | |
6dbd682b | 2337 | if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) { |
1da177e4 LT |
2338 | dbg ("ignoring completions from FSTNs"); |
2339 | } | |
6dbd682b | 2340 | type = Q_NEXT_TYPE(ehci, q.fstn->hw_next); |
1da177e4 LT |
2341 | q = q.fstn->fstn_next; |
2342 | break; | |
2343 | case Q_TYPE_ITD: | |
79592b72 DB |
2344 | /* If this ITD is still active, leave it for |
2345 | * later processing ... check the next entry. | |
b40e43fc AS |
2346 | * No need to check for activity unless the |
2347 | * frame is current. | |
79592b72 | 2348 | */ |
b40e43fc AS |
2349 | if (frame == clock_frame && live) { |
2350 | rmb(); | |
2351 | for (uf = 0; uf < 8; uf++) { | |
2352 | if (q.itd->hw_transaction[uf] & | |
2353 | ITD_ACTIVE(ehci)) | |
2354 | break; | |
2355 | } | |
2356 | if (uf < 8) { | |
2357 | incomplete = true; | |
2358 | q_p = &q.itd->itd_next; | |
2359 | hw_p = &q.itd->hw_next; | |
2360 | type = Q_NEXT_TYPE(ehci, | |
6dbd682b | 2361 | q.itd->hw_next); |
b40e43fc AS |
2362 | q = *q_p; |
2363 | break; | |
2364 | } | |
1da177e4 | 2365 | } |
1da177e4 | 2366 | |
79592b72 DB |
2367 | /* Take finished ITDs out of the schedule |
2368 | * and process them: recycle, maybe report | |
2369 | * URB completion. HC won't cache the | |
1da177e4 LT |
2370 | * pointer for much longer, if at all. |
2371 | */ | |
2372 | *q_p = q.itd->itd_next; | |
3d091a6f AX |
2373 | if (!ehci->use_dummy_qh || |
2374 | q.itd->hw_next != EHCI_LIST_END(ehci)) | |
2375 | *hw_p = q.itd->hw_next; | |
2376 | else | |
2377 | *hw_p = ehci->dummy->qh_dma; | |
6dbd682b | 2378 | type = Q_NEXT_TYPE(ehci, q.itd->hw_next); |
1da177e4 | 2379 | wmb(); |
7d12e780 | 2380 | modified = itd_complete (ehci, q.itd); |
1da177e4 LT |
2381 | q = *q_p; |
2382 | break; | |
2383 | case Q_TYPE_SITD: | |
79592b72 DB |
2384 | /* If this SITD is still active, leave it for |
2385 | * later processing ... check the next entry. | |
b40e43fc AS |
2386 | * No need to check for activity unless the |
2387 | * frame is current. | |
79592b72 | 2388 | */ |
22e18694 | 2389 | if (((frame == clock_frame) || |
bccbefaa | 2390 | (((frame + 1) & (ehci->periodic_size - 1)) |
22e18694 DE |
2391 | == clock_frame)) |
2392 | && live | |
2393 | && (q.sitd->hw_results & | |
2394 | SITD_ACTIVE(ehci))) { | |
2395 | ||
79592b72 | 2396 | incomplete = true; |
1da177e4 LT |
2397 | q_p = &q.sitd->sitd_next; |
2398 | hw_p = &q.sitd->hw_next; | |
6dbd682b SR |
2399 | type = Q_NEXT_TYPE(ehci, |
2400 | q.sitd->hw_next); | |
1da177e4 LT |
2401 | q = *q_p; |
2402 | break; | |
2403 | } | |
79592b72 DB |
2404 | |
2405 | /* Take finished SITDs out of the schedule | |
2406 | * and process them: recycle, maybe report | |
2407 | * URB completion. | |
2408 | */ | |
1da177e4 | 2409 | *q_p = q.sitd->sitd_next; |
3d091a6f AX |
2410 | if (!ehci->use_dummy_qh || |
2411 | q.sitd->hw_next != EHCI_LIST_END(ehci)) | |
2412 | *hw_p = q.sitd->hw_next; | |
2413 | else | |
2414 | *hw_p = ehci->dummy->qh_dma; | |
6dbd682b | 2415 | type = Q_NEXT_TYPE(ehci, q.sitd->hw_next); |
1da177e4 | 2416 | wmb(); |
7d12e780 | 2417 | modified = sitd_complete (ehci, q.sitd); |
1da177e4 LT |
2418 | q = *q_p; |
2419 | break; | |
2420 | default: | |
2421 | dbg ("corrupt type %d frame %d shadow %p", | |
2422 | type, frame, q.ptr); | |
2423 | // BUG (); | |
2424 | q.ptr = NULL; | |
2425 | } | |
2426 | ||
2427 | /* assume completion callbacks modify the queue */ | |
aa16ca30 DB |
2428 | if (unlikely (modified)) { |
2429 | if (likely(ehci->periodic_sched > 0)) | |
2430 | goto restart; | |
01c17142 | 2431 | /* short-circuit this scan */ |
aa16ca30 DB |
2432 | now_uframe = clock; |
2433 | break; | |
2434 | } | |
1da177e4 LT |
2435 | } |
2436 | ||
79592b72 DB |
2437 | /* If we can tell we caught up to the hardware, stop now. |
2438 | * We can't advance our scan without collecting the ISO | |
2439 | * transfers that are still pending in this frame. | |
2440 | */ | |
2441 | if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { | |
2442 | ehci->next_uframe = now_uframe; | |
2443 | break; | |
2444 | } | |
1da177e4 LT |
2445 | |
2446 | // FIXME: this assumes we won't get lapped when | |
2447 | // latencies climb; that should be rare, but... | |
2448 | // detect it, and just go all the way around. | |
2449 | // FLR might help detect this case, so long as latencies | |
2450 | // don't exceed periodic_size msec (default 1.024 sec). | |
2451 | ||
2452 | // FIXME: likewise assumes HC doesn't halt mid-scan | |
2453 | ||
2454 | if (now_uframe == clock) { | |
2455 | unsigned now; | |
2456 | ||
aa16ca30 DB |
2457 | if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) |
2458 | || ehci->periodic_sched == 0) | |
1da177e4 LT |
2459 | break; |
2460 | ehci->next_uframe = now_uframe; | |
bccbefaa AS |
2461 | now = ehci_readl(ehci, &ehci->regs->frame_index) & |
2462 | (mod - 1); | |
1da177e4 LT |
2463 | if (now_uframe == now) |
2464 | break; | |
2465 | ||
2466 | /* rescan the rest of this frame, then ... */ | |
2467 | clock = now; | |
b40e43fc | 2468 | clock_frame = clock >> 3; |
9aa09d2f | 2469 | if (ehci->clock_frame != clock_frame) { |
0e5f231b | 2470 | free_cached_lists(ehci); |
9aa09d2f | 2471 | ehci->clock_frame = clock_frame; |
1e12c910 | 2472 | ++ehci->periodic_stamp; |
9aa09d2f | 2473 | } |
1da177e4 LT |
2474 | } else { |
2475 | now_uframe++; | |
bccbefaa | 2476 | now_uframe &= mod - 1; |
1da177e4 | 2477 | } |
53bd6a60 | 2478 | } |
1da177e4 | 2479 | } |