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USB: make usb_release_interface static
[deliverable/linux.git] / drivers / usb / host / ehci-sched.c
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
53bd6a60 4 *
1da177e4
LT		 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20/* this file is part of ehci-hcd.c */
21
22/*-------------------------------------------------------------------------*/
23
24/*
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
27 *
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
31 *
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
35 */
36
37static int ehci_get_frame (struct usb_hcd *hcd);
38
39/*-------------------------------------------------------------------------*/
40
41/*
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
45 */
46static union ehci_shadow *
6dbd682b
SR		 47periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
1da177e4 49{
6dbd682b 50 switch (hc32_to_cpu(ehci, tag)) {
1da177e4
LT		 51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
60 }
61}
62
63/* caller must hold ehci->lock */
64static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
65{
6dbd682b
SR		 66 union ehci_shadow *prev_p = &ehci->pshadow[frame];
67 __hc32 *hw_p = &ehci->periodic[frame];
1da177e4
LT		 68 union ehci_shadow here = *prev_p;
69
70 /* find predecessor of "ptr"; hw and shadow lists are in sync */
71 while (here.ptr && here.ptr != ptr) {
6dbd682b
SR		 72 prev_p = periodic_next_shadow(ehci, prev_p,
73 Q_NEXT_TYPE(ehci, *hw_p));
1da177e4
LT		 74 hw_p = here.hw_next;
75 here = *prev_p;
76 }
77 /* an interrupt entry (at list end) could have been shared */
78 if (!here.ptr)
79 return;
80
81 /* update shadow and hardware lists ... the old "next" pointers
82 * from ptr may still be in use, the caller updates them.
83 */
6dbd682b
SR		 84 *prev_p = *periodic_next_shadow(ehci, &here,
85 Q_NEXT_TYPE(ehci, *hw_p));
1da177e4
LT		 86 *hw_p = *here.hw_next;
87}
88
89/* how many of the uframe's 125 usecs are allocated? */
90static unsigned short
91periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
92{
6dbd682b 93 __hc32 *hw_p = &ehci->periodic [frame];
1da177e4
LT		 94 union ehci_shadow *q = &ehci->pshadow [frame];
95 unsigned usecs = 0;
96
97 while (q->ptr) {
6dbd682b 98 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
1da177e4
LT		 99 case Q_TYPE_QH:
100 /* is it in the S-mask? */
6dbd682b 101 if (q->qh->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
1da177e4
LT		 102 usecs += q->qh->usecs;
103 /* ... or C-mask? */
6dbd682b
SR		 104 if (q->qh->hw_info2 & cpu_to_hc32(ehci,
105 1 << (8 + uframe)))
1da177e4
LT		 106 usecs += q->qh->c_usecs;
107 hw_p = &q->qh->hw_next;
108 q = &q->qh->qh_next;
109 break;
110 // case Q_TYPE_FSTN:
111 default:
112 /* for "save place" FSTNs, count the relevant INTR
113 * bandwidth from the previous frame
114 */
6dbd682b 115 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
1da177e4
LT		 116 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
117 }
118 hw_p = &q->fstn->hw_next;
119 q = &q->fstn->fstn_next;
120 break;
121 case Q_TYPE_ITD:
122 usecs += q->itd->usecs [uframe];
123 hw_p = &q->itd->hw_next;
124 q = &q->itd->itd_next;
125 break;
126 case Q_TYPE_SITD:
127 /* is it in the S-mask? (count SPLIT, DATA) */
6dbd682b
SR		 128 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
129 1 << uframe)) {
1da177e4 130 if (q->sitd->hw_fullspeed_ep &
6dbd682b 131 cpu_to_hc32(ehci, 1<<31))
1da177e4
LT		 132 usecs += q->sitd->stream->usecs;
133 else /* worst case for OUT start-split */
134 usecs += HS_USECS_ISO (188);
135 }
136
137 /* ... C-mask? (count CSPLIT, DATA) */
138 if (q->sitd->hw_uframe &
6dbd682b 139 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
1da177e4
LT		 140 /* worst case for IN complete-split */
141 usecs += q->sitd->stream->c_usecs;
142 }
143
144 hw_p = &q->sitd->hw_next;
145 q = &q->sitd->sitd_next;
146 break;
147 }
148 }
149#ifdef DEBUG
150 if (usecs > 100)
151 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
152 frame * 8 + uframe, usecs);
153#endif
154 return usecs;
155}
156
157/*-------------------------------------------------------------------------*/
158
159static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
160{
161 if (!dev1->tt || !dev2->tt)
162 return 0;
163 if (dev1->tt != dev2->tt)
164 return 0;
165 if (dev1->tt->multi)
166 return dev1->ttport == dev2->ttport;
167 else
168 return 1;
169}
170
ba47f66b
DS		 171#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
172
173/* Which uframe does the low/fullspeed transfer start in?
174 *
175 * The parameter is the mask of ssplits in "H-frame" terms
176 * and this returns the transfer start uframe in "B-frame" terms,
177 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
178 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
179 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
180 */
6dbd682b 181static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
ba47f66b 182{
6dbd682b 183 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
ba47f66b
DS		 184 if (!smask) {
185 ehci_err(ehci, "invalid empty smask!\n");
186 /* uframe 7 can't have bw so this will indicate failure */
187 return 7;
188 }
189 return ffs(smask) - 1;
190}
191
192static const unsigned char
193max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
194
195/* carryover low/fullspeed bandwidth that crosses uframe boundries */
196static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
197{
198 int i;
199 for (i=0; i<7; i++) {
200 if (max_tt_usecs[i] < tt_usecs[i]) {
201 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
202 tt_usecs[i] = max_tt_usecs[i];
203 }
204 }
205}
206
207/* How many of the tt's periodic downstream 1000 usecs are allocated?
208 *
209 * While this measures the bandwidth in terms of usecs/uframe,
210 * the low/fullspeed bus has no notion of uframes, so any particular
211 * low/fullspeed transfer can "carry over" from one uframe to the next,
212 * since the TT just performs downstream transfers in sequence.
213 *
214 * For example two seperate 100 usec transfers can start in the same uframe,
215 * and the second one would "carry over" 75 usecs into the next uframe.
216 */
217static void
218periodic_tt_usecs (
219 struct ehci_hcd *ehci,
220 struct usb_device *dev,
221 unsigned frame,
222 unsigned short tt_usecs[8]
223)
224{
6dbd682b 225 __hc32 *hw_p = &ehci->periodic [frame];
ba47f66b
DS		 226 union ehci_shadow *q = &ehci->pshadow [frame];
227 unsigned char uf;
228
229 memset(tt_usecs, 0, 16);
230
231 while (q->ptr) {
6dbd682b 232 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
ba47f66b
DS		 233 case Q_TYPE_ITD:
234 hw_p = &q->itd->hw_next;
235 q = &q->itd->itd_next;
236 continue;
237 case Q_TYPE_QH:
238 if (same_tt(dev, q->qh->dev)) {
239 uf = tt_start_uframe(ehci, q->qh->hw_info2);
240 tt_usecs[uf] += q->qh->tt_usecs;
241 }
242 hw_p = &q->qh->hw_next;
243 q = &q->qh->qh_next;
244 continue;
245 case Q_TYPE_SITD:
246 if (same_tt(dev, q->sitd->urb->dev)) {
247 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
248 tt_usecs[uf] += q->sitd->stream->tt_usecs;
249 }
250 hw_p = &q->sitd->hw_next;
251 q = &q->sitd->sitd_next;
252 continue;
253 // case Q_TYPE_FSTN:
254 default:
6dbd682b
SR		 255 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
256 frame);
ba47f66b
DS		 257 hw_p = &q->fstn->hw_next;
258 q = &q->fstn->fstn_next;
259 }
260 }
261
262 carryover_tt_bandwidth(tt_usecs);
263
264 if (max_tt_usecs[7] < tt_usecs[7])
265 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
266 frame, tt_usecs[7] - max_tt_usecs[7]);
267}
268
269/*
270 * Return true if the device's tt's downstream bus is available for a
271 * periodic transfer of the specified length (usecs), starting at the
272 * specified frame/uframe. Note that (as summarized in section 11.19
273 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
274 * uframe.
275 *
276 * The uframe parameter is when the fullspeed/lowspeed transfer
277 * should be executed in "B-frame" terms, which is the same as the
278 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
279 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
280 * See the EHCI spec sec 4.5 and fig 4.7.
281 *
282 * This checks if the full/lowspeed bus, at the specified starting uframe,
283 * has the specified bandwidth available, according to rules listed
284 * in USB 2.0 spec section 11.18.1 fig 11-60.
285 *
286 * This does not check if the transfer would exceed the max ssplit
287 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
288 * since proper scheduling limits ssplits to less than 16 per uframe.
289 */
290static int tt_available (
291 struct ehci_hcd *ehci,
292 unsigned period,
293 struct usb_device *dev,
294 unsigned frame,
295 unsigned uframe,
296 u16 usecs
297)
298{
299 if ((period == 0) || (uframe >= 7)) /* error */
300 return 0;
301
302 for (; frame < ehci->periodic_size; frame += period) {
303 unsigned short tt_usecs[8];
304
305 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
306
307 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
308 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
309 frame, usecs, uframe,
310 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
311 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
312
313 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
314 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
315 frame, uframe);
316 return 0;
317 }
318
319 /* special case for isoc transfers larger than 125us:
320 * the first and each subsequent fully used uframe
321 * must be empty, so as to not illegally delay
322 * already scheduled transactions
323 */
324 if (125 < usecs) {
325 int ufs = (usecs / 125) - 1;
326 int i;
327 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
328 if (0 < tt_usecs[i]) {
329 ehci_vdbg(ehci,
330 "multi-uframe xfer can't fit "
331 "in frame %d uframe %d\n",
332 frame, i);
333 return 0;
334 }
335 }
336
337 tt_usecs[uframe] += usecs;
338
339 carryover_tt_bandwidth(tt_usecs);
340
341 /* fail if the carryover pushed bw past the last uframe's limit */
342 if (max_tt_usecs[7] < tt_usecs[7]) {
343 ehci_vdbg(ehci,
344 "tt unavailable usecs %d frame %d uframe %d\n",
345 usecs, frame, uframe);
346 return 0;
347 }
348 }
349
350 return 1;
351}
352
353#else
354
1da177e4
LT		 355/* return true iff the device's transaction translator is available
356 * for a periodic transfer starting at the specified frame, using
357 * all the uframes in the mask.
358 */
359static int tt_no_collision (
360 struct ehci_hcd *ehci,
361 unsigned period,
362 struct usb_device *dev,
363 unsigned frame,
364 u32 uf_mask
365)
366{
367 if (period == 0) /* error */
368 return 0;
369
370 /* note bandwidth wastage: split never follows csplit
371 * (different dev or endpoint) until the next uframe.
372 * calling convention doesn't make that distinction.
373 */
374 for (; frame < ehci->periodic_size; frame += period) {
375 union ehci_shadow here;
6dbd682b 376 __hc32 type;
1da177e4
LT		 377
378 here = ehci->pshadow [frame];
6dbd682b 379 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
1da177e4 380 while (here.ptr) {
6dbd682b 381 switch (hc32_to_cpu(ehci, type)) {
1da177e4 382 case Q_TYPE_ITD:
6dbd682b 383 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
1da177e4
LT		 384 here = here.itd->itd_next;
385 continue;
386 case Q_TYPE_QH:
387 if (same_tt (dev, here.qh->dev)) {
388 u32 mask;
389
6dbd682b
SR		 390 mask = hc32_to_cpu(ehci,
391 here.qh->hw_info2);
1da177e4
LT		 392 /* "knows" no gap is needed */
393 mask |= mask >> 8;
394 if (mask & uf_mask)
395 break;
396 }
6dbd682b 397 type = Q_NEXT_TYPE(ehci, here.qh->hw_next);
1da177e4
LT		 398 here = here.qh->qh_next;
399 continue;
400 case Q_TYPE_SITD:
401 if (same_tt (dev, here.sitd->urb->dev)) {
402 u16 mask;
403
6dbd682b 404 mask = hc32_to_cpu(ehci, here.sitd
1da177e4
LT		 405 ->hw_uframe);
406 /* FIXME assumes no gap for IN! */
407 mask |= mask >> 8;
408 if (mask & uf_mask)
409 break;
410 }
6dbd682b 411 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
1da177e4
LT		 412 here = here.sitd->sitd_next;
413 continue;
414 // case Q_TYPE_FSTN:
415 default:
416 ehci_dbg (ehci,
417 "periodic frame %d bogus type %d\n",
418 frame, type);
419 }
420
421 /* collision or error */
422 return 0;
423 }
424 }
425
426 /* no collision */
427 return 1;
428}
429
ba47f66b
DS		 430#endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
431
1da177e4
LT		 432/*-------------------------------------------------------------------------*/
433
434static int enable_periodic (struct ehci_hcd *ehci)
435{
436 u32 cmd;
437 int status;
438
439 /* did clearing PSE did take effect yet?
440 * takes effect only at frame boundaries...
441 */
083522d7 442 status = handshake(ehci, &ehci->regs->status, STS_PSS, 0, 9 * 125);
1da177e4
LT		 443 if (status != 0) {
444 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
445 return status;
446 }
447
083522d7
BH		 448 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
449 ehci_writel(ehci, cmd, &ehci->regs->command);
1da177e4
LT		 450 /* posted write ... PSS happens later */
451 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
452
453 /* make sure ehci_work scans these */
083522d7
BH		 454 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
455 % (ehci->periodic_size << 3);
1da177e4
LT		 456 return 0;
457}
458
459static int disable_periodic (struct ehci_hcd *ehci)
460{
461 u32 cmd;
462 int status;
463
464 /* did setting PSE not take effect yet?
465 * takes effect only at frame boundaries...
466 */
083522d7 467 status = handshake(ehci, &ehci->regs->status, STS_PSS, STS_PSS, 9 * 125);
1da177e4
LT		 468 if (status != 0) {
469 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
470 return status;
471 }
472
083522d7
BH		 473 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
474 ehci_writel(ehci, cmd, &ehci->regs->command);
1da177e4
LT		 475 /* posted write ... */
476
477 ehci->next_uframe = -1;
478 return 0;
479}
480
481/*-------------------------------------------------------------------------*/
482
483/* periodic schedule slots have iso tds (normal or split) first, then a
484 * sparse tree for active interrupt transfers.
485 *
486 * this just links in a qh; caller guarantees uframe masks are set right.
487 * no FSTN support (yet; ehci 0.96+)
488 */
489static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
490{
491 unsigned i;
492 unsigned period = qh->period;
493
494 dev_dbg (&qh->dev->dev,
495 "link qh%d-%04x/%p start %d [%d/%d us]\n",
6dbd682b 496 period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
1da177e4
LT		 497 qh, qh->start, qh->usecs, qh->c_usecs);
498
499 /* high bandwidth, or otherwise every microframe */
500 if (period == 0)
501 period = 1;
502
503 for (i = qh->start; i < ehci->periodic_size; i += period) {
6dbd682b
SR		 504 union ehci_shadow *prev = &ehci->pshadow[i];
505 __hc32 *hw_p = &ehci->periodic[i];
1da177e4 506 union ehci_shadow here = *prev;
6dbd682b 507 __hc32 type = 0;
1da177e4
LT		 508
509 /* skip the iso nodes at list head */
510 while (here.ptr) {
6dbd682b
SR		 511 type = Q_NEXT_TYPE(ehci, *hw_p);
512 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1da177e4 513 break;
6dbd682b 514 prev = periodic_next_shadow(ehci, prev, type);
1da177e4
LT		 515 hw_p = &here.qh->hw_next;
516 here = *prev;
517 }
518
519 /* sorting each branch by period (slow-->fast)
520 * enables sharing interior tree nodes
521 */
522 while (here.ptr && qh != here.qh) {
523 if (qh->period > here.qh->period)
524 break;
525 prev = &here.qh->qh_next;
526 hw_p = &here.qh->hw_next;
527 here = *prev;
528 }
529 /* link in this qh, unless some earlier pass did that */
530 if (qh != here.qh) {
531 qh->qh_next = here;
532 if (here.qh)
533 qh->hw_next = *hw_p;
534 wmb ();
535 prev->qh = qh;
6dbd682b 536 *hw_p = QH_NEXT (ehci, qh->qh_dma);
1da177e4
LT		 537 }
538 }
539 qh->qh_state = QH_STATE_LINKED;
540 qh_get (qh);
541
542 /* update per-qh bandwidth for usbfs */
543 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
544 ? ((qh->usecs + qh->c_usecs) / qh->period)
545 : (qh->usecs * 8);
546
547 /* maybe enable periodic schedule processing */
548 if (!ehci->periodic_sched++)
549 return enable_periodic (ehci);
550
551 return 0;
552}
553
554static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
555{
556 unsigned i;
557 unsigned period;
558
559 // FIXME:
560 // IF this isn't high speed
561 // and this qh is active in the current uframe
562 // (and overlay token SplitXstate is false?)
563 // THEN
6dbd682b 564 // qh->hw_info1 |= __constant_cpu_to_hc32(1 << 7 /* "ignore" */);
1da177e4
LT		 565
566 /* high bandwidth, or otherwise part of every microframe */
567 if ((period = qh->period) == 0)
568 period = 1;
569
570 for (i = qh->start; i < ehci->periodic_size; i += period)
571 periodic_unlink (ehci, i, qh);
572
573 /* update per-qh bandwidth for usbfs */
574 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
575 ? ((qh->usecs + qh->c_usecs) / qh->period)
576 : (qh->usecs * 8);
577
578 dev_dbg (&qh->dev->dev,
579 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
7dedacf4 580 qh->period,
6dbd682b 581 hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
1da177e4
LT		 582 qh, qh->start, qh->usecs, qh->c_usecs);
583
584 /* qh->qh_next still "live" to HC */
585 qh->qh_state = QH_STATE_UNLINK;
586 qh->qh_next.ptr = NULL;
587 qh_put (qh);
588
589 /* maybe turn off periodic schedule */
590 ehci->periodic_sched--;
591 if (!ehci->periodic_sched)
592 (void) disable_periodic (ehci);
593}
594
595static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
596{
597 unsigned wait;
598
599 qh_unlink_periodic (ehci, qh);
600
601 /* simple/paranoid: always delay, expecting the HC needs to read
602 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
603 * expect khubd to clean up after any CSPLITs we won't issue.
604 * active high speed queues may need bigger delays...
605 */
606 if (list_empty (&qh->qtd_list)
6dbd682b 607 || (cpu_to_hc32(ehci, QH_CMASK)
1da177e4
LT		 608 & qh->hw_info2) != 0)
609 wait = 2;
610 else
611 wait = 55; /* worst case: 3 * 1024 */
612
613 udelay (wait);
614 qh->qh_state = QH_STATE_IDLE;
6dbd682b 615 qh->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 616 wmb ();
617}
618
619/*-------------------------------------------------------------------------*/
620
621static int check_period (
53bd6a60 622 struct ehci_hcd *ehci,
1da177e4
LT		 623 unsigned frame,
624 unsigned uframe,
625 unsigned period,
626 unsigned usecs
627) {
628 int claimed;
629
630 /* complete split running into next frame?
631 * given FSTN support, we could sometimes check...
632 */
633 if (uframe >= 8)
634 return 0;
635
636 /*
637 * 80% periodic == 100 usec/uframe available
53bd6a60 638 * convert "usecs we need" to "max already claimed"
1da177e4
LT		 639 */
640 usecs = 100 - usecs;
641
642 /* we "know" 2 and 4 uframe intervals were rejected; so
643 * for period 0, check _every_ microframe in the schedule.
644 */
645 if (unlikely (period == 0)) {
646 do {
647 for (uframe = 0; uframe < 7; uframe++) {
648 claimed = periodic_usecs (ehci, frame, uframe);
649 if (claimed > usecs)
650 return 0;
651 }
652 } while ((frame += 1) < ehci->periodic_size);
653
654 /* just check the specified uframe, at that period */
655 } else {
656 do {
657 claimed = periodic_usecs (ehci, frame, uframe);
658 if (claimed > usecs)
659 return 0;
660 } while ((frame += period) < ehci->periodic_size);
661 }
662
663 // success!
664 return 1;
665}
666
667static int check_intr_schedule (
53bd6a60 668 struct ehci_hcd *ehci,
1da177e4
LT		 669 unsigned frame,
670 unsigned uframe,
671 const struct ehci_qh *qh,
6dbd682b 672 __hc32 *c_maskp
1da177e4
LT		 673)
674{
53bd6a60 675 int retval = -ENOSPC;
ba47f66b 676 u8 mask = 0;
1da177e4
LT		 677
678 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
679 goto done;
680
681 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
682 goto done;
683 if (!qh->c_usecs) {
684 retval = 0;
685 *c_maskp = 0;
686 goto done;
687 }
688
ba47f66b
DS		 689#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
690 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
691 qh->tt_usecs)) {
692 unsigned i;
693
694 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
695 for (i=uframe+1; i<8 && i<uframe+4; i++)
696 if (!check_period (ehci, frame, i,
697 qh->period, qh->c_usecs))
698 goto done;
699 else
700 mask |= 1 << i;
701
702 retval = 0;
703
6dbd682b 704 *c_maskp = cpu_to_hc32(ehci, mask << 8);
ba47f66b
DS		 705 }
706#else
1da177e4
LT		 707 /* Make sure this tt's buffer is also available for CSPLITs.
708 * We pessimize a bit; probably the typical full speed case
709 * doesn't need the second CSPLIT.
53bd6a60 710 *
1da177e4
LT		 711 * NOTE: both SPLIT and CSPLIT could be checked in just
712 * one smart pass...
713 */
714 mask = 0x03 << (uframe + qh->gap_uf);
6dbd682b 715 *c_maskp = cpu_to_hc32(ehci, mask << 8);
1da177e4
LT		 716
717 mask |= 1 << uframe;
718 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
719 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
720 qh->period, qh->c_usecs))
721 goto done;
722 if (!check_period (ehci, frame, uframe + qh->gap_uf,
723 qh->period, qh->c_usecs))
724 goto done;
725 retval = 0;
726 }
ba47f66b 727#endif
1da177e4
LT		 728done:
729 return retval;
730}
731
732/* "first fit" scheduling policy used the first time through,
733 * or when the previous schedule slot can't be re-used.
734 */
6dbd682b 735static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
1da177e4 736{
53bd6a60 737 int status;
1da177e4 738 unsigned uframe;
6dbd682b 739 __hc32 c_mask;
1da177e4
LT		 740 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
741
742 qh_refresh(ehci, qh);
6dbd682b 743 qh->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 744 frame = qh->start;
745
746 /* reuse the previous schedule slots, if we can */
747 if (frame < qh->period) {
6dbd682b 748 uframe = ffs(hc32_to_cpup(ehci, &qh->hw_info2) & QH_SMASK);
1da177e4
LT		 749 status = check_intr_schedule (ehci, frame, --uframe,
750 qh, &c_mask);
751 } else {
752 uframe = 0;
753 c_mask = 0;
754 status = -ENOSPC;
755 }
756
757 /* else scan the schedule to find a group of slots such that all
758 * uframes have enough periodic bandwidth available.
759 */
760 if (status) {
761 /* "normal" case, uframing flexible except with splits */
762 if (qh->period) {
763 frame = qh->period - 1;
764 do {
765 for (uframe = 0; uframe < 8; uframe++) {
766 status = check_intr_schedule (ehci,
767 frame, uframe, qh,
768 &c_mask);
769 if (status == 0)
770 break;
771 }
772 } while (status && frame--);
773
774 /* qh->period == 0 means every uframe */
775 } else {
776 frame = 0;
777 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
778 }
779 if (status)
780 goto done;
781 qh->start = frame;
782
783 /* reset S-frame and (maybe) C-frame masks */
6dbd682b 784 qh->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
1da177e4 785 qh->hw_info2 |= qh->period
6dbd682b
SR		 786 ? cpu_to_hc32(ehci, 1 << uframe)
787 : cpu_to_hc32(ehci, QH_SMASK);
1da177e4
LT		 788 qh->hw_info2 |= c_mask;
789 } else
790 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
791
792 /* stuff into the periodic schedule */
53bd6a60 793 status = qh_link_periodic (ehci, qh);
1da177e4
LT		 794done:
795 return status;
796}
797
798static int intr_submit (
799 struct ehci_hcd *ehci,
800 struct usb_host_endpoint *ep,
801 struct urb *urb,
802 struct list_head *qtd_list,
55016f10 803 gfp_t mem_flags
1da177e4
LT		 804) {
805 unsigned epnum;
806 unsigned long flags;
807 struct ehci_qh *qh;
808 int status = 0;
809 struct list_head empty;
810
811 /* get endpoint and transfer/schedule data */
812 epnum = ep->desc.bEndpointAddress;
813
814 spin_lock_irqsave (&ehci->lock, flags);
815
8de98402 816 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
6dbd682b 817 &ehci_to_hcd(ehci)->flags))) {
8de98402
BH		 818 status = -ESHUTDOWN;
819 goto done;
820 }
821
1da177e4
LT		 822 /* get qh and force any scheduling errors */
823 INIT_LIST_HEAD (&empty);
824 qh = qh_append_tds (ehci, urb, &empty, epnum, &ep->hcpriv);
825 if (qh == NULL) {
826 status = -ENOMEM;
827 goto done;
828 }
829 if (qh->qh_state == QH_STATE_IDLE) {
830 if ((status = qh_schedule (ehci, qh)) != 0)
831 goto done;
832 }
833
834 /* then queue the urb's tds to the qh */
835 qh = qh_append_tds (ehci, urb, qtd_list, epnum, &ep->hcpriv);
836 BUG_ON (qh == NULL);
837
838 /* ... update usbfs periodic stats */
839 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
840
841done:
842 spin_unlock_irqrestore (&ehci->lock, flags);
843 if (status)
844 qtd_list_free (ehci, urb, qtd_list);
845
846 return status;
847}
848
849/*-------------------------------------------------------------------------*/
850
851/* ehci_iso_stream ops work with both ITD and SITD */
852
853static struct ehci_iso_stream *
55016f10 854iso_stream_alloc (gfp_t mem_flags)
1da177e4
LT		 855{
856 struct ehci_iso_stream *stream;
857
7b842b6e 858 stream = kzalloc(sizeof *stream, mem_flags);
1da177e4 859 if (likely (stream != NULL)) {
1da177e4
LT		 860 INIT_LIST_HEAD(&stream->td_list);
861 INIT_LIST_HEAD(&stream->free_list);
862 stream->next_uframe = -1;
863 stream->refcount = 1;
864 }
865 return stream;
866}
867
868static void
869iso_stream_init (
870 struct ehci_hcd *ehci,
871 struct ehci_iso_stream *stream,
872 struct usb_device *dev,
873 int pipe,
874 unsigned interval
875)
876{
877 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
878
879 u32 buf1;
880 unsigned epnum, maxp;
881 int is_input;
882 long bandwidth;
883
884 /*
885 * this might be a "high bandwidth" highspeed endpoint,
886 * as encoded in the ep descriptor's wMaxPacket field
887 */
888 epnum = usb_pipeendpoint (pipe);
889 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
890 maxp = usb_maxpacket(dev, pipe, !is_input);
891 if (is_input) {
892 buf1 = (1 << 11);
893 } else {
894 buf1 = 0;
895 }
896
897 /* knows about ITD vs SITD */
898 if (dev->speed == USB_SPEED_HIGH) {
899 unsigned multi = hb_mult(maxp);
900
901 stream->highspeed = 1;
902
903 maxp = max_packet(maxp);
904 buf1 |= maxp;
905 maxp *= multi;
906
6dbd682b
SR		 907 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
908 stream->buf1 = cpu_to_hc32(ehci, buf1);
909 stream->buf2 = cpu_to_hc32(ehci, multi);
1da177e4
LT		 910
911 /* usbfs wants to report the average usecs per frame tied up
912 * when transfers on this endpoint are scheduled ...
913 */
914 stream->usecs = HS_USECS_ISO (maxp);
915 bandwidth = stream->usecs * 8;
916 bandwidth /= 1 << (interval - 1);
917
918 } else {
919 u32 addr;
d0384200 920 int think_time;
469d0229 921 int hs_transfers;
1da177e4
LT		 922
923 addr = dev->ttport << 24;
924 if (!ehci_is_TDI(ehci)
925 || (dev->tt->hub !=
926 ehci_to_hcd(ehci)->self.root_hub))
927 addr |= dev->tt->hub->devnum << 16;
928 addr |= epnum << 8;
929 addr |= dev->devnum;
930 stream->usecs = HS_USECS_ISO (maxp);
d0384200 931 think_time = dev->tt ? dev->tt->think_time : 0;
932 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
933 dev->speed, is_input, 1, maxp));
469d0229 934 hs_transfers = max (1u, (maxp + 187) / 188);
1da177e4
LT		 935 if (is_input) {
936 u32 tmp;
937
938 addr |= 1 << 31;
939 stream->c_usecs = stream->usecs;
940 stream->usecs = HS_USECS_ISO (1);
941 stream->raw_mask = 1;
942
469d0229
CL		 943 /* c-mask as specified in USB 2.0 11.18.4 3.c */
944 tmp = (1 << (hs_transfers + 2)) - 1;
945 stream->raw_mask |= tmp << (8 + 2);
1da177e4 946 } else
469d0229 947 stream->raw_mask = smask_out [hs_transfers - 1];
1da177e4
LT		 948 bandwidth = stream->usecs + stream->c_usecs;
949 bandwidth /= 1 << (interval + 2);
950
951 /* stream->splits gets created from raw_mask later */
6dbd682b 952 stream->address = cpu_to_hc32(ehci, addr);
1da177e4
LT		 953 }
954 stream->bandwidth = bandwidth;
955
956 stream->udev = dev;
957
958 stream->bEndpointAddress = is_input | epnum;
959 stream->interval = interval;
960 stream->maxp = maxp;
961}
962
963static void
964iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
965{
966 stream->refcount--;
967
968 /* free whenever just a dev->ep reference remains.
969 * not like a QH -- no persistent state (toggle, halt)
970 */
971 if (stream->refcount == 1) {
972 int is_in;
973
974 // BUG_ON (!list_empty(&stream->td_list));
975
976 while (!list_empty (&stream->free_list)) {
977 struct list_head *entry;
978
979 entry = stream->free_list.next;
980 list_del (entry);
981
982 /* knows about ITD vs SITD */
983 if (stream->highspeed) {
984 struct ehci_itd *itd;
985
986 itd = list_entry (entry, struct ehci_itd,
987 itd_list);
988 dma_pool_free (ehci->itd_pool, itd,
989 itd->itd_dma);
990 } else {
991 struct ehci_sitd *sitd;
992
993 sitd = list_entry (entry, struct ehci_sitd,
994 sitd_list);
995 dma_pool_free (ehci->sitd_pool, sitd,
996 sitd->sitd_dma);
997 }
998 }
999
1000 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1001 stream->bEndpointAddress &= 0x0f;
1002 stream->ep->hcpriv = NULL;
1003
1004 if (stream->rescheduled) {
1005 ehci_info (ehci, "ep%d%s-iso rescheduled "
1006 "%lu times in %lu seconds\n",
1007 stream->bEndpointAddress, is_in ? "in" : "out",
1008 stream->rescheduled,
1009 ((jiffies - stream->start)/HZ)
1010 );
1011 }
1012
1013 kfree(stream);
1014 }
1015}
1016
1017static inline struct ehci_iso_stream *
1018iso_stream_get (struct ehci_iso_stream *stream)
1019{
1020 if (likely (stream != NULL))
1021 stream->refcount++;
1022 return stream;
1023}
1024
1025static struct ehci_iso_stream *
1026iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1027{
1028 unsigned epnum;
1029 struct ehci_iso_stream *stream;
1030 struct usb_host_endpoint *ep;
1031 unsigned long flags;
1032
1033 epnum = usb_pipeendpoint (urb->pipe);
1034 if (usb_pipein(urb->pipe))
1035 ep = urb->dev->ep_in[epnum];
1036 else
1037 ep = urb->dev->ep_out[epnum];
1038
1039 spin_lock_irqsave (&ehci->lock, flags);
1040 stream = ep->hcpriv;
1041
1042 if (unlikely (stream == NULL)) {
1043 stream = iso_stream_alloc(GFP_ATOMIC);
1044 if (likely (stream != NULL)) {
1045 /* dev->ep owns the initial refcount */
1046 ep->hcpriv = stream;
1047 stream->ep = ep;
1048 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1049 urb->interval);
1050 }
1051
1052 /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
1053 } else if (unlikely (stream->hw_info1 != 0)) {
1054 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1055 urb->dev->devpath, epnum,
1056 usb_pipein(urb->pipe) ? "in" : "out");
1057 stream = NULL;
1058 }
1059
1060 /* caller guarantees an eventual matching iso_stream_put */
1061 stream = iso_stream_get (stream);
1062
1063 spin_unlock_irqrestore (&ehci->lock, flags);
1064 return stream;
1065}
1066
1067/*-------------------------------------------------------------------------*/
1068
1069/* ehci_iso_sched ops can be ITD-only or SITD-only */
1070
1071static struct ehci_iso_sched *
55016f10 1072iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1da177e4
LT		 1073{
1074 struct ehci_iso_sched *iso_sched;
1075 int size = sizeof *iso_sched;
1076
1077 size += packets * sizeof (struct ehci_iso_packet);
80b6ca48 1078 iso_sched = kzalloc(size, mem_flags);
1da177e4 1079 if (likely (iso_sched != NULL)) {
1da177e4
LT		 1080 INIT_LIST_HEAD (&iso_sched->td_list);
1081 }
1082 return iso_sched;
1083}
1084
1085static inline void
6dbd682b
SR		 1086itd_sched_init(
1087 struct ehci_hcd *ehci,
1da177e4
LT		 1088 struct ehci_iso_sched *iso_sched,
1089 struct ehci_iso_stream *stream,
1090 struct urb *urb
1091)
1092{
1093 unsigned i;
1094 dma_addr_t dma = urb->transfer_dma;
1095
1096 /* how many uframes are needed for these transfers */
1097 iso_sched->span = urb->number_of_packets * stream->interval;
1098
1099 /* figure out per-uframe itd fields that we'll need later
1100 * when we fit new itds into the schedule.
1101 */
1102 for (i = 0; i < urb->number_of_packets; i++) {
1103 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1104 unsigned length;
1105 dma_addr_t buf;
1106 u32 trans;
1107
1108 length = urb->iso_frame_desc [i].length;
1109 buf = dma + urb->iso_frame_desc [i].offset;
1110
1111 trans = EHCI_ISOC_ACTIVE;
1112 trans |= buf & 0x0fff;
1113 if (unlikely (((i + 1) == urb->number_of_packets))
1114 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1115 trans |= EHCI_ITD_IOC;
1116 trans |= length << 16;
6dbd682b 1117 uframe->transaction = cpu_to_hc32(ehci, trans);
1da177e4 1118
77078570 1119 /* might need to cross a buffer page within a uframe */
1da177e4
LT		 1120 uframe->bufp = (buf & ~(u64)0x0fff);
1121 buf += length;
1122 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1123 uframe->cross = 1;
1124 }
1125}
1126
1127static void
1128iso_sched_free (
1129 struct ehci_iso_stream *stream,
1130 struct ehci_iso_sched *iso_sched
1131)
1132{
1133 if (!iso_sched)
1134 return;
1135 // caller must hold ehci->lock!
1136 list_splice (&iso_sched->td_list, &stream->free_list);
1137 kfree (iso_sched);
1138}
1139
1140static int
1141itd_urb_transaction (
1142 struct ehci_iso_stream *stream,
1143 struct ehci_hcd *ehci,
1144 struct urb *urb,
55016f10 1145 gfp_t mem_flags
1da177e4
LT		 1146)
1147{
1148 struct ehci_itd *itd;
1149 dma_addr_t itd_dma;
1150 int i;
1151 unsigned num_itds;
1152 struct ehci_iso_sched *sched;
1153 unsigned long flags;
1154
1155 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1156 if (unlikely (sched == NULL))
1157 return -ENOMEM;
1158
6dbd682b 1159 itd_sched_init(ehci, sched, stream, urb);
1da177e4
LT		 1160
1161 if (urb->interval < 8)
1162 num_itds = 1 + (sched->span + 7) / 8;
1163 else
1164 num_itds = urb->number_of_packets;
1165
1166 /* allocate/init ITDs */
1167 spin_lock_irqsave (&ehci->lock, flags);
1168 for (i = 0; i < num_itds; i++) {
1169
1170 /* free_list.next might be cache-hot ... but maybe
1171 * the HC caches it too. avoid that issue for now.
1172 */
1173
1174 /* prefer previously-allocated itds */
1175 if (likely (!list_empty(&stream->free_list))) {
1176 itd = list_entry (stream->free_list.prev,
6dbd682b 1177 struct ehci_itd, itd_list);
1da177e4
LT		 1178 list_del (&itd->itd_list);
1179 itd_dma = itd->itd_dma;
1180 } else
1181 itd = NULL;
1182
1183 if (!itd) {
1184 spin_unlock_irqrestore (&ehci->lock, flags);
1185 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1186 &itd_dma);
1187 spin_lock_irqsave (&ehci->lock, flags);
1188 }
1189
1190 if (unlikely (NULL == itd)) {
1191 iso_sched_free (stream, sched);
1192 spin_unlock_irqrestore (&ehci->lock, flags);
1193 return -ENOMEM;
1194 }
1195 memset (itd, 0, sizeof *itd);
1196 itd->itd_dma = itd_dma;
1197 list_add (&itd->itd_list, &sched->td_list);
1198 }
1199 spin_unlock_irqrestore (&ehci->lock, flags);
1200
1201 /* temporarily store schedule info in hcpriv */
1202 urb->hcpriv = sched;
1203 urb->error_count = 0;
1204 return 0;
1205}
1206
1207/*-------------------------------------------------------------------------*/
1208
1209static inline int
1210itd_slot_ok (
1211 struct ehci_hcd *ehci,
1212 u32 mod,
1213 u32 uframe,
1214 u8 usecs,
1215 u32 period
1216)
1217{
1218 uframe %= period;
1219 do {
1220 /* can't commit more than 80% periodic == 100 usec */
1221 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1222 > (100 - usecs))
1223 return 0;
1224
1225 /* we know urb->interval is 2^N uframes */
1226 uframe += period;
1227 } while (uframe < mod);
1228 return 1;
1229}
1230
1231static inline int
1232sitd_slot_ok (
1233 struct ehci_hcd *ehci,
1234 u32 mod,
1235 struct ehci_iso_stream *stream,
1236 u32 uframe,
1237 struct ehci_iso_sched *sched,
1238 u32 period_uframes
1239)
1240{
1241 u32 mask, tmp;
1242 u32 frame, uf;
1243
1244 mask = stream->raw_mask << (uframe & 7);
1245
1246 /* for IN, don't wrap CSPLIT into the next frame */
1247 if (mask & ~0xffff)
1248 return 0;
1249
1250 /* this multi-pass logic is simple, but performance may
1251 * suffer when the schedule data isn't cached.
1252 */
1253
1254 /* check bandwidth */
1255 uframe %= period_uframes;
1256 do {
1257 u32 max_used;
1258
1259 frame = uframe >> 3;
1260 uf = uframe & 7;
1261
ba47f66b
DS		 1262#ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1263 /* The tt's fullspeed bus bandwidth must be available.
1264 * tt_available scheduling guarantees 10+% for control/bulk.
1265 */
1266 if (!tt_available (ehci, period_uframes << 3,
1267 stream->udev, frame, uf, stream->tt_usecs))
1268 return 0;
1269#else
1da177e4
LT		 1270 /* tt must be idle for start(s), any gap, and csplit.
1271 * assume scheduling slop leaves 10+% for control/bulk.
1272 */
1273 if (!tt_no_collision (ehci, period_uframes << 3,
1274 stream->udev, frame, mask))
1275 return 0;
ba47f66b 1276#endif
1da177e4
LT		 1277
1278 /* check starts (OUT uses more than one) */
1279 max_used = 100 - stream->usecs;
1280 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1281 if (periodic_usecs (ehci, frame, uf) > max_used)
1282 return 0;
1283 }
1284
1285 /* for IN, check CSPLIT */
1286 if (stream->c_usecs) {
0c734622 1287 uf = uframe & 7;
1da177e4
LT		 1288 max_used = 100 - stream->c_usecs;
1289 do {
1290 tmp = 1 << uf;
1291 tmp <<= 8;
1292 if ((stream->raw_mask & tmp) == 0)
1293 continue;
1294 if (periodic_usecs (ehci, frame, uf)
1295 > max_used)
1296 return 0;
1297 } while (++uf < 8);
1298 }
1299
1300 /* we know urb->interval is 2^N uframes */
1301 uframe += period_uframes;
1302 } while (uframe < mod);
1303
6dbd682b 1304 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1da177e4
LT		 1305 return 1;
1306}
1307
1308/*
1309 * This scheduler plans almost as far into the future as it has actual
1310 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1311 * "as small as possible" to be cache-friendlier.) That limits the size
1312 * transfers you can stream reliably; avoid more than 64 msec per urb.
1313 * Also avoid queue depths of less than ehci's worst irq latency (affected
1314 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1315 * and other factors); or more than about 230 msec total (for portability,
1316 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1317 */
1318
1319#define SCHEDULE_SLOP 10 /* frames */
1320
1321static int
1322iso_stream_schedule (
1323 struct ehci_hcd *ehci,
1324 struct urb *urb,
1325 struct ehci_iso_stream *stream
1326)
1327{
1328 u32 now, start, max, period;
1329 int status;
1330 unsigned mod = ehci->periodic_size << 3;
1331 struct ehci_iso_sched *sched = urb->hcpriv;
1332
1333 if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1334 ehci_dbg (ehci, "iso request %p too long\n", urb);
1335 status = -EFBIG;
1336 goto fail;
1337 }
1338
1339 if ((stream->depth + sched->span) > mod) {
1340 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1341 urb, stream->depth, sched->span, mod);
1342 status = -EFBIG;
1343 goto fail;
1344 }
1345
083522d7 1346 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1da177e4
LT		 1347
1348 /* when's the last uframe this urb could start? */
1349 max = now + mod;
1350
1351 /* typical case: reuse current schedule. stream is still active,
1352 * and no gaps from host falling behind (irq delays etc)
1353 */
1354 if (likely (!list_empty (&stream->td_list))) {
1355 start = stream->next_uframe;
1356 if (start < now)
1357 start += mod;
1358 if (likely ((start + sched->span) < max))
1359 goto ready;
1360 /* else fell behind; someday, try to reschedule */
1361 status = -EL2NSYNC;
1362 goto fail;
1363 }
1364
1365 /* need to schedule; when's the next (u)frame we could start?
1366 * this is bigger than ehci->i_thresh allows; scheduling itself
1367 * isn't free, the slop should handle reasonably slow cpus. it
1368 * can also help high bandwidth if the dma and irq loads don't
1369 * jump until after the queue is primed.
1370 */
1371 start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1372 start %= mod;
1373 stream->next_uframe = start;
1374
1375 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1376
1377 period = urb->interval;
1378 if (!stream->highspeed)
1379 period <<= 3;
1380
1381 /* find a uframe slot with enough bandwidth */
1382 for (; start < (stream->next_uframe + period); start++) {
1383 int enough_space;
1384
1385 /* check schedule: enough space? */
1386 if (stream->highspeed)
1387 enough_space = itd_slot_ok (ehci, mod, start,
1388 stream->usecs, period);
1389 else {
1390 if ((start % 8) >= 6)
1391 continue;
1392 enough_space = sitd_slot_ok (ehci, mod, stream,
1393 start, sched, period);
1394 }
1395
1396 /* schedule it here if there's enough bandwidth */
1397 if (enough_space) {
1398 stream->next_uframe = start % mod;
1399 goto ready;
1400 }
1401 }
1402
1403 /* no room in the schedule */
1404 ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1405 list_empty (&stream->td_list) ? "" : "re",
1406 urb, now, max);
1407 status = -ENOSPC;
1408
1409fail:
1410 iso_sched_free (stream, sched);
1411 urb->hcpriv = NULL;
1412 return status;
1413
1414ready:
1415 /* report high speed start in uframes; full speed, in frames */
1416 urb->start_frame = stream->next_uframe;
1417 if (!stream->highspeed)
1418 urb->start_frame >>= 3;
1419 return 0;
1420}
1421
1422/*-------------------------------------------------------------------------*/
1423
1424static inline void
6dbd682b
SR		 1425itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1426 struct ehci_itd *itd)
1da177e4
LT		 1427{
1428 int i;
1429
77078570 1430 /* it's been recently zeroed */
6dbd682b 1431 itd->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 1432 itd->hw_bufp [0] = stream->buf0;
1433 itd->hw_bufp [1] = stream->buf1;
1434 itd->hw_bufp [2] = stream->buf2;
1435
1436 for (i = 0; i < 8; i++)
1437 itd->index[i] = -1;
1438
1439 /* All other fields are filled when scheduling */
1440}
1441
1442static inline void
6dbd682b
SR		 1443itd_patch(
1444 struct ehci_hcd *ehci,
1da177e4
LT		 1445 struct ehci_itd *itd,
1446 struct ehci_iso_sched *iso_sched,
1447 unsigned index,
77078570 1448 u16 uframe
1da177e4
LT		 1449)
1450{
1451 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1452 unsigned pg = itd->pg;
1453
1454 // BUG_ON (pg == 6 && uf->cross);
1455
1456 uframe &= 0x07;
1457 itd->index [uframe] = index;
1458
6dbd682b
SR		 1459 itd->hw_transaction[uframe] = uf->transaction;
1460 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1461 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1462 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1da177e4
LT		 1463
1464 /* iso_frame_desc[].offset must be strictly increasing */
77078570 1465 if (unlikely (uf->cross)) {
1da177e4 1466 u64 bufp = uf->bufp + 4096;
6dbd682b 1467
1da177e4 1468 itd->pg = ++pg;
6dbd682b
SR		 1469 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1470 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1da177e4
LT		 1471 }
1472}
1473
1474static inline void
1475itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1476{
1477 /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1478 itd->itd_next = ehci->pshadow [frame];
1479 itd->hw_next = ehci->periodic [frame];
1480 ehci->pshadow [frame].itd = itd;
1481 itd->frame = frame;
1482 wmb ();
6dbd682b 1483 ehci->periodic[frame] = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1da177e4
LT		 1484}
1485
1486/* fit urb's itds into the selected schedule slot; activate as needed */
1487static int
1488itd_link_urb (
1489 struct ehci_hcd *ehci,
1490 struct urb *urb,
1491 unsigned mod,
1492 struct ehci_iso_stream *stream
1493)
1494{
77078570 1495 int packet;
1da177e4
LT		 1496 unsigned next_uframe, uframe, frame;
1497 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1498 struct ehci_itd *itd;
1499
1500 next_uframe = stream->next_uframe % mod;
1501
1502 if (unlikely (list_empty(&stream->td_list))) {
1503 ehci_to_hcd(ehci)->self.bandwidth_allocated
1504 += stream->bandwidth;
1505 ehci_vdbg (ehci,
1506 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1507 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1508 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1509 urb->interval,
1510 next_uframe >> 3, next_uframe & 0x7);
1511 stream->start = jiffies;
1512 }
1513 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1514
1515 /* fill iTDs uframe by uframe */
1516 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1517 if (itd == NULL) {
1518 /* ASSERT: we have all necessary itds */
1519 // BUG_ON (list_empty (&iso_sched->td_list));
1520
1521 /* ASSERT: no itds for this endpoint in this uframe */
1522
1523 itd = list_entry (iso_sched->td_list.next,
1524 struct ehci_itd, itd_list);
1525 list_move_tail (&itd->itd_list, &stream->td_list);
1526 itd->stream = iso_stream_get (stream);
1527 itd->urb = usb_get_urb (urb);
6dbd682b 1528 itd_init (ehci, stream, itd);
1da177e4
LT		 1529 }
1530
1531 uframe = next_uframe & 0x07;
1532 frame = next_uframe >> 3;
1533
1534 itd->usecs [uframe] = stream->usecs;
6dbd682b 1535 itd_patch(ehci, itd, iso_sched, packet, uframe);
1da177e4
LT		 1536
1537 next_uframe += stream->interval;
1538 stream->depth += stream->interval;
1539 next_uframe %= mod;
1540 packet++;
1541
1542 /* link completed itds into the schedule */
1543 if (((next_uframe >> 3) != frame)
1544 || packet == urb->number_of_packets) {
1545 itd_link (ehci, frame % ehci->periodic_size, itd);
1546 itd = NULL;
1547 }
1548 }
1549 stream->next_uframe = next_uframe;
1550
1551 /* don't need that schedule data any more */
1552 iso_sched_free (stream, iso_sched);
1553 urb->hcpriv = NULL;
1554
1555 timer_action (ehci, TIMER_IO_WATCHDOG);
1556 if (unlikely (!ehci->periodic_sched++))
1557 return enable_periodic (ehci);
1558 return 0;
1559}
1560
1561#define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1562
1563static unsigned
1564itd_complete (
1565 struct ehci_hcd *ehci,
7d12e780 1566 struct ehci_itd *itd
1da177e4
LT		 1567) {
1568 struct urb *urb = itd->urb;
1569 struct usb_iso_packet_descriptor *desc;
1570 u32 t;
1571 unsigned uframe;
1572 int urb_index = -1;
1573 struct ehci_iso_stream *stream = itd->stream;
1574 struct usb_device *dev;
1575
1576 /* for each uframe with a packet */
1577 for (uframe = 0; uframe < 8; uframe++) {
1578 if (likely (itd->index[uframe] == -1))
1579 continue;
1580 urb_index = itd->index[uframe];
1581 desc = &urb->iso_frame_desc [urb_index];
1582
6dbd682b 1583 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1da177e4
LT		 1584 itd->hw_transaction [uframe] = 0;
1585 stream->depth -= stream->interval;
1586
1587 /* report transfer status */
1588 if (unlikely (t & ISO_ERRS)) {
1589 urb->error_count++;
1590 if (t & EHCI_ISOC_BUF_ERR)
1591 desc->status = usb_pipein (urb->pipe)
1592 ? -ENOSR /* hc couldn't read */
1593 : -ECOMM; /* hc couldn't write */
1594 else if (t & EHCI_ISOC_BABBLE)
1595 desc->status = -EOVERFLOW;
1596 else /* (t & EHCI_ISOC_XACTERR) */
1597 desc->status = -EPROTO;
1598
1599 /* HC need not update length with this error */
1600 if (!(t & EHCI_ISOC_BABBLE))
1601 desc->actual_length = EHCI_ITD_LENGTH (t);
1602 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1603 desc->status = 0;
1604 desc->actual_length = EHCI_ITD_LENGTH (t);
1605 }
1606 }
1607
1608 usb_put_urb (urb);
1609 itd->urb = NULL;
1610 itd->stream = NULL;
1611 list_move (&itd->itd_list, &stream->free_list);
1612 iso_stream_put (ehci, stream);
1613
1614 /* handle completion now? */
1615 if (likely ((urb_index + 1) != urb->number_of_packets))
1616 return 0;
1617
1618 /* ASSERT: it's really the last itd for this urb
1619 list_for_each_entry (itd, &stream->td_list, itd_list)
1620 BUG_ON (itd->urb == urb);
1621 */
1622
1623 /* give urb back to the driver ... can be out-of-order */
6a8e87b2 1624 dev = urb->dev;
7d12e780 1625 ehci_urb_done (ehci, urb);
1da177e4
LT		 1626 urb = NULL;
1627
1628 /* defer stopping schedule; completion can submit */
1629 ehci->periodic_sched--;
1630 if (unlikely (!ehci->periodic_sched))
1631 (void) disable_periodic (ehci);
1632 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1633
1634 if (unlikely (list_empty (&stream->td_list))) {
1635 ehci_to_hcd(ehci)->self.bandwidth_allocated
1636 -= stream->bandwidth;
1637 ehci_vdbg (ehci,
1638 "deschedule devp %s ep%d%s-iso\n",
1639 dev->devpath, stream->bEndpointAddress & 0x0f,
1640 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1641 }
1642 iso_stream_put (ehci, stream);
1da177e4
LT		 1643
1644 return 1;
1645}
1646
1647/*-------------------------------------------------------------------------*/
1648
5db539e4 1649static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
55016f10 1650 gfp_t mem_flags)
1da177e4
LT		 1651{
1652 int status = -EINVAL;
1653 unsigned long flags;
1654 struct ehci_iso_stream *stream;
1655
1656 /* Get iso_stream head */
1657 stream = iso_stream_find (ehci, urb);
1658 if (unlikely (stream == NULL)) {
1659 ehci_dbg (ehci, "can't get iso stream\n");
1660 return -ENOMEM;
1661 }
1662 if (unlikely (urb->interval != stream->interval)) {
1663 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1664 stream->interval, urb->interval);
1665 goto done;
1666 }
1667
1668#ifdef EHCI_URB_TRACE
1669 ehci_dbg (ehci,
1670 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1671 __FUNCTION__, urb->dev->devpath, urb,
1672 usb_pipeendpoint (urb->pipe),
1673 usb_pipein (urb->pipe) ? "in" : "out",
1674 urb->transfer_buffer_length,
1675 urb->number_of_packets, urb->interval,
1676 stream);
1677#endif
1678
1679 /* allocate ITDs w/o locking anything */
1680 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1681 if (unlikely (status < 0)) {
1682 ehci_dbg (ehci, "can't init itds\n");
1683 goto done;
1684 }
1685
1686 /* schedule ... need to lock */
1687 spin_lock_irqsave (&ehci->lock, flags);
8de98402
BH		 1688 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1689 &ehci_to_hcd(ehci)->flags)))
1690 status = -ESHUTDOWN;
1691 else
1692 status = iso_stream_schedule (ehci, urb, stream);
53bd6a60 1693 if (likely (status == 0))
1da177e4
LT		 1694 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1695 spin_unlock_irqrestore (&ehci->lock, flags);
1696
1697done:
1698 if (unlikely (status < 0))
1699 iso_stream_put (ehci, stream);
1700 return status;
1701}
1702
1703#ifdef CONFIG_USB_EHCI_SPLIT_ISO
1704
1705/*-------------------------------------------------------------------------*/
1706
1707/*
1708 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1709 * TTs in USB 2.0 hubs. These need microframe scheduling.
1710 */
1711
1712static inline void
6dbd682b
SR		 1713sitd_sched_init(
1714 struct ehci_hcd *ehci,
1da177e4
LT		 1715 struct ehci_iso_sched *iso_sched,
1716 struct ehci_iso_stream *stream,
1717 struct urb *urb
1718)
1719{
1720 unsigned i;
1721 dma_addr_t dma = urb->transfer_dma;
1722
1723 /* how many frames are needed for these transfers */
1724 iso_sched->span = urb->number_of_packets * stream->interval;
1725
1726 /* figure out per-frame sitd fields that we'll need later
1727 * when we fit new sitds into the schedule.
1728 */
1729 for (i = 0; i < urb->number_of_packets; i++) {
1730 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1731 unsigned length;
1732 dma_addr_t buf;
1733 u32 trans;
1734
1735 length = urb->iso_frame_desc [i].length & 0x03ff;
1736 buf = dma + urb->iso_frame_desc [i].offset;
1737
1738 trans = SITD_STS_ACTIVE;
1739 if (((i + 1) == urb->number_of_packets)
1740 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1741 trans |= SITD_IOC;
1742 trans |= length << 16;
6dbd682b 1743 packet->transaction = cpu_to_hc32(ehci, trans);
1da177e4
LT		 1744
1745 /* might need to cross a buffer page within a td */
1746 packet->bufp = buf;
1747 packet->buf1 = (buf + length) & ~0x0fff;
1748 if (packet->buf1 != (buf & ~(u64)0x0fff))
1749 packet->cross = 1;
1750
53bd6a60 1751 /* OUT uses multiple start-splits */
1da177e4
LT		 1752 if (stream->bEndpointAddress & USB_DIR_IN)
1753 continue;
1754 length = (length + 187) / 188;
1755 if (length > 1) /* BEGIN vs ALL */
1756 length |= 1 << 3;
1757 packet->buf1 |= length;
1758 }
1759}
1760
1761static int
1762sitd_urb_transaction (
1763 struct ehci_iso_stream *stream,
1764 struct ehci_hcd *ehci,
1765 struct urb *urb,
55016f10 1766 gfp_t mem_flags
1da177e4
LT		 1767)
1768{
1769 struct ehci_sitd *sitd;
1770 dma_addr_t sitd_dma;
1771 int i;
1772 struct ehci_iso_sched *iso_sched;
1773 unsigned long flags;
1774
1775 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1776 if (iso_sched == NULL)
1777 return -ENOMEM;
1778
6dbd682b 1779 sitd_sched_init(ehci, iso_sched, stream, urb);
1da177e4
LT		 1780
1781 /* allocate/init sITDs */
1782 spin_lock_irqsave (&ehci->lock, flags);
1783 for (i = 0; i < urb->number_of_packets; i++) {
1784
1785 /* NOTE: for now, we don't try to handle wraparound cases
1786 * for IN (using sitd->hw_backpointer, like a FSTN), which
1787 * means we never need two sitds for full speed packets.
1788 */
1789
1790 /* free_list.next might be cache-hot ... but maybe
1791 * the HC caches it too. avoid that issue for now.
1792 */
1793
1794 /* prefer previously-allocated sitds */
1795 if (!list_empty(&stream->free_list)) {
1796 sitd = list_entry (stream->free_list.prev,
1797 struct ehci_sitd, sitd_list);
1798 list_del (&sitd->sitd_list);
1799 sitd_dma = sitd->sitd_dma;
1800 } else
1801 sitd = NULL;
1802
1803 if (!sitd) {
1804 spin_unlock_irqrestore (&ehci->lock, flags);
1805 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1806 &sitd_dma);
1807 spin_lock_irqsave (&ehci->lock, flags);
1808 }
1809
1810 if (!sitd) {
1811 iso_sched_free (stream, iso_sched);
1812 spin_unlock_irqrestore (&ehci->lock, flags);
1813 return -ENOMEM;
1814 }
1815 memset (sitd, 0, sizeof *sitd);
1816 sitd->sitd_dma = sitd_dma;
1817 list_add (&sitd->sitd_list, &iso_sched->td_list);
1818 }
1819
1820 /* temporarily store schedule info in hcpriv */
1821 urb->hcpriv = iso_sched;
1822 urb->error_count = 0;
1823
1824 spin_unlock_irqrestore (&ehci->lock, flags);
1825 return 0;
1826}
1827
1828/*-------------------------------------------------------------------------*/
1829
1830static inline void
6dbd682b
SR		 1831sitd_patch(
1832 struct ehci_hcd *ehci,
1da177e4
LT		 1833 struct ehci_iso_stream *stream,
1834 struct ehci_sitd *sitd,
1835 struct ehci_iso_sched *iso_sched,
1836 unsigned index
1837)
1838{
1839 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1840 u64 bufp = uf->bufp;
1841
6dbd682b 1842 sitd->hw_next = EHCI_LIST_END(ehci);
1da177e4
LT		 1843 sitd->hw_fullspeed_ep = stream->address;
1844 sitd->hw_uframe = stream->splits;
1845 sitd->hw_results = uf->transaction;
6dbd682b 1846 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1da177e4
LT		 1847
1848 bufp = uf->bufp;
6dbd682b
SR		 1849 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1850 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1da177e4 1851
6dbd682b 1852 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1da177e4
LT		 1853 if (uf->cross)
1854 bufp += 4096;
6dbd682b 1855 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1da177e4
LT		 1856 sitd->index = index;
1857}
1858
1859static inline void
1860sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1861{
1862 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1863 sitd->sitd_next = ehci->pshadow [frame];
1864 sitd->hw_next = ehci->periodic [frame];
1865 ehci->pshadow [frame].sitd = sitd;
1866 sitd->frame = frame;
1867 wmb ();
6dbd682b 1868 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1da177e4
LT		 1869}
1870
1871/* fit urb's sitds into the selected schedule slot; activate as needed */
1872static int
1873sitd_link_urb (
1874 struct ehci_hcd *ehci,
1875 struct urb *urb,
1876 unsigned mod,
1877 struct ehci_iso_stream *stream
1878)
1879{
1880 int packet;
1881 unsigned next_uframe;
1882 struct ehci_iso_sched *sched = urb->hcpriv;
1883 struct ehci_sitd *sitd;
1884
1885 next_uframe = stream->next_uframe;
1886
1887 if (list_empty(&stream->td_list)) {
1888 /* usbfs ignores TT bandwidth */
1889 ehci_to_hcd(ehci)->self.bandwidth_allocated
1890 += stream->bandwidth;
1891 ehci_vdbg (ehci,
1892 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
1893 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1894 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1895 (next_uframe >> 3) % ehci->periodic_size,
6dbd682b 1896 stream->interval, hc32_to_cpu(ehci, stream->splits));
1da177e4
LT		 1897 stream->start = jiffies;
1898 }
1899 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1900
1901 /* fill sITDs frame by frame */
1902 for (packet = 0, sitd = NULL;
1903 packet < urb->number_of_packets;
1904 packet++) {
1905
1906 /* ASSERT: we have all necessary sitds */
1907 BUG_ON (list_empty (&sched->td_list));
1908
1909 /* ASSERT: no itds for this endpoint in this frame */
1910
1911 sitd = list_entry (sched->td_list.next,
1912 struct ehci_sitd, sitd_list);
1913 list_move_tail (&sitd->sitd_list, &stream->td_list);
1914 sitd->stream = iso_stream_get (stream);
1915 sitd->urb = usb_get_urb (urb);
1916
6dbd682b 1917 sitd_patch(ehci, stream, sitd, sched, packet);
1da177e4
LT		 1918 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
1919 sitd);
1920
1921 next_uframe += stream->interval << 3;
1922 stream->depth += stream->interval << 3;
1923 }
1924 stream->next_uframe = next_uframe % mod;
1925
1926 /* don't need that schedule data any more */
1927 iso_sched_free (stream, sched);
1928 urb->hcpriv = NULL;
1929
1930 timer_action (ehci, TIMER_IO_WATCHDOG);
1931 if (!ehci->periodic_sched++)
1932 return enable_periodic (ehci);
1933 return 0;
1934}
1935
1936/*-------------------------------------------------------------------------*/
1937
1938#define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
53bd6a60 1939 | SITD_STS_XACT | SITD_STS_MMF)
1da177e4
LT		 1940
1941static unsigned
1942sitd_complete (
1943 struct ehci_hcd *ehci,
7d12e780 1944 struct ehci_sitd *sitd
1da177e4
LT		 1945) {
1946 struct urb *urb = sitd->urb;
1947 struct usb_iso_packet_descriptor *desc;
1948 u32 t;
1949 int urb_index = -1;
1950 struct ehci_iso_stream *stream = sitd->stream;
1951 struct usb_device *dev;
1952
1953 urb_index = sitd->index;
1954 desc = &urb->iso_frame_desc [urb_index];
6dbd682b 1955 t = hc32_to_cpup(ehci, &sitd->hw_results);
1da177e4
LT		 1956
1957 /* report transfer status */
1958 if (t & SITD_ERRS) {
1959 urb->error_count++;
1960 if (t & SITD_STS_DBE)
1961 desc->status = usb_pipein (urb->pipe)
1962 ? -ENOSR /* hc couldn't read */
1963 : -ECOMM; /* hc couldn't write */
1964 else if (t & SITD_STS_BABBLE)
1965 desc->status = -EOVERFLOW;
1966 else /* XACT, MMF, etc */
1967 desc->status = -EPROTO;
1968 } else {
1969 desc->status = 0;
1970 desc->actual_length = desc->length - SITD_LENGTH (t);
1971 }
1972
1973 usb_put_urb (urb);
1974 sitd->urb = NULL;
1975 sitd->stream = NULL;
1976 list_move (&sitd->sitd_list, &stream->free_list);
1977 stream->depth -= stream->interval << 3;
1978 iso_stream_put (ehci, stream);
1979
1980 /* handle completion now? */
1981 if ((urb_index + 1) != urb->number_of_packets)
1982 return 0;
1983
1984 /* ASSERT: it's really the last sitd for this urb
1985 list_for_each_entry (sitd, &stream->td_list, sitd_list)
1986 BUG_ON (sitd->urb == urb);
1987 */
1988
1989 /* give urb back to the driver */
6a8e87b2 1990 dev = urb->dev;
7d12e780 1991 ehci_urb_done (ehci, urb);
1da177e4
LT		 1992 urb = NULL;
1993
1994 /* defer stopping schedule; completion can submit */
1995 ehci->periodic_sched--;
1996 if (!ehci->periodic_sched)
1997 (void) disable_periodic (ehci);
1998 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1999
2000 if (list_empty (&stream->td_list)) {
2001 ehci_to_hcd(ehci)->self.bandwidth_allocated
2002 -= stream->bandwidth;
2003 ehci_vdbg (ehci,
2004 "deschedule devp %s ep%d%s-iso\n",
2005 dev->devpath, stream->bEndpointAddress & 0x0f,
2006 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2007 }
2008 iso_stream_put (ehci, stream);
1da177e4
LT		 2009
2010 return 1;
2011}
2012
2013
5db539e4 2014static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
55016f10 2015 gfp_t mem_flags)
1da177e4
LT		 2016{
2017 int status = -EINVAL;
2018 unsigned long flags;
2019 struct ehci_iso_stream *stream;
2020
2021 /* Get iso_stream head */
2022 stream = iso_stream_find (ehci, urb);
2023 if (stream == NULL) {
2024 ehci_dbg (ehci, "can't get iso stream\n");
2025 return -ENOMEM;
2026 }
2027 if (urb->interval != stream->interval) {
2028 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2029 stream->interval, urb->interval);
2030 goto done;
2031 }
2032
2033#ifdef EHCI_URB_TRACE
2034 ehci_dbg (ehci,
2035 "submit %p dev%s ep%d%s-iso len %d\n",
2036 urb, urb->dev->devpath,
2037 usb_pipeendpoint (urb->pipe),
2038 usb_pipein (urb->pipe) ? "in" : "out",
2039 urb->transfer_buffer_length);
2040#endif
2041
2042 /* allocate SITDs */
2043 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2044 if (status < 0) {
2045 ehci_dbg (ehci, "can't init sitds\n");
2046 goto done;
2047 }
2048
2049 /* schedule ... need to lock */
2050 spin_lock_irqsave (&ehci->lock, flags);
8de98402
BH		 2051 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
2052 &ehci_to_hcd(ehci)->flags)))
2053 status = -ESHUTDOWN;
2054 else
2055 status = iso_stream_schedule (ehci, urb, stream);
53bd6a60 2056 if (status == 0)
1da177e4
LT		 2057 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2058 spin_unlock_irqrestore (&ehci->lock, flags);
2059
2060done:
2061 if (status < 0)
2062 iso_stream_put (ehci, stream);
2063 return status;
2064}
2065
2066#else
2067
2068static inline int
bf8b2b53 2069sitd_submit (struct ehci_hcd *ehci, struct urb *urb, gfp_t mem_flags)
1da177e4
LT		 2070{
2071 ehci_dbg (ehci, "split iso support is disabled\n");
2072 return -ENOSYS;
2073}
2074
2075static inline unsigned
2076sitd_complete (
2077 struct ehci_hcd *ehci,
7d12e780 2078 struct ehci_sitd *sitd
1da177e4
LT		 2079) {
2080 ehci_err (ehci, "sitd_complete %p?\n", sitd);
2081 return 0;
2082}
2083
2084#endif /* USB_EHCI_SPLIT_ISO */
2085
2086/*-------------------------------------------------------------------------*/
2087
2088static void
7d12e780 2089scan_periodic (struct ehci_hcd *ehci)
1da177e4
LT		 2090{
2091 unsigned frame, clock, now_uframe, mod;
2092 unsigned modified;
2093
2094 mod = ehci->periodic_size << 3;
2095
2096 /*
2097 * When running, scan from last scan point up to "now"
2098 * else clean up by scanning everything that's left.
2099 * Touches as few pages as possible: cache-friendly.
2100 */
2101 now_uframe = ehci->next_uframe;
2102 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
083522d7 2103 clock = ehci_readl(ehci, &ehci->regs->frame_index);
1da177e4
LT		 2104 else
2105 clock = now_uframe + mod - 1;
2106 clock %= mod;
2107
2108 for (;;) {
2109 union ehci_shadow q, *q_p;
6dbd682b 2110 __hc32 type, *hw_p;
1da177e4
LT		 2111 unsigned uframes;
2112
2113 /* don't scan past the live uframe */
2114 frame = now_uframe >> 3;
2115 if (frame == (clock >> 3))
2116 uframes = now_uframe & 0x07;
2117 else {
2118 /* safe to scan the whole frame at once */
2119 now_uframe |= 0x07;
2120 uframes = 8;
2121 }
2122
2123restart:
2124 /* scan each element in frame's queue for completions */
2125 q_p = &ehci->pshadow [frame];
2126 hw_p = &ehci->periodic [frame];
2127 q.ptr = q_p->ptr;
6dbd682b 2128 type = Q_NEXT_TYPE(ehci, *hw_p);
1da177e4
LT		 2129 modified = 0;
2130
2131 while (q.ptr != NULL) {
2132 unsigned uf;
2133 union ehci_shadow temp;
2134 int live;
2135
2136 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
6dbd682b 2137 switch (hc32_to_cpu(ehci, type)) {
1da177e4
LT		 2138 case Q_TYPE_QH:
2139 /* handle any completions */
2140 temp.qh = qh_get (q.qh);
6dbd682b 2141 type = Q_NEXT_TYPE(ehci, q.qh->hw_next);
1da177e4 2142 q = q.qh->qh_next;
7d12e780 2143 modified = qh_completions (ehci, temp.qh);
1da177e4
LT		 2144 if (unlikely (list_empty (&temp.qh->qtd_list)))
2145 intr_deschedule (ehci, temp.qh);
2146 qh_put (temp.qh);
2147 break;
2148 case Q_TYPE_FSTN:
2149 /* for "save place" FSTNs, look at QH entries
2150 * in the previous frame for completions.
2151 */
6dbd682b 2152 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
1da177e4
LT		 2153 dbg ("ignoring completions from FSTNs");
2154 }
6dbd682b 2155 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
1da177e4
LT		 2156 q = q.fstn->fstn_next;
2157 break;
2158 case Q_TYPE_ITD:
2159 /* skip itds for later in the frame */
2160 rmb ();
2161 for (uf = live ? uframes : 8; uf < 8; uf++) {
2162 if (0 == (q.itd->hw_transaction [uf]
6dbd682b 2163 & ITD_ACTIVE(ehci)))
1da177e4
LT		 2164 continue;
2165 q_p = &q.itd->itd_next;
2166 hw_p = &q.itd->hw_next;
6dbd682b
SR		 2167 type = Q_NEXT_TYPE(ehci,
2168 q.itd->hw_next);
1da177e4
LT		 2169 q = *q_p;
2170 break;
2171 }
2172 if (uf != 8)
2173 break;
2174
2175 /* this one's ready ... HC won't cache the
2176 * pointer for much longer, if at all.
2177 */
2178 *q_p = q.itd->itd_next;
2179 *hw_p = q.itd->hw_next;
6dbd682b 2180 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
1da177e4 2181 wmb();
7d12e780 2182 modified = itd_complete (ehci, q.itd);
1da177e4
LT		 2183 q = *q_p;
2184 break;
2185 case Q_TYPE_SITD:
6dbd682b 2186 if ((q.sitd->hw_results & SITD_ACTIVE(ehci))
1da177e4
LT		 2187 && live) {
2188 q_p = &q.sitd->sitd_next;
2189 hw_p = &q.sitd->hw_next;
6dbd682b
SR		 2190 type = Q_NEXT_TYPE(ehci,
2191 q.sitd->hw_next);
1da177e4
LT		 2192 q = *q_p;
2193 break;
2194 }
2195 *q_p = q.sitd->sitd_next;
2196 *hw_p = q.sitd->hw_next;
6dbd682b 2197 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
1da177e4 2198 wmb();
7d12e780 2199 modified = sitd_complete (ehci, q.sitd);
1da177e4
LT		 2200 q = *q_p;
2201 break;
2202 default:
2203 dbg ("corrupt type %d frame %d shadow %p",
2204 type, frame, q.ptr);
2205 // BUG ();
2206 q.ptr = NULL;
2207 }
2208
2209 /* assume completion callbacks modify the queue */
2210 if (unlikely (modified))
2211 goto restart;
2212 }
2213
2214 /* stop when we catch up to the HC */
2215
2216 // FIXME: this assumes we won't get lapped when
2217 // latencies climb; that should be rare, but...
2218 // detect it, and just go all the way around.
2219 // FLR might help detect this case, so long as latencies
2220 // don't exceed periodic_size msec (default 1.024 sec).
2221
2222 // FIXME: likewise assumes HC doesn't halt mid-scan
2223
2224 if (now_uframe == clock) {
2225 unsigned now;
2226
2227 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2228 break;
2229 ehci->next_uframe = now_uframe;
083522d7 2230 now = ehci_readl(ehci, &ehci->regs->frame_index) % mod;
1da177e4
LT		 2231 if (now_uframe == now)
2232 break;
2233
2234 /* rescan the rest of this frame, then ... */
2235 clock = now;
2236 } else {
2237 now_uframe++;
2238 now_uframe %= mod;
2239 }
53bd6a60 2240 }
1da177e4 2241}
Linux kernel - Deliverables
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