Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2001-2004 by David Brownell | |
3 | * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers | |
53bd6a60 | 4 | * |
1da177e4 LT |
5 | * This program is free software; you can redistribute it and/or modify it |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software Foundation, | |
17 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | /* this file is part of ehci-hcd.c */ | |
21 | ||
22 | /*-------------------------------------------------------------------------*/ | |
23 | ||
24 | /* | |
25 | * EHCI scheduled transaction support: interrupt, iso, split iso | |
26 | * These are called "periodic" transactions in the EHCI spec. | |
27 | * | |
28 | * Note that for interrupt transfers, the QH/QTD manipulation is shared | |
29 | * with the "asynchronous" transaction support (control/bulk transfers). | |
30 | * The only real difference is in how interrupt transfers are scheduled. | |
31 | * | |
32 | * For ISO, we make an "iso_stream" head to serve the same role as a QH. | |
33 | * It keeps track of every ITD (or SITD) that's linked, and holds enough | |
34 | * pre-calculated schedule data to make appending to the queue be quick. | |
35 | */ | |
36 | ||
37 | static int ehci_get_frame (struct usb_hcd *hcd); | |
38 | ||
68aa95d5 AS |
39 | #ifdef CONFIG_PCI |
40 | ||
41 | static unsigned ehci_read_frame_index(struct ehci_hcd *ehci) | |
42 | { | |
43 | unsigned uf; | |
44 | ||
45 | /* | |
46 | * The MosChip MCS9990 controller updates its microframe counter | |
47 | * a little before the frame counter, and occasionally we will read | |
48 | * the invalid intermediate value. Avoid problems by checking the | |
49 | * microframe number (the low-order 3 bits); if they are 0 then | |
50 | * re-read the register to get the correct value. | |
51 | */ | |
52 | uf = ehci_readl(ehci, &ehci->regs->frame_index); | |
53 | if (unlikely(ehci->frame_index_bug && ((uf & 7) == 0))) | |
54 | uf = ehci_readl(ehci, &ehci->regs->frame_index); | |
55 | return uf; | |
56 | } | |
57 | ||
58 | #endif | |
59 | ||
1da177e4 LT |
60 | /*-------------------------------------------------------------------------*/ |
61 | ||
62 | /* | |
63 | * periodic_next_shadow - return "next" pointer on shadow list | |
64 | * @periodic: host pointer to qh/itd/sitd | |
65 | * @tag: hardware tag for type of this record | |
66 | */ | |
67 | static union ehci_shadow * | |
6dbd682b SR |
68 | periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic, |
69 | __hc32 tag) | |
1da177e4 | 70 | { |
6dbd682b | 71 | switch (hc32_to_cpu(ehci, tag)) { |
1da177e4 LT |
72 | case Q_TYPE_QH: |
73 | return &periodic->qh->qh_next; | |
74 | case Q_TYPE_FSTN: | |
75 | return &periodic->fstn->fstn_next; | |
76 | case Q_TYPE_ITD: | |
77 | return &periodic->itd->itd_next; | |
78 | // case Q_TYPE_SITD: | |
79 | default: | |
80 | return &periodic->sitd->sitd_next; | |
81 | } | |
82 | } | |
83 | ||
3807e26d AD |
84 | static __hc32 * |
85 | shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic, | |
86 | __hc32 tag) | |
87 | { | |
88 | switch (hc32_to_cpu(ehci, tag)) { | |
89 | /* our ehci_shadow.qh is actually software part */ | |
90 | case Q_TYPE_QH: | |
91 | return &periodic->qh->hw->hw_next; | |
92 | /* others are hw parts */ | |
93 | default: | |
94 | return periodic->hw_next; | |
95 | } | |
96 | } | |
97 | ||
1da177e4 LT |
98 | /* caller must hold ehci->lock */ |
99 | static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr) | |
100 | { | |
6dbd682b SR |
101 | union ehci_shadow *prev_p = &ehci->pshadow[frame]; |
102 | __hc32 *hw_p = &ehci->periodic[frame]; | |
1da177e4 LT |
103 | union ehci_shadow here = *prev_p; |
104 | ||
105 | /* find predecessor of "ptr"; hw and shadow lists are in sync */ | |
106 | while (here.ptr && here.ptr != ptr) { | |
6dbd682b SR |
107 | prev_p = periodic_next_shadow(ehci, prev_p, |
108 | Q_NEXT_TYPE(ehci, *hw_p)); | |
3807e26d AD |
109 | hw_p = shadow_next_periodic(ehci, &here, |
110 | Q_NEXT_TYPE(ehci, *hw_p)); | |
1da177e4 LT |
111 | here = *prev_p; |
112 | } | |
113 | /* an interrupt entry (at list end) could have been shared */ | |
114 | if (!here.ptr) | |
115 | return; | |
116 | ||
117 | /* update shadow and hardware lists ... the old "next" pointers | |
118 | * from ptr may still be in use, the caller updates them. | |
119 | */ | |
6dbd682b SR |
120 | *prev_p = *periodic_next_shadow(ehci, &here, |
121 | Q_NEXT_TYPE(ehci, *hw_p)); | |
3d091a6f AX |
122 | |
123 | if (!ehci->use_dummy_qh || | |
124 | *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p)) | |
125 | != EHCI_LIST_END(ehci)) | |
126 | *hw_p = *shadow_next_periodic(ehci, &here, | |
127 | Q_NEXT_TYPE(ehci, *hw_p)); | |
128 | else | |
129 | *hw_p = ehci->dummy->qh_dma; | |
1da177e4 LT |
130 | } |
131 | ||
132 | /* how many of the uframe's 125 usecs are allocated? */ | |
133 | static unsigned short | |
134 | periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe) | |
135 | { | |
6dbd682b | 136 | __hc32 *hw_p = &ehci->periodic [frame]; |
1da177e4 LT |
137 | union ehci_shadow *q = &ehci->pshadow [frame]; |
138 | unsigned usecs = 0; | |
3807e26d | 139 | struct ehci_qh_hw *hw; |
1da177e4 LT |
140 | |
141 | while (q->ptr) { | |
6dbd682b | 142 | switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) { |
1da177e4 | 143 | case Q_TYPE_QH: |
3807e26d | 144 | hw = q->qh->hw; |
1da177e4 | 145 | /* is it in the S-mask? */ |
3807e26d | 146 | if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe)) |
1da177e4 LT |
147 | usecs += q->qh->usecs; |
148 | /* ... or C-mask? */ | |
3807e26d | 149 | if (hw->hw_info2 & cpu_to_hc32(ehci, |
6dbd682b | 150 | 1 << (8 + uframe))) |
1da177e4 | 151 | usecs += q->qh->c_usecs; |
3807e26d | 152 | hw_p = &hw->hw_next; |
1da177e4 LT |
153 | q = &q->qh->qh_next; |
154 | break; | |
155 | // case Q_TYPE_FSTN: | |
156 | default: | |
157 | /* for "save place" FSTNs, count the relevant INTR | |
158 | * bandwidth from the previous frame | |
159 | */ | |
6dbd682b | 160 | if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) { |
1da177e4 LT |
161 | ehci_dbg (ehci, "ignoring FSTN cost ...\n"); |
162 | } | |
163 | hw_p = &q->fstn->hw_next; | |
164 | q = &q->fstn->fstn_next; | |
165 | break; | |
166 | case Q_TYPE_ITD: | |
3b6fcfd0 KW |
167 | if (q->itd->hw_transaction[uframe]) |
168 | usecs += q->itd->stream->usecs; | |
1da177e4 LT |
169 | hw_p = &q->itd->hw_next; |
170 | q = &q->itd->itd_next; | |
171 | break; | |
172 | case Q_TYPE_SITD: | |
173 | /* is it in the S-mask? (count SPLIT, DATA) */ | |
6dbd682b SR |
174 | if (q->sitd->hw_uframe & cpu_to_hc32(ehci, |
175 | 1 << uframe)) { | |
1da177e4 | 176 | if (q->sitd->hw_fullspeed_ep & |
6dbd682b | 177 | cpu_to_hc32(ehci, 1<<31)) |
1da177e4 LT |
178 | usecs += q->sitd->stream->usecs; |
179 | else /* worst case for OUT start-split */ | |
180 | usecs += HS_USECS_ISO (188); | |
181 | } | |
182 | ||
183 | /* ... C-mask? (count CSPLIT, DATA) */ | |
184 | if (q->sitd->hw_uframe & | |
6dbd682b | 185 | cpu_to_hc32(ehci, 1 << (8 + uframe))) { |
1da177e4 LT |
186 | /* worst case for IN complete-split */ |
187 | usecs += q->sitd->stream->c_usecs; | |
188 | } | |
189 | ||
190 | hw_p = &q->sitd->hw_next; | |
191 | q = &q->sitd->sitd_next; | |
192 | break; | |
193 | } | |
194 | } | |
195 | #ifdef DEBUG | |
cc62a7eb | 196 | if (usecs > ehci->uframe_periodic_max) |
1da177e4 LT |
197 | ehci_err (ehci, "uframe %d sched overrun: %d usecs\n", |
198 | frame * 8 + uframe, usecs); | |
199 | #endif | |
200 | return usecs; | |
201 | } | |
202 | ||
203 | /*-------------------------------------------------------------------------*/ | |
204 | ||
205 | static int same_tt (struct usb_device *dev1, struct usb_device *dev2) | |
206 | { | |
207 | if (!dev1->tt || !dev2->tt) | |
208 | return 0; | |
209 | if (dev1->tt != dev2->tt) | |
210 | return 0; | |
211 | if (dev1->tt->multi) | |
212 | return dev1->ttport == dev2->ttport; | |
213 | else | |
214 | return 1; | |
215 | } | |
216 | ||
ba47f66b DS |
217 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED |
218 | ||
219 | /* Which uframe does the low/fullspeed transfer start in? | |
220 | * | |
221 | * The parameter is the mask of ssplits in "H-frame" terms | |
222 | * and this returns the transfer start uframe in "B-frame" terms, | |
223 | * which allows both to match, e.g. a ssplit in "H-frame" uframe 0 | |
224 | * will cause a transfer in "B-frame" uframe 0. "B-frames" lag | |
225 | * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7. | |
226 | */ | |
6dbd682b | 227 | static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask) |
ba47f66b | 228 | { |
6dbd682b | 229 | unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask); |
ba47f66b DS |
230 | if (!smask) { |
231 | ehci_err(ehci, "invalid empty smask!\n"); | |
232 | /* uframe 7 can't have bw so this will indicate failure */ | |
233 | return 7; | |
234 | } | |
235 | return ffs(smask) - 1; | |
236 | } | |
237 | ||
238 | static const unsigned char | |
239 | max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 }; | |
240 | ||
241 | /* carryover low/fullspeed bandwidth that crosses uframe boundries */ | |
242 | static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8]) | |
243 | { | |
244 | int i; | |
245 | for (i=0; i<7; i++) { | |
246 | if (max_tt_usecs[i] < tt_usecs[i]) { | |
247 | tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i]; | |
248 | tt_usecs[i] = max_tt_usecs[i]; | |
249 | } | |
250 | } | |
251 | } | |
252 | ||
253 | /* How many of the tt's periodic downstream 1000 usecs are allocated? | |
254 | * | |
255 | * While this measures the bandwidth in terms of usecs/uframe, | |
256 | * the low/fullspeed bus has no notion of uframes, so any particular | |
257 | * low/fullspeed transfer can "carry over" from one uframe to the next, | |
258 | * since the TT just performs downstream transfers in sequence. | |
259 | * | |
dc0d5c1e | 260 | * For example two separate 100 usec transfers can start in the same uframe, |
ba47f66b DS |
261 | * and the second one would "carry over" 75 usecs into the next uframe. |
262 | */ | |
263 | static void | |
264 | periodic_tt_usecs ( | |
265 | struct ehci_hcd *ehci, | |
266 | struct usb_device *dev, | |
267 | unsigned frame, | |
268 | unsigned short tt_usecs[8] | |
269 | ) | |
270 | { | |
6dbd682b | 271 | __hc32 *hw_p = &ehci->periodic [frame]; |
ba47f66b DS |
272 | union ehci_shadow *q = &ehci->pshadow [frame]; |
273 | unsigned char uf; | |
274 | ||
275 | memset(tt_usecs, 0, 16); | |
276 | ||
277 | while (q->ptr) { | |
6dbd682b | 278 | switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) { |
ba47f66b DS |
279 | case Q_TYPE_ITD: |
280 | hw_p = &q->itd->hw_next; | |
281 | q = &q->itd->itd_next; | |
282 | continue; | |
283 | case Q_TYPE_QH: | |
284 | if (same_tt(dev, q->qh->dev)) { | |
3807e26d | 285 | uf = tt_start_uframe(ehci, q->qh->hw->hw_info2); |
ba47f66b DS |
286 | tt_usecs[uf] += q->qh->tt_usecs; |
287 | } | |
3807e26d | 288 | hw_p = &q->qh->hw->hw_next; |
ba47f66b DS |
289 | q = &q->qh->qh_next; |
290 | continue; | |
291 | case Q_TYPE_SITD: | |
292 | if (same_tt(dev, q->sitd->urb->dev)) { | |
293 | uf = tt_start_uframe(ehci, q->sitd->hw_uframe); | |
294 | tt_usecs[uf] += q->sitd->stream->tt_usecs; | |
295 | } | |
296 | hw_p = &q->sitd->hw_next; | |
297 | q = &q->sitd->sitd_next; | |
298 | continue; | |
299 | // case Q_TYPE_FSTN: | |
300 | default: | |
6dbd682b SR |
301 | ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n", |
302 | frame); | |
ba47f66b DS |
303 | hw_p = &q->fstn->hw_next; |
304 | q = &q->fstn->fstn_next; | |
305 | } | |
306 | } | |
307 | ||
308 | carryover_tt_bandwidth(tt_usecs); | |
309 | ||
310 | if (max_tt_usecs[7] < tt_usecs[7]) | |
311 | ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n", | |
312 | frame, tt_usecs[7] - max_tt_usecs[7]); | |
313 | } | |
314 | ||
315 | /* | |
316 | * Return true if the device's tt's downstream bus is available for a | |
317 | * periodic transfer of the specified length (usecs), starting at the | |
318 | * specified frame/uframe. Note that (as summarized in section 11.19 | |
319 | * of the usb 2.0 spec) TTs can buffer multiple transactions for each | |
320 | * uframe. | |
321 | * | |
322 | * The uframe parameter is when the fullspeed/lowspeed transfer | |
323 | * should be executed in "B-frame" terms, which is the same as the | |
324 | * highspeed ssplit's uframe (which is in "H-frame" terms). For example | |
325 | * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0. | |
326 | * See the EHCI spec sec 4.5 and fig 4.7. | |
327 | * | |
328 | * This checks if the full/lowspeed bus, at the specified starting uframe, | |
329 | * has the specified bandwidth available, according to rules listed | |
330 | * in USB 2.0 spec section 11.18.1 fig 11-60. | |
331 | * | |
332 | * This does not check if the transfer would exceed the max ssplit | |
333 | * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4, | |
334 | * since proper scheduling limits ssplits to less than 16 per uframe. | |
335 | */ | |
336 | static int tt_available ( | |
337 | struct ehci_hcd *ehci, | |
338 | unsigned period, | |
339 | struct usb_device *dev, | |
340 | unsigned frame, | |
341 | unsigned uframe, | |
342 | u16 usecs | |
343 | ) | |
344 | { | |
345 | if ((period == 0) || (uframe >= 7)) /* error */ | |
346 | return 0; | |
347 | ||
348 | for (; frame < ehci->periodic_size; frame += period) { | |
349 | unsigned short tt_usecs[8]; | |
350 | ||
351 | periodic_tt_usecs (ehci, dev, frame, tt_usecs); | |
352 | ||
353 | ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in" | |
354 | " schedule %d/%d/%d/%d/%d/%d/%d/%d\n", | |
355 | frame, usecs, uframe, | |
356 | tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3], | |
357 | tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]); | |
358 | ||
359 | if (max_tt_usecs[uframe] <= tt_usecs[uframe]) { | |
360 | ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n", | |
361 | frame, uframe); | |
362 | return 0; | |
363 | } | |
364 | ||
365 | /* special case for isoc transfers larger than 125us: | |
366 | * the first and each subsequent fully used uframe | |
367 | * must be empty, so as to not illegally delay | |
368 | * already scheduled transactions | |
369 | */ | |
370 | if (125 < usecs) { | |
c065c60e | 371 | int ufs = (usecs / 125); |
ba47f66b DS |
372 | int i; |
373 | for (i = uframe; i < (uframe + ufs) && i < 8; i++) | |
374 | if (0 < tt_usecs[i]) { | |
375 | ehci_vdbg(ehci, | |
376 | "multi-uframe xfer can't fit " | |
377 | "in frame %d uframe %d\n", | |
378 | frame, i); | |
379 | return 0; | |
380 | } | |
381 | } | |
382 | ||
383 | tt_usecs[uframe] += usecs; | |
384 | ||
385 | carryover_tt_bandwidth(tt_usecs); | |
386 | ||
387 | /* fail if the carryover pushed bw past the last uframe's limit */ | |
388 | if (max_tt_usecs[7] < tt_usecs[7]) { | |
389 | ehci_vdbg(ehci, | |
390 | "tt unavailable usecs %d frame %d uframe %d\n", | |
391 | usecs, frame, uframe); | |
392 | return 0; | |
393 | } | |
394 | } | |
395 | ||
396 | return 1; | |
397 | } | |
398 | ||
399 | #else | |
400 | ||
1da177e4 LT |
401 | /* return true iff the device's transaction translator is available |
402 | * for a periodic transfer starting at the specified frame, using | |
403 | * all the uframes in the mask. | |
404 | */ | |
405 | static int tt_no_collision ( | |
406 | struct ehci_hcd *ehci, | |
407 | unsigned period, | |
408 | struct usb_device *dev, | |
409 | unsigned frame, | |
410 | u32 uf_mask | |
411 | ) | |
412 | { | |
413 | if (period == 0) /* error */ | |
414 | return 0; | |
415 | ||
416 | /* note bandwidth wastage: split never follows csplit | |
417 | * (different dev or endpoint) until the next uframe. | |
418 | * calling convention doesn't make that distinction. | |
419 | */ | |
420 | for (; frame < ehci->periodic_size; frame += period) { | |
421 | union ehci_shadow here; | |
6dbd682b | 422 | __hc32 type; |
3807e26d | 423 | struct ehci_qh_hw *hw; |
1da177e4 LT |
424 | |
425 | here = ehci->pshadow [frame]; | |
6dbd682b | 426 | type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]); |
1da177e4 | 427 | while (here.ptr) { |
6dbd682b | 428 | switch (hc32_to_cpu(ehci, type)) { |
1da177e4 | 429 | case Q_TYPE_ITD: |
6dbd682b | 430 | type = Q_NEXT_TYPE(ehci, here.itd->hw_next); |
1da177e4 LT |
431 | here = here.itd->itd_next; |
432 | continue; | |
433 | case Q_TYPE_QH: | |
3807e26d | 434 | hw = here.qh->hw; |
1da177e4 LT |
435 | if (same_tt (dev, here.qh->dev)) { |
436 | u32 mask; | |
437 | ||
6dbd682b | 438 | mask = hc32_to_cpu(ehci, |
3807e26d | 439 | hw->hw_info2); |
1da177e4 LT |
440 | /* "knows" no gap is needed */ |
441 | mask |= mask >> 8; | |
442 | if (mask & uf_mask) | |
443 | break; | |
444 | } | |
3807e26d | 445 | type = Q_NEXT_TYPE(ehci, hw->hw_next); |
1da177e4 LT |
446 | here = here.qh->qh_next; |
447 | continue; | |
448 | case Q_TYPE_SITD: | |
449 | if (same_tt (dev, here.sitd->urb->dev)) { | |
450 | u16 mask; | |
451 | ||
6dbd682b | 452 | mask = hc32_to_cpu(ehci, here.sitd |
1da177e4 LT |
453 | ->hw_uframe); |
454 | /* FIXME assumes no gap for IN! */ | |
455 | mask |= mask >> 8; | |
456 | if (mask & uf_mask) | |
457 | break; | |
458 | } | |
6dbd682b | 459 | type = Q_NEXT_TYPE(ehci, here.sitd->hw_next); |
1da177e4 LT |
460 | here = here.sitd->sitd_next; |
461 | continue; | |
462 | // case Q_TYPE_FSTN: | |
463 | default: | |
464 | ehci_dbg (ehci, | |
465 | "periodic frame %d bogus type %d\n", | |
466 | frame, type); | |
467 | } | |
468 | ||
469 | /* collision or error */ | |
470 | return 0; | |
471 | } | |
472 | } | |
473 | ||
474 | /* no collision */ | |
475 | return 1; | |
476 | } | |
477 | ||
ba47f66b DS |
478 | #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */ |
479 | ||
1da177e4 LT |
480 | /*-------------------------------------------------------------------------*/ |
481 | ||
b015cb79 | 482 | static void enable_periodic(struct ehci_hcd *ehci) |
1da177e4 | 483 | { |
3ca9aeba | 484 | if (ehci->periodic_count++) |
b015cb79 | 485 | return; |
01c17142 | 486 | |
3ca9aeba AS |
487 | /* Stop waiting to turn off the periodic schedule */ |
488 | ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_PERIODIC); | |
1da177e4 | 489 | |
3ca9aeba AS |
490 | /* Don't start the schedule until PSS is 0 */ |
491 | ehci_poll_PSS(ehci); | |
1da177e4 LT |
492 | } |
493 | ||
b015cb79 | 494 | static void disable_periodic(struct ehci_hcd *ehci) |
1da177e4 | 495 | { |
3ca9aeba | 496 | if (--ehci->periodic_count) |
b015cb79 | 497 | return; |
01c17142 | 498 | |
3ca9aeba | 499 | ehci->next_uframe = -1; /* the periodic schedule is empty */ |
d63c66d2 | 500 | |
3ca9aeba AS |
501 | /* Don't turn off the schedule until PSS is 1 */ |
502 | ehci_poll_PSS(ehci); | |
1da177e4 LT |
503 | } |
504 | ||
505 | /*-------------------------------------------------------------------------*/ | |
506 | ||
507 | /* periodic schedule slots have iso tds (normal or split) first, then a | |
508 | * sparse tree for active interrupt transfers. | |
509 | * | |
510 | * this just links in a qh; caller guarantees uframe masks are set right. | |
511 | * no FSTN support (yet; ehci 0.96+) | |
512 | */ | |
b015cb79 | 513 | static void qh_link_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 LT |
514 | { |
515 | unsigned i; | |
516 | unsigned period = qh->period; | |
517 | ||
518 | dev_dbg (&qh->dev->dev, | |
519 | "link qh%d-%04x/%p start %d [%d/%d us]\n", | |
3807e26d AD |
520 | period, hc32_to_cpup(ehci, &qh->hw->hw_info2) |
521 | & (QH_CMASK | QH_SMASK), | |
1da177e4 LT |
522 | qh, qh->start, qh->usecs, qh->c_usecs); |
523 | ||
524 | /* high bandwidth, or otherwise every microframe */ | |
525 | if (period == 0) | |
526 | period = 1; | |
527 | ||
528 | for (i = qh->start; i < ehci->periodic_size; i += period) { | |
6dbd682b SR |
529 | union ehci_shadow *prev = &ehci->pshadow[i]; |
530 | __hc32 *hw_p = &ehci->periodic[i]; | |
1da177e4 | 531 | union ehci_shadow here = *prev; |
6dbd682b | 532 | __hc32 type = 0; |
1da177e4 LT |
533 | |
534 | /* skip the iso nodes at list head */ | |
535 | while (here.ptr) { | |
6dbd682b SR |
536 | type = Q_NEXT_TYPE(ehci, *hw_p); |
537 | if (type == cpu_to_hc32(ehci, Q_TYPE_QH)) | |
1da177e4 | 538 | break; |
6dbd682b | 539 | prev = periodic_next_shadow(ehci, prev, type); |
3807e26d | 540 | hw_p = shadow_next_periodic(ehci, &here, type); |
1da177e4 LT |
541 | here = *prev; |
542 | } | |
543 | ||
544 | /* sorting each branch by period (slow-->fast) | |
545 | * enables sharing interior tree nodes | |
546 | */ | |
547 | while (here.ptr && qh != here.qh) { | |
548 | if (qh->period > here.qh->period) | |
549 | break; | |
550 | prev = &here.qh->qh_next; | |
3807e26d | 551 | hw_p = &here.qh->hw->hw_next; |
1da177e4 LT |
552 | here = *prev; |
553 | } | |
554 | /* link in this qh, unless some earlier pass did that */ | |
555 | if (qh != here.qh) { | |
556 | qh->qh_next = here; | |
557 | if (here.qh) | |
3807e26d | 558 | qh->hw->hw_next = *hw_p; |
1da177e4 LT |
559 | wmb (); |
560 | prev->qh = qh; | |
6dbd682b | 561 | *hw_p = QH_NEXT (ehci, qh->qh_dma); |
1da177e4 LT |
562 | } |
563 | } | |
564 | qh->qh_state = QH_STATE_LINKED; | |
ef4638f9 | 565 | qh->xacterrs = 0; |
1da177e4 LT |
566 | |
567 | /* update per-qh bandwidth for usbfs */ | |
568 | ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period | |
569 | ? ((qh->usecs + qh->c_usecs) / qh->period) | |
570 | : (qh->usecs * 8); | |
571 | ||
572 | /* maybe enable periodic schedule processing */ | |
b015cb79 | 573 | enable_periodic(ehci); |
1da177e4 LT |
574 | } |
575 | ||
b015cb79 | 576 | static void qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 LT |
577 | { |
578 | unsigned i; | |
579 | unsigned period; | |
580 | ||
df202255 AS |
581 | /* |
582 | * If qh is for a low/full-speed device, simply unlinking it | |
583 | * could interfere with an ongoing split transaction. To unlink | |
584 | * it safely would require setting the QH_INACTIVATE bit and | |
585 | * waiting at least one frame, as described in EHCI 4.12.2.5. | |
586 | * | |
587 | * We won't bother with any of this. Instead, we assume that the | |
588 | * only reason for unlinking an interrupt QH while the current URB | |
589 | * is still active is to dequeue all the URBs (flush the whole | |
590 | * endpoint queue). | |
591 | * | |
592 | * If rebalancing the periodic schedule is ever implemented, this | |
593 | * approach will no longer be valid. | |
594 | */ | |
1da177e4 LT |
595 | |
596 | /* high bandwidth, or otherwise part of every microframe */ | |
597 | if ((period = qh->period) == 0) | |
598 | period = 1; | |
599 | ||
600 | for (i = qh->start; i < ehci->periodic_size; i += period) | |
601 | periodic_unlink (ehci, i, qh); | |
602 | ||
603 | /* update per-qh bandwidth for usbfs */ | |
604 | ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period | |
605 | ? ((qh->usecs + qh->c_usecs) / qh->period) | |
606 | : (qh->usecs * 8); | |
607 | ||
608 | dev_dbg (&qh->dev->dev, | |
609 | "unlink qh%d-%04x/%p start %d [%d/%d us]\n", | |
7dedacf4 | 610 | qh->period, |
3807e26d | 611 | hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK), |
1da177e4 LT |
612 | qh, qh->start, qh->usecs, qh->c_usecs); |
613 | ||
614 | /* qh->qh_next still "live" to HC */ | |
615 | qh->qh_state = QH_STATE_UNLINK; | |
616 | qh->qh_next.ptr = NULL; | |
1da177e4 LT |
617 | } |
618 | ||
df202255 | 619 | static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 | 620 | { |
a448c9d8 AS |
621 | /* If the QH isn't linked then there's nothing we can do |
622 | * unless we were called during a giveback, in which case | |
623 | * qh_completions() has to deal with it. | |
624 | */ | |
625 | if (qh->qh_state != QH_STATE_LINKED) { | |
626 | if (qh->qh_state == QH_STATE_COMPLETING) | |
627 | qh->needs_rescan = 1; | |
628 | return; | |
629 | } | |
1da177e4 LT |
630 | |
631 | qh_unlink_periodic (ehci, qh); | |
632 | ||
df202255 AS |
633 | /* Make sure the unlinks are visible before starting the timer */ |
634 | wmb(); | |
635 | ||
636 | /* | |
637 | * The EHCI spec doesn't say how long it takes the controller to | |
638 | * stop accessing an unlinked interrupt QH. The timer delay is | |
639 | * 9 uframes; presumably that will be long enough. | |
1da177e4 | 640 | */ |
df202255 AS |
641 | qh->unlink_cycle = ehci->intr_unlink_cycle; |
642 | ||
643 | /* New entries go at the end of the intr_unlink list */ | |
644 | if (ehci->intr_unlink) | |
645 | ehci->intr_unlink_last->unlink_next = qh; | |
1da177e4 | 646 | else |
df202255 AS |
647 | ehci->intr_unlink = qh; |
648 | ehci->intr_unlink_last = qh; | |
649 | ||
650 | if (ehci->intr_unlinking) | |
651 | ; /* Avoid recursive calls */ | |
652 | else if (ehci->rh_state < EHCI_RH_RUNNING) | |
653 | ehci_handle_intr_unlinks(ehci); | |
654 | else if (ehci->intr_unlink == qh) { | |
655 | ehci_enable_event(ehci, EHCI_HRTIMER_UNLINK_INTR, true); | |
656 | ++ehci->intr_unlink_cycle; | |
657 | } | |
658 | } | |
659 | ||
660 | static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh) | |
661 | { | |
662 | struct ehci_qh_hw *hw = qh->hw; | |
663 | int rc; | |
1da177e4 | 664 | |
1da177e4 | 665 | qh->qh_state = QH_STATE_IDLE; |
3807e26d | 666 | hw->hw_next = EHCI_LIST_END(ehci); |
a448c9d8 AS |
667 | |
668 | qh_completions(ehci, qh); | |
669 | ||
670 | /* reschedule QH iff another request is queued */ | |
df202255 | 671 | if (!list_empty(&qh->qtd_list) && ehci->rh_state == EHCI_RH_RUNNING) { |
a448c9d8 AS |
672 | rc = qh_schedule(ehci, qh); |
673 | ||
674 | /* An error here likely indicates handshake failure | |
675 | * or no space left in the schedule. Neither fault | |
676 | * should happen often ... | |
677 | * | |
678 | * FIXME kill the now-dysfunctional queued urbs | |
679 | */ | |
680 | if (rc != 0) | |
681 | ehci_err(ehci, "can't reschedule qh %p, err %d\n", | |
682 | qh, rc); | |
683 | } | |
3ca9aeba AS |
684 | |
685 | /* maybe turn off periodic schedule */ | |
686 | disable_periodic(ehci); | |
1da177e4 LT |
687 | } |
688 | ||
689 | /*-------------------------------------------------------------------------*/ | |
690 | ||
691 | static int check_period ( | |
53bd6a60 | 692 | struct ehci_hcd *ehci, |
1da177e4 LT |
693 | unsigned frame, |
694 | unsigned uframe, | |
695 | unsigned period, | |
696 | unsigned usecs | |
697 | ) { | |
698 | int claimed; | |
699 | ||
700 | /* complete split running into next frame? | |
701 | * given FSTN support, we could sometimes check... | |
702 | */ | |
703 | if (uframe >= 8) | |
704 | return 0; | |
705 | ||
cc62a7eb KS |
706 | /* convert "usecs we need" to "max already claimed" */ |
707 | usecs = ehci->uframe_periodic_max - usecs; | |
1da177e4 LT |
708 | |
709 | /* we "know" 2 and 4 uframe intervals were rejected; so | |
710 | * for period 0, check _every_ microframe in the schedule. | |
711 | */ | |
712 | if (unlikely (period == 0)) { | |
713 | do { | |
714 | for (uframe = 0; uframe < 7; uframe++) { | |
715 | claimed = periodic_usecs (ehci, frame, uframe); | |
716 | if (claimed > usecs) | |
717 | return 0; | |
718 | } | |
719 | } while ((frame += 1) < ehci->periodic_size); | |
720 | ||
721 | /* just check the specified uframe, at that period */ | |
722 | } else { | |
723 | do { | |
724 | claimed = periodic_usecs (ehci, frame, uframe); | |
725 | if (claimed > usecs) | |
726 | return 0; | |
727 | } while ((frame += period) < ehci->periodic_size); | |
728 | } | |
729 | ||
730 | // success! | |
731 | return 1; | |
732 | } | |
733 | ||
734 | static int check_intr_schedule ( | |
53bd6a60 | 735 | struct ehci_hcd *ehci, |
1da177e4 LT |
736 | unsigned frame, |
737 | unsigned uframe, | |
738 | const struct ehci_qh *qh, | |
6dbd682b | 739 | __hc32 *c_maskp |
1da177e4 LT |
740 | ) |
741 | { | |
53bd6a60 | 742 | int retval = -ENOSPC; |
ba47f66b | 743 | u8 mask = 0; |
1da177e4 LT |
744 | |
745 | if (qh->c_usecs && uframe >= 6) /* FSTN territory? */ | |
746 | goto done; | |
747 | ||
748 | if (!check_period (ehci, frame, uframe, qh->period, qh->usecs)) | |
749 | goto done; | |
750 | if (!qh->c_usecs) { | |
751 | retval = 0; | |
752 | *c_maskp = 0; | |
753 | goto done; | |
754 | } | |
755 | ||
ba47f66b DS |
756 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED |
757 | if (tt_available (ehci, qh->period, qh->dev, frame, uframe, | |
758 | qh->tt_usecs)) { | |
759 | unsigned i; | |
760 | ||
761 | /* TODO : this may need FSTN for SSPLIT in uframe 5. */ | |
762 | for (i=uframe+1; i<8 && i<uframe+4; i++) | |
763 | if (!check_period (ehci, frame, i, | |
764 | qh->period, qh->c_usecs)) | |
765 | goto done; | |
766 | else | |
767 | mask |= 1 << i; | |
768 | ||
769 | retval = 0; | |
770 | ||
6dbd682b | 771 | *c_maskp = cpu_to_hc32(ehci, mask << 8); |
ba47f66b DS |
772 | } |
773 | #else | |
1da177e4 LT |
774 | /* Make sure this tt's buffer is also available for CSPLITs. |
775 | * We pessimize a bit; probably the typical full speed case | |
776 | * doesn't need the second CSPLIT. | |
53bd6a60 | 777 | * |
1da177e4 LT |
778 | * NOTE: both SPLIT and CSPLIT could be checked in just |
779 | * one smart pass... | |
780 | */ | |
781 | mask = 0x03 << (uframe + qh->gap_uf); | |
6dbd682b | 782 | *c_maskp = cpu_to_hc32(ehci, mask << 8); |
1da177e4 LT |
783 | |
784 | mask |= 1 << uframe; | |
785 | if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) { | |
786 | if (!check_period (ehci, frame, uframe + qh->gap_uf + 1, | |
787 | qh->period, qh->c_usecs)) | |
788 | goto done; | |
789 | if (!check_period (ehci, frame, uframe + qh->gap_uf, | |
790 | qh->period, qh->c_usecs)) | |
791 | goto done; | |
792 | retval = 0; | |
793 | } | |
ba47f66b | 794 | #endif |
1da177e4 LT |
795 | done: |
796 | return retval; | |
797 | } | |
798 | ||
799 | /* "first fit" scheduling policy used the first time through, | |
800 | * or when the previous schedule slot can't be re-used. | |
801 | */ | |
6dbd682b | 802 | static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh) |
1da177e4 | 803 | { |
53bd6a60 | 804 | int status; |
1da177e4 | 805 | unsigned uframe; |
6dbd682b | 806 | __hc32 c_mask; |
1da177e4 | 807 | unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */ |
3807e26d | 808 | struct ehci_qh_hw *hw = qh->hw; |
1da177e4 LT |
809 | |
810 | qh_refresh(ehci, qh); | |
3807e26d | 811 | hw->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
812 | frame = qh->start; |
813 | ||
814 | /* reuse the previous schedule slots, if we can */ | |
815 | if (frame < qh->period) { | |
3807e26d | 816 | uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK); |
1da177e4 LT |
817 | status = check_intr_schedule (ehci, frame, --uframe, |
818 | qh, &c_mask); | |
819 | } else { | |
820 | uframe = 0; | |
821 | c_mask = 0; | |
822 | status = -ENOSPC; | |
823 | } | |
824 | ||
825 | /* else scan the schedule to find a group of slots such that all | |
826 | * uframes have enough periodic bandwidth available. | |
827 | */ | |
828 | if (status) { | |
829 | /* "normal" case, uframing flexible except with splits */ | |
830 | if (qh->period) { | |
68335e81 AS |
831 | int i; |
832 | ||
833 | for (i = qh->period; status && i > 0; --i) { | |
834 | frame = ++ehci->random_frame % qh->period; | |
1da177e4 LT |
835 | for (uframe = 0; uframe < 8; uframe++) { |
836 | status = check_intr_schedule (ehci, | |
837 | frame, uframe, qh, | |
838 | &c_mask); | |
839 | if (status == 0) | |
840 | break; | |
841 | } | |
68335e81 | 842 | } |
1da177e4 LT |
843 | |
844 | /* qh->period == 0 means every uframe */ | |
845 | } else { | |
846 | frame = 0; | |
847 | status = check_intr_schedule (ehci, 0, 0, qh, &c_mask); | |
848 | } | |
849 | if (status) | |
850 | goto done; | |
851 | qh->start = frame; | |
852 | ||
853 | /* reset S-frame and (maybe) C-frame masks */ | |
3807e26d AD |
854 | hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK)); |
855 | hw->hw_info2 |= qh->period | |
6dbd682b SR |
856 | ? cpu_to_hc32(ehci, 1 << uframe) |
857 | : cpu_to_hc32(ehci, QH_SMASK); | |
3807e26d | 858 | hw->hw_info2 |= c_mask; |
1da177e4 LT |
859 | } else |
860 | ehci_dbg (ehci, "reused qh %p schedule\n", qh); | |
861 | ||
862 | /* stuff into the periodic schedule */ | |
b015cb79 | 863 | qh_link_periodic(ehci, qh); |
1da177e4 LT |
864 | done: |
865 | return status; | |
866 | } | |
867 | ||
868 | static int intr_submit ( | |
869 | struct ehci_hcd *ehci, | |
1da177e4 LT |
870 | struct urb *urb, |
871 | struct list_head *qtd_list, | |
55016f10 | 872 | gfp_t mem_flags |
1da177e4 LT |
873 | ) { |
874 | unsigned epnum; | |
875 | unsigned long flags; | |
876 | struct ehci_qh *qh; | |
e9df41c5 | 877 | int status; |
1da177e4 LT |
878 | struct list_head empty; |
879 | ||
880 | /* get endpoint and transfer/schedule data */ | |
e9df41c5 | 881 | epnum = urb->ep->desc.bEndpointAddress; |
1da177e4 LT |
882 | |
883 | spin_lock_irqsave (&ehci->lock, flags); | |
884 | ||
541c7d43 | 885 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 886 | status = -ESHUTDOWN; |
e9df41c5 | 887 | goto done_not_linked; |
8de98402 | 888 | } |
e9df41c5 AS |
889 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); |
890 | if (unlikely(status)) | |
891 | goto done_not_linked; | |
8de98402 | 892 | |
1da177e4 LT |
893 | /* get qh and force any scheduling errors */ |
894 | INIT_LIST_HEAD (&empty); | |
e9df41c5 | 895 | qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv); |
1da177e4 LT |
896 | if (qh == NULL) { |
897 | status = -ENOMEM; | |
898 | goto done; | |
899 | } | |
900 | if (qh->qh_state == QH_STATE_IDLE) { | |
901 | if ((status = qh_schedule (ehci, qh)) != 0) | |
902 | goto done; | |
903 | } | |
904 | ||
905 | /* then queue the urb's tds to the qh */ | |
e9df41c5 | 906 | qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); |
1da177e4 LT |
907 | BUG_ON (qh == NULL); |
908 | ||
909 | /* ... update usbfs periodic stats */ | |
910 | ehci_to_hcd(ehci)->self.bandwidth_int_reqs++; | |
911 | ||
912 | done: | |
e9df41c5 AS |
913 | if (unlikely(status)) |
914 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
915 | done_not_linked: | |
1da177e4 LT |
916 | spin_unlock_irqrestore (&ehci->lock, flags); |
917 | if (status) | |
918 | qtd_list_free (ehci, urb, qtd_list); | |
919 | ||
920 | return status; | |
921 | } | |
922 | ||
923 | /*-------------------------------------------------------------------------*/ | |
924 | ||
925 | /* ehci_iso_stream ops work with both ITD and SITD */ | |
926 | ||
927 | static struct ehci_iso_stream * | |
55016f10 | 928 | iso_stream_alloc (gfp_t mem_flags) |
1da177e4 LT |
929 | { |
930 | struct ehci_iso_stream *stream; | |
931 | ||
7b842b6e | 932 | stream = kzalloc(sizeof *stream, mem_flags); |
1da177e4 | 933 | if (likely (stream != NULL)) { |
1da177e4 LT |
934 | INIT_LIST_HEAD(&stream->td_list); |
935 | INIT_LIST_HEAD(&stream->free_list); | |
936 | stream->next_uframe = -1; | |
937 | stream->refcount = 1; | |
938 | } | |
939 | return stream; | |
940 | } | |
941 | ||
942 | static void | |
943 | iso_stream_init ( | |
944 | struct ehci_hcd *ehci, | |
945 | struct ehci_iso_stream *stream, | |
946 | struct usb_device *dev, | |
947 | int pipe, | |
948 | unsigned interval | |
949 | ) | |
950 | { | |
951 | static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f }; | |
952 | ||
953 | u32 buf1; | |
954 | unsigned epnum, maxp; | |
955 | int is_input; | |
956 | long bandwidth; | |
957 | ||
958 | /* | |
959 | * this might be a "high bandwidth" highspeed endpoint, | |
960 | * as encoded in the ep descriptor's wMaxPacket field | |
961 | */ | |
962 | epnum = usb_pipeendpoint (pipe); | |
963 | is_input = usb_pipein (pipe) ? USB_DIR_IN : 0; | |
964 | maxp = usb_maxpacket(dev, pipe, !is_input); | |
965 | if (is_input) { | |
966 | buf1 = (1 << 11); | |
967 | } else { | |
968 | buf1 = 0; | |
969 | } | |
970 | ||
971 | /* knows about ITD vs SITD */ | |
972 | if (dev->speed == USB_SPEED_HIGH) { | |
973 | unsigned multi = hb_mult(maxp); | |
974 | ||
975 | stream->highspeed = 1; | |
976 | ||
977 | maxp = max_packet(maxp); | |
978 | buf1 |= maxp; | |
979 | maxp *= multi; | |
980 | ||
6dbd682b SR |
981 | stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum); |
982 | stream->buf1 = cpu_to_hc32(ehci, buf1); | |
983 | stream->buf2 = cpu_to_hc32(ehci, multi); | |
1da177e4 LT |
984 | |
985 | /* usbfs wants to report the average usecs per frame tied up | |
986 | * when transfers on this endpoint are scheduled ... | |
987 | */ | |
988 | stream->usecs = HS_USECS_ISO (maxp); | |
989 | bandwidth = stream->usecs * 8; | |
372dd6e8 | 990 | bandwidth /= interval; |
1da177e4 LT |
991 | |
992 | } else { | |
993 | u32 addr; | |
d0384200 | 994 | int think_time; |
469d0229 | 995 | int hs_transfers; |
1da177e4 LT |
996 | |
997 | addr = dev->ttport << 24; | |
998 | if (!ehci_is_TDI(ehci) | |
999 | || (dev->tt->hub != | |
1000 | ehci_to_hcd(ehci)->self.root_hub)) | |
1001 | addr |= dev->tt->hub->devnum << 16; | |
1002 | addr |= epnum << 8; | |
1003 | addr |= dev->devnum; | |
1004 | stream->usecs = HS_USECS_ISO (maxp); | |
d0384200 | 1005 | think_time = dev->tt ? dev->tt->think_time : 0; |
1006 | stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time ( | |
1007 | dev->speed, is_input, 1, maxp)); | |
469d0229 | 1008 | hs_transfers = max (1u, (maxp + 187) / 188); |
1da177e4 LT |
1009 | if (is_input) { |
1010 | u32 tmp; | |
1011 | ||
1012 | addr |= 1 << 31; | |
1013 | stream->c_usecs = stream->usecs; | |
1014 | stream->usecs = HS_USECS_ISO (1); | |
1015 | stream->raw_mask = 1; | |
1016 | ||
469d0229 CL |
1017 | /* c-mask as specified in USB 2.0 11.18.4 3.c */ |
1018 | tmp = (1 << (hs_transfers + 2)) - 1; | |
1019 | stream->raw_mask |= tmp << (8 + 2); | |
1da177e4 | 1020 | } else |
469d0229 | 1021 | stream->raw_mask = smask_out [hs_transfers - 1]; |
1da177e4 | 1022 | bandwidth = stream->usecs + stream->c_usecs; |
372dd6e8 | 1023 | bandwidth /= interval << 3; |
1da177e4 LT |
1024 | |
1025 | /* stream->splits gets created from raw_mask later */ | |
6dbd682b | 1026 | stream->address = cpu_to_hc32(ehci, addr); |
1da177e4 LT |
1027 | } |
1028 | stream->bandwidth = bandwidth; | |
1029 | ||
1030 | stream->udev = dev; | |
1031 | ||
1032 | stream->bEndpointAddress = is_input | epnum; | |
1033 | stream->interval = interval; | |
1034 | stream->maxp = maxp; | |
1035 | } | |
1036 | ||
1037 | static void | |
1038 | iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream) | |
1039 | { | |
1040 | stream->refcount--; | |
1041 | ||
1042 | /* free whenever just a dev->ep reference remains. | |
1043 | * not like a QH -- no persistent state (toggle, halt) | |
1044 | */ | |
1045 | if (stream->refcount == 1) { | |
1da177e4 LT |
1046 | // BUG_ON (!list_empty(&stream->td_list)); |
1047 | ||
1048 | while (!list_empty (&stream->free_list)) { | |
1049 | struct list_head *entry; | |
1050 | ||
1051 | entry = stream->free_list.next; | |
1052 | list_del (entry); | |
1053 | ||
1054 | /* knows about ITD vs SITD */ | |
1055 | if (stream->highspeed) { | |
1056 | struct ehci_itd *itd; | |
1057 | ||
1058 | itd = list_entry (entry, struct ehci_itd, | |
1059 | itd_list); | |
1060 | dma_pool_free (ehci->itd_pool, itd, | |
1061 | itd->itd_dma); | |
1062 | } else { | |
1063 | struct ehci_sitd *sitd; | |
1064 | ||
1065 | sitd = list_entry (entry, struct ehci_sitd, | |
1066 | sitd_list); | |
1067 | dma_pool_free (ehci->sitd_pool, sitd, | |
1068 | sitd->sitd_dma); | |
1069 | } | |
1070 | } | |
1071 | ||
1da177e4 | 1072 | stream->bEndpointAddress &= 0x0f; |
9aa09d2f KW |
1073 | if (stream->ep) |
1074 | stream->ep->hcpriv = NULL; | |
1da177e4 | 1075 | |
1da177e4 LT |
1076 | kfree(stream); |
1077 | } | |
1078 | } | |
1079 | ||
1080 | static inline struct ehci_iso_stream * | |
1081 | iso_stream_get (struct ehci_iso_stream *stream) | |
1082 | { | |
1083 | if (likely (stream != NULL)) | |
1084 | stream->refcount++; | |
1085 | return stream; | |
1086 | } | |
1087 | ||
1088 | static struct ehci_iso_stream * | |
1089 | iso_stream_find (struct ehci_hcd *ehci, struct urb *urb) | |
1090 | { | |
1091 | unsigned epnum; | |
1092 | struct ehci_iso_stream *stream; | |
1093 | struct usb_host_endpoint *ep; | |
1094 | unsigned long flags; | |
1095 | ||
1096 | epnum = usb_pipeendpoint (urb->pipe); | |
1097 | if (usb_pipein(urb->pipe)) | |
1098 | ep = urb->dev->ep_in[epnum]; | |
1099 | else | |
1100 | ep = urb->dev->ep_out[epnum]; | |
1101 | ||
1102 | spin_lock_irqsave (&ehci->lock, flags); | |
1103 | stream = ep->hcpriv; | |
1104 | ||
1105 | if (unlikely (stream == NULL)) { | |
1106 | stream = iso_stream_alloc(GFP_ATOMIC); | |
1107 | if (likely (stream != NULL)) { | |
1108 | /* dev->ep owns the initial refcount */ | |
1109 | ep->hcpriv = stream; | |
1110 | stream->ep = ep; | |
1111 | iso_stream_init(ehci, stream, urb->dev, urb->pipe, | |
1112 | urb->interval); | |
1113 | } | |
1114 | ||
1082f57a CL |
1115 | /* if dev->ep [epnum] is a QH, hw is set */ |
1116 | } else if (unlikely (stream->hw != NULL)) { | |
1da177e4 LT |
1117 | ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n", |
1118 | urb->dev->devpath, epnum, | |
1119 | usb_pipein(urb->pipe) ? "in" : "out"); | |
1120 | stream = NULL; | |
1121 | } | |
1122 | ||
1123 | /* caller guarantees an eventual matching iso_stream_put */ | |
1124 | stream = iso_stream_get (stream); | |
1125 | ||
1126 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1127 | return stream; | |
1128 | } | |
1129 | ||
1130 | /*-------------------------------------------------------------------------*/ | |
1131 | ||
1132 | /* ehci_iso_sched ops can be ITD-only or SITD-only */ | |
1133 | ||
1134 | static struct ehci_iso_sched * | |
55016f10 | 1135 | iso_sched_alloc (unsigned packets, gfp_t mem_flags) |
1da177e4 LT |
1136 | { |
1137 | struct ehci_iso_sched *iso_sched; | |
1138 | int size = sizeof *iso_sched; | |
1139 | ||
1140 | size += packets * sizeof (struct ehci_iso_packet); | |
80b6ca48 | 1141 | iso_sched = kzalloc(size, mem_flags); |
1da177e4 | 1142 | if (likely (iso_sched != NULL)) { |
1da177e4 LT |
1143 | INIT_LIST_HEAD (&iso_sched->td_list); |
1144 | } | |
1145 | return iso_sched; | |
1146 | } | |
1147 | ||
1148 | static inline void | |
6dbd682b SR |
1149 | itd_sched_init( |
1150 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1151 | struct ehci_iso_sched *iso_sched, |
1152 | struct ehci_iso_stream *stream, | |
1153 | struct urb *urb | |
1154 | ) | |
1155 | { | |
1156 | unsigned i; | |
1157 | dma_addr_t dma = urb->transfer_dma; | |
1158 | ||
1159 | /* how many uframes are needed for these transfers */ | |
1160 | iso_sched->span = urb->number_of_packets * stream->interval; | |
1161 | ||
1162 | /* figure out per-uframe itd fields that we'll need later | |
1163 | * when we fit new itds into the schedule. | |
1164 | */ | |
1165 | for (i = 0; i < urb->number_of_packets; i++) { | |
1166 | struct ehci_iso_packet *uframe = &iso_sched->packet [i]; | |
1167 | unsigned length; | |
1168 | dma_addr_t buf; | |
1169 | u32 trans; | |
1170 | ||
1171 | length = urb->iso_frame_desc [i].length; | |
1172 | buf = dma + urb->iso_frame_desc [i].offset; | |
1173 | ||
1174 | trans = EHCI_ISOC_ACTIVE; | |
1175 | trans |= buf & 0x0fff; | |
1176 | if (unlikely (((i + 1) == urb->number_of_packets)) | |
1177 | && !(urb->transfer_flags & URB_NO_INTERRUPT)) | |
1178 | trans |= EHCI_ITD_IOC; | |
1179 | trans |= length << 16; | |
6dbd682b | 1180 | uframe->transaction = cpu_to_hc32(ehci, trans); |
1da177e4 | 1181 | |
77078570 | 1182 | /* might need to cross a buffer page within a uframe */ |
1da177e4 LT |
1183 | uframe->bufp = (buf & ~(u64)0x0fff); |
1184 | buf += length; | |
1185 | if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff)))) | |
1186 | uframe->cross = 1; | |
1187 | } | |
1188 | } | |
1189 | ||
1190 | static void | |
1191 | iso_sched_free ( | |
1192 | struct ehci_iso_stream *stream, | |
1193 | struct ehci_iso_sched *iso_sched | |
1194 | ) | |
1195 | { | |
1196 | if (!iso_sched) | |
1197 | return; | |
1198 | // caller must hold ehci->lock! | |
1199 | list_splice (&iso_sched->td_list, &stream->free_list); | |
1200 | kfree (iso_sched); | |
1201 | } | |
1202 | ||
1203 | static int | |
1204 | itd_urb_transaction ( | |
1205 | struct ehci_iso_stream *stream, | |
1206 | struct ehci_hcd *ehci, | |
1207 | struct urb *urb, | |
55016f10 | 1208 | gfp_t mem_flags |
1da177e4 LT |
1209 | ) |
1210 | { | |
1211 | struct ehci_itd *itd; | |
1212 | dma_addr_t itd_dma; | |
1213 | int i; | |
1214 | unsigned num_itds; | |
1215 | struct ehci_iso_sched *sched; | |
1216 | unsigned long flags; | |
1217 | ||
1218 | sched = iso_sched_alloc (urb->number_of_packets, mem_flags); | |
1219 | if (unlikely (sched == NULL)) | |
1220 | return -ENOMEM; | |
1221 | ||
6dbd682b | 1222 | itd_sched_init(ehci, sched, stream, urb); |
1da177e4 LT |
1223 | |
1224 | if (urb->interval < 8) | |
1225 | num_itds = 1 + (sched->span + 7) / 8; | |
1226 | else | |
1227 | num_itds = urb->number_of_packets; | |
1228 | ||
1229 | /* allocate/init ITDs */ | |
1230 | spin_lock_irqsave (&ehci->lock, flags); | |
1231 | for (i = 0; i < num_itds; i++) { | |
1232 | ||
1233 | /* free_list.next might be cache-hot ... but maybe | |
1234 | * the HC caches it too. avoid that issue for now. | |
1235 | */ | |
1236 | ||
1237 | /* prefer previously-allocated itds */ | |
1238 | if (likely (!list_empty(&stream->free_list))) { | |
1239 | itd = list_entry (stream->free_list.prev, | |
6dbd682b | 1240 | struct ehci_itd, itd_list); |
1da177e4 LT |
1241 | list_del (&itd->itd_list); |
1242 | itd_dma = itd->itd_dma; | |
3d01f0fe | 1243 | } else { |
1da177e4 LT |
1244 | spin_unlock_irqrestore (&ehci->lock, flags); |
1245 | itd = dma_pool_alloc (ehci->itd_pool, mem_flags, | |
1246 | &itd_dma); | |
1247 | spin_lock_irqsave (&ehci->lock, flags); | |
3d01f0fe KW |
1248 | if (!itd) { |
1249 | iso_sched_free(stream, sched); | |
1250 | spin_unlock_irqrestore(&ehci->lock, flags); | |
1251 | return -ENOMEM; | |
1252 | } | |
1da177e4 LT |
1253 | } |
1254 | ||
1da177e4 LT |
1255 | memset (itd, 0, sizeof *itd); |
1256 | itd->itd_dma = itd_dma; | |
1257 | list_add (&itd->itd_list, &sched->td_list); | |
1258 | } | |
1259 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1260 | ||
1261 | /* temporarily store schedule info in hcpriv */ | |
1262 | urb->hcpriv = sched; | |
1263 | urb->error_count = 0; | |
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | /*-------------------------------------------------------------------------*/ | |
1268 | ||
1269 | static inline int | |
1270 | itd_slot_ok ( | |
1271 | struct ehci_hcd *ehci, | |
1272 | u32 mod, | |
1273 | u32 uframe, | |
1274 | u8 usecs, | |
1275 | u32 period | |
1276 | ) | |
1277 | { | |
1278 | uframe %= period; | |
1279 | do { | |
cc62a7eb | 1280 | /* can't commit more than uframe_periodic_max usec */ |
1da177e4 | 1281 | if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7) |
cc62a7eb | 1282 | > (ehci->uframe_periodic_max - usecs)) |
1da177e4 LT |
1283 | return 0; |
1284 | ||
1285 | /* we know urb->interval is 2^N uframes */ | |
1286 | uframe += period; | |
1287 | } while (uframe < mod); | |
1288 | return 1; | |
1289 | } | |
1290 | ||
1291 | static inline int | |
1292 | sitd_slot_ok ( | |
1293 | struct ehci_hcd *ehci, | |
1294 | u32 mod, | |
1295 | struct ehci_iso_stream *stream, | |
1296 | u32 uframe, | |
1297 | struct ehci_iso_sched *sched, | |
1298 | u32 period_uframes | |
1299 | ) | |
1300 | { | |
1301 | u32 mask, tmp; | |
1302 | u32 frame, uf; | |
1303 | ||
1304 | mask = stream->raw_mask << (uframe & 7); | |
1305 | ||
1306 | /* for IN, don't wrap CSPLIT into the next frame */ | |
1307 | if (mask & ~0xffff) | |
1308 | return 0; | |
1309 | ||
65b8e5cb AS |
1310 | /* check bandwidth */ |
1311 | uframe %= period_uframes; | |
1312 | frame = uframe >> 3; | |
1313 | ||
1314 | #ifdef CONFIG_USB_EHCI_TT_NEWSCHED | |
1315 | /* The tt's fullspeed bus bandwidth must be available. | |
1316 | * tt_available scheduling guarantees 10+% for control/bulk. | |
1317 | */ | |
1318 | uf = uframe & 7; | |
1319 | if (!tt_available(ehci, period_uframes >> 3, | |
1320 | stream->udev, frame, uf, stream->tt_usecs)) | |
1321 | return 0; | |
1322 | #else | |
1323 | /* tt must be idle for start(s), any gap, and csplit. | |
1324 | * assume scheduling slop leaves 10+% for control/bulk. | |
1325 | */ | |
1326 | if (!tt_no_collision(ehci, period_uframes >> 3, | |
1327 | stream->udev, frame, mask)) | |
1328 | return 0; | |
1329 | #endif | |
1330 | ||
1da177e4 LT |
1331 | /* this multi-pass logic is simple, but performance may |
1332 | * suffer when the schedule data isn't cached. | |
1333 | */ | |
1da177e4 LT |
1334 | do { |
1335 | u32 max_used; | |
1336 | ||
1337 | frame = uframe >> 3; | |
1338 | uf = uframe & 7; | |
1339 | ||
1da177e4 | 1340 | /* check starts (OUT uses more than one) */ |
cc62a7eb | 1341 | max_used = ehci->uframe_periodic_max - stream->usecs; |
1da177e4 LT |
1342 | for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) { |
1343 | if (periodic_usecs (ehci, frame, uf) > max_used) | |
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | /* for IN, check CSPLIT */ | |
1348 | if (stream->c_usecs) { | |
0c734622 | 1349 | uf = uframe & 7; |
cc62a7eb | 1350 | max_used = ehci->uframe_periodic_max - stream->c_usecs; |
1da177e4 LT |
1351 | do { |
1352 | tmp = 1 << uf; | |
1353 | tmp <<= 8; | |
1354 | if ((stream->raw_mask & tmp) == 0) | |
1355 | continue; | |
1356 | if (periodic_usecs (ehci, frame, uf) | |
1357 | > max_used) | |
1358 | return 0; | |
1359 | } while (++uf < 8); | |
1360 | } | |
1361 | ||
1362 | /* we know urb->interval is 2^N uframes */ | |
1363 | uframe += period_uframes; | |
1364 | } while (uframe < mod); | |
1365 | ||
6dbd682b | 1366 | stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7)); |
1da177e4 LT |
1367 | return 1; |
1368 | } | |
1369 | ||
1370 | /* | |
1371 | * This scheduler plans almost as far into the future as it has actual | |
1372 | * periodic schedule slots. (Affected by TUNE_FLS, which defaults to | |
1373 | * "as small as possible" to be cache-friendlier.) That limits the size | |
1374 | * transfers you can stream reliably; avoid more than 64 msec per urb. | |
1375 | * Also avoid queue depths of less than ehci's worst irq latency (affected | |
1376 | * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter, | |
1377 | * and other factors); or more than about 230 msec total (for portability, | |
1378 | * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler! | |
1379 | */ | |
1380 | ||
d7e055f1 | 1381 | #define SCHEDULE_SLOP 80 /* microframes */ |
1da177e4 LT |
1382 | |
1383 | static int | |
1384 | iso_stream_schedule ( | |
1385 | struct ehci_hcd *ehci, | |
1386 | struct urb *urb, | |
1387 | struct ehci_iso_stream *stream | |
1388 | ) | |
1389 | { | |
ffda0803 | 1390 | u32 now, next, start, period, span; |
1da177e4 LT |
1391 | int status; |
1392 | unsigned mod = ehci->periodic_size << 3; | |
1393 | struct ehci_iso_sched *sched = urb->hcpriv; | |
1394 | ||
ffda0803 AS |
1395 | period = urb->interval; |
1396 | span = sched->span; | |
1397 | if (!stream->highspeed) { | |
1398 | period <<= 3; | |
1399 | span <<= 3; | |
1400 | } | |
1401 | ||
1402 | if (span > mod - SCHEDULE_SLOP) { | |
1da177e4 LT |
1403 | ehci_dbg (ehci, "iso request %p too long\n", urb); |
1404 | status = -EFBIG; | |
1405 | goto fail; | |
1406 | } | |
1407 | ||
68aa95d5 | 1408 | now = ehci_read_frame_index(ehci) & (mod - 1); |
1da177e4 | 1409 | |
b40e43fc AS |
1410 | /* Typical case: reuse current schedule, stream is still active. |
1411 | * Hopefully there are no gaps from the host falling behind | |
1412 | * (irq delays etc), but if there are we'll take the next | |
1413 | * slot in the schedule, implicitly assuming URB_ISO_ASAP. | |
1da177e4 LT |
1414 | */ |
1415 | if (likely (!list_empty (&stream->td_list))) { | |
1fb2e055 | 1416 | u32 excess; |
dccd574c SS |
1417 | |
1418 | /* For high speed devices, allow scheduling within the | |
ae68a83b AS |
1419 | * isochronous scheduling threshold. For full speed devices |
1420 | * and Intel PCI-based controllers, don't (work around for | |
1421 | * Intel ICH9 bug). | |
dccd574c | 1422 | */ |
ae68a83b | 1423 | if (!stream->highspeed && ehci->fs_i_thresh) |
dccd574c SS |
1424 | next = now + ehci->i_thresh; |
1425 | else | |
1426 | next = now; | |
b40e43fc | 1427 | |
1fb2e055 AS |
1428 | /* Fell behind (by up to twice the slop amount)? |
1429 | * We decide based on the time of the last currently-scheduled | |
1430 | * slot, not the time of the next available slot. | |
1431 | */ | |
1432 | excess = (stream->next_uframe - period - next) & (mod - 1); | |
1433 | if (excess >= mod - 2 * SCHEDULE_SLOP) | |
1434 | start = next + excess - mod + period * | |
1435 | DIV_ROUND_UP(mod - excess, period); | |
1436 | else | |
1437 | start = next + excess + period; | |
1438 | if (start - now >= mod) { | |
1439 | ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n", | |
1440 | urb, start - now - period, period, | |
1441 | mod); | |
b40e43fc AS |
1442 | status = -EFBIG; |
1443 | goto fail; | |
1444 | } | |
1da177e4 LT |
1445 | } |
1446 | ||
1447 | /* need to schedule; when's the next (u)frame we could start? | |
1448 | * this is bigger than ehci->i_thresh allows; scheduling itself | |
1449 | * isn't free, the slop should handle reasonably slow cpus. it | |
1450 | * can also help high bandwidth if the dma and irq loads don't | |
1451 | * jump until after the queue is primed. | |
1452 | */ | |
1fb2e055 | 1453 | else { |
e3420901 | 1454 | int done = 0; |
1fb2e055 AS |
1455 | start = SCHEDULE_SLOP + (now & ~0x07); |
1456 | ||
1457 | /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */ | |
1458 | ||
811c926c TP |
1459 | /* find a uframe slot with enough bandwidth. |
1460 | * Early uframes are more precious because full-speed | |
1461 | * iso IN transfers can't use late uframes, | |
1462 | * and therefore they should be allocated last. | |
1463 | */ | |
1464 | next = start; | |
1465 | start += period; | |
1466 | do { | |
1467 | start--; | |
1fb2e055 AS |
1468 | /* check schedule: enough space? */ |
1469 | if (stream->highspeed) { | |
1470 | if (itd_slot_ok(ehci, mod, start, | |
1471 | stream->usecs, period)) | |
e3420901 | 1472 | done = 1; |
1fb2e055 AS |
1473 | } else { |
1474 | if ((start % 8) >= 6) | |
1475 | continue; | |
1476 | if (sitd_slot_ok(ehci, mod, stream, | |
1477 | start, sched, period)) | |
e3420901 | 1478 | done = 1; |
1fb2e055 | 1479 | } |
e3420901 | 1480 | } while (start > next && !done); |
1da177e4 | 1481 | |
1fb2e055 | 1482 | /* no room in the schedule */ |
e3420901 | 1483 | if (!done) { |
1fb2e055 AS |
1484 | ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n", |
1485 | urb, now, now + mod); | |
1486 | status = -ENOSPC; | |
1487 | goto fail; | |
1da177e4 LT |
1488 | } |
1489 | } | |
1490 | ||
1fb2e055 AS |
1491 | /* Tried to schedule too far into the future? */ |
1492 | if (unlikely(start - now + span - period | |
1493 | >= mod - 2 * SCHEDULE_SLOP)) { | |
1494 | ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n", | |
1495 | urb, start - now, span - period, | |
1496 | mod - 2 * SCHEDULE_SLOP); | |
1497 | status = -EFBIG; | |
1498 | goto fail; | |
1499 | } | |
1da177e4 | 1500 | |
1fb2e055 | 1501 | stream->next_uframe = start & (mod - 1); |
1da177e4 | 1502 | |
1da177e4 LT |
1503 | /* report high speed start in uframes; full speed, in frames */ |
1504 | urb->start_frame = stream->next_uframe; | |
1505 | if (!stream->highspeed) | |
1506 | urb->start_frame >>= 3; | |
1507 | return 0; | |
1fb2e055 AS |
1508 | |
1509 | fail: | |
1510 | iso_sched_free(stream, sched); | |
1511 | urb->hcpriv = NULL; | |
1512 | return status; | |
1da177e4 LT |
1513 | } |
1514 | ||
1515 | /*-------------------------------------------------------------------------*/ | |
1516 | ||
1517 | static inline void | |
6dbd682b SR |
1518 | itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream, |
1519 | struct ehci_itd *itd) | |
1da177e4 LT |
1520 | { |
1521 | int i; | |
1522 | ||
77078570 | 1523 | /* it's been recently zeroed */ |
6dbd682b | 1524 | itd->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
1525 | itd->hw_bufp [0] = stream->buf0; |
1526 | itd->hw_bufp [1] = stream->buf1; | |
1527 | itd->hw_bufp [2] = stream->buf2; | |
1528 | ||
1529 | for (i = 0; i < 8; i++) | |
1530 | itd->index[i] = -1; | |
1531 | ||
1532 | /* All other fields are filled when scheduling */ | |
1533 | } | |
1534 | ||
1535 | static inline void | |
6dbd682b SR |
1536 | itd_patch( |
1537 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1538 | struct ehci_itd *itd, |
1539 | struct ehci_iso_sched *iso_sched, | |
1540 | unsigned index, | |
77078570 | 1541 | u16 uframe |
1da177e4 LT |
1542 | ) |
1543 | { | |
1544 | struct ehci_iso_packet *uf = &iso_sched->packet [index]; | |
1545 | unsigned pg = itd->pg; | |
1546 | ||
1547 | // BUG_ON (pg == 6 && uf->cross); | |
1548 | ||
1549 | uframe &= 0x07; | |
1550 | itd->index [uframe] = index; | |
1551 | ||
6dbd682b SR |
1552 | itd->hw_transaction[uframe] = uf->transaction; |
1553 | itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12); | |
1554 | itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0); | |
1555 | itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32)); | |
1da177e4 LT |
1556 | |
1557 | /* iso_frame_desc[].offset must be strictly increasing */ | |
77078570 | 1558 | if (unlikely (uf->cross)) { |
1da177e4 | 1559 | u64 bufp = uf->bufp + 4096; |
6dbd682b | 1560 | |
1da177e4 | 1561 | itd->pg = ++pg; |
6dbd682b SR |
1562 | itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0); |
1563 | itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32)); | |
1da177e4 LT |
1564 | } |
1565 | } | |
1566 | ||
1567 | static inline void | |
1568 | itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd) | |
1569 | { | |
92bc3648 CL |
1570 | union ehci_shadow *prev = &ehci->pshadow[frame]; |
1571 | __hc32 *hw_p = &ehci->periodic[frame]; | |
1572 | union ehci_shadow here = *prev; | |
1573 | __hc32 type = 0; | |
1574 | ||
1575 | /* skip any iso nodes which might belong to previous microframes */ | |
1576 | while (here.ptr) { | |
1577 | type = Q_NEXT_TYPE(ehci, *hw_p); | |
1578 | if (type == cpu_to_hc32(ehci, Q_TYPE_QH)) | |
1579 | break; | |
1580 | prev = periodic_next_shadow(ehci, prev, type); | |
1581 | hw_p = shadow_next_periodic(ehci, &here, type); | |
1582 | here = *prev; | |
1583 | } | |
1584 | ||
1585 | itd->itd_next = here; | |
1586 | itd->hw_next = *hw_p; | |
1587 | prev->itd = itd; | |
1da177e4 LT |
1588 | itd->frame = frame; |
1589 | wmb (); | |
92bc3648 | 1590 | *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD); |
1da177e4 LT |
1591 | } |
1592 | ||
1593 | /* fit urb's itds into the selected schedule slot; activate as needed */ | |
b015cb79 | 1594 | static void itd_link_urb( |
1da177e4 LT |
1595 | struct ehci_hcd *ehci, |
1596 | struct urb *urb, | |
1597 | unsigned mod, | |
1598 | struct ehci_iso_stream *stream | |
1599 | ) | |
1600 | { | |
77078570 | 1601 | int packet; |
1da177e4 LT |
1602 | unsigned next_uframe, uframe, frame; |
1603 | struct ehci_iso_sched *iso_sched = urb->hcpriv; | |
1604 | struct ehci_itd *itd; | |
1605 | ||
bccbefaa | 1606 | next_uframe = stream->next_uframe & (mod - 1); |
1da177e4 LT |
1607 | |
1608 | if (unlikely (list_empty(&stream->td_list))) { | |
1609 | ehci_to_hcd(ehci)->self.bandwidth_allocated | |
1610 | += stream->bandwidth; | |
1611 | ehci_vdbg (ehci, | |
1612 | "schedule devp %s ep%d%s-iso period %d start %d.%d\n", | |
1613 | urb->dev->devpath, stream->bEndpointAddress & 0x0f, | |
1614 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out", | |
1615 | urb->interval, | |
1616 | next_uframe >> 3, next_uframe & 0x7); | |
1da177e4 | 1617 | } |
05570297 AH |
1618 | |
1619 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | |
ad93562b AX |
1620 | if (ehci->amd_pll_fix == 1) |
1621 | usb_amd_quirk_pll_disable(); | |
05570297 AH |
1622 | } |
1623 | ||
1da177e4 LT |
1624 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; |
1625 | ||
1626 | /* fill iTDs uframe by uframe */ | |
1627 | for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) { | |
1628 | if (itd == NULL) { | |
1629 | /* ASSERT: we have all necessary itds */ | |
1630 | // BUG_ON (list_empty (&iso_sched->td_list)); | |
1631 | ||
1632 | /* ASSERT: no itds for this endpoint in this uframe */ | |
1633 | ||
1634 | itd = list_entry (iso_sched->td_list.next, | |
1635 | struct ehci_itd, itd_list); | |
1636 | list_move_tail (&itd->itd_list, &stream->td_list); | |
1637 | itd->stream = iso_stream_get (stream); | |
508db8c9 | 1638 | itd->urb = urb; |
6dbd682b | 1639 | itd_init (ehci, stream, itd); |
1da177e4 LT |
1640 | } |
1641 | ||
1642 | uframe = next_uframe & 0x07; | |
1643 | frame = next_uframe >> 3; | |
1644 | ||
6dbd682b | 1645 | itd_patch(ehci, itd, iso_sched, packet, uframe); |
1da177e4 LT |
1646 | |
1647 | next_uframe += stream->interval; | |
bccbefaa | 1648 | next_uframe &= mod - 1; |
1da177e4 LT |
1649 | packet++; |
1650 | ||
1651 | /* link completed itds into the schedule */ | |
1652 | if (((next_uframe >> 3) != frame) | |
1653 | || packet == urb->number_of_packets) { | |
bccbefaa | 1654 | itd_link(ehci, frame & (ehci->periodic_size - 1), itd); |
1da177e4 LT |
1655 | itd = NULL; |
1656 | } | |
1657 | } | |
1658 | stream->next_uframe = next_uframe; | |
1659 | ||
1660 | /* don't need that schedule data any more */ | |
1661 | iso_sched_free (stream, iso_sched); | |
1662 | urb->hcpriv = NULL; | |
1663 | ||
1664 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
b015cb79 | 1665 | enable_periodic(ehci); |
1da177e4 LT |
1666 | } |
1667 | ||
1668 | #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR) | |
1669 | ||
30bf54e6 DB |
1670 | /* Process and recycle a completed ITD. Return true iff its urb completed, |
1671 | * and hence its completion callback probably added things to the hardware | |
1672 | * schedule. | |
1673 | * | |
1674 | * Note that we carefully avoid recycling this descriptor until after any | |
1675 | * completion callback runs, so that it won't be reused quickly. That is, | |
1676 | * assuming (a) no more than two urbs per frame on this endpoint, and also | |
1677 | * (b) only this endpoint's completions submit URBs. It seems some silicon | |
1678 | * corrupts things if you reuse completed descriptors very quickly... | |
1679 | */ | |
1da177e4 LT |
1680 | static unsigned |
1681 | itd_complete ( | |
1682 | struct ehci_hcd *ehci, | |
7d12e780 | 1683 | struct ehci_itd *itd |
1da177e4 LT |
1684 | ) { |
1685 | struct urb *urb = itd->urb; | |
1686 | struct usb_iso_packet_descriptor *desc; | |
1687 | u32 t; | |
1688 | unsigned uframe; | |
1689 | int urb_index = -1; | |
1690 | struct ehci_iso_stream *stream = itd->stream; | |
1691 | struct usb_device *dev; | |
30bf54e6 | 1692 | unsigned retval = false; |
1da177e4 LT |
1693 | |
1694 | /* for each uframe with a packet */ | |
1695 | for (uframe = 0; uframe < 8; uframe++) { | |
1696 | if (likely (itd->index[uframe] == -1)) | |
1697 | continue; | |
1698 | urb_index = itd->index[uframe]; | |
1699 | desc = &urb->iso_frame_desc [urb_index]; | |
1700 | ||
6dbd682b | 1701 | t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]); |
1da177e4 | 1702 | itd->hw_transaction [uframe] = 0; |
1da177e4 LT |
1703 | |
1704 | /* report transfer status */ | |
1705 | if (unlikely (t & ISO_ERRS)) { | |
1706 | urb->error_count++; | |
1707 | if (t & EHCI_ISOC_BUF_ERR) | |
1708 | desc->status = usb_pipein (urb->pipe) | |
1709 | ? -ENOSR /* hc couldn't read */ | |
1710 | : -ECOMM; /* hc couldn't write */ | |
1711 | else if (t & EHCI_ISOC_BABBLE) | |
1712 | desc->status = -EOVERFLOW; | |
1713 | else /* (t & EHCI_ISOC_XACTERR) */ | |
1714 | desc->status = -EPROTO; | |
1715 | ||
1716 | /* HC need not update length with this error */ | |
ec6d67e3 AS |
1717 | if (!(t & EHCI_ISOC_BABBLE)) { |
1718 | desc->actual_length = EHCI_ITD_LENGTH(t); | |
1719 | urb->actual_length += desc->actual_length; | |
1720 | } | |
1da177e4 LT |
1721 | } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) { |
1722 | desc->status = 0; | |
ec6d67e3 AS |
1723 | desc->actual_length = EHCI_ITD_LENGTH(t); |
1724 | urb->actual_length += desc->actual_length; | |
b40e43fc AS |
1725 | } else { |
1726 | /* URB was too late */ | |
1727 | desc->status = -EXDEV; | |
1da177e4 LT |
1728 | } |
1729 | } | |
1730 | ||
1da177e4 LT |
1731 | /* handle completion now? */ |
1732 | if (likely ((urb_index + 1) != urb->number_of_packets)) | |
30bf54e6 | 1733 | goto done; |
1da177e4 LT |
1734 | |
1735 | /* ASSERT: it's really the last itd for this urb | |
1736 | list_for_each_entry (itd, &stream->td_list, itd_list) | |
1737 | BUG_ON (itd->urb == urb); | |
1738 | */ | |
1739 | ||
aa16ca30 | 1740 | /* give urb back to the driver; completion often (re)submits */ |
6a8e87b2 | 1741 | dev = urb->dev; |
14c04c0f | 1742 | ehci_urb_done(ehci, urb, 0); |
30bf54e6 | 1743 | retval = true; |
1da177e4 | 1744 | urb = NULL; |
b015cb79 | 1745 | disable_periodic(ehci); |
1da177e4 LT |
1746 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
1747 | ||
05570297 | 1748 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { |
ad93562b AX |
1749 | if (ehci->amd_pll_fix == 1) |
1750 | usb_amd_quirk_pll_enable(); | |
05570297 AH |
1751 | } |
1752 | ||
508db8c9 | 1753 | if (unlikely(list_is_singular(&stream->td_list))) { |
1da177e4 LT |
1754 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
1755 | -= stream->bandwidth; | |
1756 | ehci_vdbg (ehci, | |
1757 | "deschedule devp %s ep%d%s-iso\n", | |
1758 | dev->devpath, stream->bEndpointAddress & 0x0f, | |
1759 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out"); | |
1760 | } | |
1761 | iso_stream_put (ehci, stream); | |
9aa09d2f | 1762 | |
30bf54e6 | 1763 | done: |
30bf54e6 | 1764 | itd->urb = NULL; |
9aa09d2f KW |
1765 | if (ehci->clock_frame != itd->frame || itd->index[7] != -1) { |
1766 | /* OK to recycle this ITD now. */ | |
1767 | itd->stream = NULL; | |
1768 | list_move(&itd->itd_list, &stream->free_list); | |
1769 | iso_stream_put(ehci, stream); | |
1770 | } else { | |
1771 | /* HW might remember this ITD, so we can't recycle it yet. | |
1772 | * Move it to a safe place until a new frame starts. | |
1773 | */ | |
1774 | list_move(&itd->itd_list, &ehci->cached_itd_list); | |
1775 | if (stream->refcount == 2) { | |
1776 | /* If iso_stream_put() were called here, stream | |
1777 | * would be freed. Instead, just prevent reuse. | |
1778 | */ | |
1779 | stream->ep->hcpriv = NULL; | |
1780 | stream->ep = NULL; | |
1781 | } | |
1782 | } | |
30bf54e6 | 1783 | return retval; |
1da177e4 LT |
1784 | } |
1785 | ||
1786 | /*-------------------------------------------------------------------------*/ | |
1787 | ||
5db539e4 | 1788 | static int itd_submit (struct ehci_hcd *ehci, struct urb *urb, |
55016f10 | 1789 | gfp_t mem_flags) |
1da177e4 LT |
1790 | { |
1791 | int status = -EINVAL; | |
1792 | unsigned long flags; | |
1793 | struct ehci_iso_stream *stream; | |
1794 | ||
1795 | /* Get iso_stream head */ | |
1796 | stream = iso_stream_find (ehci, urb); | |
1797 | if (unlikely (stream == NULL)) { | |
1798 | ehci_dbg (ehci, "can't get iso stream\n"); | |
1799 | return -ENOMEM; | |
1800 | } | |
1801 | if (unlikely (urb->interval != stream->interval)) { | |
1802 | ehci_dbg (ehci, "can't change iso interval %d --> %d\n", | |
1803 | stream->interval, urb->interval); | |
1804 | goto done; | |
1805 | } | |
1806 | ||
1807 | #ifdef EHCI_URB_TRACE | |
1808 | ehci_dbg (ehci, | |
1809 | "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n", | |
441b62c1 | 1810 | __func__, urb->dev->devpath, urb, |
1da177e4 LT |
1811 | usb_pipeendpoint (urb->pipe), |
1812 | usb_pipein (urb->pipe) ? "in" : "out", | |
1813 | urb->transfer_buffer_length, | |
1814 | urb->number_of_packets, urb->interval, | |
1815 | stream); | |
1816 | #endif | |
1817 | ||
1818 | /* allocate ITDs w/o locking anything */ | |
1819 | status = itd_urb_transaction (stream, ehci, urb, mem_flags); | |
1820 | if (unlikely (status < 0)) { | |
1821 | ehci_dbg (ehci, "can't init itds\n"); | |
1822 | goto done; | |
1823 | } | |
1824 | ||
1825 | /* schedule ... need to lock */ | |
1826 | spin_lock_irqsave (&ehci->lock, flags); | |
541c7d43 | 1827 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 1828 | status = -ESHUTDOWN; |
e9df41c5 AS |
1829 | goto done_not_linked; |
1830 | } | |
1831 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); | |
1832 | if (unlikely(status)) | |
1833 | goto done_not_linked; | |
1834 | status = iso_stream_schedule(ehci, urb, stream); | |
53bd6a60 | 1835 | if (likely (status == 0)) |
1da177e4 | 1836 | itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream); |
e9df41c5 AS |
1837 | else |
1838 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
1839 | done_not_linked: | |
1da177e4 LT |
1840 | spin_unlock_irqrestore (&ehci->lock, flags); |
1841 | ||
1842 | done: | |
1843 | if (unlikely (status < 0)) | |
1844 | iso_stream_put (ehci, stream); | |
1845 | return status; | |
1846 | } | |
1847 | ||
1da177e4 LT |
1848 | /*-------------------------------------------------------------------------*/ |
1849 | ||
1850 | /* | |
1851 | * "Split ISO TDs" ... used for USB 1.1 devices going through the | |
1852 | * TTs in USB 2.0 hubs. These need microframe scheduling. | |
1853 | */ | |
1854 | ||
1855 | static inline void | |
6dbd682b SR |
1856 | sitd_sched_init( |
1857 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1858 | struct ehci_iso_sched *iso_sched, |
1859 | struct ehci_iso_stream *stream, | |
1860 | struct urb *urb | |
1861 | ) | |
1862 | { | |
1863 | unsigned i; | |
1864 | dma_addr_t dma = urb->transfer_dma; | |
1865 | ||
1866 | /* how many frames are needed for these transfers */ | |
1867 | iso_sched->span = urb->number_of_packets * stream->interval; | |
1868 | ||
1869 | /* figure out per-frame sitd fields that we'll need later | |
1870 | * when we fit new sitds into the schedule. | |
1871 | */ | |
1872 | for (i = 0; i < urb->number_of_packets; i++) { | |
1873 | struct ehci_iso_packet *packet = &iso_sched->packet [i]; | |
1874 | unsigned length; | |
1875 | dma_addr_t buf; | |
1876 | u32 trans; | |
1877 | ||
1878 | length = urb->iso_frame_desc [i].length & 0x03ff; | |
1879 | buf = dma + urb->iso_frame_desc [i].offset; | |
1880 | ||
1881 | trans = SITD_STS_ACTIVE; | |
1882 | if (((i + 1) == urb->number_of_packets) | |
1883 | && !(urb->transfer_flags & URB_NO_INTERRUPT)) | |
1884 | trans |= SITD_IOC; | |
1885 | trans |= length << 16; | |
6dbd682b | 1886 | packet->transaction = cpu_to_hc32(ehci, trans); |
1da177e4 LT |
1887 | |
1888 | /* might need to cross a buffer page within a td */ | |
1889 | packet->bufp = buf; | |
1890 | packet->buf1 = (buf + length) & ~0x0fff; | |
1891 | if (packet->buf1 != (buf & ~(u64)0x0fff)) | |
1892 | packet->cross = 1; | |
1893 | ||
53bd6a60 | 1894 | /* OUT uses multiple start-splits */ |
1da177e4 LT |
1895 | if (stream->bEndpointAddress & USB_DIR_IN) |
1896 | continue; | |
1897 | length = (length + 187) / 188; | |
1898 | if (length > 1) /* BEGIN vs ALL */ | |
1899 | length |= 1 << 3; | |
1900 | packet->buf1 |= length; | |
1901 | } | |
1902 | } | |
1903 | ||
1904 | static int | |
1905 | sitd_urb_transaction ( | |
1906 | struct ehci_iso_stream *stream, | |
1907 | struct ehci_hcd *ehci, | |
1908 | struct urb *urb, | |
55016f10 | 1909 | gfp_t mem_flags |
1da177e4 LT |
1910 | ) |
1911 | { | |
1912 | struct ehci_sitd *sitd; | |
1913 | dma_addr_t sitd_dma; | |
1914 | int i; | |
1915 | struct ehci_iso_sched *iso_sched; | |
1916 | unsigned long flags; | |
1917 | ||
1918 | iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags); | |
1919 | if (iso_sched == NULL) | |
1920 | return -ENOMEM; | |
1921 | ||
6dbd682b | 1922 | sitd_sched_init(ehci, iso_sched, stream, urb); |
1da177e4 LT |
1923 | |
1924 | /* allocate/init sITDs */ | |
1925 | spin_lock_irqsave (&ehci->lock, flags); | |
1926 | for (i = 0; i < urb->number_of_packets; i++) { | |
1927 | ||
1928 | /* NOTE: for now, we don't try to handle wraparound cases | |
1929 | * for IN (using sitd->hw_backpointer, like a FSTN), which | |
1930 | * means we never need two sitds for full speed packets. | |
1931 | */ | |
1932 | ||
1933 | /* free_list.next might be cache-hot ... but maybe | |
1934 | * the HC caches it too. avoid that issue for now. | |
1935 | */ | |
1936 | ||
1937 | /* prefer previously-allocated sitds */ | |
1938 | if (!list_empty(&stream->free_list)) { | |
1939 | sitd = list_entry (stream->free_list.prev, | |
1940 | struct ehci_sitd, sitd_list); | |
1941 | list_del (&sitd->sitd_list); | |
1942 | sitd_dma = sitd->sitd_dma; | |
3d01f0fe | 1943 | } else { |
1da177e4 LT |
1944 | spin_unlock_irqrestore (&ehci->lock, flags); |
1945 | sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags, | |
1946 | &sitd_dma); | |
1947 | spin_lock_irqsave (&ehci->lock, flags); | |
3d01f0fe KW |
1948 | if (!sitd) { |
1949 | iso_sched_free(stream, iso_sched); | |
1950 | spin_unlock_irqrestore(&ehci->lock, flags); | |
1951 | return -ENOMEM; | |
1952 | } | |
1da177e4 LT |
1953 | } |
1954 | ||
1da177e4 LT |
1955 | memset (sitd, 0, sizeof *sitd); |
1956 | sitd->sitd_dma = sitd_dma; | |
1957 | list_add (&sitd->sitd_list, &iso_sched->td_list); | |
1958 | } | |
1959 | ||
1960 | /* temporarily store schedule info in hcpriv */ | |
1961 | urb->hcpriv = iso_sched; | |
1962 | urb->error_count = 0; | |
1963 | ||
1964 | spin_unlock_irqrestore (&ehci->lock, flags); | |
1965 | return 0; | |
1966 | } | |
1967 | ||
1968 | /*-------------------------------------------------------------------------*/ | |
1969 | ||
1970 | static inline void | |
6dbd682b SR |
1971 | sitd_patch( |
1972 | struct ehci_hcd *ehci, | |
1da177e4 LT |
1973 | struct ehci_iso_stream *stream, |
1974 | struct ehci_sitd *sitd, | |
1975 | struct ehci_iso_sched *iso_sched, | |
1976 | unsigned index | |
1977 | ) | |
1978 | { | |
1979 | struct ehci_iso_packet *uf = &iso_sched->packet [index]; | |
1980 | u64 bufp = uf->bufp; | |
1981 | ||
6dbd682b | 1982 | sitd->hw_next = EHCI_LIST_END(ehci); |
1da177e4 LT |
1983 | sitd->hw_fullspeed_ep = stream->address; |
1984 | sitd->hw_uframe = stream->splits; | |
1985 | sitd->hw_results = uf->transaction; | |
6dbd682b | 1986 | sitd->hw_backpointer = EHCI_LIST_END(ehci); |
1da177e4 LT |
1987 | |
1988 | bufp = uf->bufp; | |
6dbd682b SR |
1989 | sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp); |
1990 | sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32); | |
1da177e4 | 1991 | |
6dbd682b | 1992 | sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1); |
1da177e4 LT |
1993 | if (uf->cross) |
1994 | bufp += 4096; | |
6dbd682b | 1995 | sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32); |
1da177e4 LT |
1996 | sitd->index = index; |
1997 | } | |
1998 | ||
1999 | static inline void | |
2000 | sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd) | |
2001 | { | |
2002 | /* note: sitd ordering could matter (CSPLIT then SSPLIT) */ | |
2003 | sitd->sitd_next = ehci->pshadow [frame]; | |
2004 | sitd->hw_next = ehci->periodic [frame]; | |
2005 | ehci->pshadow [frame].sitd = sitd; | |
2006 | sitd->frame = frame; | |
2007 | wmb (); | |
6dbd682b | 2008 | ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD); |
1da177e4 LT |
2009 | } |
2010 | ||
2011 | /* fit urb's sitds into the selected schedule slot; activate as needed */ | |
b015cb79 | 2012 | static void sitd_link_urb( |
1da177e4 LT |
2013 | struct ehci_hcd *ehci, |
2014 | struct urb *urb, | |
2015 | unsigned mod, | |
2016 | struct ehci_iso_stream *stream | |
2017 | ) | |
2018 | { | |
2019 | int packet; | |
2020 | unsigned next_uframe; | |
2021 | struct ehci_iso_sched *sched = urb->hcpriv; | |
2022 | struct ehci_sitd *sitd; | |
2023 | ||
2024 | next_uframe = stream->next_uframe; | |
2025 | ||
2026 | if (list_empty(&stream->td_list)) { | |
2027 | /* usbfs ignores TT bandwidth */ | |
2028 | ehci_to_hcd(ehci)->self.bandwidth_allocated | |
2029 | += stream->bandwidth; | |
2030 | ehci_vdbg (ehci, | |
2031 | "sched devp %s ep%d%s-iso [%d] %dms/%04x\n", | |
2032 | urb->dev->devpath, stream->bEndpointAddress & 0x0f, | |
2033 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out", | |
bccbefaa | 2034 | (next_uframe >> 3) & (ehci->periodic_size - 1), |
6dbd682b | 2035 | stream->interval, hc32_to_cpu(ehci, stream->splits)); |
1da177e4 | 2036 | } |
05570297 AH |
2037 | |
2038 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { | |
ad93562b AX |
2039 | if (ehci->amd_pll_fix == 1) |
2040 | usb_amd_quirk_pll_disable(); | |
05570297 AH |
2041 | } |
2042 | ||
1da177e4 LT |
2043 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; |
2044 | ||
2045 | /* fill sITDs frame by frame */ | |
2046 | for (packet = 0, sitd = NULL; | |
2047 | packet < urb->number_of_packets; | |
2048 | packet++) { | |
2049 | ||
2050 | /* ASSERT: we have all necessary sitds */ | |
2051 | BUG_ON (list_empty (&sched->td_list)); | |
2052 | ||
2053 | /* ASSERT: no itds for this endpoint in this frame */ | |
2054 | ||
2055 | sitd = list_entry (sched->td_list.next, | |
2056 | struct ehci_sitd, sitd_list); | |
2057 | list_move_tail (&sitd->sitd_list, &stream->td_list); | |
2058 | sitd->stream = iso_stream_get (stream); | |
508db8c9 | 2059 | sitd->urb = urb; |
1da177e4 | 2060 | |
6dbd682b | 2061 | sitd_patch(ehci, stream, sitd, sched, packet); |
bccbefaa | 2062 | sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1), |
1da177e4 LT |
2063 | sitd); |
2064 | ||
2065 | next_uframe += stream->interval << 3; | |
1da177e4 | 2066 | } |
bccbefaa | 2067 | stream->next_uframe = next_uframe & (mod - 1); |
1da177e4 LT |
2068 | |
2069 | /* don't need that schedule data any more */ | |
2070 | iso_sched_free (stream, sched); | |
2071 | urb->hcpriv = NULL; | |
2072 | ||
2073 | timer_action (ehci, TIMER_IO_WATCHDOG); | |
b015cb79 | 2074 | enable_periodic(ehci); |
1da177e4 LT |
2075 | } |
2076 | ||
2077 | /*-------------------------------------------------------------------------*/ | |
2078 | ||
2079 | #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \ | |
53bd6a60 | 2080 | | SITD_STS_XACT | SITD_STS_MMF) |
1da177e4 | 2081 | |
30bf54e6 DB |
2082 | /* Process and recycle a completed SITD. Return true iff its urb completed, |
2083 | * and hence its completion callback probably added things to the hardware | |
2084 | * schedule. | |
2085 | * | |
2086 | * Note that we carefully avoid recycling this descriptor until after any | |
2087 | * completion callback runs, so that it won't be reused quickly. That is, | |
2088 | * assuming (a) no more than two urbs per frame on this endpoint, and also | |
2089 | * (b) only this endpoint's completions submit URBs. It seems some silicon | |
2090 | * corrupts things if you reuse completed descriptors very quickly... | |
2091 | */ | |
1da177e4 LT |
2092 | static unsigned |
2093 | sitd_complete ( | |
2094 | struct ehci_hcd *ehci, | |
7d12e780 | 2095 | struct ehci_sitd *sitd |
1da177e4 LT |
2096 | ) { |
2097 | struct urb *urb = sitd->urb; | |
2098 | struct usb_iso_packet_descriptor *desc; | |
2099 | u32 t; | |
2100 | int urb_index = -1; | |
2101 | struct ehci_iso_stream *stream = sitd->stream; | |
2102 | struct usb_device *dev; | |
30bf54e6 | 2103 | unsigned retval = false; |
1da177e4 LT |
2104 | |
2105 | urb_index = sitd->index; | |
2106 | desc = &urb->iso_frame_desc [urb_index]; | |
6dbd682b | 2107 | t = hc32_to_cpup(ehci, &sitd->hw_results); |
1da177e4 LT |
2108 | |
2109 | /* report transfer status */ | |
2110 | if (t & SITD_ERRS) { | |
2111 | urb->error_count++; | |
2112 | if (t & SITD_STS_DBE) | |
2113 | desc->status = usb_pipein (urb->pipe) | |
2114 | ? -ENOSR /* hc couldn't read */ | |
2115 | : -ECOMM; /* hc couldn't write */ | |
2116 | else if (t & SITD_STS_BABBLE) | |
2117 | desc->status = -EOVERFLOW; | |
2118 | else /* XACT, MMF, etc */ | |
2119 | desc->status = -EPROTO; | |
2120 | } else { | |
2121 | desc->status = 0; | |
ec6d67e3 AS |
2122 | desc->actual_length = desc->length - SITD_LENGTH(t); |
2123 | urb->actual_length += desc->actual_length; | |
1da177e4 | 2124 | } |
1da177e4 LT |
2125 | |
2126 | /* handle completion now? */ | |
2127 | if ((urb_index + 1) != urb->number_of_packets) | |
30bf54e6 | 2128 | goto done; |
1da177e4 LT |
2129 | |
2130 | /* ASSERT: it's really the last sitd for this urb | |
2131 | list_for_each_entry (sitd, &stream->td_list, sitd_list) | |
2132 | BUG_ON (sitd->urb == urb); | |
2133 | */ | |
2134 | ||
aa16ca30 | 2135 | /* give urb back to the driver; completion often (re)submits */ |
6a8e87b2 | 2136 | dev = urb->dev; |
14c04c0f | 2137 | ehci_urb_done(ehci, urb, 0); |
30bf54e6 | 2138 | retval = true; |
1da177e4 | 2139 | urb = NULL; |
b015cb79 | 2140 | disable_periodic(ehci); |
1da177e4 LT |
2141 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
2142 | ||
05570297 | 2143 | if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { |
ad93562b AX |
2144 | if (ehci->amd_pll_fix == 1) |
2145 | usb_amd_quirk_pll_enable(); | |
05570297 AH |
2146 | } |
2147 | ||
508db8c9 | 2148 | if (list_is_singular(&stream->td_list)) { |
1da177e4 LT |
2149 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
2150 | -= stream->bandwidth; | |
2151 | ehci_vdbg (ehci, | |
2152 | "deschedule devp %s ep%d%s-iso\n", | |
2153 | dev->devpath, stream->bEndpointAddress & 0x0f, | |
2154 | (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out"); | |
2155 | } | |
2156 | iso_stream_put (ehci, stream); | |
0e5f231b | 2157 | |
30bf54e6 | 2158 | done: |
30bf54e6 | 2159 | sitd->urb = NULL; |
0e5f231b AS |
2160 | if (ehci->clock_frame != sitd->frame) { |
2161 | /* OK to recycle this SITD now. */ | |
2162 | sitd->stream = NULL; | |
2163 | list_move(&sitd->sitd_list, &stream->free_list); | |
2164 | iso_stream_put(ehci, stream); | |
2165 | } else { | |
2166 | /* HW might remember this SITD, so we can't recycle it yet. | |
2167 | * Move it to a safe place until a new frame starts. | |
2168 | */ | |
2169 | list_move(&sitd->sitd_list, &ehci->cached_sitd_list); | |
2170 | if (stream->refcount == 2) { | |
2171 | /* If iso_stream_put() were called here, stream | |
2172 | * would be freed. Instead, just prevent reuse. | |
2173 | */ | |
2174 | stream->ep->hcpriv = NULL; | |
2175 | stream->ep = NULL; | |
2176 | } | |
2177 | } | |
30bf54e6 | 2178 | return retval; |
1da177e4 LT |
2179 | } |
2180 | ||
2181 | ||
5db539e4 | 2182 | static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb, |
55016f10 | 2183 | gfp_t mem_flags) |
1da177e4 LT |
2184 | { |
2185 | int status = -EINVAL; | |
2186 | unsigned long flags; | |
2187 | struct ehci_iso_stream *stream; | |
2188 | ||
2189 | /* Get iso_stream head */ | |
2190 | stream = iso_stream_find (ehci, urb); | |
2191 | if (stream == NULL) { | |
2192 | ehci_dbg (ehci, "can't get iso stream\n"); | |
2193 | return -ENOMEM; | |
2194 | } | |
2195 | if (urb->interval != stream->interval) { | |
2196 | ehci_dbg (ehci, "can't change iso interval %d --> %d\n", | |
2197 | stream->interval, urb->interval); | |
2198 | goto done; | |
2199 | } | |
2200 | ||
2201 | #ifdef EHCI_URB_TRACE | |
2202 | ehci_dbg (ehci, | |
2203 | "submit %p dev%s ep%d%s-iso len %d\n", | |
2204 | urb, urb->dev->devpath, | |
2205 | usb_pipeendpoint (urb->pipe), | |
2206 | usb_pipein (urb->pipe) ? "in" : "out", | |
2207 | urb->transfer_buffer_length); | |
2208 | #endif | |
2209 | ||
2210 | /* allocate SITDs */ | |
2211 | status = sitd_urb_transaction (stream, ehci, urb, mem_flags); | |
2212 | if (status < 0) { | |
2213 | ehci_dbg (ehci, "can't init sitds\n"); | |
2214 | goto done; | |
2215 | } | |
2216 | ||
2217 | /* schedule ... need to lock */ | |
2218 | spin_lock_irqsave (&ehci->lock, flags); | |
541c7d43 | 2219 | if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { |
8de98402 | 2220 | status = -ESHUTDOWN; |
e9df41c5 AS |
2221 | goto done_not_linked; |
2222 | } | |
2223 | status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); | |
2224 | if (unlikely(status)) | |
2225 | goto done_not_linked; | |
2226 | status = iso_stream_schedule(ehci, urb, stream); | |
53bd6a60 | 2227 | if (status == 0) |
1da177e4 | 2228 | sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream); |
e9df41c5 AS |
2229 | else |
2230 | usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); | |
2231 | done_not_linked: | |
1da177e4 LT |
2232 | spin_unlock_irqrestore (&ehci->lock, flags); |
2233 | ||
2234 | done: | |
2235 | if (status < 0) | |
2236 | iso_stream_put (ehci, stream); | |
2237 | return status; | |
2238 | } | |
2239 | ||
1da177e4 LT |
2240 | /*-------------------------------------------------------------------------*/ |
2241 | ||
0e5f231b | 2242 | static void free_cached_lists(struct ehci_hcd *ehci) |
9aa09d2f KW |
2243 | { |
2244 | struct ehci_itd *itd, *n; | |
0e5f231b | 2245 | struct ehci_sitd *sitd, *sn; |
9aa09d2f KW |
2246 | |
2247 | list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) { | |
2248 | struct ehci_iso_stream *stream = itd->stream; | |
2249 | itd->stream = NULL; | |
2250 | list_move(&itd->itd_list, &stream->free_list); | |
2251 | iso_stream_put(ehci, stream); | |
2252 | } | |
0e5f231b AS |
2253 | |
2254 | list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) { | |
2255 | struct ehci_iso_stream *stream = sitd->stream; | |
2256 | sitd->stream = NULL; | |
2257 | list_move(&sitd->sitd_list, &stream->free_list); | |
2258 | iso_stream_put(ehci, stream); | |
2259 | } | |
9aa09d2f KW |
2260 | } |
2261 | ||
2262 | /*-------------------------------------------------------------------------*/ | |
2263 | ||
1da177e4 | 2264 | static void |
7d12e780 | 2265 | scan_periodic (struct ehci_hcd *ehci) |
1da177e4 | 2266 | { |
b40e43fc | 2267 | unsigned now_uframe, frame, clock, clock_frame, mod; |
1da177e4 LT |
2268 | unsigned modified; |
2269 | ||
2270 | mod = ehci->periodic_size << 3; | |
2271 | ||
2272 | /* | |
2273 | * When running, scan from last scan point up to "now" | |
2274 | * else clean up by scanning everything that's left. | |
2275 | * Touches as few pages as possible: cache-friendly. | |
2276 | */ | |
2277 | now_uframe = ehci->next_uframe; | |
c0c53dbc | 2278 | if (ehci->rh_state >= EHCI_RH_RUNNING) { |
68aa95d5 | 2279 | clock = ehci_read_frame_index(ehci); |
bccbefaa | 2280 | clock_frame = (clock >> 3) & (ehci->periodic_size - 1); |
9aa09d2f | 2281 | } else { |
1da177e4 | 2282 | clock = now_uframe + mod - 1; |
9aa09d2f KW |
2283 | clock_frame = -1; |
2284 | } | |
2285 | if (ehci->clock_frame != clock_frame) { | |
0e5f231b | 2286 | free_cached_lists(ehci); |
9aa09d2f KW |
2287 | ehci->clock_frame = clock_frame; |
2288 | } | |
bccbefaa | 2289 | clock &= mod - 1; |
b40e43fc | 2290 | clock_frame = clock >> 3; |
1e12c910 | 2291 | ++ehci->periodic_stamp; |
1da177e4 LT |
2292 | |
2293 | for (;;) { | |
2294 | union ehci_shadow q, *q_p; | |
6dbd682b | 2295 | __hc32 type, *hw_p; |
79592b72 | 2296 | unsigned incomplete = false; |
1da177e4 | 2297 | |
1da177e4 | 2298 | frame = now_uframe >> 3; |
1da177e4 LT |
2299 | |
2300 | restart: | |
2301 | /* scan each element in frame's queue for completions */ | |
2302 | q_p = &ehci->pshadow [frame]; | |
2303 | hw_p = &ehci->periodic [frame]; | |
2304 | q.ptr = q_p->ptr; | |
6dbd682b | 2305 | type = Q_NEXT_TYPE(ehci, *hw_p); |
1da177e4 LT |
2306 | modified = 0; |
2307 | ||
2308 | while (q.ptr != NULL) { | |
2309 | unsigned uf; | |
2310 | union ehci_shadow temp; | |
2311 | int live; | |
2312 | ||
c0c53dbc | 2313 | live = (ehci->rh_state >= EHCI_RH_RUNNING); |
6dbd682b | 2314 | switch (hc32_to_cpu(ehci, type)) { |
1da177e4 LT |
2315 | case Q_TYPE_QH: |
2316 | /* handle any completions */ | |
c83e1a9f | 2317 | temp.qh = q.qh; |
3807e26d | 2318 | type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next); |
1da177e4 | 2319 | q = q.qh->qh_next; |
1e12c910 AS |
2320 | if (temp.qh->stamp != ehci->periodic_stamp) { |
2321 | modified = qh_completions(ehci, temp.qh); | |
2322 | if (!modified) | |
2323 | temp.qh->stamp = ehci->periodic_stamp; | |
2324 | if (unlikely(list_empty(&temp.qh->qtd_list) || | |
2325 | temp.qh->needs_rescan)) | |
df202255 | 2326 | start_unlink_intr(ehci, temp.qh); |
1e12c910 | 2327 | } |
1da177e4 LT |
2328 | break; |
2329 | case Q_TYPE_FSTN: | |
2330 | /* for "save place" FSTNs, look at QH entries | |
2331 | * in the previous frame for completions. | |
2332 | */ | |
6dbd682b | 2333 | if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) { |
2d0fe1bb GKH |
2334 | ehci_dbg(ehci, |
2335 | "ignoring completions from FSTNs\n"); | |
1da177e4 | 2336 | } |
6dbd682b | 2337 | type = Q_NEXT_TYPE(ehci, q.fstn->hw_next); |
1da177e4 LT |
2338 | q = q.fstn->fstn_next; |
2339 | break; | |
2340 | case Q_TYPE_ITD: | |
79592b72 DB |
2341 | /* If this ITD is still active, leave it for |
2342 | * later processing ... check the next entry. | |
b40e43fc AS |
2343 | * No need to check for activity unless the |
2344 | * frame is current. | |
79592b72 | 2345 | */ |
b40e43fc AS |
2346 | if (frame == clock_frame && live) { |
2347 | rmb(); | |
2348 | for (uf = 0; uf < 8; uf++) { | |
2349 | if (q.itd->hw_transaction[uf] & | |
2350 | ITD_ACTIVE(ehci)) | |
2351 | break; | |
2352 | } | |
2353 | if (uf < 8) { | |
2354 | incomplete = true; | |
2355 | q_p = &q.itd->itd_next; | |
2356 | hw_p = &q.itd->hw_next; | |
2357 | type = Q_NEXT_TYPE(ehci, | |
6dbd682b | 2358 | q.itd->hw_next); |
b40e43fc AS |
2359 | q = *q_p; |
2360 | break; | |
2361 | } | |
1da177e4 | 2362 | } |
1da177e4 | 2363 | |
79592b72 DB |
2364 | /* Take finished ITDs out of the schedule |
2365 | * and process them: recycle, maybe report | |
2366 | * URB completion. HC won't cache the | |
1da177e4 LT |
2367 | * pointer for much longer, if at all. |
2368 | */ | |
2369 | *q_p = q.itd->itd_next; | |
3d091a6f AX |
2370 | if (!ehci->use_dummy_qh || |
2371 | q.itd->hw_next != EHCI_LIST_END(ehci)) | |
2372 | *hw_p = q.itd->hw_next; | |
2373 | else | |
2374 | *hw_p = ehci->dummy->qh_dma; | |
6dbd682b | 2375 | type = Q_NEXT_TYPE(ehci, q.itd->hw_next); |
1da177e4 | 2376 | wmb(); |
7d12e780 | 2377 | modified = itd_complete (ehci, q.itd); |
1da177e4 LT |
2378 | q = *q_p; |
2379 | break; | |
2380 | case Q_TYPE_SITD: | |
79592b72 DB |
2381 | /* If this SITD is still active, leave it for |
2382 | * later processing ... check the next entry. | |
b40e43fc AS |
2383 | * No need to check for activity unless the |
2384 | * frame is current. | |
79592b72 | 2385 | */ |
22e18694 | 2386 | if (((frame == clock_frame) || |
bccbefaa | 2387 | (((frame + 1) & (ehci->periodic_size - 1)) |
22e18694 DE |
2388 | == clock_frame)) |
2389 | && live | |
2390 | && (q.sitd->hw_results & | |
2391 | SITD_ACTIVE(ehci))) { | |
2392 | ||
79592b72 | 2393 | incomplete = true; |
1da177e4 LT |
2394 | q_p = &q.sitd->sitd_next; |
2395 | hw_p = &q.sitd->hw_next; | |
6dbd682b SR |
2396 | type = Q_NEXT_TYPE(ehci, |
2397 | q.sitd->hw_next); | |
1da177e4 LT |
2398 | q = *q_p; |
2399 | break; | |
2400 | } | |
79592b72 DB |
2401 | |
2402 | /* Take finished SITDs out of the schedule | |
2403 | * and process them: recycle, maybe report | |
2404 | * URB completion. | |
2405 | */ | |
1da177e4 | 2406 | *q_p = q.sitd->sitd_next; |
3d091a6f AX |
2407 | if (!ehci->use_dummy_qh || |
2408 | q.sitd->hw_next != EHCI_LIST_END(ehci)) | |
2409 | *hw_p = q.sitd->hw_next; | |
2410 | else | |
2411 | *hw_p = ehci->dummy->qh_dma; | |
6dbd682b | 2412 | type = Q_NEXT_TYPE(ehci, q.sitd->hw_next); |
1da177e4 | 2413 | wmb(); |
7d12e780 | 2414 | modified = sitd_complete (ehci, q.sitd); |
1da177e4 LT |
2415 | q = *q_p; |
2416 | break; | |
2417 | default: | |
2d0fe1bb | 2418 | ehci_dbg(ehci, "corrupt type %d frame %d shadow %p\n", |
1da177e4 LT |
2419 | type, frame, q.ptr); |
2420 | // BUG (); | |
2421 | q.ptr = NULL; | |
2422 | } | |
2423 | ||
2424 | /* assume completion callbacks modify the queue */ | |
aa16ca30 | 2425 | if (unlikely (modified)) { |
3ca9aeba | 2426 | if (likely(ehci->periodic_count > 0)) |
aa16ca30 | 2427 | goto restart; |
01c17142 | 2428 | /* short-circuit this scan */ |
aa16ca30 DB |
2429 | now_uframe = clock; |
2430 | break; | |
2431 | } | |
1da177e4 LT |
2432 | } |
2433 | ||
79592b72 DB |
2434 | /* If we can tell we caught up to the hardware, stop now. |
2435 | * We can't advance our scan without collecting the ISO | |
2436 | * transfers that are still pending in this frame. | |
2437 | */ | |
c0c53dbc | 2438 | if (incomplete && ehci->rh_state >= EHCI_RH_RUNNING) { |
79592b72 DB |
2439 | ehci->next_uframe = now_uframe; |
2440 | break; | |
2441 | } | |
1da177e4 LT |
2442 | |
2443 | // FIXME: this assumes we won't get lapped when | |
2444 | // latencies climb; that should be rare, but... | |
2445 | // detect it, and just go all the way around. | |
2446 | // FLR might help detect this case, so long as latencies | |
2447 | // don't exceed periodic_size msec (default 1.024 sec). | |
2448 | ||
2449 | // FIXME: likewise assumes HC doesn't halt mid-scan | |
2450 | ||
2451 | if (now_uframe == clock) { | |
2452 | unsigned now; | |
2453 | ||
c0c53dbc | 2454 | if (ehci->rh_state < EHCI_RH_RUNNING |
3ca9aeba | 2455 | || ehci->periodic_count == 0) |
1da177e4 LT |
2456 | break; |
2457 | ehci->next_uframe = now_uframe; | |
68aa95d5 | 2458 | now = ehci_read_frame_index(ehci) & (mod - 1); |
1da177e4 LT |
2459 | if (now_uframe == now) |
2460 | break; | |
2461 | ||
2462 | /* rescan the rest of this frame, then ... */ | |
2463 | clock = now; | |
b40e43fc | 2464 | clock_frame = clock >> 3; |
9aa09d2f | 2465 | if (ehci->clock_frame != clock_frame) { |
0e5f231b | 2466 | free_cached_lists(ehci); |
9aa09d2f | 2467 | ehci->clock_frame = clock_frame; |
1e12c910 | 2468 | ++ehci->periodic_stamp; |
9aa09d2f | 2469 | } |
1da177e4 LT |
2470 | } else { |
2471 | now_uframe++; | |
bccbefaa | 2472 | now_uframe &= mod - 1; |
1da177e4 | 2473 | } |
53bd6a60 | 2474 | } |
1da177e4 | 2475 | } |