Commit | Line | Data |
---|---|---|
79ad3b5a BG |
1 | /* |
2 | * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
bbdabdb6 | 5 | * Copyright (C) 2009 - 2013 NVIDIA Corporation |
79ad3b5a BG |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
ded017ee | 20 | #include <linux/err.h> |
79ad3b5a BG |
21 | #include <linux/platform_device.h> |
22 | #include <linux/platform_data/tegra_usb.h> | |
23 | #include <linux/irq.h> | |
24 | #include <linux/usb/otg.h> | |
4a53f4e6 OJ |
25 | #include <linux/gpio.h> |
26 | #include <linux/of.h> | |
27 | #include <linux/of_gpio.h> | |
ebf20de4 | 28 | #include <linux/pm_runtime.h> |
bbdabdb6 | 29 | #include <linux/usb/ehci_def.h> |
1ba8216f | 30 | #include <linux/usb/tegra_usb_phy.h> |
54388b28 SW |
31 | |
32 | #define TEGRA_USB_BASE 0xC5000000 | |
33 | #define TEGRA_USB2_BASE 0xC5004000 | |
34 | #define TEGRA_USB3_BASE 0xC5008000 | |
79ad3b5a | 35 | |
bbdabdb6 VB |
36 | /* PORTSC registers */ |
37 | #define TEGRA_USB_PORTSC1 0x184 | |
38 | #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) | |
39 | #define TEGRA_USB_PORTSC1_PHCD (1 << 23) | |
40 | ||
fbf9865c RM |
41 | #define TEGRA_USB_DMA_ALIGN 32 |
42 | ||
79ad3b5a BG |
43 | struct tegra_ehci_hcd { |
44 | struct ehci_hcd *ehci; | |
45 | struct tegra_usb_phy *phy; | |
46 | struct clk *clk; | |
86753811 | 47 | struct usb_phy *transceiver; |
79ad3b5a | 48 | int host_resumed; |
79ad3b5a | 49 | int port_resuming; |
585355c5 | 50 | bool needs_double_reset; |
79ad3b5a BG |
51 | enum tegra_usb_phy_port_speed port_speed; |
52 | }; | |
53 | ||
54 | static void tegra_ehci_power_up(struct usb_hcd *hcd) | |
55 | { | |
56 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
57 | ||
20de12cc | 58 | clk_prepare_enable(tegra->clk); |
ab137d04 | 59 | usb_phy_set_suspend(hcd->phy, 0); |
79ad3b5a BG |
60 | tegra->host_resumed = 1; |
61 | } | |
62 | ||
63 | static void tegra_ehci_power_down(struct usb_hcd *hcd) | |
64 | { | |
65 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
66 | ||
67 | tegra->host_resumed = 0; | |
ab137d04 | 68 | usb_phy_set_suspend(hcd->phy, 1); |
20de12cc | 69 | clk_disable_unprepare(tegra->clk); |
79ad3b5a BG |
70 | } |
71 | ||
1f594b64 JL |
72 | static int tegra_ehci_internal_port_reset( |
73 | struct ehci_hcd *ehci, | |
74 | u32 __iomem *portsc_reg | |
75 | ) | |
76 | { | |
77 | u32 temp; | |
78 | unsigned long flags; | |
79 | int retval = 0; | |
80 | int i, tries; | |
81 | u32 saved_usbintr; | |
82 | ||
83 | spin_lock_irqsave(&ehci->lock, flags); | |
84 | saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); | |
85 | /* disable USB interrupt */ | |
86 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
87 | spin_unlock_irqrestore(&ehci->lock, flags); | |
88 | ||
89 | /* | |
90 | * Here we have to do Port Reset at most twice for | |
91 | * Port Enable bit to be set. | |
92 | */ | |
93 | for (i = 0; i < 2; i++) { | |
94 | temp = ehci_readl(ehci, portsc_reg); | |
95 | temp |= PORT_RESET; | |
96 | ehci_writel(ehci, temp, portsc_reg); | |
97 | mdelay(10); | |
98 | temp &= ~PORT_RESET; | |
99 | ehci_writel(ehci, temp, portsc_reg); | |
100 | mdelay(1); | |
101 | tries = 100; | |
102 | do { | |
103 | mdelay(1); | |
104 | /* | |
105 | * Up to this point, Port Enable bit is | |
106 | * expected to be set after 2 ms waiting. | |
107 | * USB1 usually takes extra 45 ms, for safety, | |
108 | * we take 100 ms as timeout. | |
109 | */ | |
110 | temp = ehci_readl(ehci, portsc_reg); | |
111 | } while (!(temp & PORT_PE) && tries--); | |
112 | if (temp & PORT_PE) | |
113 | break; | |
114 | } | |
115 | if (i == 2) | |
116 | retval = -ETIMEDOUT; | |
117 | ||
118 | /* | |
119 | * Clear Connect Status Change bit if it's set. | |
120 | * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. | |
121 | */ | |
122 | if (temp & PORT_CSC) | |
123 | ehci_writel(ehci, PORT_CSC, portsc_reg); | |
124 | ||
125 | /* | |
126 | * Write to clear any interrupt status bits that might be set | |
127 | * during port reset. | |
128 | */ | |
129 | temp = ehci_readl(ehci, &ehci->regs->status); | |
130 | ehci_writel(ehci, temp, &ehci->regs->status); | |
131 | ||
132 | /* restore original interrupt enable bits */ | |
133 | ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); | |
134 | return retval; | |
135 | } | |
136 | ||
79ad3b5a BG |
137 | static int tegra_ehci_hub_control( |
138 | struct usb_hcd *hcd, | |
139 | u16 typeReq, | |
140 | u16 wValue, | |
141 | u16 wIndex, | |
142 | char *buf, | |
143 | u16 wLength | |
144 | ) | |
145 | { | |
146 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
147 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
148 | u32 __iomem *status_reg; | |
149 | u32 temp; | |
150 | unsigned long flags; | |
151 | int retval = 0; | |
152 | ||
153 | status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; | |
154 | ||
155 | spin_lock_irqsave(&ehci->lock, flags); | |
156 | ||
6d5f89c7 | 157 | if (typeReq == GetPortStatus) { |
79ad3b5a BG |
158 | temp = ehci_readl(ehci, status_reg); |
159 | if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { | |
160 | /* Resume completed, re-enable disconnect detection */ | |
161 | tegra->port_resuming = 0; | |
ab137d04 | 162 | tegra_usb_phy_postresume(hcd->phy); |
79ad3b5a BG |
163 | } |
164 | } | |
165 | ||
166 | else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { | |
167 | temp = ehci_readl(ehci, status_reg); | |
168 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { | |
169 | retval = -EPIPE; | |
170 | goto done; | |
171 | } | |
172 | ||
b0876574 | 173 | temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E); |
79ad3b5a BG |
174 | temp |= PORT_WKDISC_E | PORT_WKOC_E; |
175 | ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); | |
176 | ||
177 | /* | |
178 | * If a transaction is in progress, there may be a delay in | |
179 | * suspending the port. Poll until the port is suspended. | |
180 | */ | |
181 | if (handshake(ehci, status_reg, PORT_SUSPEND, | |
182 | PORT_SUSPEND, 5000)) | |
183 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | |
184 | ||
185 | set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); | |
186 | goto done; | |
187 | } | |
188 | ||
1f594b64 | 189 | /* For USB1 port we need to issue Port Reset twice internally */ |
585355c5 | 190 | if (tegra->needs_double_reset && |
1f594b64 JL |
191 | (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { |
192 | spin_unlock_irqrestore(&ehci->lock, flags); | |
193 | return tegra_ehci_internal_port_reset(ehci, status_reg); | |
194 | } | |
195 | ||
79ad3b5a BG |
196 | /* |
197 | * Tegra host controller will time the resume operation to clear the bit | |
198 | * when the port control state switches to HS or FS Idle. This behavior | |
199 | * is different from EHCI where the host controller driver is required | |
200 | * to set this bit to a zero after the resume duration is timed in the | |
201 | * driver. | |
202 | */ | |
203 | else if (typeReq == ClearPortFeature && | |
204 | wValue == USB_PORT_FEAT_SUSPEND) { | |
205 | temp = ehci_readl(ehci, status_reg); | |
206 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) { | |
207 | retval = -EPIPE; | |
208 | goto done; | |
209 | } | |
210 | ||
211 | if (!(temp & PORT_SUSPEND)) | |
212 | goto done; | |
213 | ||
214 | /* Disable disconnect detection during port resume */ | |
ab137d04 | 215 | tegra_usb_phy_preresume(hcd->phy); |
79ad3b5a BG |
216 | |
217 | ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); | |
218 | ||
219 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
220 | /* start resume signalling */ | |
221 | ehci_writel(ehci, temp | PORT_RESUME, status_reg); | |
a448e4dc | 222 | set_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
223 | |
224 | spin_unlock_irqrestore(&ehci->lock, flags); | |
225 | msleep(20); | |
226 | spin_lock_irqsave(&ehci->lock, flags); | |
227 | ||
228 | /* Poll until the controller clears RESUME and SUSPEND */ | |
229 | if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) | |
230 | pr_err("%s: timeout waiting for RESUME\n", __func__); | |
231 | if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) | |
232 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | |
233 | ||
234 | ehci->reset_done[wIndex-1] = 0; | |
a448e4dc | 235 | clear_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
236 | |
237 | tegra->port_resuming = 1; | |
238 | goto done; | |
239 | } | |
240 | ||
241 | spin_unlock_irqrestore(&ehci->lock, flags); | |
242 | ||
243 | /* Handle the hub control events here */ | |
244 | return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); | |
245 | done: | |
246 | spin_unlock_irqrestore(&ehci->lock, flags); | |
247 | return retval; | |
248 | } | |
249 | ||
250 | static void tegra_ehci_restart(struct usb_hcd *hcd) | |
251 | { | |
252 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
253 | ||
254 | ehci_reset(ehci); | |
255 | ||
256 | /* setup the frame list and Async q heads */ | |
257 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); | |
258 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
259 | /* setup the command register and set the controller in RUN mode */ | |
260 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); | |
261 | ehci->command |= CMD_RUN; | |
262 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | |
263 | ||
264 | down_write(&ehci_cf_port_reset_rwsem); | |
265 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | |
266 | /* flush posted writes */ | |
267 | ehci_readl(ehci, &ehci->regs->command); | |
268 | up_write(&ehci_cf_port_reset_rwsem); | |
269 | } | |
270 | ||
79ad3b5a BG |
271 | static void tegra_ehci_shutdown(struct usb_hcd *hcd) |
272 | { | |
273 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
274 | ||
275 | /* ehci_shutdown touches the USB controller registers, make sure | |
276 | * controller has clocks to it */ | |
277 | if (!tegra->host_resumed) | |
278 | tegra_ehci_power_up(hcd); | |
279 | ||
280 | ehci_shutdown(hcd); | |
281 | } | |
282 | ||
283 | static int tegra_ehci_setup(struct usb_hcd *hcd) | |
284 | { | |
285 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
79ad3b5a BG |
286 | |
287 | /* EHCI registers start at offset 0x100 */ | |
288 | ehci->caps = hcd->regs + 0x100; | |
79ad3b5a BG |
289 | |
290 | /* switch to host mode */ | |
291 | hcd->has_tt = 1; | |
79ad3b5a | 292 | |
c73cee71 | 293 | return ehci_setup(hcd); |
79ad3b5a BG |
294 | } |
295 | ||
fe375774 | 296 | struct dma_aligned_buffer { |
fbf9865c RM |
297 | void *kmalloc_ptr; |
298 | void *old_xfer_buffer; | |
299 | u8 data[0]; | |
300 | }; | |
301 | ||
fe375774 | 302 | static void free_dma_aligned_buffer(struct urb *urb) |
fbf9865c | 303 | { |
fe375774 | 304 | struct dma_aligned_buffer *temp; |
fbf9865c RM |
305 | |
306 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
307 | return; | |
308 | ||
fe375774 VB |
309 | temp = container_of(urb->transfer_buffer, |
310 | struct dma_aligned_buffer, data); | |
fbf9865c | 311 | |
fe375774 | 312 | if (usb_urb_dir_in(urb)) |
fbf9865c RM |
313 | memcpy(temp->old_xfer_buffer, temp->data, |
314 | urb->transfer_buffer_length); | |
315 | urb->transfer_buffer = temp->old_xfer_buffer; | |
316 | kfree(temp->kmalloc_ptr); | |
317 | ||
318 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
319 | } | |
320 | ||
fe375774 | 321 | static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) |
fbf9865c | 322 | { |
fe375774 | 323 | struct dma_aligned_buffer *temp, *kmalloc_ptr; |
fbf9865c RM |
324 | size_t kmalloc_size; |
325 | ||
326 | if (urb->num_sgs || urb->sg || | |
327 | urb->transfer_buffer_length == 0 || | |
328 | !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) | |
329 | return 0; | |
330 | ||
fbf9865c RM |
331 | /* Allocate a buffer with enough padding for alignment */ |
332 | kmalloc_size = urb->transfer_buffer_length + | |
fe375774 | 333 | sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1; |
fbf9865c RM |
334 | |
335 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); | |
336 | if (!kmalloc_ptr) | |
337 | return -ENOMEM; | |
338 | ||
fe375774 | 339 | /* Position our struct dma_aligned_buffer such that data is aligned */ |
fbf9865c | 340 | temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; |
fbf9865c RM |
341 | temp->kmalloc_ptr = kmalloc_ptr; |
342 | temp->old_xfer_buffer = urb->transfer_buffer; | |
fe375774 | 343 | if (usb_urb_dir_out(urb)) |
fbf9865c RM |
344 | memcpy(temp->data, urb->transfer_buffer, |
345 | urb->transfer_buffer_length); | |
346 | urb->transfer_buffer = temp->data; | |
347 | ||
348 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
354 | gfp_t mem_flags) | |
355 | { | |
356 | int ret; | |
357 | ||
fe375774 | 358 | ret = alloc_dma_aligned_buffer(urb, mem_flags); |
fbf9865c RM |
359 | if (ret) |
360 | return ret; | |
361 | ||
362 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
363 | if (ret) | |
fe375774 | 364 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
365 | |
366 | return ret; | |
367 | } | |
368 | ||
369 | static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
370 | { | |
371 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
fe375774 | 372 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
373 | } |
374 | ||
79ad3b5a BG |
375 | static const struct hc_driver tegra_ehci_hc_driver = { |
376 | .description = hcd_name, | |
377 | .product_desc = "Tegra EHCI Host Controller", | |
378 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
79ad3b5a BG |
379 | .flags = HCD_USB2 | HCD_MEMORY, |
380 | ||
c6fa0b4c | 381 | /* standard ehci functions */ |
79ad3b5a | 382 | .irq = ehci_irq, |
79ad3b5a BG |
383 | .start = ehci_run, |
384 | .stop = ehci_stop, | |
79ad3b5a BG |
385 | .urb_enqueue = ehci_urb_enqueue, |
386 | .urb_dequeue = ehci_urb_dequeue, | |
387 | .endpoint_disable = ehci_endpoint_disable, | |
388 | .endpoint_reset = ehci_endpoint_reset, | |
389 | .get_frame_number = ehci_get_frame, | |
390 | .hub_status_data = ehci_hub_status_data, | |
79ad3b5a | 391 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, |
c6fa0b4c VB |
392 | .relinquish_port = ehci_relinquish_port, |
393 | .port_handed_over = ehci_port_handed_over, | |
394 | ||
395 | /* modified ehci functions for tegra */ | |
396 | .reset = tegra_ehci_setup, | |
397 | .shutdown = tegra_ehci_shutdown, | |
398 | .map_urb_for_dma = tegra_ehci_map_urb_for_dma, | |
399 | .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma, | |
400 | .hub_control = tegra_ehci_hub_control, | |
79ad3b5a | 401 | #ifdef CONFIG_PM |
ebf20de4 AS |
402 | .bus_suspend = ehci_bus_suspend, |
403 | .bus_resume = ehci_bus_resume, | |
79ad3b5a | 404 | #endif |
79ad3b5a BG |
405 | }; |
406 | ||
434103ad SW |
407 | static int setup_vbus_gpio(struct platform_device *pdev, |
408 | struct tegra_ehci_platform_data *pdata) | |
4a53f4e6 OJ |
409 | { |
410 | int err = 0; | |
411 | int gpio; | |
412 | ||
434103ad SW |
413 | gpio = pdata->vbus_gpio; |
414 | if (!gpio_is_valid(gpio)) | |
415 | gpio = of_get_named_gpio(pdev->dev.of_node, | |
416 | "nvidia,vbus-gpio", 0); | |
4a53f4e6 OJ |
417 | if (!gpio_is_valid(gpio)) |
418 | return 0; | |
419 | ||
420 | err = gpio_request(gpio, "vbus_gpio"); | |
421 | if (err) { | |
422 | dev_err(&pdev->dev, "can't request vbus gpio %d", gpio); | |
423 | return err; | |
424 | } | |
425 | err = gpio_direction_output(gpio, 1); | |
426 | if (err) { | |
427 | dev_err(&pdev->dev, "can't enable vbus\n"); | |
428 | return err; | |
429 | } | |
4a53f4e6 OJ |
430 | |
431 | return err; | |
432 | } | |
433 | ||
ebf20de4 AS |
434 | #ifdef CONFIG_PM |
435 | ||
436 | static int controller_suspend(struct device *dev) | |
437 | { | |
438 | struct tegra_ehci_hcd *tegra = | |
439 | platform_get_drvdata(to_platform_device(dev)); | |
440 | struct ehci_hcd *ehci = tegra->ehci; | |
441 | struct usb_hcd *hcd = ehci_to_hcd(ehci); | |
442 | struct ehci_regs __iomem *hw = ehci->regs; | |
443 | unsigned long flags; | |
444 | ||
445 | if (time_before(jiffies, ehci->next_statechange)) | |
446 | msleep(10); | |
447 | ||
c4f34764 | 448 | ehci_halt(ehci); |
ebf20de4 | 449 | |
c4f34764 | 450 | spin_lock_irqsave(&ehci->lock, flags); |
ebf20de4 | 451 | tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3; |
ebf20de4 | 452 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
ebf20de4 AS |
453 | spin_unlock_irqrestore(&ehci->lock, flags); |
454 | ||
455 | tegra_ehci_power_down(hcd); | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static int controller_resume(struct device *dev) | |
460 | { | |
461 | struct tegra_ehci_hcd *tegra = | |
462 | platform_get_drvdata(to_platform_device(dev)); | |
463 | struct ehci_hcd *ehci = tegra->ehci; | |
464 | struct usb_hcd *hcd = ehci_to_hcd(ehci); | |
465 | struct ehci_regs __iomem *hw = ehci->regs; | |
466 | unsigned long val; | |
467 | ||
468 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
469 | tegra_ehci_power_up(hcd); | |
470 | ||
471 | if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) { | |
472 | /* Wait for the phy to detect new devices | |
473 | * before we restart the controller */ | |
474 | msleep(10); | |
475 | goto restart; | |
476 | } | |
477 | ||
478 | /* Force the phy to keep data lines in suspend state */ | |
ab137d04 | 479 | tegra_ehci_phy_restore_start(hcd->phy, tegra->port_speed); |
ebf20de4 AS |
480 | |
481 | /* Enable host mode */ | |
482 | tdi_reset(ehci); | |
483 | ||
484 | /* Enable Port Power */ | |
485 | val = readl(&hw->port_status[0]); | |
486 | val |= PORT_POWER; | |
487 | writel(val, &hw->port_status[0]); | |
488 | udelay(10); | |
489 | ||
490 | /* Check if the phy resume from LP0. When the phy resume from LP0 | |
491 | * USB register will be reset. */ | |
492 | if (!readl(&hw->async_next)) { | |
493 | /* Program the field PTC based on the saved speed mode */ | |
494 | val = readl(&hw->port_status[0]); | |
495 | val &= ~PORT_TEST(~0); | |
496 | if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH) | |
497 | val |= PORT_TEST_FORCE; | |
498 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL) | |
499 | val |= PORT_TEST(6); | |
500 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | |
501 | val |= PORT_TEST(7); | |
502 | writel(val, &hw->port_status[0]); | |
503 | udelay(10); | |
504 | ||
505 | /* Disable test mode by setting PTC field to NORMAL_OP */ | |
506 | val = readl(&hw->port_status[0]); | |
507 | val &= ~PORT_TEST(~0); | |
508 | writel(val, &hw->port_status[0]); | |
509 | udelay(10); | |
510 | } | |
511 | ||
512 | /* Poll until CCS is enabled */ | |
513 | if (handshake(ehci, &hw->port_status[0], PORT_CONNECT, | |
514 | PORT_CONNECT, 2000)) { | |
515 | pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__); | |
516 | goto restart; | |
517 | } | |
518 | ||
519 | /* Poll until PE is enabled */ | |
520 | if (handshake(ehci, &hw->port_status[0], PORT_PE, | |
521 | PORT_PE, 2000)) { | |
522 | pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__); | |
523 | goto restart; | |
524 | } | |
525 | ||
526 | /* Clear the PCI status, to avoid an interrupt taken upon resume */ | |
527 | val = readl(&hw->status); | |
528 | val |= STS_PCD; | |
529 | writel(val, &hw->status); | |
530 | ||
531 | /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */ | |
532 | val = readl(&hw->port_status[0]); | |
533 | if ((val & PORT_POWER) && (val & PORT_PE)) { | |
534 | val |= PORT_SUSPEND; | |
535 | writel(val, &hw->port_status[0]); | |
536 | ||
537 | /* Wait until port suspend completes */ | |
538 | if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND, | |
539 | PORT_SUSPEND, 1000)) { | |
540 | pr_err("%s: timeout waiting for PORT_SUSPEND\n", | |
541 | __func__); | |
542 | goto restart; | |
543 | } | |
544 | } | |
545 | ||
ab137d04 | 546 | tegra_ehci_phy_restore_end(hcd->phy); |
ebf20de4 AS |
547 | goto done; |
548 | ||
549 | restart: | |
550 | if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) | |
ab137d04 | 551 | tegra_ehci_phy_restore_end(hcd->phy); |
ebf20de4 AS |
552 | |
553 | tegra_ehci_restart(hcd); | |
554 | ||
555 | done: | |
ab137d04 | 556 | tegra_usb_phy_preresume(hcd->phy); |
ebf20de4 AS |
557 | tegra->port_resuming = 1; |
558 | return 0; | |
559 | } | |
560 | ||
561 | static int tegra_ehci_suspend(struct device *dev) | |
562 | { | |
563 | struct tegra_ehci_hcd *tegra = | |
564 | platform_get_drvdata(to_platform_device(dev)); | |
565 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
566 | int rc = 0; | |
567 | ||
568 | /* | |
569 | * When system sleep is supported and USB controller wakeup is | |
570 | * implemented: If the controller is runtime-suspended and the | |
571 | * wakeup setting needs to be changed, call pm_runtime_resume(). | |
572 | */ | |
573 | if (HCD_HW_ACCESSIBLE(hcd)) | |
574 | rc = controller_suspend(dev); | |
575 | return rc; | |
576 | } | |
577 | ||
578 | static int tegra_ehci_resume(struct device *dev) | |
579 | { | |
580 | int rc; | |
581 | ||
582 | rc = controller_resume(dev); | |
583 | if (rc == 0) { | |
584 | pm_runtime_disable(dev); | |
585 | pm_runtime_set_active(dev); | |
586 | pm_runtime_enable(dev); | |
587 | } | |
588 | return rc; | |
589 | } | |
590 | ||
591 | static int tegra_ehci_runtime_suspend(struct device *dev) | |
592 | { | |
593 | return controller_suspend(dev); | |
594 | } | |
595 | ||
596 | static int tegra_ehci_runtime_resume(struct device *dev) | |
597 | { | |
598 | return controller_resume(dev); | |
599 | } | |
600 | ||
601 | static const struct dev_pm_ops tegra_ehci_pm_ops = { | |
602 | .suspend = tegra_ehci_suspend, | |
603 | .resume = tegra_ehci_resume, | |
604 | .runtime_suspend = tegra_ehci_runtime_suspend, | |
605 | .runtime_resume = tegra_ehci_runtime_resume, | |
606 | }; | |
607 | ||
608 | #endif | |
609 | ||
bbdabdb6 VB |
610 | /* Bits of PORTSC1, which will get cleared by writing 1 into them */ |
611 | #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) | |
612 | ||
613 | void tegra_ehci_set_pts(struct usb_phy *x, u8 pts_val) | |
614 | { | |
615 | unsigned long val; | |
616 | struct usb_hcd *hcd = bus_to_hcd(x->otg->host); | |
617 | void __iomem *base = hcd->regs; | |
618 | ||
619 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
620 | val &= ~TEGRA_USB_PORTSC1_PTS(3); | |
621 | val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3); | |
622 | writel(val, base + TEGRA_USB_PORTSC1); | |
623 | } | |
624 | EXPORT_SYMBOL_GPL(tegra_ehci_set_pts); | |
625 | ||
626 | void tegra_ehci_set_phcd(struct usb_phy *x, bool enable) | |
627 | { | |
628 | unsigned long val; | |
629 | struct usb_hcd *hcd = bus_to_hcd(x->otg->host); | |
630 | void __iomem *base = hcd->regs; | |
631 | ||
632 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
633 | if (enable) | |
634 | val |= TEGRA_USB_PORTSC1_PHCD; | |
635 | else | |
636 | val &= ~TEGRA_USB_PORTSC1_PHCD; | |
637 | writel(val, base + TEGRA_USB_PORTSC1); | |
638 | } | |
639 | EXPORT_SYMBOL_GPL(tegra_ehci_set_phcd); | |
640 | ||
4a53f4e6 OJ |
641 | static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32); |
642 | ||
79ad3b5a BG |
643 | static int tegra_ehci_probe(struct platform_device *pdev) |
644 | { | |
645 | struct resource *res; | |
646 | struct usb_hcd *hcd; | |
647 | struct tegra_ehci_hcd *tegra; | |
648 | struct tegra_ehci_platform_data *pdata; | |
649 | int err = 0; | |
650 | int irq; | |
651 | int instance = pdev->id; | |
bbdabdb6 | 652 | struct usb_phy *u_phy; |
79ad3b5a BG |
653 | |
654 | pdata = pdev->dev.platform_data; | |
655 | if (!pdata) { | |
656 | dev_err(&pdev->dev, "Platform data missing\n"); | |
657 | return -EINVAL; | |
658 | } | |
659 | ||
4a53f4e6 OJ |
660 | /* Right now device-tree probed devices don't get dma_mask set. |
661 | * Since shared usb code relies on it, set it here for now. | |
662 | * Once we have dma capability bindings this can go away. | |
663 | */ | |
664 | if (!pdev->dev.dma_mask) | |
665 | pdev->dev.dma_mask = &tegra_ehci_dma_mask; | |
666 | ||
434103ad | 667 | setup_vbus_gpio(pdev, pdata); |
4a53f4e6 | 668 | |
bc2ff98f JL |
669 | tegra = devm_kzalloc(&pdev->dev, sizeof(struct tegra_ehci_hcd), |
670 | GFP_KERNEL); | |
79ad3b5a BG |
671 | if (!tegra) |
672 | return -ENOMEM; | |
673 | ||
674 | hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, | |
675 | dev_name(&pdev->dev)); | |
676 | if (!hcd) { | |
677 | dev_err(&pdev->dev, "Unable to create HCD\n"); | |
bc2ff98f | 678 | return -ENOMEM; |
79ad3b5a BG |
679 | } |
680 | ||
681 | platform_set_drvdata(pdev, tegra); | |
682 | ||
bc2ff98f | 683 | tegra->clk = devm_clk_get(&pdev->dev, NULL); |
79ad3b5a BG |
684 | if (IS_ERR(tegra->clk)) { |
685 | dev_err(&pdev->dev, "Can't get ehci clock\n"); | |
686 | err = PTR_ERR(tegra->clk); | |
687 | goto fail_clk; | |
688 | } | |
689 | ||
20de12cc | 690 | err = clk_prepare_enable(tegra->clk); |
79ad3b5a | 691 | if (err) |
bc2ff98f | 692 | goto fail_clk; |
79ad3b5a | 693 | |
585355c5 VB |
694 | tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node, |
695 | "nvidia,needs-double-reset"); | |
696 | ||
79ad3b5a BG |
697 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
698 | if (!res) { | |
699 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
700 | err = -ENXIO; | |
701 | goto fail_io; | |
702 | } | |
703 | hcd->rsrc_start = res->start; | |
704 | hcd->rsrc_len = resource_size(res); | |
bc2ff98f | 705 | hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
79ad3b5a BG |
706 | if (!hcd->regs) { |
707 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
708 | err = -ENOMEM; | |
709 | goto fail_io; | |
710 | } | |
711 | ||
4a53f4e6 OJ |
712 | /* This is pretty ugly and needs to be fixed when we do only |
713 | * device-tree probing. Old code relies on the platform_device | |
714 | * numbering that we lack for device-tree-instantiated devices. | |
715 | */ | |
716 | if (instance < 0) { | |
717 | switch (res->start) { | |
718 | case TEGRA_USB_BASE: | |
719 | instance = 0; | |
720 | break; | |
721 | case TEGRA_USB2_BASE: | |
722 | instance = 1; | |
723 | break; | |
724 | case TEGRA_USB3_BASE: | |
725 | instance = 2; | |
726 | break; | |
727 | default: | |
728 | err = -ENODEV; | |
729 | dev_err(&pdev->dev, "unknown usb instance\n"); | |
bc2ff98f | 730 | goto fail_io; |
4a53f4e6 OJ |
731 | } |
732 | } | |
733 | ||
aa607ebf SW |
734 | tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs, |
735 | pdata->phy_config, | |
736 | TEGRA_USB_PHY_MODE_HOST); | |
79ad3b5a BG |
737 | if (IS_ERR(tegra->phy)) { |
738 | dev_err(&pdev->dev, "Failed to open USB phy\n"); | |
739 | err = -ENXIO; | |
bc2ff98f | 740 | goto fail_io; |
79ad3b5a BG |
741 | } |
742 | ||
bbdabdb6 | 743 | hcd->phy = u_phy = &tegra->phy->u_phy; |
ab137d04 VB |
744 | usb_phy_init(hcd->phy); |
745 | ||
bbdabdb6 VB |
746 | u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
747 | GFP_KERNEL); | |
748 | if (!u_phy->otg) { | |
749 | dev_err(&pdev->dev, "Failed to alloc memory for otg\n"); | |
750 | err = -ENOMEM; | |
751 | goto fail_io; | |
752 | } | |
753 | u_phy->otg->host = hcd_to_bus(hcd); | |
754 | ||
ab137d04 | 755 | err = usb_phy_set_suspend(hcd->phy, 0); |
79ad3b5a BG |
756 | if (err) { |
757 | dev_err(&pdev->dev, "Failed to power on the phy\n"); | |
758 | goto fail; | |
759 | } | |
760 | ||
761 | tegra->host_resumed = 1; | |
79ad3b5a BG |
762 | tegra->ehci = hcd_to_ehci(hcd); |
763 | ||
764 | irq = platform_get_irq(pdev, 0); | |
765 | if (!irq) { | |
766 | dev_err(&pdev->dev, "Failed to get IRQ\n"); | |
767 | err = -ENODEV; | |
768 | goto fail; | |
769 | } | |
79ad3b5a BG |
770 | |
771 | #ifdef CONFIG_USB_OTG_UTILS | |
772 | if (pdata->operating_mode == TEGRA_USB_OTG) { | |
bc2ff98f JL |
773 | tegra->transceiver = |
774 | devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); | |
ded017ee | 775 | if (!IS_ERR_OR_NULL(tegra->transceiver)) |
6e13c650 | 776 | otg_set_host(tegra->transceiver->otg, &hcd->self); |
79ad3b5a BG |
777 | } |
778 | #endif | |
779 | ||
b5dd18d8 | 780 | err = usb_add_hcd(hcd, irq, IRQF_SHARED); |
79ad3b5a BG |
781 | if (err) { |
782 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); | |
783 | goto fail; | |
784 | } | |
785 | ||
ebf20de4 AS |
786 | pm_runtime_set_active(&pdev->dev); |
787 | pm_runtime_get_noresume(&pdev->dev); | |
788 | ||
789 | /* Don't skip the pm_runtime_forbid call if wakeup isn't working */ | |
790 | /* if (!pdata->power_down_on_bus_suspend) */ | |
791 | pm_runtime_forbid(&pdev->dev); | |
792 | pm_runtime_enable(&pdev->dev); | |
793 | pm_runtime_put_sync(&pdev->dev); | |
79ad3b5a BG |
794 | return err; |
795 | ||
796 | fail: | |
797 | #ifdef CONFIG_USB_OTG_UTILS | |
bc2ff98f | 798 | if (!IS_ERR_OR_NULL(tegra->transceiver)) |
6e13c650 | 799 | otg_set_host(tegra->transceiver->otg, NULL); |
79ad3b5a | 800 | #endif |
ab137d04 | 801 | usb_phy_shutdown(hcd->phy); |
79ad3b5a | 802 | fail_io: |
20de12cc | 803 | clk_disable_unprepare(tegra->clk); |
79ad3b5a BG |
804 | fail_clk: |
805 | usb_put_hcd(hcd); | |
79ad3b5a BG |
806 | return err; |
807 | } | |
808 | ||
79ad3b5a BG |
809 | static int tegra_ehci_remove(struct platform_device *pdev) |
810 | { | |
811 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | |
812 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
813 | ||
ebf20de4 AS |
814 | pm_runtime_get_sync(&pdev->dev); |
815 | pm_runtime_disable(&pdev->dev); | |
816 | pm_runtime_put_noidle(&pdev->dev); | |
817 | ||
79ad3b5a | 818 | #ifdef CONFIG_USB_OTG_UTILS |
bc2ff98f | 819 | if (!IS_ERR_OR_NULL(tegra->transceiver)) |
6e13c650 | 820 | otg_set_host(tegra->transceiver->otg, NULL); |
79ad3b5a BG |
821 | #endif |
822 | ||
ab137d04 | 823 | usb_phy_shutdown(hcd->phy); |
79ad3b5a | 824 | usb_remove_hcd(hcd); |
ecc8a0cd VB |
825 | usb_put_hcd(hcd); |
826 | ||
20de12cc | 827 | clk_disable_unprepare(tegra->clk); |
79ad3b5a | 828 | |
79ad3b5a BG |
829 | return 0; |
830 | } | |
831 | ||
832 | static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) | |
833 | { | |
834 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | |
835 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
836 | ||
837 | if (hcd->driver->shutdown) | |
838 | hcd->driver->shutdown(hcd); | |
839 | } | |
840 | ||
d3608b6d | 841 | static struct of_device_id tegra_ehci_of_match[] = { |
4a53f4e6 OJ |
842 | { .compatible = "nvidia,tegra20-ehci", }, |
843 | { }, | |
844 | }; | |
845 | ||
79ad3b5a BG |
846 | static struct platform_driver tegra_ehci_driver = { |
847 | .probe = tegra_ehci_probe, | |
848 | .remove = tegra_ehci_remove, | |
79ad3b5a BG |
849 | .shutdown = tegra_ehci_hcd_shutdown, |
850 | .driver = { | |
851 | .name = "tegra-ehci", | |
4a53f4e6 | 852 | .of_match_table = tegra_ehci_of_match, |
ebf20de4 AS |
853 | #ifdef CONFIG_PM |
854 | .pm = &tegra_ehci_pm_ops, | |
855 | #endif | |
79ad3b5a BG |
856 | } |
857 | }; |