Commit | Line | Data |
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79ad3b5a BG |
1 | /* |
2 | * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * Copyright (C) 2009 NVIDIA Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/platform_data/tegra_usb.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/usb/otg.h> | |
4a53f4e6 OJ |
24 | #include <linux/gpio.h> |
25 | #include <linux/of.h> | |
26 | #include <linux/of_gpio.h> | |
ebf20de4 | 27 | #include <linux/pm_runtime.h> |
4a53f4e6 | 28 | |
79ad3b5a | 29 | #include <mach/usb_phy.h> |
4a53f4e6 | 30 | #include <mach/iomap.h> |
79ad3b5a | 31 | |
fbf9865c RM |
32 | #define TEGRA_USB_DMA_ALIGN 32 |
33 | ||
79ad3b5a BG |
34 | struct tegra_ehci_hcd { |
35 | struct ehci_hcd *ehci; | |
36 | struct tegra_usb_phy *phy; | |
37 | struct clk *clk; | |
38 | struct clk *emc_clk; | |
86753811 | 39 | struct usb_phy *transceiver; |
79ad3b5a | 40 | int host_resumed; |
79ad3b5a | 41 | int port_resuming; |
79ad3b5a BG |
42 | enum tegra_usb_phy_port_speed port_speed; |
43 | }; | |
44 | ||
45 | static void tegra_ehci_power_up(struct usb_hcd *hcd) | |
46 | { | |
47 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
48 | ||
49 | clk_enable(tegra->emc_clk); | |
50 | clk_enable(tegra->clk); | |
51 | tegra_usb_phy_power_on(tegra->phy); | |
52 | tegra->host_resumed = 1; | |
53 | } | |
54 | ||
55 | static void tegra_ehci_power_down(struct usb_hcd *hcd) | |
56 | { | |
57 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
58 | ||
59 | tegra->host_resumed = 0; | |
60 | tegra_usb_phy_power_off(tegra->phy); | |
61 | clk_disable(tegra->clk); | |
62 | clk_disable(tegra->emc_clk); | |
63 | } | |
64 | ||
1f594b64 JL |
65 | static int tegra_ehci_internal_port_reset( |
66 | struct ehci_hcd *ehci, | |
67 | u32 __iomem *portsc_reg | |
68 | ) | |
69 | { | |
70 | u32 temp; | |
71 | unsigned long flags; | |
72 | int retval = 0; | |
73 | int i, tries; | |
74 | u32 saved_usbintr; | |
75 | ||
76 | spin_lock_irqsave(&ehci->lock, flags); | |
77 | saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable); | |
78 | /* disable USB interrupt */ | |
79 | ehci_writel(ehci, 0, &ehci->regs->intr_enable); | |
80 | spin_unlock_irqrestore(&ehci->lock, flags); | |
81 | ||
82 | /* | |
83 | * Here we have to do Port Reset at most twice for | |
84 | * Port Enable bit to be set. | |
85 | */ | |
86 | for (i = 0; i < 2; i++) { | |
87 | temp = ehci_readl(ehci, portsc_reg); | |
88 | temp |= PORT_RESET; | |
89 | ehci_writel(ehci, temp, portsc_reg); | |
90 | mdelay(10); | |
91 | temp &= ~PORT_RESET; | |
92 | ehci_writel(ehci, temp, portsc_reg); | |
93 | mdelay(1); | |
94 | tries = 100; | |
95 | do { | |
96 | mdelay(1); | |
97 | /* | |
98 | * Up to this point, Port Enable bit is | |
99 | * expected to be set after 2 ms waiting. | |
100 | * USB1 usually takes extra 45 ms, for safety, | |
101 | * we take 100 ms as timeout. | |
102 | */ | |
103 | temp = ehci_readl(ehci, portsc_reg); | |
104 | } while (!(temp & PORT_PE) && tries--); | |
105 | if (temp & PORT_PE) | |
106 | break; | |
107 | } | |
108 | if (i == 2) | |
109 | retval = -ETIMEDOUT; | |
110 | ||
111 | /* | |
112 | * Clear Connect Status Change bit if it's set. | |
113 | * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared. | |
114 | */ | |
115 | if (temp & PORT_CSC) | |
116 | ehci_writel(ehci, PORT_CSC, portsc_reg); | |
117 | ||
118 | /* | |
119 | * Write to clear any interrupt status bits that might be set | |
120 | * during port reset. | |
121 | */ | |
122 | temp = ehci_readl(ehci, &ehci->regs->status); | |
123 | ehci_writel(ehci, temp, &ehci->regs->status); | |
124 | ||
125 | /* restore original interrupt enable bits */ | |
126 | ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable); | |
127 | return retval; | |
128 | } | |
129 | ||
79ad3b5a BG |
130 | static int tegra_ehci_hub_control( |
131 | struct usb_hcd *hcd, | |
132 | u16 typeReq, | |
133 | u16 wValue, | |
134 | u16 wIndex, | |
135 | char *buf, | |
136 | u16 wLength | |
137 | ) | |
138 | { | |
139 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
140 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
141 | u32 __iomem *status_reg; | |
142 | u32 temp; | |
143 | unsigned long flags; | |
144 | int retval = 0; | |
145 | ||
146 | status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1]; | |
147 | ||
148 | spin_lock_irqsave(&ehci->lock, flags); | |
149 | ||
6d5f89c7 | 150 | if (typeReq == GetPortStatus) { |
79ad3b5a BG |
151 | temp = ehci_readl(ehci, status_reg); |
152 | if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { | |
153 | /* Resume completed, re-enable disconnect detection */ | |
154 | tegra->port_resuming = 0; | |
155 | tegra_usb_phy_postresume(tegra->phy); | |
156 | } | |
157 | } | |
158 | ||
159 | else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) { | |
160 | temp = ehci_readl(ehci, status_reg); | |
161 | if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) { | |
162 | retval = -EPIPE; | |
163 | goto done; | |
164 | } | |
165 | ||
b0876574 | 166 | temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E); |
79ad3b5a BG |
167 | temp |= PORT_WKDISC_E | PORT_WKOC_E; |
168 | ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); | |
169 | ||
170 | /* | |
171 | * If a transaction is in progress, there may be a delay in | |
172 | * suspending the port. Poll until the port is suspended. | |
173 | */ | |
174 | if (handshake(ehci, status_reg, PORT_SUSPEND, | |
175 | PORT_SUSPEND, 5000)) | |
176 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | |
177 | ||
178 | set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports); | |
179 | goto done; | |
180 | } | |
181 | ||
1f594b64 JL |
182 | /* For USB1 port we need to issue Port Reset twice internally */ |
183 | if (tegra->phy->instance == 0 && | |
184 | (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) { | |
185 | spin_unlock_irqrestore(&ehci->lock, flags); | |
186 | return tegra_ehci_internal_port_reset(ehci, status_reg); | |
187 | } | |
188 | ||
79ad3b5a BG |
189 | /* |
190 | * Tegra host controller will time the resume operation to clear the bit | |
191 | * when the port control state switches to HS or FS Idle. This behavior | |
192 | * is different from EHCI where the host controller driver is required | |
193 | * to set this bit to a zero after the resume duration is timed in the | |
194 | * driver. | |
195 | */ | |
196 | else if (typeReq == ClearPortFeature && | |
197 | wValue == USB_PORT_FEAT_SUSPEND) { | |
198 | temp = ehci_readl(ehci, status_reg); | |
199 | if ((temp & PORT_RESET) || !(temp & PORT_PE)) { | |
200 | retval = -EPIPE; | |
201 | goto done; | |
202 | } | |
203 | ||
204 | if (!(temp & PORT_SUSPEND)) | |
205 | goto done; | |
206 | ||
207 | /* Disable disconnect detection during port resume */ | |
208 | tegra_usb_phy_preresume(tegra->phy); | |
209 | ||
210 | ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25); | |
211 | ||
212 | temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS); | |
213 | /* start resume signalling */ | |
214 | ehci_writel(ehci, temp | PORT_RESUME, status_reg); | |
a448e4dc | 215 | set_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
216 | |
217 | spin_unlock_irqrestore(&ehci->lock, flags); | |
218 | msleep(20); | |
219 | spin_lock_irqsave(&ehci->lock, flags); | |
220 | ||
221 | /* Poll until the controller clears RESUME and SUSPEND */ | |
222 | if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000)) | |
223 | pr_err("%s: timeout waiting for RESUME\n", __func__); | |
224 | if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000)) | |
225 | pr_err("%s: timeout waiting for SUSPEND\n", __func__); | |
226 | ||
227 | ehci->reset_done[wIndex-1] = 0; | |
a448e4dc | 228 | clear_bit(wIndex-1, &ehci->resuming_ports); |
79ad3b5a BG |
229 | |
230 | tegra->port_resuming = 1; | |
231 | goto done; | |
232 | } | |
233 | ||
234 | spin_unlock_irqrestore(&ehci->lock, flags); | |
235 | ||
236 | /* Handle the hub control events here */ | |
237 | return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength); | |
238 | done: | |
239 | spin_unlock_irqrestore(&ehci->lock, flags); | |
240 | return retval; | |
241 | } | |
242 | ||
243 | static void tegra_ehci_restart(struct usb_hcd *hcd) | |
244 | { | |
245 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
246 | ||
247 | ehci_reset(ehci); | |
248 | ||
249 | /* setup the frame list and Async q heads */ | |
250 | ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); | |
251 | ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); | |
252 | /* setup the command register and set the controller in RUN mode */ | |
253 | ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); | |
254 | ehci->command |= CMD_RUN; | |
255 | ehci_writel(ehci, ehci->command, &ehci->regs->command); | |
256 | ||
257 | down_write(&ehci_cf_port_reset_rwsem); | |
258 | ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); | |
259 | /* flush posted writes */ | |
260 | ehci_readl(ehci, &ehci->regs->command); | |
261 | up_write(&ehci_cf_port_reset_rwsem); | |
262 | } | |
263 | ||
79ad3b5a BG |
264 | static void tegra_ehci_shutdown(struct usb_hcd *hcd) |
265 | { | |
266 | struct tegra_ehci_hcd *tegra = dev_get_drvdata(hcd->self.controller); | |
267 | ||
268 | /* ehci_shutdown touches the USB controller registers, make sure | |
269 | * controller has clocks to it */ | |
270 | if (!tegra->host_resumed) | |
271 | tegra_ehci_power_up(hcd); | |
272 | ||
273 | ehci_shutdown(hcd); | |
274 | } | |
275 | ||
276 | static int tegra_ehci_setup(struct usb_hcd *hcd) | |
277 | { | |
278 | struct ehci_hcd *ehci = hcd_to_ehci(hcd); | |
279 | int retval; | |
280 | ||
281 | /* EHCI registers start at offset 0x100 */ | |
282 | ehci->caps = hcd->regs + 0x100; | |
283 | ehci->regs = hcd->regs + 0x100 + | |
c430131a | 284 | HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); |
79ad3b5a BG |
285 | |
286 | dbg_hcs_params(ehci, "reset"); | |
287 | dbg_hcc_params(ehci, "reset"); | |
288 | ||
289 | /* cache this readonly data; minimize chip reads */ | |
290 | ehci->hcs_params = readl(&ehci->caps->hcs_params); | |
291 | ||
292 | /* switch to host mode */ | |
293 | hcd->has_tt = 1; | |
294 | ehci_reset(ehci); | |
295 | ||
296 | retval = ehci_halt(ehci); | |
297 | if (retval) | |
298 | return retval; | |
299 | ||
300 | /* data structure init */ | |
301 | retval = ehci_init(hcd); | |
302 | if (retval) | |
303 | return retval; | |
304 | ||
305 | ehci->sbrn = 0x20; | |
306 | ||
307 | ehci_port_power(ehci, 1); | |
308 | return retval; | |
309 | } | |
310 | ||
fe375774 | 311 | struct dma_aligned_buffer { |
fbf9865c RM |
312 | void *kmalloc_ptr; |
313 | void *old_xfer_buffer; | |
314 | u8 data[0]; | |
315 | }; | |
316 | ||
fe375774 | 317 | static void free_dma_aligned_buffer(struct urb *urb) |
fbf9865c | 318 | { |
fe375774 | 319 | struct dma_aligned_buffer *temp; |
fbf9865c RM |
320 | |
321 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
322 | return; | |
323 | ||
fe375774 VB |
324 | temp = container_of(urb->transfer_buffer, |
325 | struct dma_aligned_buffer, data); | |
fbf9865c | 326 | |
fe375774 | 327 | if (usb_urb_dir_in(urb)) |
fbf9865c RM |
328 | memcpy(temp->old_xfer_buffer, temp->data, |
329 | urb->transfer_buffer_length); | |
330 | urb->transfer_buffer = temp->old_xfer_buffer; | |
331 | kfree(temp->kmalloc_ptr); | |
332 | ||
333 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
334 | } | |
335 | ||
fe375774 | 336 | static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) |
fbf9865c | 337 | { |
fe375774 | 338 | struct dma_aligned_buffer *temp, *kmalloc_ptr; |
fbf9865c RM |
339 | size_t kmalloc_size; |
340 | ||
341 | if (urb->num_sgs || urb->sg || | |
342 | urb->transfer_buffer_length == 0 || | |
343 | !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1))) | |
344 | return 0; | |
345 | ||
fbf9865c RM |
346 | /* Allocate a buffer with enough padding for alignment */ |
347 | kmalloc_size = urb->transfer_buffer_length + | |
fe375774 | 348 | sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1; |
fbf9865c RM |
349 | |
350 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); | |
351 | if (!kmalloc_ptr) | |
352 | return -ENOMEM; | |
353 | ||
fe375774 | 354 | /* Position our struct dma_aligned_buffer such that data is aligned */ |
fbf9865c | 355 | temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1; |
fbf9865c RM |
356 | temp->kmalloc_ptr = kmalloc_ptr; |
357 | temp->old_xfer_buffer = urb->transfer_buffer; | |
fe375774 | 358 | if (usb_urb_dir_out(urb)) |
fbf9865c RM |
359 | memcpy(temp->data, urb->transfer_buffer, |
360 | urb->transfer_buffer_length); | |
361 | urb->transfer_buffer = temp->data; | |
362 | ||
363 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
369 | gfp_t mem_flags) | |
370 | { | |
371 | int ret; | |
372 | ||
fe375774 | 373 | ret = alloc_dma_aligned_buffer(urb, mem_flags); |
fbf9865c RM |
374 | if (ret) |
375 | return ret; | |
376 | ||
377 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
378 | if (ret) | |
fe375774 | 379 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
380 | |
381 | return ret; | |
382 | } | |
383 | ||
384 | static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
385 | { | |
386 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
fe375774 | 387 | free_dma_aligned_buffer(urb); |
fbf9865c RM |
388 | } |
389 | ||
79ad3b5a BG |
390 | static const struct hc_driver tegra_ehci_hc_driver = { |
391 | .description = hcd_name, | |
392 | .product_desc = "Tegra EHCI Host Controller", | |
393 | .hcd_priv_size = sizeof(struct ehci_hcd), | |
79ad3b5a BG |
394 | .flags = HCD_USB2 | HCD_MEMORY, |
395 | ||
c6fa0b4c | 396 | /* standard ehci functions */ |
79ad3b5a | 397 | .irq = ehci_irq, |
79ad3b5a BG |
398 | .start = ehci_run, |
399 | .stop = ehci_stop, | |
79ad3b5a BG |
400 | .urb_enqueue = ehci_urb_enqueue, |
401 | .urb_dequeue = ehci_urb_dequeue, | |
402 | .endpoint_disable = ehci_endpoint_disable, | |
403 | .endpoint_reset = ehci_endpoint_reset, | |
404 | .get_frame_number = ehci_get_frame, | |
405 | .hub_status_data = ehci_hub_status_data, | |
79ad3b5a | 406 | .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, |
c6fa0b4c VB |
407 | .relinquish_port = ehci_relinquish_port, |
408 | .port_handed_over = ehci_port_handed_over, | |
409 | ||
410 | /* modified ehci functions for tegra */ | |
411 | .reset = tegra_ehci_setup, | |
412 | .shutdown = tegra_ehci_shutdown, | |
413 | .map_urb_for_dma = tegra_ehci_map_urb_for_dma, | |
414 | .unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma, | |
415 | .hub_control = tegra_ehci_hub_control, | |
79ad3b5a | 416 | #ifdef CONFIG_PM |
ebf20de4 AS |
417 | .bus_suspend = ehci_bus_suspend, |
418 | .bus_resume = ehci_bus_resume, | |
79ad3b5a | 419 | #endif |
79ad3b5a BG |
420 | }; |
421 | ||
434103ad SW |
422 | static int setup_vbus_gpio(struct platform_device *pdev, |
423 | struct tegra_ehci_platform_data *pdata) | |
4a53f4e6 OJ |
424 | { |
425 | int err = 0; | |
426 | int gpio; | |
427 | ||
434103ad SW |
428 | gpio = pdata->vbus_gpio; |
429 | if (!gpio_is_valid(gpio)) | |
430 | gpio = of_get_named_gpio(pdev->dev.of_node, | |
431 | "nvidia,vbus-gpio", 0); | |
4a53f4e6 OJ |
432 | if (!gpio_is_valid(gpio)) |
433 | return 0; | |
434 | ||
435 | err = gpio_request(gpio, "vbus_gpio"); | |
436 | if (err) { | |
437 | dev_err(&pdev->dev, "can't request vbus gpio %d", gpio); | |
438 | return err; | |
439 | } | |
440 | err = gpio_direction_output(gpio, 1); | |
441 | if (err) { | |
442 | dev_err(&pdev->dev, "can't enable vbus\n"); | |
443 | return err; | |
444 | } | |
4a53f4e6 OJ |
445 | |
446 | return err; | |
447 | } | |
448 | ||
ebf20de4 AS |
449 | #ifdef CONFIG_PM |
450 | ||
451 | static int controller_suspend(struct device *dev) | |
452 | { | |
453 | struct tegra_ehci_hcd *tegra = | |
454 | platform_get_drvdata(to_platform_device(dev)); | |
455 | struct ehci_hcd *ehci = tegra->ehci; | |
456 | struct usb_hcd *hcd = ehci_to_hcd(ehci); | |
457 | struct ehci_regs __iomem *hw = ehci->regs; | |
458 | unsigned long flags; | |
459 | ||
460 | if (time_before(jiffies, ehci->next_statechange)) | |
461 | msleep(10); | |
462 | ||
463 | spin_lock_irqsave(&ehci->lock, flags); | |
464 | ||
465 | tegra->port_speed = (readl(&hw->port_status[0]) >> 26) & 0x3; | |
466 | ehci_halt(ehci); | |
467 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
468 | ||
469 | spin_unlock_irqrestore(&ehci->lock, flags); | |
470 | ||
471 | tegra_ehci_power_down(hcd); | |
472 | return 0; | |
473 | } | |
474 | ||
475 | static int controller_resume(struct device *dev) | |
476 | { | |
477 | struct tegra_ehci_hcd *tegra = | |
478 | platform_get_drvdata(to_platform_device(dev)); | |
479 | struct ehci_hcd *ehci = tegra->ehci; | |
480 | struct usb_hcd *hcd = ehci_to_hcd(ehci); | |
481 | struct ehci_regs __iomem *hw = ehci->regs; | |
482 | unsigned long val; | |
483 | ||
484 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
485 | tegra_ehci_power_up(hcd); | |
486 | ||
487 | if (tegra->port_speed > TEGRA_USB_PHY_PORT_SPEED_HIGH) { | |
488 | /* Wait for the phy to detect new devices | |
489 | * before we restart the controller */ | |
490 | msleep(10); | |
491 | goto restart; | |
492 | } | |
493 | ||
494 | /* Force the phy to keep data lines in suspend state */ | |
495 | tegra_ehci_phy_restore_start(tegra->phy, tegra->port_speed); | |
496 | ||
497 | /* Enable host mode */ | |
498 | tdi_reset(ehci); | |
499 | ||
500 | /* Enable Port Power */ | |
501 | val = readl(&hw->port_status[0]); | |
502 | val |= PORT_POWER; | |
503 | writel(val, &hw->port_status[0]); | |
504 | udelay(10); | |
505 | ||
506 | /* Check if the phy resume from LP0. When the phy resume from LP0 | |
507 | * USB register will be reset. */ | |
508 | if (!readl(&hw->async_next)) { | |
509 | /* Program the field PTC based on the saved speed mode */ | |
510 | val = readl(&hw->port_status[0]); | |
511 | val &= ~PORT_TEST(~0); | |
512 | if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_HIGH) | |
513 | val |= PORT_TEST_FORCE; | |
514 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_FULL) | |
515 | val |= PORT_TEST(6); | |
516 | else if (tegra->port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | |
517 | val |= PORT_TEST(7); | |
518 | writel(val, &hw->port_status[0]); | |
519 | udelay(10); | |
520 | ||
521 | /* Disable test mode by setting PTC field to NORMAL_OP */ | |
522 | val = readl(&hw->port_status[0]); | |
523 | val &= ~PORT_TEST(~0); | |
524 | writel(val, &hw->port_status[0]); | |
525 | udelay(10); | |
526 | } | |
527 | ||
528 | /* Poll until CCS is enabled */ | |
529 | if (handshake(ehci, &hw->port_status[0], PORT_CONNECT, | |
530 | PORT_CONNECT, 2000)) { | |
531 | pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__); | |
532 | goto restart; | |
533 | } | |
534 | ||
535 | /* Poll until PE is enabled */ | |
536 | if (handshake(ehci, &hw->port_status[0], PORT_PE, | |
537 | PORT_PE, 2000)) { | |
538 | pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__); | |
539 | goto restart; | |
540 | } | |
541 | ||
542 | /* Clear the PCI status, to avoid an interrupt taken upon resume */ | |
543 | val = readl(&hw->status); | |
544 | val |= STS_PCD; | |
545 | writel(val, &hw->status); | |
546 | ||
547 | /* Put controller in suspend mode by writing 1 to SUSP bit of PORTSC */ | |
548 | val = readl(&hw->port_status[0]); | |
549 | if ((val & PORT_POWER) && (val & PORT_PE)) { | |
550 | val |= PORT_SUSPEND; | |
551 | writel(val, &hw->port_status[0]); | |
552 | ||
553 | /* Wait until port suspend completes */ | |
554 | if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND, | |
555 | PORT_SUSPEND, 1000)) { | |
556 | pr_err("%s: timeout waiting for PORT_SUSPEND\n", | |
557 | __func__); | |
558 | goto restart; | |
559 | } | |
560 | } | |
561 | ||
562 | tegra_ehci_phy_restore_end(tegra->phy); | |
563 | goto done; | |
564 | ||
565 | restart: | |
566 | if (tegra->port_speed <= TEGRA_USB_PHY_PORT_SPEED_HIGH) | |
567 | tegra_ehci_phy_restore_end(tegra->phy); | |
568 | ||
569 | tegra_ehci_restart(hcd); | |
570 | ||
571 | done: | |
572 | tegra_usb_phy_preresume(tegra->phy); | |
573 | tegra->port_resuming = 1; | |
574 | return 0; | |
575 | } | |
576 | ||
577 | static int tegra_ehci_suspend(struct device *dev) | |
578 | { | |
579 | struct tegra_ehci_hcd *tegra = | |
580 | platform_get_drvdata(to_platform_device(dev)); | |
581 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
582 | int rc = 0; | |
583 | ||
584 | /* | |
585 | * When system sleep is supported and USB controller wakeup is | |
586 | * implemented: If the controller is runtime-suspended and the | |
587 | * wakeup setting needs to be changed, call pm_runtime_resume(). | |
588 | */ | |
589 | if (HCD_HW_ACCESSIBLE(hcd)) | |
590 | rc = controller_suspend(dev); | |
591 | return rc; | |
592 | } | |
593 | ||
594 | static int tegra_ehci_resume(struct device *dev) | |
595 | { | |
596 | int rc; | |
597 | ||
598 | rc = controller_resume(dev); | |
599 | if (rc == 0) { | |
600 | pm_runtime_disable(dev); | |
601 | pm_runtime_set_active(dev); | |
602 | pm_runtime_enable(dev); | |
603 | } | |
604 | return rc; | |
605 | } | |
606 | ||
607 | static int tegra_ehci_runtime_suspend(struct device *dev) | |
608 | { | |
609 | return controller_suspend(dev); | |
610 | } | |
611 | ||
612 | static int tegra_ehci_runtime_resume(struct device *dev) | |
613 | { | |
614 | return controller_resume(dev); | |
615 | } | |
616 | ||
617 | static const struct dev_pm_ops tegra_ehci_pm_ops = { | |
618 | .suspend = tegra_ehci_suspend, | |
619 | .resume = tegra_ehci_resume, | |
620 | .runtime_suspend = tegra_ehci_runtime_suspend, | |
621 | .runtime_resume = tegra_ehci_runtime_resume, | |
622 | }; | |
623 | ||
624 | #endif | |
625 | ||
4a53f4e6 OJ |
626 | static u64 tegra_ehci_dma_mask = DMA_BIT_MASK(32); |
627 | ||
79ad3b5a BG |
628 | static int tegra_ehci_probe(struct platform_device *pdev) |
629 | { | |
630 | struct resource *res; | |
631 | struct usb_hcd *hcd; | |
632 | struct tegra_ehci_hcd *tegra; | |
633 | struct tegra_ehci_platform_data *pdata; | |
634 | int err = 0; | |
635 | int irq; | |
636 | int instance = pdev->id; | |
637 | ||
638 | pdata = pdev->dev.platform_data; | |
639 | if (!pdata) { | |
640 | dev_err(&pdev->dev, "Platform data missing\n"); | |
641 | return -EINVAL; | |
642 | } | |
643 | ||
4a53f4e6 OJ |
644 | /* Right now device-tree probed devices don't get dma_mask set. |
645 | * Since shared usb code relies on it, set it here for now. | |
646 | * Once we have dma capability bindings this can go away. | |
647 | */ | |
648 | if (!pdev->dev.dma_mask) | |
649 | pdev->dev.dma_mask = &tegra_ehci_dma_mask; | |
650 | ||
434103ad | 651 | setup_vbus_gpio(pdev, pdata); |
4a53f4e6 | 652 | |
79ad3b5a BG |
653 | tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); |
654 | if (!tegra) | |
655 | return -ENOMEM; | |
656 | ||
657 | hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev, | |
658 | dev_name(&pdev->dev)); | |
659 | if (!hcd) { | |
660 | dev_err(&pdev->dev, "Unable to create HCD\n"); | |
661 | err = -ENOMEM; | |
662 | goto fail_hcd; | |
663 | } | |
664 | ||
665 | platform_set_drvdata(pdev, tegra); | |
666 | ||
667 | tegra->clk = clk_get(&pdev->dev, NULL); | |
668 | if (IS_ERR(tegra->clk)) { | |
669 | dev_err(&pdev->dev, "Can't get ehci clock\n"); | |
670 | err = PTR_ERR(tegra->clk); | |
671 | goto fail_clk; | |
672 | } | |
673 | ||
674 | err = clk_enable(tegra->clk); | |
675 | if (err) | |
676 | goto fail_clken; | |
677 | ||
678 | tegra->emc_clk = clk_get(&pdev->dev, "emc"); | |
679 | if (IS_ERR(tegra->emc_clk)) { | |
680 | dev_err(&pdev->dev, "Can't get emc clock\n"); | |
681 | err = PTR_ERR(tegra->emc_clk); | |
682 | goto fail_emc_clk; | |
683 | } | |
684 | ||
685 | clk_enable(tegra->emc_clk); | |
686 | clk_set_rate(tegra->emc_clk, 400000000); | |
687 | ||
688 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
689 | if (!res) { | |
690 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
691 | err = -ENXIO; | |
692 | goto fail_io; | |
693 | } | |
694 | hcd->rsrc_start = res->start; | |
695 | hcd->rsrc_len = resource_size(res); | |
696 | hcd->regs = ioremap(res->start, resource_size(res)); | |
697 | if (!hcd->regs) { | |
698 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
699 | err = -ENOMEM; | |
700 | goto fail_io; | |
701 | } | |
702 | ||
4a53f4e6 OJ |
703 | /* This is pretty ugly and needs to be fixed when we do only |
704 | * device-tree probing. Old code relies on the platform_device | |
705 | * numbering that we lack for device-tree-instantiated devices. | |
706 | */ | |
707 | if (instance < 0) { | |
708 | switch (res->start) { | |
709 | case TEGRA_USB_BASE: | |
710 | instance = 0; | |
711 | break; | |
712 | case TEGRA_USB2_BASE: | |
713 | instance = 1; | |
714 | break; | |
715 | case TEGRA_USB3_BASE: | |
716 | instance = 2; | |
717 | break; | |
718 | default: | |
719 | err = -ENODEV; | |
720 | dev_err(&pdev->dev, "unknown usb instance\n"); | |
721 | goto fail_phy; | |
722 | } | |
723 | } | |
724 | ||
aa607ebf SW |
725 | tegra->phy = tegra_usb_phy_open(&pdev->dev, instance, hcd->regs, |
726 | pdata->phy_config, | |
727 | TEGRA_USB_PHY_MODE_HOST); | |
79ad3b5a BG |
728 | if (IS_ERR(tegra->phy)) { |
729 | dev_err(&pdev->dev, "Failed to open USB phy\n"); | |
730 | err = -ENXIO; | |
731 | goto fail_phy; | |
732 | } | |
733 | ||
734 | err = tegra_usb_phy_power_on(tegra->phy); | |
735 | if (err) { | |
736 | dev_err(&pdev->dev, "Failed to power on the phy\n"); | |
737 | goto fail; | |
738 | } | |
739 | ||
740 | tegra->host_resumed = 1; | |
79ad3b5a BG |
741 | tegra->ehci = hcd_to_ehci(hcd); |
742 | ||
743 | irq = platform_get_irq(pdev, 0); | |
744 | if (!irq) { | |
745 | dev_err(&pdev->dev, "Failed to get IRQ\n"); | |
746 | err = -ENODEV; | |
747 | goto fail; | |
748 | } | |
79ad3b5a BG |
749 | |
750 | #ifdef CONFIG_USB_OTG_UTILS | |
751 | if (pdata->operating_mode == TEGRA_USB_OTG) { | |
b96d3b08 | 752 | tegra->transceiver = usb_get_transceiver(); |
79ad3b5a | 753 | if (tegra->transceiver) |
6e13c650 | 754 | otg_set_host(tegra->transceiver->otg, &hcd->self); |
79ad3b5a BG |
755 | } |
756 | #endif | |
757 | ||
b5dd18d8 | 758 | err = usb_add_hcd(hcd, irq, IRQF_SHARED); |
79ad3b5a BG |
759 | if (err) { |
760 | dev_err(&pdev->dev, "Failed to add USB HCD\n"); | |
761 | goto fail; | |
762 | } | |
763 | ||
ebf20de4 AS |
764 | pm_runtime_set_active(&pdev->dev); |
765 | pm_runtime_get_noresume(&pdev->dev); | |
766 | ||
767 | /* Don't skip the pm_runtime_forbid call if wakeup isn't working */ | |
768 | /* if (!pdata->power_down_on_bus_suspend) */ | |
769 | pm_runtime_forbid(&pdev->dev); | |
770 | pm_runtime_enable(&pdev->dev); | |
771 | pm_runtime_put_sync(&pdev->dev); | |
79ad3b5a BG |
772 | return err; |
773 | ||
774 | fail: | |
775 | #ifdef CONFIG_USB_OTG_UTILS | |
776 | if (tegra->transceiver) { | |
6e13c650 | 777 | otg_set_host(tegra->transceiver->otg, NULL); |
b96d3b08 | 778 | usb_put_transceiver(tegra->transceiver); |
79ad3b5a BG |
779 | } |
780 | #endif | |
781 | tegra_usb_phy_close(tegra->phy); | |
782 | fail_phy: | |
783 | iounmap(hcd->regs); | |
784 | fail_io: | |
785 | clk_disable(tegra->emc_clk); | |
786 | clk_put(tegra->emc_clk); | |
787 | fail_emc_clk: | |
788 | clk_disable(tegra->clk); | |
789 | fail_clken: | |
790 | clk_put(tegra->clk); | |
791 | fail_clk: | |
792 | usb_put_hcd(hcd); | |
793 | fail_hcd: | |
794 | kfree(tegra); | |
795 | return err; | |
796 | } | |
797 | ||
79ad3b5a BG |
798 | static int tegra_ehci_remove(struct platform_device *pdev) |
799 | { | |
800 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | |
801 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
802 | ||
803 | if (tegra == NULL || hcd == NULL) | |
804 | return -EINVAL; | |
805 | ||
ebf20de4 AS |
806 | pm_runtime_get_sync(&pdev->dev); |
807 | pm_runtime_disable(&pdev->dev); | |
808 | pm_runtime_put_noidle(&pdev->dev); | |
809 | ||
79ad3b5a BG |
810 | #ifdef CONFIG_USB_OTG_UTILS |
811 | if (tegra->transceiver) { | |
6e13c650 | 812 | otg_set_host(tegra->transceiver->otg, NULL); |
b96d3b08 | 813 | usb_put_transceiver(tegra->transceiver); |
79ad3b5a BG |
814 | } |
815 | #endif | |
816 | ||
817 | usb_remove_hcd(hcd); | |
818 | usb_put_hcd(hcd); | |
819 | ||
820 | tegra_usb_phy_close(tegra->phy); | |
821 | iounmap(hcd->regs); | |
822 | ||
823 | clk_disable(tegra->clk); | |
824 | clk_put(tegra->clk); | |
825 | ||
826 | clk_disable(tegra->emc_clk); | |
827 | clk_put(tegra->emc_clk); | |
828 | ||
829 | kfree(tegra); | |
830 | return 0; | |
831 | } | |
832 | ||
833 | static void tegra_ehci_hcd_shutdown(struct platform_device *pdev) | |
834 | { | |
835 | struct tegra_ehci_hcd *tegra = platform_get_drvdata(pdev); | |
836 | struct usb_hcd *hcd = ehci_to_hcd(tegra->ehci); | |
837 | ||
838 | if (hcd->driver->shutdown) | |
839 | hcd->driver->shutdown(hcd); | |
840 | } | |
841 | ||
4a53f4e6 OJ |
842 | static struct of_device_id tegra_ehci_of_match[] __devinitdata = { |
843 | { .compatible = "nvidia,tegra20-ehci", }, | |
844 | { }, | |
845 | }; | |
846 | ||
79ad3b5a BG |
847 | static struct platform_driver tegra_ehci_driver = { |
848 | .probe = tegra_ehci_probe, | |
849 | .remove = tegra_ehci_remove, | |
79ad3b5a BG |
850 | .shutdown = tegra_ehci_hcd_shutdown, |
851 | .driver = { | |
852 | .name = "tegra-ehci", | |
4a53f4e6 | 853 | .of_match_table = tegra_ehci_of_match, |
ebf20de4 AS |
854 | #ifdef CONFIG_PM |
855 | .pm = &tegra_ehci_pm_ops, | |
856 | #endif | |
79ad3b5a BG |
857 | } |
858 | }; |