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[PATCH] USB: ub documentation update
[deliverable/linux.git] / drivers / usb / host / ehci.h
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1da177e4
LT		 1/*
2 * Copyright (c) 2001-2002 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
22/* definitions used for the EHCI driver */
23
24/* statistics can be kept for for tuning/monitoring */
25struct ehci_stats {
26 /* irq usage */
27 unsigned long normal;
28 unsigned long error;
29 unsigned long reclaim;
30 unsigned long lost_iaa;
31
32 /* termination of urbs from core */
33 unsigned long complete;
34 unsigned long unlink;
35};
36
37/* ehci_hcd->lock guards shared data against other CPUs:
38 * ehci_hcd: async, reclaim, periodic (and shadow), ...
39 * usb_host_endpoint: hcpriv
40 * ehci_qh: qh_next, qtd_list
41 * ehci_qtd: qtd_list
42 *
43 * Also, hold this lock when talking to HC registers or
44 * when updating hw_* fields in shared qh/qtd/... structures.
45 */
46
47#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
48
49struct ehci_hcd { /* one per controller */
56c1e26d
DB		 50 /* glue to PCI and HCD framework */
51 struct ehci_caps __iomem *caps;
52 struct ehci_regs __iomem *regs;
53 struct ehci_dbg_port __iomem *debug;
54
55 __u32 hcs_params; /* cached register copy */
1da177e4
LT		 56 spinlock_t lock;
57
58 /* async schedule support */
59 struct ehci_qh *async;
60 struct ehci_qh *reclaim;
61 unsigned reclaim_ready : 1;
62 unsigned scanning : 1;
63
64 /* periodic schedule support */
65#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
66 unsigned periodic_size;
67 __le32 *periodic; /* hw periodic table */
68 dma_addr_t periodic_dma;
69 unsigned i_thresh; /* uframes HC might cache */
70
71 union ehci_shadow *pshadow; /* mirror hw periodic table */
72 int next_uframe; /* scan periodic, start here */
73 unsigned periodic_sched; /* periodic activity count */
74
75 /* per root hub port */
76 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
77
78 /* per-HC memory pools (could be per-bus, but ...) */
79 struct dma_pool *qh_pool; /* qh per active urb */
80 struct dma_pool *qtd_pool; /* one or more per qh */
81 struct dma_pool *itd_pool; /* itd per iso urb */
82 struct dma_pool *sitd_pool; /* sitd per split iso urb */
83
84 struct timer_list watchdog;
85 struct notifier_block reboot_notifier;
86 unsigned long actions;
87 unsigned stamp;
88 unsigned long next_statechange;
89 u32 command;
90
91 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */
92
1da177e4
LT		 93 /* irq statistics */
94#ifdef EHCI_STATS
95 struct ehci_stats stats;
96# define COUNT(x) do { (x)++; } while (0)
97#else
98# define COUNT(x) do {} while (0)
99#endif
100};
101
102/* convert between an HCD pointer and the corresponding EHCI_HCD */
103static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
104{
105 return (struct ehci_hcd *) (hcd->hcd_priv);
106}
107static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
108{
109 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
110}
111
112
113enum ehci_timer_action {
114 TIMER_IO_WATCHDOG,
115 TIMER_IAA_WATCHDOG,
116 TIMER_ASYNC_SHRINK,
117 TIMER_ASYNC_OFF,
118};
119
120static inline void
121timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
122{
123 clear_bit (action, &ehci->actions);
124}
125
126static inline void
127timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
128{
129 if (!test_and_set_bit (action, &ehci->actions)) {
130 unsigned long t;
131
132 switch (action) {
133 case TIMER_IAA_WATCHDOG:
134 t = EHCI_IAA_JIFFIES;
135 break;
136 case TIMER_IO_WATCHDOG:
137 t = EHCI_IO_JIFFIES;
138 break;
139 case TIMER_ASYNC_OFF:
140 t = EHCI_ASYNC_JIFFIES;
141 break;
142 // case TIMER_ASYNC_SHRINK:
143 default:
144 t = EHCI_SHRINK_JIFFIES;
145 break;
146 }
147 t += jiffies;
148 // all timings except IAA watchdog can be overridden.
149 // async queue SHRINK often precedes IAA. while it's ready
150 // to go OFF neither can matter, and afterwards the IO
151 // watchdog stops unless there's still periodic traffic.
152 if (action != TIMER_IAA_WATCHDOG
153 && t > ehci->watchdog.expires
154 && timer_pending (&ehci->watchdog))
155 return;
156 mod_timer (&ehci->watchdog, t);
157 }
158}
159
160/*-------------------------------------------------------------------------*/
161
162/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
163
164/* Section 2.2 Host Controller Capability Registers */
165struct ehci_caps {
166 /* these fields are specified as 8 and 16 bit registers,
167 * but some hosts can't perform 8 or 16 bit PCI accesses.
168 */
56c1e26d 169 u32 hc_capbase;
1da177e4
LT		 170#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
171#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
172 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
173#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
174#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
175#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
176#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
177#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
178#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
179#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
180
181 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
182#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
183#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
184#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
185#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
186#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
187#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
188 u8 portroute [8]; /* nibbles for routing - offset 0xC */
189} __attribute__ ((packed));
190
191
192/* Section 2.3 Host Controller Operational Registers */
193struct ehci_regs {
194
195 /* USBCMD: offset 0x00 */
196 u32 command;
197/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
198#define CMD_PARK (1<<11) /* enable "park" on async qh */
199#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
200#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
201#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
202#define CMD_ASE (1<<5) /* async schedule enable */
203#define CMD_PSE (1<<4) /* periodic schedule enable */
204/* 3:2 is periodic frame list size */
205#define CMD_RESET (1<<1) /* reset HC not bus */
206#define CMD_RUN (1<<0) /* start/stop HC */
207
208 /* USBSTS: offset 0x04 */
209 u32 status;
210#define STS_ASS (1<<15) /* Async Schedule Status */
211#define STS_PSS (1<<14) /* Periodic Schedule Status */
212#define STS_RECL (1<<13) /* Reclamation */
213#define STS_HALT (1<<12) /* Not running (any reason) */
214/* some bits reserved */
215 /* these STS_* flags are also intr_enable bits (USBINTR) */
216#define STS_IAA (1<<5) /* Interrupted on async advance */
217#define STS_FATAL (1<<4) /* such as some PCI access errors */
218#define STS_FLR (1<<3) /* frame list rolled over */
219#define STS_PCD (1<<2) /* port change detect */
220#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
221#define STS_INT (1<<0) /* "normal" completion (short, ...) */
222
223 /* USBINTR: offset 0x08 */
224 u32 intr_enable;
225
226 /* FRINDEX: offset 0x0C */
227 u32 frame_index; /* current microframe number */
228 /* CTRLDSSEGMENT: offset 0x10 */
229 u32 segment; /* address bits 63:32 if needed */
230 /* PERIODICLISTBASE: offset 0x14 */
231 u32 frame_list; /* points to periodic list */
232 /* ASYNCLISTADDR: offset 0x18 */
233 u32 async_next; /* address of next async queue head */
234
235 u32 reserved [9];
236
237 /* CONFIGFLAG: offset 0x40 */
238 u32 configured_flag;
239#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
240
241 /* PORTSC: offset 0x44 */
242 u32 port_status [0]; /* up to N_PORTS */
243/* 31:23 reserved */
244#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
245#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
246#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
247/* 19:16 for port testing */
248#define PORT_LED_OFF (0<<14)
249#define PORT_LED_AMBER (1<<14)
250#define PORT_LED_GREEN (2<<14)
251#define PORT_LED_MASK (3<<14)
252#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
253#define PORT_POWER (1<<12) /* true: has power (see PPC) */
254#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
255/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
256/* 9 reserved */
257#define PORT_RESET (1<<8) /* reset port */
258#define PORT_SUSPEND (1<<7) /* suspend port */
259#define PORT_RESUME (1<<6) /* resume it */
260#define PORT_OCC (1<<5) /* over current change */
261#define PORT_OC (1<<4) /* over current active */
262#define PORT_PEC (1<<3) /* port enable change */
263#define PORT_PE (1<<2) /* port enable */
264#define PORT_CSC (1<<1) /* connect status change */
265#define PORT_CONNECT (1<<0) /* device connected */
266} __attribute__ ((packed));
267
268/* Appendix C, Debug port ... intended for use with special "debug devices"
269 * that can help if there's no serial console. (nonstandard enumeration.)
270 */
271struct ehci_dbg_port {
272 u32 control;
273#define DBGP_OWNER (1<<30)
274#define DBGP_ENABLED (1<<28)
275#define DBGP_DONE (1<<16)
276#define DBGP_INUSE (1<<10)
56c1e26d 277#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
1da177e4
LT		 278# define DBGP_ERR_BAD 1
279# define DBGP_ERR_SIGNAL 2
280#define DBGP_ERROR (1<<6)
281#define DBGP_GO (1<<5)
282#define DBGP_OUT (1<<4)
283#define DBGP_LEN(x) (((x)>>0)&0x0f)
284 u32 pids;
285#define DBGP_PID_GET(x) (((x)>>16)&0xff)
56c1e26d 286#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
1da177e4
LT		 287 u32 data03;
288 u32 data47;
289 u32 address;
56c1e26d 290#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
1da177e4
LT		 291} __attribute__ ((packed));
292
293/*-------------------------------------------------------------------------*/
294
295#define QTD_NEXT(dma) cpu_to_le32((u32)dma)
296
297/*
298 * EHCI Specification 0.95 Section 3.5
299 * QTD: describe data transfer components (buffer, direction, ...)
300 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
301 *
302 * These are associated only with "QH" (Queue Head) structures,
303 * used with control, bulk, and interrupt transfers.
304 */
305struct ehci_qtd {
306 /* first part defined by EHCI spec */
307 __le32 hw_next; /* see EHCI 3.5.1 */
308 __le32 hw_alt_next; /* see EHCI 3.5.2 */
309 __le32 hw_token; /* see EHCI 3.5.3 */
310#define QTD_TOGGLE (1 << 31) /* data toggle */
311#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
312#define QTD_IOC (1 << 15) /* interrupt on complete */
313#define QTD_CERR(tok) (((tok)>>10) & 0x3)
314#define QTD_PID(tok) (((tok)>>8) & 0x3)
315#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
316#define QTD_STS_HALT (1 << 6) /* halted on error */
317#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
318#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
319#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
320#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
321#define QTD_STS_STS (1 << 1) /* split transaction state */
322#define QTD_STS_PING (1 << 0) /* issue PING? */
323 __le32 hw_buf [5]; /* see EHCI 3.5.4 */
324 __le32 hw_buf_hi [5]; /* Appendix B */
325
326 /* the rest is HCD-private */
327 dma_addr_t qtd_dma; /* qtd address */
328 struct list_head qtd_list; /* sw qtd list */
329 struct urb *urb; /* qtd's urb */
330 size_t length; /* length of buffer */
331} __attribute__ ((aligned (32)));
332
333/* mask NakCnt+T in qh->hw_alt_next */
334#define QTD_MASK __constant_cpu_to_le32 (~0x1f)
335
336#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
337
338/*-------------------------------------------------------------------------*/
339
340/* type tag from {qh,itd,sitd,fstn}->hw_next */
341#define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
342
343/* values for that type tag */
344#define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1)
345#define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1)
346#define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1)
347#define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1)
348
349/* next async queue entry, or pointer to interrupt/periodic QH */
350#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
351
352/* for periodic/async schedules and qtd lists, mark end of list */
353#define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */
354
355/*
356 * Entries in periodic shadow table are pointers to one of four kinds
357 * of data structure. That's dictated by the hardware; a type tag is
358 * encoded in the low bits of the hardware's periodic schedule. Use
359 * Q_NEXT_TYPE to get the tag.
360 *
361 * For entries in the async schedule, the type tag always says "qh".
362 */
363union ehci_shadow {
364 struct ehci_qh *qh; /* Q_TYPE_QH */
365 struct ehci_itd *itd; /* Q_TYPE_ITD */
366 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
367 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
9a5d3e98 368 __le32 *hw_next; /* (all types) */
1da177e4
LT		 369 void *ptr;
370};
371
372/*-------------------------------------------------------------------------*/
373
374/*
375 * EHCI Specification 0.95 Section 3.6
376 * QH: describes control/bulk/interrupt endpoints
377 * See Fig 3-7 "Queue Head Structure Layout".
378 *
379 * These appear in both the async and (for interrupt) periodic schedules.
380 */
381
382struct ehci_qh {
383 /* first part defined by EHCI spec */
384 __le32 hw_next; /* see EHCI 3.6.1 */
385 __le32 hw_info1; /* see EHCI 3.6.2 */
386#define QH_HEAD 0x00008000
387 __le32 hw_info2; /* see EHCI 3.6.2 */
388 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */
389
390 /* qtd overlay (hardware parts of a struct ehci_qtd) */
391 __le32 hw_qtd_next;
392 __le32 hw_alt_next;
393 __le32 hw_token;
394 __le32 hw_buf [5];
395 __le32 hw_buf_hi [5];
396
397 /* the rest is HCD-private */
398 dma_addr_t qh_dma; /* address of qh */
399 union ehci_shadow qh_next; /* ptr to qh; or periodic */
400 struct list_head qtd_list; /* sw qtd list */
401 struct ehci_qtd *dummy;
402 struct ehci_qh *reclaim; /* next to reclaim */
403
404 struct ehci_hcd *ehci;
405 struct kref kref;
406 unsigned stamp;
407
408 u8 qh_state;
409#define QH_STATE_LINKED 1 /* HC sees this */
410#define QH_STATE_UNLINK 2 /* HC may still see this */
411#define QH_STATE_IDLE 3 /* HC doesn't see this */
412#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
413#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
414
415 /* periodic schedule info */
416 u8 usecs; /* intr bandwidth */
417 u8 gap_uf; /* uframes split/csplit gap */
418 u8 c_usecs; /* ... split completion bw */
419 unsigned short period; /* polling interval */
420 unsigned short start; /* where polling starts */
421#define NO_FRAME ((unsigned short)~0) /* pick new start */
422 struct usb_device *dev; /* access to TT */
423} __attribute__ ((aligned (32)));
424
425/*-------------------------------------------------------------------------*/
426
427/* description of one iso transaction (up to 3 KB data if highspeed) */
428struct ehci_iso_packet {
429 /* These will be copied to iTD when scheduling */
430 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
431 __le32 transaction; /* itd->hw_transaction[i] |= */
432 u8 cross; /* buf crosses pages */
433 /* for full speed OUT splits */
434 u32 buf1;
435};
436
437/* temporary schedule data for packets from iso urbs (both speeds)
438 * each packet is one logical usb transaction to the device (not TT),
439 * beginning at stream->next_uframe
440 */
441struct ehci_iso_sched {
442 struct list_head td_list;
443 unsigned span;
444 struct ehci_iso_packet packet [0];
445};
446
447/*
448 * ehci_iso_stream - groups all (s)itds for this endpoint.
449 * acts like a qh would, if EHCI had them for ISO.
450 */
451struct ehci_iso_stream {
452 /* first two fields match QH, but info1 == 0 */
453 __le32 hw_next;
454 __le32 hw_info1;
455
456 u32 refcount;
457 u8 bEndpointAddress;
458 u8 highspeed;
459 u16 depth; /* depth in uframes */
460 struct list_head td_list; /* queued itds/sitds */
461 struct list_head free_list; /* list of unused itds/sitds */
462 struct usb_device *udev;
463 struct usb_host_endpoint *ep;
464
465 /* output of (re)scheduling */
466 unsigned long start; /* jiffies */
467 unsigned long rescheduled;
468 int next_uframe;
469 __le32 splits;
470
471 /* the rest is derived from the endpoint descriptor,
472 * trusting urb->interval == f(epdesc->bInterval) and
473 * including the extra info for hw_bufp[0..2]
474 */
475 u8 interval;
476 u8 usecs, c_usecs;
477 u16 maxp;
478 u16 raw_mask;
479 unsigned bandwidth;
480
481 /* This is used to initialize iTD's hw_bufp fields */
482 __le32 buf0;
483 __le32 buf1;
484 __le32 buf2;
485
486 /* this is used to initialize sITD's tt info */
487 __le32 address;
488};
489
490/*-------------------------------------------------------------------------*/
491
492/*
493 * EHCI Specification 0.95 Section 3.3
494 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
495 *
496 * Schedule records for high speed iso xfers
497 */
498struct ehci_itd {
499 /* first part defined by EHCI spec */
500 __le32 hw_next; /* see EHCI 3.3.1 */
501 __le32 hw_transaction [8]; /* see EHCI 3.3.2 */
502#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
503#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
504#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
505#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
506#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
507#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
508
509#define ITD_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
510
511 __le32 hw_bufp [7]; /* see EHCI 3.3.3 */
512 __le32 hw_bufp_hi [7]; /* Appendix B */
513
514 /* the rest is HCD-private */
515 dma_addr_t itd_dma; /* for this itd */
516 union ehci_shadow itd_next; /* ptr to periodic q entry */
517
518 struct urb *urb;
519 struct ehci_iso_stream *stream; /* endpoint's queue */
520 struct list_head itd_list; /* list of stream's itds */
521
522 /* any/all hw_transactions here may be used by that urb */
523 unsigned frame; /* where scheduled */
524 unsigned pg;
525 unsigned index[8]; /* in urb->iso_frame_desc */
526 u8 usecs[8];
527} __attribute__ ((aligned (32)));
528
529/*-------------------------------------------------------------------------*/
530
531/*
532 * EHCI Specification 0.95 Section 3.4
533 * siTD, aka split-transaction isochronous Transfer Descriptor
534 * ... describe full speed iso xfers through TT in hubs
535 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
536 */
537struct ehci_sitd {
538 /* first part defined by EHCI spec */
539 __le32 hw_next;
540/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
541 __le32 hw_fullspeed_ep; /* EHCI table 3-9 */
542 __le32 hw_uframe; /* EHCI table 3-10 */
543 __le32 hw_results; /* EHCI table 3-11 */
544#define SITD_IOC (1 << 31) /* interrupt on completion */
545#define SITD_PAGE (1 << 30) /* buffer 0/1 */
546#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
547#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
548#define SITD_STS_ERR (1 << 6) /* error from TT */
549#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
550#define SITD_STS_BABBLE (1 << 4) /* device was babbling */
551#define SITD_STS_XACT (1 << 3) /* illegal IN response */
552#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
553#define SITD_STS_STS (1 << 1) /* split transaction state */
554
555#define SITD_ACTIVE __constant_cpu_to_le32(SITD_STS_ACTIVE)
556
557 __le32 hw_buf [2]; /* EHCI table 3-12 */
558 __le32 hw_backpointer; /* EHCI table 3-13 */
559 __le32 hw_buf_hi [2]; /* Appendix B */
560
561 /* the rest is HCD-private */
562 dma_addr_t sitd_dma;
563 union ehci_shadow sitd_next; /* ptr to periodic q entry */
564
565 struct urb *urb;
566 struct ehci_iso_stream *stream; /* endpoint's queue */
567 struct list_head sitd_list; /* list of stream's sitds */
568 unsigned frame;
569 unsigned index;
570} __attribute__ ((aligned (32)));
571
572/*-------------------------------------------------------------------------*/
573
574/*
575 * EHCI Specification 0.96 Section 3.7
576 * Periodic Frame Span Traversal Node (FSTN)
577 *
578 * Manages split interrupt transactions (using TT) that span frame boundaries
579 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
580 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
581 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
582 */
583struct ehci_fstn {
584 __le32 hw_next; /* any periodic q entry */
585 __le32 hw_prev; /* qh or EHCI_LIST_END */
586
587 /* the rest is HCD-private */
588 dma_addr_t fstn_dma;
589 union ehci_shadow fstn_next; /* ptr to periodic q entry */
590} __attribute__ ((aligned (32)));
591
592/*-------------------------------------------------------------------------*/
593
594#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
595
596/*
597 * Some EHCI controllers have a Transaction Translator built into the
598 * root hub. This is a non-standard feature. Each controller will need
599 * to add code to the following inline functions, and call them as
600 * needed (mostly in root hub code).
601 */
602
603#define ehci_is_TDI(e) ((e)->is_tdi_rh_tt)
604
605/* Returns the speed of a device attached to a port on the root hub. */
606static inline unsigned int
607ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
608{
609 if (ehci_is_TDI(ehci)) {
610 switch ((portsc>>26)&3) {
611 case 0:
612 return 0;
613 case 1:
614 return (1<<USB_PORT_FEAT_LOWSPEED);
615 case 2:
616 default:
617 return (1<<USB_PORT_FEAT_HIGHSPEED);
618 }
619 }
620 return (1<<USB_PORT_FEAT_HIGHSPEED);
621}
622
623#else
624
625#define ehci_is_TDI(e) (0)
626
627#define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
628#endif
629
630/*-------------------------------------------------------------------------*/
631
632#ifndef DEBUG
633#define STUB_DEBUG_FILES
634#endif /* DEBUG */
635
636/*-------------------------------------------------------------------------*/
637
638#endif /* __LINUX_EHCI_HCD_H */
Linux kernel - Deliverables
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