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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2001-2002 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_EHCI_HCD_H | |
20 | #define __LINUX_EHCI_HCD_H | |
21 | ||
22 | /* definitions used for the EHCI driver */ | |
23 | ||
6dbd682b SR |
24 | /* |
25 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | |
26 | * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on | |
27 | * the host controller implementation. | |
28 | * | |
29 | * To facilitate the strongest possible byte-order checking from "sparse" | |
30 | * and so on, we use __leXX unless that's not practical. | |
31 | */ | |
32 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
33 | typedef __u32 __bitwise __hc32; | |
34 | typedef __u16 __bitwise __hc16; | |
35 | #else | |
36 | #define __hc32 __le32 | |
37 | #define __hc16 __le16 | |
38 | #endif | |
39 | ||
411c9403 | 40 | /* statistics can be kept for tuning/monitoring */ |
1da177e4 LT |
41 | struct ehci_stats { |
42 | /* irq usage */ | |
43 | unsigned long normal; | |
44 | unsigned long error; | |
99ac5b1e | 45 | unsigned long iaa; |
1da177e4 LT |
46 | unsigned long lost_iaa; |
47 | ||
48 | /* termination of urbs from core */ | |
49 | unsigned long complete; | |
50 | unsigned long unlink; | |
51 | }; | |
52 | ||
53 | /* ehci_hcd->lock guards shared data against other CPUs: | |
99ac5b1e | 54 | * ehci_hcd: async, unlink, periodic (and shadow), ... |
1da177e4 LT |
55 | * usb_host_endpoint: hcpriv |
56 | * ehci_qh: qh_next, qtd_list | |
57 | * ehci_qtd: qtd_list | |
58 | * | |
59 | * Also, hold this lock when talking to HC registers or | |
60 | * when updating hw_* fields in shared qh/qtd/... structures. | |
61 | */ | |
62 | ||
63 | #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ | |
64 | ||
c0c53dbc AS |
65 | /* |
66 | * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the | |
67 | * controller may be doing DMA. Lower values mean there's no DMA. | |
68 | */ | |
e8799906 AS |
69 | enum ehci_rh_state { |
70 | EHCI_RH_HALTED, | |
71 | EHCI_RH_SUSPENDED, | |
c0c53dbc AS |
72 | EHCI_RH_RUNNING, |
73 | EHCI_RH_STOPPING | |
e8799906 AS |
74 | }; |
75 | ||
d58b4bcc AS |
76 | /* |
77 | * Timer events, ordered by increasing delay length. | |
78 | * Always update event_delays_ns[] and event_handlers[] (defined in | |
79 | * ehci-timer.c) in parallel with this list. | |
80 | */ | |
81 | enum ehci_hrtimer_event { | |
31446610 | 82 | EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ |
3ca9aeba AS |
83 | EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ |
84 | EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ | |
31446610 | 85 | EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ |
d58b4bcc AS |
86 | EHCI_HRTIMER_NUM_EVENTS /* Must come last */ |
87 | }; | |
88 | #define EHCI_HRTIMER_NO_EVENT 99 | |
89 | ||
1da177e4 | 90 | struct ehci_hcd { /* one per controller */ |
d58b4bcc AS |
91 | /* timing support */ |
92 | enum ehci_hrtimer_event next_hrtimer_event; | |
93 | unsigned enabled_hrtimer_events; | |
94 | ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; | |
95 | struct hrtimer hrtimer; | |
96 | ||
3ca9aeba | 97 | int PSS_poll_count; |
31446610 | 98 | int ASS_poll_count; |
3ca9aeba | 99 | |
56c1e26d DB |
100 | /* glue to PCI and HCD framework */ |
101 | struct ehci_caps __iomem *caps; | |
102 | struct ehci_regs __iomem *regs; | |
103 | struct ehci_dbg_port __iomem *debug; | |
104 | ||
105 | __u32 hcs_params; /* cached register copy */ | |
1da177e4 | 106 | spinlock_t lock; |
e8799906 | 107 | enum ehci_rh_state rh_state; |
1da177e4 LT |
108 | |
109 | /* async schedule support */ | |
110 | struct ehci_qh *async; | |
3d091a6f | 111 | struct ehci_qh *dummy; /* For AMD quirk use */ |
99ac5b1e | 112 | struct ehci_qh *async_unlink; |
2f5bb665 | 113 | struct ehci_qh *async_unlink_last; |
004c1968 | 114 | struct ehci_qh *qh_scan_next; |
1da177e4 | 115 | unsigned scanning : 1; |
31446610 | 116 | unsigned async_count; /* async activity count */ |
1da177e4 LT |
117 | |
118 | /* periodic schedule support */ | |
119 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ | |
120 | unsigned periodic_size; | |
6dbd682b | 121 | __hc32 *periodic; /* hw periodic table */ |
1da177e4 LT |
122 | dma_addr_t periodic_dma; |
123 | unsigned i_thresh; /* uframes HC might cache */ | |
124 | ||
125 | union ehci_shadow *pshadow; /* mirror hw periodic table */ | |
126 | int next_uframe; /* scan periodic, start here */ | |
3ca9aeba | 127 | unsigned periodic_count; /* periodic activity count */ |
cc62a7eb KS |
128 | unsigned uframe_periodic_max; /* max periodic time per uframe */ |
129 | ||
1da177e4 | 130 | |
0e5f231b | 131 | /* list of itds & sitds completed while clock_frame was still active */ |
9aa09d2f | 132 | struct list_head cached_itd_list; |
0e5f231b | 133 | struct list_head cached_sitd_list; |
9aa09d2f KW |
134 | unsigned clock_frame; |
135 | ||
1da177e4 LT |
136 | /* per root hub port */ |
137 | unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; | |
383975d7 | 138 | |
57e06c11 AS |
139 | /* bit vectors (one bit per port) */ |
140 | unsigned long bus_suspended; /* which ports were | |
141 | already suspended at the start of a bus suspend */ | |
142 | unsigned long companion_ports; /* which ports are | |
143 | dedicated to the companion controller */ | |
383975d7 AS |
144 | unsigned long owned_ports; /* which ports are |
145 | owned by the companion during a bus suspend */ | |
d1f114d1 AS |
146 | unsigned long port_c_suspend; /* which ports have |
147 | the change-suspend feature turned on */ | |
eafe5b99 AS |
148 | unsigned long suspended_ports; /* which ports are |
149 | suspended */ | |
a448e4dc AS |
150 | unsigned long resuming_ports; /* which ports have |
151 | started to resume */ | |
1da177e4 LT |
152 | |
153 | /* per-HC memory pools (could be per-bus, but ...) */ | |
154 | struct dma_pool *qh_pool; /* qh per active urb */ | |
155 | struct dma_pool *qtd_pool; /* one or more per qh */ | |
156 | struct dma_pool *itd_pool; /* itd per iso urb */ | |
157 | struct dma_pool *sitd_pool; /* sitd per split iso urb */ | |
158 | ||
07d29b63 | 159 | struct timer_list iaa_watchdog; |
1da177e4 | 160 | struct timer_list watchdog; |
1da177e4 | 161 | unsigned long actions; |
1e12c910 | 162 | unsigned periodic_stamp; |
68335e81 | 163 | unsigned random_frame; |
1da177e4 | 164 | unsigned long next_statechange; |
ee4ecb8a | 165 | ktime_t last_periodic_enable; |
1da177e4 LT |
166 | u32 command; |
167 | ||
8cd42e97 | 168 | /* SILICON QUIRKS */ |
f8aeb3bb | 169 | unsigned no_selective_suspend:1; |
8cd42e97 | 170 | unsigned has_fsl_port_bug:1; /* FreeScale */ |
083522d7 | 171 | unsigned big_endian_mmio:1; |
6dbd682b | 172 | unsigned big_endian_desc:1; |
c430131a | 173 | unsigned big_endian_capbase:1; |
796bcae7 | 174 | unsigned has_amcc_usb23:1; |
403dbd36 | 175 | unsigned need_io_watchdog:1; |
ad93562b | 176 | unsigned amd_pll_fix:1; |
ae68a83b | 177 | unsigned fs_i_thresh:1; /* Intel iso scheduling */ |
3d091a6f | 178 | unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ |
2f7ac6c1 | 179 | unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ |
68aa95d5 | 180 | unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ |
796bcae7 VB |
181 | |
182 | /* required for usb32 quirk */ | |
183 | #define OHCI_CTRL_HCFS (3 << 6) | |
184 | #define OHCI_USB_OPER (2 << 6) | |
185 | #define OHCI_USB_SUSPEND (3 << 6) | |
186 | ||
187 | #define OHCI_HCCTRL_OFFSET 0x4 | |
188 | #define OHCI_HCCTRL_LEN 0x4 | |
189 | __hc32 *ohci_hcctrl_reg; | |
331ac6b2 | 190 | unsigned has_hostpc:1; |
48f24970 | 191 | unsigned has_lpm:1; /* support link power management */ |
5a9cdf33 | 192 | unsigned has_ppcd:1; /* support per-port change bits */ |
f8aeb3bb | 193 | u8 sbrn; /* packed release number */ |
1da177e4 | 194 | |
1da177e4 LT |
195 | /* irq statistics */ |
196 | #ifdef EHCI_STATS | |
197 | struct ehci_stats stats; | |
198 | # define COUNT(x) do { (x)++; } while (0) | |
199 | #else | |
200 | # define COUNT(x) do {} while (0) | |
694cc208 TJ |
201 | #endif |
202 | ||
203 | /* debug files */ | |
204 | #ifdef DEBUG | |
205 | struct dentry *debug_dir; | |
1da177e4 LT |
206 | #endif |
207 | }; | |
208 | ||
53bd6a60 | 209 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
1da177e4 LT |
210 | static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) |
211 | { | |
212 | return (struct ehci_hcd *) (hcd->hcd_priv); | |
213 | } | |
214 | static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) | |
215 | { | |
216 | return container_of ((void *) ehci, struct usb_hcd, hcd_priv); | |
217 | } | |
218 | ||
219 | ||
07d29b63 AS |
220 | static inline void |
221 | iaa_watchdog_start(struct ehci_hcd *ehci) | |
222 | { | |
223 | WARN_ON(timer_pending(&ehci->iaa_watchdog)); | |
224 | mod_timer(&ehci->iaa_watchdog, | |
225 | jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); | |
226 | } | |
227 | ||
228 | static inline void iaa_watchdog_done(struct ehci_hcd *ehci) | |
229 | { | |
230 | del_timer(&ehci->iaa_watchdog); | |
231 | } | |
232 | ||
1da177e4 LT |
233 | enum ehci_timer_action { |
234 | TIMER_IO_WATCHDOG, | |
1da177e4 | 235 | TIMER_ASYNC_SHRINK, |
1da177e4 LT |
236 | }; |
237 | ||
238 | static inline void | |
239 | timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) | |
240 | { | |
241 | clear_bit (action, &ehci->actions); | |
242 | } | |
243 | ||
0e5f231b | 244 | static void free_cached_lists(struct ehci_hcd *ehci); |
9aa09d2f | 245 | |
1da177e4 LT |
246 | /*-------------------------------------------------------------------------*/ |
247 | ||
0af36739 | 248 | #include <linux/usb/ehci_def.h> |
1da177e4 LT |
249 | |
250 | /*-------------------------------------------------------------------------*/ | |
251 | ||
6dbd682b | 252 | #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) |
1da177e4 LT |
253 | |
254 | /* | |
255 | * EHCI Specification 0.95 Section 3.5 | |
53bd6a60 | 256 | * QTD: describe data transfer components (buffer, direction, ...) |
1da177e4 LT |
257 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
258 | * | |
259 | * These are associated only with "QH" (Queue Head) structures, | |
260 | * used with control, bulk, and interrupt transfers. | |
261 | */ | |
262 | struct ehci_qtd { | |
263 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
264 | __hc32 hw_next; /* see EHCI 3.5.1 */ |
265 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ | |
266 | __hc32 hw_token; /* see EHCI 3.5.3 */ | |
1da177e4 LT |
267 | #define QTD_TOGGLE (1 << 31) /* data toggle */ |
268 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) | |
269 | #define QTD_IOC (1 << 15) /* interrupt on complete */ | |
270 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) | |
271 | #define QTD_PID(tok) (((tok)>>8) & 0x3) | |
272 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
273 | #define QTD_STS_HALT (1 << 6) /* halted on error */ | |
274 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
275 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ | |
276 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ | |
277 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
278 | #define QTD_STS_STS (1 << 1) /* split transaction state */ | |
279 | #define QTD_STS_PING (1 << 0) /* issue PING? */ | |
6dbd682b SR |
280 | |
281 | #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) | |
282 | #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) | |
283 | #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) | |
284 | ||
285 | __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ | |
286 | __hc32 hw_buf_hi [5]; /* Appendix B */ | |
1da177e4 LT |
287 | |
288 | /* the rest is HCD-private */ | |
289 | dma_addr_t qtd_dma; /* qtd address */ | |
290 | struct list_head qtd_list; /* sw qtd list */ | |
291 | struct urb *urb; /* qtd's urb */ | |
292 | size_t length; /* length of buffer */ | |
293 | } __attribute__ ((aligned (32))); | |
294 | ||
295 | /* mask NakCnt+T in qh->hw_alt_next */ | |
6dbd682b | 296 | #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) |
1da177e4 LT |
297 | |
298 | #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) | |
299 | ||
300 | /*-------------------------------------------------------------------------*/ | |
301 | ||
302 | /* type tag from {qh,itd,sitd,fstn}->hw_next */ | |
6dbd682b | 303 | #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) |
1da177e4 | 304 | |
6dbd682b SR |
305 | /* |
306 | * Now the following defines are not converted using the | |
551509d2 | 307 | * cpu_to_le32() macro anymore, since we have to support |
6dbd682b SR |
308 | * "dynamic" switching between be and le support, so that the driver |
309 | * can be used on one system with SoC EHCI controller using big-endian | |
310 | * descriptors as well as a normal little-endian PCI EHCI controller. | |
311 | */ | |
1da177e4 | 312 | /* values for that type tag */ |
6dbd682b SR |
313 | #define Q_TYPE_ITD (0 << 1) |
314 | #define Q_TYPE_QH (1 << 1) | |
315 | #define Q_TYPE_SITD (2 << 1) | |
316 | #define Q_TYPE_FSTN (3 << 1) | |
1da177e4 LT |
317 | |
318 | /* next async queue entry, or pointer to interrupt/periodic QH */ | |
6dbd682b | 319 | #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) |
1da177e4 LT |
320 | |
321 | /* for periodic/async schedules and qtd lists, mark end of list */ | |
6dbd682b | 322 | #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ |
1da177e4 LT |
323 | |
324 | /* | |
325 | * Entries in periodic shadow table are pointers to one of four kinds | |
326 | * of data structure. That's dictated by the hardware; a type tag is | |
327 | * encoded in the low bits of the hardware's periodic schedule. Use | |
328 | * Q_NEXT_TYPE to get the tag. | |
329 | * | |
330 | * For entries in the async schedule, the type tag always says "qh". | |
331 | */ | |
332 | union ehci_shadow { | |
53bd6a60 | 333 | struct ehci_qh *qh; /* Q_TYPE_QH */ |
1da177e4 LT |
334 | struct ehci_itd *itd; /* Q_TYPE_ITD */ |
335 | struct ehci_sitd *sitd; /* Q_TYPE_SITD */ | |
336 | struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ | |
6dbd682b | 337 | __hc32 *hw_next; /* (all types) */ |
1da177e4 LT |
338 | void *ptr; |
339 | }; | |
340 | ||
341 | /*-------------------------------------------------------------------------*/ | |
342 | ||
343 | /* | |
344 | * EHCI Specification 0.95 Section 3.6 | |
345 | * QH: describes control/bulk/interrupt endpoints | |
346 | * See Fig 3-7 "Queue Head Structure Layout". | |
347 | * | |
348 | * These appear in both the async and (for interrupt) periodic schedules. | |
349 | */ | |
350 | ||
3807e26d AD |
351 | /* first part defined by EHCI spec */ |
352 | struct ehci_qh_hw { | |
6dbd682b SR |
353 | __hc32 hw_next; /* see EHCI 3.6.1 */ |
354 | __hc32 hw_info1; /* see EHCI 3.6.2 */ | |
4c53de72 AS |
355 | #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ |
356 | #define QH_HEAD (1 << 15) /* Head of async reclamation list */ | |
357 | #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ | |
358 | #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ | |
359 | #define QH_LOW_SPEED (1 << 12) | |
360 | #define QH_FULL_SPEED (0 << 12) | |
361 | #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ | |
6dbd682b | 362 | __hc32 hw_info2; /* see EHCI 3.6.2 */ |
7dedacf4 DB |
363 | #define QH_SMASK 0x000000ff |
364 | #define QH_CMASK 0x0000ff00 | |
365 | #define QH_HUBADDR 0x007f0000 | |
366 | #define QH_HUBPORT 0x3f800000 | |
367 | #define QH_MULT 0xc0000000 | |
6dbd682b | 368 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
53bd6a60 | 369 | |
1da177e4 | 370 | /* qtd overlay (hardware parts of a struct ehci_qtd) */ |
6dbd682b SR |
371 | __hc32 hw_qtd_next; |
372 | __hc32 hw_alt_next; | |
373 | __hc32 hw_token; | |
374 | __hc32 hw_buf [5]; | |
375 | __hc32 hw_buf_hi [5]; | |
3807e26d | 376 | } __attribute__ ((aligned(32))); |
1da177e4 | 377 | |
3807e26d AD |
378 | struct ehci_qh { |
379 | struct ehci_qh_hw *hw; | |
1da177e4 LT |
380 | /* the rest is HCD-private */ |
381 | dma_addr_t qh_dma; /* address of qh */ | |
382 | union ehci_shadow qh_next; /* ptr to qh; or periodic */ | |
383 | struct list_head qtd_list; /* sw qtd list */ | |
384 | struct ehci_qtd *dummy; | |
99ac5b1e | 385 | struct ehci_qh *unlink_next; /* next on unlink list */ |
1da177e4 | 386 | |
004c1968 | 387 | unsigned long unlink_time; |
1da177e4 LT |
388 | unsigned stamp; |
389 | ||
3a44494e | 390 | u8 needs_rescan; /* Dequeue during giveback */ |
1da177e4 LT |
391 | u8 qh_state; |
392 | #define QH_STATE_LINKED 1 /* HC sees this */ | |
393 | #define QH_STATE_UNLINK 2 /* HC may still see this */ | |
394 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ | |
99ac5b1e | 395 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ |
1da177e4 LT |
396 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ |
397 | ||
a2c2706e AS |
398 | u8 xacterrs; /* XactErr retry counter */ |
399 | #define QH_XACTERR_MAX 32 /* XactErr retry limit */ | |
400 | ||
1da177e4 LT |
401 | /* periodic schedule info */ |
402 | u8 usecs; /* intr bandwidth */ | |
403 | u8 gap_uf; /* uframes split/csplit gap */ | |
404 | u8 c_usecs; /* ... split completion bw */ | |
d0384200 | 405 | u16 tt_usecs; /* tt downstream bandwidth */ |
1da177e4 LT |
406 | unsigned short period; /* polling interval */ |
407 | unsigned short start; /* where polling starts */ | |
408 | #define NO_FRAME ((unsigned short)~0) /* pick new start */ | |
914b7012 | 409 | |
1da177e4 | 410 | struct usb_device *dev; /* access to TT */ |
e04f5f7e | 411 | unsigned is_out:1; /* bulk or intr OUT */ |
914b7012 | 412 | unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ |
3807e26d | 413 | }; |
1da177e4 LT |
414 | |
415 | /*-------------------------------------------------------------------------*/ | |
416 | ||
417 | /* description of one iso transaction (up to 3 KB data if highspeed) */ | |
418 | struct ehci_iso_packet { | |
419 | /* These will be copied to iTD when scheduling */ | |
420 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ | |
6dbd682b | 421 | __hc32 transaction; /* itd->hw_transaction[i] |= */ |
1da177e4 LT |
422 | u8 cross; /* buf crosses pages */ |
423 | /* for full speed OUT splits */ | |
424 | u32 buf1; | |
425 | }; | |
426 | ||
427 | /* temporary schedule data for packets from iso urbs (both speeds) | |
428 | * each packet is one logical usb transaction to the device (not TT), | |
429 | * beginning at stream->next_uframe | |
430 | */ | |
431 | struct ehci_iso_sched { | |
432 | struct list_head td_list; | |
433 | unsigned span; | |
434 | struct ehci_iso_packet packet [0]; | |
435 | }; | |
436 | ||
437 | /* | |
438 | * ehci_iso_stream - groups all (s)itds for this endpoint. | |
439 | * acts like a qh would, if EHCI had them for ISO. | |
440 | */ | |
441 | struct ehci_iso_stream { | |
1082f57a CL |
442 | /* first field matches ehci_hq, but is NULL */ |
443 | struct ehci_qh_hw *hw; | |
1da177e4 LT |
444 | |
445 | u32 refcount; | |
446 | u8 bEndpointAddress; | |
447 | u8 highspeed; | |
1da177e4 LT |
448 | struct list_head td_list; /* queued itds/sitds */ |
449 | struct list_head free_list; /* list of unused itds/sitds */ | |
450 | struct usb_device *udev; | |
53bd6a60 | 451 | struct usb_host_endpoint *ep; |
1da177e4 LT |
452 | |
453 | /* output of (re)scheduling */ | |
1da177e4 | 454 | int next_uframe; |
6dbd682b | 455 | __hc32 splits; |
1da177e4 LT |
456 | |
457 | /* the rest is derived from the endpoint descriptor, | |
458 | * trusting urb->interval == f(epdesc->bInterval) and | |
459 | * including the extra info for hw_bufp[0..2] | |
460 | */ | |
1da177e4 | 461 | u8 usecs, c_usecs; |
c06d4dcf | 462 | u16 interval; |
d0384200 | 463 | u16 tt_usecs; |
1da177e4 LT |
464 | u16 maxp; |
465 | u16 raw_mask; | |
466 | unsigned bandwidth; | |
467 | ||
468 | /* This is used to initialize iTD's hw_bufp fields */ | |
6dbd682b SR |
469 | __hc32 buf0; |
470 | __hc32 buf1; | |
471 | __hc32 buf2; | |
1da177e4 LT |
472 | |
473 | /* this is used to initialize sITD's tt info */ | |
6dbd682b | 474 | __hc32 address; |
1da177e4 LT |
475 | }; |
476 | ||
477 | /*-------------------------------------------------------------------------*/ | |
478 | ||
479 | /* | |
480 | * EHCI Specification 0.95 Section 3.3 | |
481 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" | |
482 | * | |
483 | * Schedule records for high speed iso xfers | |
484 | */ | |
485 | struct ehci_itd { | |
486 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
487 | __hc32 hw_next; /* see EHCI 3.3.1 */ |
488 | __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ | |
1da177e4 LT |
489 | #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
490 | #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ | |
491 | #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ | |
492 | #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ | |
493 | #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) | |
494 | #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ | |
495 | ||
6dbd682b | 496 | #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) |
1da177e4 | 497 | |
6dbd682b SR |
498 | __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ |
499 | __hc32 hw_bufp_hi [7]; /* Appendix B */ | |
1da177e4 LT |
500 | |
501 | /* the rest is HCD-private */ | |
502 | dma_addr_t itd_dma; /* for this itd */ | |
503 | union ehci_shadow itd_next; /* ptr to periodic q entry */ | |
504 | ||
505 | struct urb *urb; | |
506 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
507 | struct list_head itd_list; /* list of stream's itds */ | |
508 | ||
509 | /* any/all hw_transactions here may be used by that urb */ | |
510 | unsigned frame; /* where scheduled */ | |
511 | unsigned pg; | |
512 | unsigned index[8]; /* in urb->iso_frame_desc */ | |
1da177e4 LT |
513 | } __attribute__ ((aligned (32))); |
514 | ||
515 | /*-------------------------------------------------------------------------*/ | |
516 | ||
517 | /* | |
53bd6a60 | 518 | * EHCI Specification 0.95 Section 3.4 |
1da177e4 LT |
519 | * siTD, aka split-transaction isochronous Transfer Descriptor |
520 | * ... describe full speed iso xfers through TT in hubs | |
521 | * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) | |
522 | */ | |
523 | struct ehci_sitd { | |
524 | /* first part defined by EHCI spec */ | |
6dbd682b | 525 | __hc32 hw_next; |
1da177e4 | 526 | /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ |
6dbd682b SR |
527 | __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ |
528 | __hc32 hw_uframe; /* EHCI table 3-10 */ | |
529 | __hc32 hw_results; /* EHCI table 3-11 */ | |
1da177e4 LT |
530 | #define SITD_IOC (1 << 31) /* interrupt on completion */ |
531 | #define SITD_PAGE (1 << 30) /* buffer 0/1 */ | |
532 | #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) | |
533 | #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
534 | #define SITD_STS_ERR (1 << 6) /* error from TT */ | |
535 | #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
536 | #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ | |
537 | #define SITD_STS_XACT (1 << 3) /* illegal IN response */ | |
538 | #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
539 | #define SITD_STS_STS (1 << 1) /* split transaction state */ | |
540 | ||
6dbd682b | 541 | #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) |
1da177e4 | 542 | |
6dbd682b SR |
543 | __hc32 hw_buf [2]; /* EHCI table 3-12 */ |
544 | __hc32 hw_backpointer; /* EHCI table 3-13 */ | |
545 | __hc32 hw_buf_hi [2]; /* Appendix B */ | |
1da177e4 LT |
546 | |
547 | /* the rest is HCD-private */ | |
548 | dma_addr_t sitd_dma; | |
549 | union ehci_shadow sitd_next; /* ptr to periodic q entry */ | |
550 | ||
551 | struct urb *urb; | |
552 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
553 | struct list_head sitd_list; /* list of stream's sitds */ | |
554 | unsigned frame; | |
555 | unsigned index; | |
556 | } __attribute__ ((aligned (32))); | |
557 | ||
558 | /*-------------------------------------------------------------------------*/ | |
559 | ||
560 | /* | |
561 | * EHCI Specification 0.96 Section 3.7 | |
562 | * Periodic Frame Span Traversal Node (FSTN) | |
563 | * | |
564 | * Manages split interrupt transactions (using TT) that span frame boundaries | |
565 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN | |
566 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until | |
567 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. | |
568 | */ | |
569 | struct ehci_fstn { | |
6dbd682b SR |
570 | __hc32 hw_next; /* any periodic q entry */ |
571 | __hc32 hw_prev; /* qh or EHCI_LIST_END */ | |
1da177e4 LT |
572 | |
573 | /* the rest is HCD-private */ | |
574 | dma_addr_t fstn_dma; | |
575 | union ehci_shadow fstn_next; /* ptr to periodic q entry */ | |
576 | } __attribute__ ((aligned (32))); | |
577 | ||
578 | /*-------------------------------------------------------------------------*/ | |
579 | ||
16032c4f AS |
580 | /* Prepare the PORTSC wakeup flags during controller suspend/resume */ |
581 | ||
4147200d AS |
582 | #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ |
583 | ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); | |
16032c4f | 584 | |
4147200d AS |
585 | #define ehci_prepare_ports_for_controller_resume(ehci) \ |
586 | ehci_adjust_port_wakeup_flags(ehci, false, false); | |
16032c4f AS |
587 | |
588 | /*-------------------------------------------------------------------------*/ | |
589 | ||
1da177e4 LT |
590 | #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT |
591 | ||
592 | /* | |
593 | * Some EHCI controllers have a Transaction Translator built into the | |
594 | * root hub. This is a non-standard feature. Each controller will need | |
595 | * to add code to the following inline functions, and call them as | |
596 | * needed (mostly in root hub code). | |
597 | */ | |
598 | ||
a8e51775 | 599 | #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) |
1da177e4 LT |
600 | |
601 | /* Returns the speed of a device attached to a port on the root hub. */ | |
602 | static inline unsigned int | |
603 | ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) | |
604 | { | |
605 | if (ehci_is_TDI(ehci)) { | |
331ac6b2 | 606 | switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { |
1da177e4 LT |
607 | case 0: |
608 | return 0; | |
609 | case 1: | |
288ead45 | 610 | return USB_PORT_STAT_LOW_SPEED; |
1da177e4 LT |
611 | case 2: |
612 | default: | |
288ead45 | 613 | return USB_PORT_STAT_HIGH_SPEED; |
1da177e4 LT |
614 | } |
615 | } | |
288ead45 | 616 | return USB_PORT_STAT_HIGH_SPEED; |
1da177e4 LT |
617 | } |
618 | ||
619 | #else | |
620 | ||
621 | #define ehci_is_TDI(e) (0) | |
622 | ||
288ead45 | 623 | #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED |
1da177e4 LT |
624 | #endif |
625 | ||
8cd42e97 KG |
626 | /*-------------------------------------------------------------------------*/ |
627 | ||
628 | #ifdef CONFIG_PPC_83xx | |
629 | /* Some Freescale processors have an erratum in which the TT | |
630 | * port number in the queue head was 0..N-1 instead of 1..N. | |
631 | */ | |
632 | #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) | |
633 | #else | |
634 | #define ehci_has_fsl_portno_bug(e) (0) | |
635 | #endif | |
636 | ||
083522d7 BH |
637 | /* |
638 | * While most USB host controllers implement their registers in | |
639 | * little-endian format, a minority (celleb companion chip) implement | |
640 | * them in big endian format. | |
641 | * | |
642 | * This attempts to support either format at compile time without a | |
643 | * runtime penalty, or both formats with the additional overhead | |
644 | * of checking a flag bit. | |
c430131a JA |
645 | * |
646 | * ehci_big_endian_capbase is a special quirk for controllers that | |
647 | * implement the HC capability registers as separate registers and not | |
648 | * as fields of a 32-bit register. | |
083522d7 BH |
649 | */ |
650 | ||
651 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
652 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) | |
c430131a | 653 | #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) |
083522d7 BH |
654 | #else |
655 | #define ehci_big_endian_mmio(e) 0 | |
c430131a | 656 | #define ehci_big_endian_capbase(e) 0 |
083522d7 BH |
657 | #endif |
658 | ||
6dbd682b SR |
659 | /* |
660 | * Big-endian read/write functions are arch-specific. | |
661 | * Other arches can be added if/when they're needed. | |
6dbd682b | 662 | */ |
91bc4d31 VB |
663 | #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) |
664 | #define readl_be(addr) __raw_readl((__force unsigned *)addr) | |
665 | #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) | |
666 | #endif | |
667 | ||
6dbd682b SR |
668 | static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, |
669 | __u32 __iomem * regs) | |
083522d7 | 670 | { |
d728e327 | 671 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 672 | return ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
673 | readl_be(regs) : |
674 | readl(regs); | |
d728e327 | 675 | #else |
68f50e52 | 676 | return readl(regs); |
d728e327 | 677 | #endif |
083522d7 BH |
678 | } |
679 | ||
6dbd682b SR |
680 | static inline void ehci_writel(const struct ehci_hcd *ehci, |
681 | const unsigned int val, __u32 __iomem *regs) | |
083522d7 | 682 | { |
d728e327 | 683 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 684 | ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
685 | writel_be(val, regs) : |
686 | writel(val, regs); | |
d728e327 | 687 | #else |
68f50e52 | 688 | writel(val, regs); |
d728e327 | 689 | #endif |
083522d7 | 690 | } |
8cd42e97 | 691 | |
796bcae7 VB |
692 | /* |
693 | * On certain ppc-44x SoC there is a HW issue, that could only worked around with | |
694 | * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. | |
25985edc | 695 | * Other common bits are dependent on has_amcc_usb23 quirk flag. |
796bcae7 VB |
696 | */ |
697 | #ifdef CONFIG_44x | |
698 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
699 | { | |
700 | u32 hc_control; | |
701 | ||
702 | hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); | |
703 | if (operational) | |
704 | hc_control |= OHCI_USB_OPER; | |
705 | else | |
706 | hc_control |= OHCI_USB_SUSPEND; | |
707 | ||
708 | writel_be(hc_control, ehci->ohci_hcctrl_reg); | |
709 | (void) readl_be(ehci->ohci_hcctrl_reg); | |
710 | } | |
711 | #else | |
712 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
713 | { } | |
714 | #endif | |
715 | ||
1da177e4 LT |
716 | /*-------------------------------------------------------------------------*/ |
717 | ||
6dbd682b SR |
718 | /* |
719 | * The AMCC 440EPx not only implements its EHCI registers in big-endian | |
720 | * format, but also its DMA data structures (descriptors). | |
721 | * | |
722 | * EHCI controllers accessed through PCI work normally (little-endian | |
723 | * everywhere), so we won't bother supporting a BE-only mode for now. | |
724 | */ | |
725 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
726 | #define ehci_big_endian_desc(e) ((e)->big_endian_desc) | |
727 | ||
728 | /* cpu to ehci */ | |
729 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
730 | { | |
731 | return ehci_big_endian_desc(ehci) | |
732 | ? (__force __hc32)cpu_to_be32(x) | |
733 | : (__force __hc32)cpu_to_le32(x); | |
734 | } | |
735 | ||
736 | /* ehci to cpu */ | |
737 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
738 | { | |
739 | return ehci_big_endian_desc(ehci) | |
740 | ? be32_to_cpu((__force __be32)x) | |
741 | : le32_to_cpu((__force __le32)x); | |
742 | } | |
743 | ||
744 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
745 | { | |
746 | return ehci_big_endian_desc(ehci) | |
747 | ? be32_to_cpup((__force __be32 *)x) | |
748 | : le32_to_cpup((__force __le32 *)x); | |
749 | } | |
750 | ||
751 | #else | |
752 | ||
753 | /* cpu to ehci */ | |
754 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
755 | { | |
756 | return cpu_to_le32(x); | |
757 | } | |
758 | ||
759 | /* ehci to cpu */ | |
760 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
761 | { | |
762 | return le32_to_cpu(x); | |
763 | } | |
764 | ||
765 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
766 | { | |
767 | return le32_to_cpup(x); | |
768 | } | |
769 | ||
770 | #endif | |
771 | ||
772 | /*-------------------------------------------------------------------------*/ | |
773 | ||
68aa95d5 AS |
774 | #ifdef CONFIG_PCI |
775 | ||
776 | /* For working around the MosChip frame-index-register bug */ | |
777 | static unsigned ehci_read_frame_index(struct ehci_hcd *ehci); | |
778 | ||
779 | #else | |
780 | ||
781 | static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci) | |
782 | { | |
783 | return ehci_readl(ehci, &ehci->regs->frame_index); | |
784 | } | |
785 | ||
786 | #endif | |
787 | ||
788 | /*-------------------------------------------------------------------------*/ | |
789 | ||
1da177e4 LT |
790 | #ifndef DEBUG |
791 | #define STUB_DEBUG_FILES | |
792 | #endif /* DEBUG */ | |
793 | ||
794 | /*-------------------------------------------------------------------------*/ | |
795 | ||
796 | #endif /* __LINUX_EHCI_HCD_H */ |