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USB: EHCI: fix up root-hub TT mess
[deliverable/linux.git] / drivers / usb / host / ehci.h
CommitLineData
1da177e4
LT		 1/*
2 * Copyright (c) 2001-2002 by David Brownell
53bd6a60 3 *
1da177e4
LT		 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
22/* definitions used for the EHCI driver */
23
6dbd682b
SR		 24/*
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
28 *
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
31 */
32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33typedef __u32 __bitwise __hc32;
34typedef __u16 __bitwise __hc16;
35#else
36#define __hc32 __le32
37#define __hc16 __le16
38#endif
39
1da177e4
LT		 40/* statistics can be kept for for tuning/monitoring */
41struct ehci_stats {
42 /* irq usage */
43 unsigned long normal;
44 unsigned long error;
45 unsigned long reclaim;
46 unsigned long lost_iaa;
47
48 /* termination of urbs from core */
49 unsigned long complete;
50 unsigned long unlink;
51};
52
53/* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
57 * ehci_qtd: qtd_list
58 *
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
61 */
62
63#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
64
65struct ehci_hcd { /* one per controller */
56c1e26d
DB		 66 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
70
71 __u32 hcs_params; /* cached register copy */
1da177e4
LT		 72 spinlock_t lock;
73
74 /* async schedule support */
75 struct ehci_qh *async;
76 struct ehci_qh *reclaim;
1da177e4
LT		 77 unsigned scanning : 1;
78
79 /* periodic schedule support */
80#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
81 unsigned periodic_size;
6dbd682b 82 __hc32 *periodic; /* hw periodic table */
1da177e4
LT		 83 dma_addr_t periodic_dma;
84 unsigned i_thresh; /* uframes HC might cache */
85
86 union ehci_shadow *pshadow; /* mirror hw periodic table */
87 int next_uframe; /* scan periodic, start here */
88 unsigned periodic_sched; /* periodic activity count */
89
90 /* per root hub port */
91 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
383975d7 92
57e06c11
AS		 93 /* bit vectors (one bit per port) */
94 unsigned long bus_suspended; /* which ports were
95 already suspended at the start of a bus suspend */
96 unsigned long companion_ports; /* which ports are
97 dedicated to the companion controller */
383975d7
AS		 98 unsigned long owned_ports; /* which ports are
99 owned by the companion during a bus suspend */
1da177e4
LT		 100
101 /* per-HC memory pools (could be per-bus, but ...) */
102 struct dma_pool *qh_pool; /* qh per active urb */
103 struct dma_pool *qtd_pool; /* one or more per qh */
104 struct dma_pool *itd_pool; /* itd per iso urb */
105 struct dma_pool *sitd_pool; /* sitd per split iso urb */
106
07d29b63 107 struct timer_list iaa_watchdog;
1da177e4 108 struct timer_list watchdog;
1da177e4
LT		 109 unsigned long actions;
110 unsigned stamp;
111 unsigned long next_statechange;
112 u32 command;
113
8cd42e97 114 /* SILICON QUIRKS */
f8aeb3bb 115 unsigned no_selective_suspend:1;
8cd42e97 116 unsigned has_fsl_port_bug:1; /* FreeScale */
083522d7 117 unsigned big_endian_mmio:1;
6dbd682b 118 unsigned big_endian_desc:1;
8cd42e97 119
f8aeb3bb 120 u8 sbrn; /* packed release number */
1da177e4 121
1da177e4
LT		 122 /* irq statistics */
123#ifdef EHCI_STATS
124 struct ehci_stats stats;
125# define COUNT(x) do { (x)++; } while (0)
126#else
127# define COUNT(x) do {} while (0)
694cc208
TJ		 128#endif
129
130 /* debug files */
131#ifdef DEBUG
132 struct dentry *debug_dir;
133 struct dentry *debug_async;
134 struct dentry *debug_periodic;
135 struct dentry *debug_registers;
1da177e4
LT		 136#endif
137};
138
53bd6a60 139/* convert between an HCD pointer and the corresponding EHCI_HCD */
1da177e4
LT		 140static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
141{
142 return (struct ehci_hcd *) (hcd->hcd_priv);
143}
144static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
145{
146 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
147}
148
149
07d29b63
AS		 150static inline void
151iaa_watchdog_start(struct ehci_hcd *ehci)
152{
153 WARN_ON(timer_pending(&ehci->iaa_watchdog));
154 mod_timer(&ehci->iaa_watchdog,
155 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
156}
157
158static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
159{
160 del_timer(&ehci->iaa_watchdog);
161}
162
1da177e4
LT		 163enum ehci_timer_action {
164 TIMER_IO_WATCHDOG,
1da177e4
LT		 165 TIMER_ASYNC_SHRINK,
166 TIMER_ASYNC_OFF,
167};
168
169static inline void
170timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
171{
172 clear_bit (action, &ehci->actions);
173}
174
175static inline void
176timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
177{
178 if (!test_and_set_bit (action, &ehci->actions)) {
179 unsigned long t;
180
181 switch (action) {
1da177e4
LT		 182 case TIMER_IO_WATCHDOG:
183 t = EHCI_IO_JIFFIES;
184 break;
185 case TIMER_ASYNC_OFF:
186 t = EHCI_ASYNC_JIFFIES;
187 break;
188 // case TIMER_ASYNC_SHRINK:
189 default:
190 t = EHCI_SHRINK_JIFFIES;
191 break;
192 }
193 t += jiffies;
194 // all timings except IAA watchdog can be overridden.
195 // async queue SHRINK often precedes IAA. while it's ready
196 // to go OFF neither can matter, and afterwards the IO
197 // watchdog stops unless there's still periodic traffic.
07d29b63 198 if (time_before_eq(t, ehci->watchdog.expires)
1da177e4
LT		 199 && timer_pending (&ehci->watchdog))
200 return;
201 mod_timer (&ehci->watchdog, t);
202 }
203}
204
205/*-------------------------------------------------------------------------*/
206
207/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
208
209/* Section 2.2 Host Controller Capability Registers */
210struct ehci_caps {
211 /* these fields are specified as 8 and 16 bit registers,
212 * but some hosts can't perform 8 or 16 bit PCI accesses.
213 */
56c1e26d 214 u32 hc_capbase;
1da177e4
LT		 215#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
216#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
217 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
218#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
219#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
220#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
221#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
53bd6a60
DB		 222#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
223#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
1da177e4
LT		 224#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
225
226 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
227#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
228#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
229#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
230#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
231#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
232#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
233 u8 portroute [8]; /* nibbles for routing - offset 0xC */
234} __attribute__ ((packed));
235
236
237/* Section 2.3 Host Controller Operational Registers */
238struct ehci_regs {
239
240 /* USBCMD: offset 0x00 */
241 u32 command;
242/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
243#define CMD_PARK (1<<11) /* enable "park" on async qh */
244#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
245#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
246#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
247#define CMD_ASE (1<<5) /* async schedule enable */
53bd6a60 248#define CMD_PSE (1<<4) /* periodic schedule enable */
1da177e4
LT		 249/* 3:2 is periodic frame list size */
250#define CMD_RESET (1<<1) /* reset HC not bus */
251#define CMD_RUN (1<<0) /* start/stop HC */
252
253 /* USBSTS: offset 0x04 */
254 u32 status;
255#define STS_ASS (1<<15) /* Async Schedule Status */
256#define STS_PSS (1<<14) /* Periodic Schedule Status */
257#define STS_RECL (1<<13) /* Reclamation */
258#define STS_HALT (1<<12) /* Not running (any reason) */
259/* some bits reserved */
260 /* these STS_* flags are also intr_enable bits (USBINTR) */
261#define STS_IAA (1<<5) /* Interrupted on async advance */
262#define STS_FATAL (1<<4) /* such as some PCI access errors */
263#define STS_FLR (1<<3) /* frame list rolled over */
264#define STS_PCD (1<<2) /* port change detect */
265#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
266#define STS_INT (1<<0) /* "normal" completion (short, ...) */
267
268 /* USBINTR: offset 0x08 */
269 u32 intr_enable;
270
271 /* FRINDEX: offset 0x0C */
272 u32 frame_index; /* current microframe number */
273 /* CTRLDSSEGMENT: offset 0x10 */
53bd6a60 274 u32 segment; /* address bits 63:32 if needed */
1da177e4 275 /* PERIODICLISTBASE: offset 0x14 */
53bd6a60 276 u32 frame_list; /* points to periodic list */
1da177e4
LT		 277 /* ASYNCLISTADDR: offset 0x18 */
278 u32 async_next; /* address of next async queue head */
279
280 u32 reserved [9];
281
282 /* CONFIGFLAG: offset 0x40 */
283 u32 configured_flag;
284#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
285
286 /* PORTSC: offset 0x44 */
287 u32 port_status [0]; /* up to N_PORTS */
288/* 31:23 reserved */
289#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
290#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
291#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
292/* 19:16 for port testing */
293#define PORT_LED_OFF (0<<14)
294#define PORT_LED_AMBER (1<<14)
295#define PORT_LED_GREEN (2<<14)
296#define PORT_LED_MASK (3<<14)
297#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
298#define PORT_POWER (1<<12) /* true: has power (see PPC) */
299#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
300/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
301/* 9 reserved */
302#define PORT_RESET (1<<8) /* reset port */
303#define PORT_SUSPEND (1<<7) /* suspend port */
304#define PORT_RESUME (1<<6) /* resume it */
305#define PORT_OCC (1<<5) /* over current change */
306#define PORT_OC (1<<4) /* over current active */
307#define PORT_PEC (1<<3) /* port enable change */
308#define PORT_PE (1<<2) /* port enable */
309#define PORT_CSC (1<<1) /* connect status change */
310#define PORT_CONNECT (1<<0) /* device connected */
10f6524a 311#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
1da177e4
LT		 312} __attribute__ ((packed));
313
d23a1377
VB		 314#define USBMODE 0x68 /* USB Device mode */
315#define USBMODE_SDIS (1<<3) /* Stream disable */
316#define USBMODE_BE (1<<2) /* BE/LE endianness select */
317#define USBMODE_CM_HC (3<<0) /* host controller mode */
318#define USBMODE_CM_IDLE (0<<0) /* idle state */
319
1da177e4
LT		 320/* Appendix C, Debug port ... intended for use with special "debug devices"
321 * that can help if there's no serial console. (nonstandard enumeration.)
322 */
323struct ehci_dbg_port {
324 u32 control;
325#define DBGP_OWNER (1<<30)
326#define DBGP_ENABLED (1<<28)
327#define DBGP_DONE (1<<16)
328#define DBGP_INUSE (1<<10)
56c1e26d 329#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
1da177e4
LT		 330# define DBGP_ERR_BAD 1
331# define DBGP_ERR_SIGNAL 2
332#define DBGP_ERROR (1<<6)
333#define DBGP_GO (1<<5)
334#define DBGP_OUT (1<<4)
335#define DBGP_LEN(x) (((x)>>0)&0x0f)
336 u32 pids;
337#define DBGP_PID_GET(x) (((x)>>16)&0xff)
56c1e26d 338#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
1da177e4
LT		 339 u32 data03;
340 u32 data47;
341 u32 address;
56c1e26d 342#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
1da177e4
LT		 343} __attribute__ ((packed));
344
345/*-------------------------------------------------------------------------*/
346
6dbd682b 347#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
1da177e4
LT		 348
349/*
350 * EHCI Specification 0.95 Section 3.5
53bd6a60 351 * QTD: describe data transfer components (buffer, direction, ...)
1da177e4
LT		 352 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
353 *
354 * These are associated only with "QH" (Queue Head) structures,
355 * used with control, bulk, and interrupt transfers.
356 */
357struct ehci_qtd {
358 /* first part defined by EHCI spec */
6dbd682b
SR		 359 __hc32 hw_next; /* see EHCI 3.5.1 */
360 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
361 __hc32 hw_token; /* see EHCI 3.5.3 */
1da177e4
LT		 362#define QTD_TOGGLE (1 << 31) /* data toggle */
363#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
364#define QTD_IOC (1 << 15) /* interrupt on complete */
365#define QTD_CERR(tok) (((tok)>>10) & 0x3)
366#define QTD_PID(tok) (((tok)>>8) & 0x3)
367#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
368#define QTD_STS_HALT (1 << 6) /* halted on error */
369#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
370#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
371#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
372#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
373#define QTD_STS_STS (1 << 1) /* split transaction state */
374#define QTD_STS_PING (1 << 0) /* issue PING? */
6dbd682b
SR		 375
376#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
377#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
378#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
379
380 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
381 __hc32 hw_buf_hi [5]; /* Appendix B */
1da177e4
LT		 382
383 /* the rest is HCD-private */
384 dma_addr_t qtd_dma; /* qtd address */
385 struct list_head qtd_list; /* sw qtd list */
386 struct urb *urb; /* qtd's urb */
387 size_t length; /* length of buffer */
388} __attribute__ ((aligned (32)));
389
390/* mask NakCnt+T in qh->hw_alt_next */
6dbd682b 391#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
1da177e4
LT		 392
393#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
394
395/*-------------------------------------------------------------------------*/
396
397/* type tag from {qh,itd,sitd,fstn}->hw_next */
6dbd682b 398#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
1da177e4 399
6dbd682b
SR		 400/*
401 * Now the following defines are not converted using the
402 * __constant_cpu_to_le32() macro anymore, since we have to support
403 * "dynamic" switching between be and le support, so that the driver
404 * can be used on one system with SoC EHCI controller using big-endian
405 * descriptors as well as a normal little-endian PCI EHCI controller.
406 */
1da177e4 407/* values for that type tag */
6dbd682b
SR		 408#define Q_TYPE_ITD (0 << 1)
409#define Q_TYPE_QH (1 << 1)
410#define Q_TYPE_SITD (2 << 1)
411#define Q_TYPE_FSTN (3 << 1)
1da177e4
LT		 412
413/* next async queue entry, or pointer to interrupt/periodic QH */
6dbd682b 414#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
1da177e4
LT		 415
416/* for periodic/async schedules and qtd lists, mark end of list */
6dbd682b 417#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
1da177e4
LT		 418
419/*
420 * Entries in periodic shadow table are pointers to one of four kinds
421 * of data structure. That's dictated by the hardware; a type tag is
422 * encoded in the low bits of the hardware's periodic schedule. Use
423 * Q_NEXT_TYPE to get the tag.
424 *
425 * For entries in the async schedule, the type tag always says "qh".
426 */
427union ehci_shadow {
53bd6a60 428 struct ehci_qh *qh; /* Q_TYPE_QH */
1da177e4
LT		 429 struct ehci_itd *itd; /* Q_TYPE_ITD */
430 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
431 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
6dbd682b 432 __hc32 *hw_next; /* (all types) */
1da177e4
LT		 433 void *ptr;
434};
435
436/*-------------------------------------------------------------------------*/
437
438/*
439 * EHCI Specification 0.95 Section 3.6
440 * QH: describes control/bulk/interrupt endpoints
441 * See Fig 3-7 "Queue Head Structure Layout".
442 *
443 * These appear in both the async and (for interrupt) periodic schedules.
444 */
445
446struct ehci_qh {
447 /* first part defined by EHCI spec */
6dbd682b
SR		 448 __hc32 hw_next; /* see EHCI 3.6.1 */
449 __hc32 hw_info1; /* see EHCI 3.6.2 */
1da177e4 450#define QH_HEAD 0x00008000
6dbd682b 451 __hc32 hw_info2; /* see EHCI 3.6.2 */
7dedacf4
DB		 452#define QH_SMASK 0x000000ff
453#define QH_CMASK 0x0000ff00
454#define QH_HUBADDR 0x007f0000
455#define QH_HUBPORT 0x3f800000
456#define QH_MULT 0xc0000000
6dbd682b 457 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
53bd6a60 458
1da177e4 459 /* qtd overlay (hardware parts of a struct ehci_qtd) */
6dbd682b
SR		 460 __hc32 hw_qtd_next;
461 __hc32 hw_alt_next;
462 __hc32 hw_token;
463 __hc32 hw_buf [5];
464 __hc32 hw_buf_hi [5];
1da177e4
LT		 465
466 /* the rest is HCD-private */
467 dma_addr_t qh_dma; /* address of qh */
468 union ehci_shadow qh_next; /* ptr to qh; or periodic */
469 struct list_head qtd_list; /* sw qtd list */
470 struct ehci_qtd *dummy;
471 struct ehci_qh *reclaim; /* next to reclaim */
472
473 struct ehci_hcd *ehci;
9c033e81
DB		 474
475 /*
476 * Do NOT use atomic operations for QH refcounting. On some CPUs
477 * (PPC7448 for example), atomic operations cannot be performed on
478 * memory that is cache-inhibited (i.e. being used for DMA).
479 * Spinlocks are used to protect all QH fields.
480 */
481 u32 refcount;
1da177e4
LT		 482 unsigned stamp;
483
484 u8 qh_state;
485#define QH_STATE_LINKED 1 /* HC sees this */
486#define QH_STATE_UNLINK 2 /* HC may still see this */
487#define QH_STATE_IDLE 3 /* HC doesn't see this */
488#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
489#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
490
491 /* periodic schedule info */
492 u8 usecs; /* intr bandwidth */
493 u8 gap_uf; /* uframes split/csplit gap */
494 u8 c_usecs; /* ... split completion bw */
d0384200 495 u16 tt_usecs; /* tt downstream bandwidth */
1da177e4
LT		 496 unsigned short period; /* polling interval */
497 unsigned short start; /* where polling starts */
498#define NO_FRAME ((unsigned short)~0) /* pick new start */
499 struct usb_device *dev; /* access to TT */
500} __attribute__ ((aligned (32)));
501
502/*-------------------------------------------------------------------------*/
503
504/* description of one iso transaction (up to 3 KB data if highspeed) */
505struct ehci_iso_packet {
506 /* These will be copied to iTD when scheduling */
507 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
6dbd682b 508 __hc32 transaction; /* itd->hw_transaction[i] |= */
1da177e4
LT		 509 u8 cross; /* buf crosses pages */
510 /* for full speed OUT splits */
511 u32 buf1;
512};
513
514/* temporary schedule data for packets from iso urbs (both speeds)
515 * each packet is one logical usb transaction to the device (not TT),
516 * beginning at stream->next_uframe
517 */
518struct ehci_iso_sched {
519 struct list_head td_list;
520 unsigned span;
521 struct ehci_iso_packet packet [0];
522};
523
524/*
525 * ehci_iso_stream - groups all (s)itds for this endpoint.
526 * acts like a qh would, if EHCI had them for ISO.
527 */
528struct ehci_iso_stream {
529 /* first two fields match QH, but info1 == 0 */
6dbd682b
SR		 530 __hc32 hw_next;
531 __hc32 hw_info1;
1da177e4
LT		 532
533 u32 refcount;
534 u8 bEndpointAddress;
535 u8 highspeed;
536 u16 depth; /* depth in uframes */
537 struct list_head td_list; /* queued itds/sitds */
538 struct list_head free_list; /* list of unused itds/sitds */
539 struct usb_device *udev;
53bd6a60 540 struct usb_host_endpoint *ep;
1da177e4
LT		 541
542 /* output of (re)scheduling */
543 unsigned long start; /* jiffies */
544 unsigned long rescheduled;
545 int next_uframe;
6dbd682b 546 __hc32 splits;
1da177e4
LT		 547
548 /* the rest is derived from the endpoint descriptor,
549 * trusting urb->interval == f(epdesc->bInterval) and
550 * including the extra info for hw_bufp[0..2]
551 */
1da177e4 552 u8 usecs, c_usecs;
c06d4dcf 553 u16 interval;
d0384200 554 u16 tt_usecs;
1da177e4
LT		 555 u16 maxp;
556 u16 raw_mask;
557 unsigned bandwidth;
558
559 /* This is used to initialize iTD's hw_bufp fields */
6dbd682b
SR		 560 __hc32 buf0;
561 __hc32 buf1;
562 __hc32 buf2;
1da177e4
LT		 563
564 /* this is used to initialize sITD's tt info */
6dbd682b 565 __hc32 address;
1da177e4
LT		 566};
567
568/*-------------------------------------------------------------------------*/
569
570/*
571 * EHCI Specification 0.95 Section 3.3
572 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
573 *
574 * Schedule records for high speed iso xfers
575 */
576struct ehci_itd {
577 /* first part defined by EHCI spec */
6dbd682b
SR		 578 __hc32 hw_next; /* see EHCI 3.3.1 */
579 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
1da177e4
LT		 580#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
581#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
582#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
583#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
584#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
585#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
586
6dbd682b 587#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
1da177e4 588
6dbd682b
SR		 589 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
590 __hc32 hw_bufp_hi [7]; /* Appendix B */
1da177e4
LT		 591
592 /* the rest is HCD-private */
593 dma_addr_t itd_dma; /* for this itd */
594 union ehci_shadow itd_next; /* ptr to periodic q entry */
595
596 struct urb *urb;
597 struct ehci_iso_stream *stream; /* endpoint's queue */
598 struct list_head itd_list; /* list of stream's itds */
599
600 /* any/all hw_transactions here may be used by that urb */
601 unsigned frame; /* where scheduled */
602 unsigned pg;
603 unsigned index[8]; /* in urb->iso_frame_desc */
1da177e4
LT		 604} __attribute__ ((aligned (32)));
605
606/*-------------------------------------------------------------------------*/
607
608/*
53bd6a60 609 * EHCI Specification 0.95 Section 3.4
1da177e4
LT		 610 * siTD, aka split-transaction isochronous Transfer Descriptor
611 * ... describe full speed iso xfers through TT in hubs
612 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
613 */
614struct ehci_sitd {
615 /* first part defined by EHCI spec */
6dbd682b 616 __hc32 hw_next;
1da177e4 617/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
6dbd682b
SR		 618 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
619 __hc32 hw_uframe; /* EHCI table 3-10 */
620 __hc32 hw_results; /* EHCI table 3-11 */
1da177e4
LT		 621#define SITD_IOC (1 << 31) /* interrupt on completion */
622#define SITD_PAGE (1 << 30) /* buffer 0/1 */
623#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
624#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
625#define SITD_STS_ERR (1 << 6) /* error from TT */
626#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
627#define SITD_STS_BABBLE (1 << 4) /* device was babbling */
628#define SITD_STS_XACT (1 << 3) /* illegal IN response */
629#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
630#define SITD_STS_STS (1 << 1) /* split transaction state */
631
6dbd682b 632#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
1da177e4 633
6dbd682b
SR		 634 __hc32 hw_buf [2]; /* EHCI table 3-12 */
635 __hc32 hw_backpointer; /* EHCI table 3-13 */
636 __hc32 hw_buf_hi [2]; /* Appendix B */
1da177e4
LT		 637
638 /* the rest is HCD-private */
639 dma_addr_t sitd_dma;
640 union ehci_shadow sitd_next; /* ptr to periodic q entry */
641
642 struct urb *urb;
643 struct ehci_iso_stream *stream; /* endpoint's queue */
644 struct list_head sitd_list; /* list of stream's sitds */
645 unsigned frame;
646 unsigned index;
647} __attribute__ ((aligned (32)));
648
649/*-------------------------------------------------------------------------*/
650
651/*
652 * EHCI Specification 0.96 Section 3.7
653 * Periodic Frame Span Traversal Node (FSTN)
654 *
655 * Manages split interrupt transactions (using TT) that span frame boundaries
656 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
657 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
658 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
659 */
660struct ehci_fstn {
6dbd682b
SR		 661 __hc32 hw_next; /* any periodic q entry */
662 __hc32 hw_prev; /* qh or EHCI_LIST_END */
1da177e4
LT		 663
664 /* the rest is HCD-private */
665 dma_addr_t fstn_dma;
666 union ehci_shadow fstn_next; /* ptr to periodic q entry */
667} __attribute__ ((aligned (32)));
668
669/*-------------------------------------------------------------------------*/
670
671#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
672
673/*
674 * Some EHCI controllers have a Transaction Translator built into the
675 * root hub. This is a non-standard feature. Each controller will need
676 * to add code to the following inline functions, and call them as
677 * needed (mostly in root hub code).
678 */
679
a8e51775 680#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
1da177e4
LT		 681
682/* Returns the speed of a device attached to a port on the root hub. */
683static inline unsigned int
684ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
685{
686 if (ehci_is_TDI(ehci)) {
687 switch ((portsc>>26)&3) {
688 case 0:
689 return 0;
690 case 1:
691 return (1<<USB_PORT_FEAT_LOWSPEED);
692 case 2:
693 default:
694 return (1<<USB_PORT_FEAT_HIGHSPEED);
695 }
696 }
697 return (1<<USB_PORT_FEAT_HIGHSPEED);
698}
699
700#else
701
702#define ehci_is_TDI(e) (0)
703
704#define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
705#endif
706
8cd42e97
KG		 707/*-------------------------------------------------------------------------*/
708
709#ifdef CONFIG_PPC_83xx
710/* Some Freescale processors have an erratum in which the TT
711 * port number in the queue head was 0..N-1 instead of 1..N.
712 */
713#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
714#else
715#define ehci_has_fsl_portno_bug(e) (0)
716#endif
717
083522d7
BH		 718/*
719 * While most USB host controllers implement their registers in
720 * little-endian format, a minority (celleb companion chip) implement
721 * them in big endian format.
722 *
723 * This attempts to support either format at compile time without a
724 * runtime penalty, or both formats with the additional overhead
725 * of checking a flag bit.
726 */
727
728#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
729#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
730#else
731#define ehci_big_endian_mmio(e) 0
732#endif
733
6dbd682b
SR		 734/*
735 * Big-endian read/write functions are arch-specific.
736 * Other arches can be added if/when they're needed.
737 *
738 * REVISIT: arch/powerpc now has readl/writel_be, so the
739 * definition below can die once the 4xx support is
740 * finally ported over.
741 */
da0e8fb0 742#if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE)
6dbd682b
SR		 743#define readl_be(addr) in_be32((__force unsigned *)addr)
744#define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
745#endif
746
91bc4d31
VB		 747#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
748#define readl_be(addr) __raw_readl((__force unsigned *)addr)
749#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
750#endif
751
6dbd682b
SR		 752static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
753 __u32 __iomem * regs)
083522d7 754{
d728e327 755#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
083522d7 756 return ehci_big_endian_mmio(ehci) ?
68f50e52
AV		 757 readl_be(regs) :
758 readl(regs);
d728e327 759#else
68f50e52 760 return readl(regs);
d728e327 761#endif
083522d7
BH		 762}
763
6dbd682b
SR		 764static inline void ehci_writel(const struct ehci_hcd *ehci,
765 const unsigned int val, __u32 __iomem *regs)
083522d7 766{
d728e327 767#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
083522d7 768 ehci_big_endian_mmio(ehci) ?
68f50e52
AV		 769 writel_be(val, regs) :
770 writel(val, regs);
d728e327 771#else
68f50e52 772 writel(val, regs);
d728e327 773#endif
083522d7 774}
8cd42e97 775
1da177e4
LT		 776/*-------------------------------------------------------------------------*/
777
6dbd682b
SR		 778/*
779 * The AMCC 440EPx not only implements its EHCI registers in big-endian
780 * format, but also its DMA data structures (descriptors).
781 *
782 * EHCI controllers accessed through PCI work normally (little-endian
783 * everywhere), so we won't bother supporting a BE-only mode for now.
784 */
785#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
786#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
787
788/* cpu to ehci */
789static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
790{
791 return ehci_big_endian_desc(ehci)
792 ? (__force __hc32)cpu_to_be32(x)
793 : (__force __hc32)cpu_to_le32(x);
794}
795
796/* ehci to cpu */
797static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
798{
799 return ehci_big_endian_desc(ehci)
800 ? be32_to_cpu((__force __be32)x)
801 : le32_to_cpu((__force __le32)x);
802}
803
804static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
805{
806 return ehci_big_endian_desc(ehci)
807 ? be32_to_cpup((__force __be32 *)x)
808 : le32_to_cpup((__force __le32 *)x);
809}
810
811#else
812
813/* cpu to ehci */
814static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
815{
816 return cpu_to_le32(x);
817}
818
819/* ehci to cpu */
820static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
821{
822 return le32_to_cpu(x);
823}
824
825static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
826{
827 return le32_to_cpup(x);
828}
829
830#endif
831
832/*-------------------------------------------------------------------------*/
833
1da177e4
LT		 834#ifndef DEBUG
835#define STUB_DEBUG_FILES
836#endif /* DEBUG */
837
838/*-------------------------------------------------------------------------*/
839
840#endif /* __LINUX_EHCI_HCD_H */
Linux kernel - Deliverables
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