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1da177e4 LT |
1 | /* |
2 | * Copyright (c) 2001-2002 by David Brownell | |
53bd6a60 | 3 | * |
1da177e4 LT |
4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but | |
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
11 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 | * for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software Foundation, | |
16 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_EHCI_HCD_H | |
20 | #define __LINUX_EHCI_HCD_H | |
21 | ||
22 | /* definitions used for the EHCI driver */ | |
23 | ||
6dbd682b SR |
24 | /* |
25 | * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to | |
26 | * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on | |
27 | * the host controller implementation. | |
28 | * | |
29 | * To facilitate the strongest possible byte-order checking from "sparse" | |
30 | * and so on, we use __leXX unless that's not practical. | |
31 | */ | |
32 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
33 | typedef __u32 __bitwise __hc32; | |
34 | typedef __u16 __bitwise __hc16; | |
35 | #else | |
36 | #define __hc32 __le32 | |
37 | #define __hc16 __le16 | |
38 | #endif | |
39 | ||
411c9403 | 40 | /* statistics can be kept for tuning/monitoring */ |
1512c91f | 41 | #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) |
9ec6e9d3 RQ |
42 | #define EHCI_STATS |
43 | #endif | |
44 | ||
1da177e4 LT |
45 | struct ehci_stats { |
46 | /* irq usage */ | |
47 | unsigned long normal; | |
48 | unsigned long error; | |
99ac5b1e | 49 | unsigned long iaa; |
1da177e4 LT |
50 | unsigned long lost_iaa; |
51 | ||
52 | /* termination of urbs from core */ | |
53 | unsigned long complete; | |
54 | unsigned long unlink; | |
55 | }; | |
56 | ||
ffa0248e AS |
57 | /* |
58 | * Scheduling and budgeting information for periodic transfers, for both | |
59 | * high-speed devices and full/low-speed devices lying behind a TT. | |
60 | */ | |
61 | struct ehci_per_sched { | |
62 | struct usb_device *udev; /* access to the TT */ | |
63 | struct usb_host_endpoint *ep; | |
64 | u16 tt_usecs; /* time on the FS/LS bus */ | |
d0ce5c6b | 65 | u16 cs_mask; /* C-mask and S-mask bytes */ |
ffa0248e AS |
66 | u16 period; /* actual period in frames */ |
67 | u16 phase; /* actual phase, frame part */ | |
d0ce5c6b AS |
68 | u8 bw_phase; /* same, for bandwidth |
69 | reservation */ | |
ffa0248e AS |
70 | u8 phase_uf; /* uframe part of the phase */ |
71 | u8 usecs, c_usecs; /* times on the HS bus */ | |
d0ce5c6b AS |
72 | u8 bw_uperiod; /* period in microframes, for |
73 | bandwidth reservation */ | |
74 | u8 bw_period; /* same, in frames */ | |
ffa0248e | 75 | }; |
91a99b5e AS |
76 | #define NO_FRAME 29999 /* frame not assigned yet */ |
77 | ||
1da177e4 | 78 | /* ehci_hcd->lock guards shared data against other CPUs: |
99ac5b1e | 79 | * ehci_hcd: async, unlink, periodic (and shadow), ... |
1da177e4 LT |
80 | * usb_host_endpoint: hcpriv |
81 | * ehci_qh: qh_next, qtd_list | |
82 | * ehci_qtd: qtd_list | |
83 | * | |
84 | * Also, hold this lock when talking to HC registers or | |
85 | * when updating hw_* fields in shared qh/qtd/... structures. | |
86 | */ | |
87 | ||
88 | #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ | |
89 | ||
c0c53dbc AS |
90 | /* |
91 | * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the | |
92 | * controller may be doing DMA. Lower values mean there's no DMA. | |
93 | */ | |
e8799906 AS |
94 | enum ehci_rh_state { |
95 | EHCI_RH_HALTED, | |
96 | EHCI_RH_SUSPENDED, | |
c0c53dbc AS |
97 | EHCI_RH_RUNNING, |
98 | EHCI_RH_STOPPING | |
e8799906 AS |
99 | }; |
100 | ||
d58b4bcc AS |
101 | /* |
102 | * Timer events, ordered by increasing delay length. | |
103 | * Always update event_delays_ns[] and event_handlers[] (defined in | |
104 | * ehci-timer.c) in parallel with this list. | |
105 | */ | |
106 | enum ehci_hrtimer_event { | |
31446610 | 107 | EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ |
3ca9aeba | 108 | EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ |
bf6387bc | 109 | EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ |
df202255 | 110 | EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ |
55934eb3 | 111 | EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ |
9118f9eb | 112 | EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ |
32830f20 | 113 | EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ |
9d938747 | 114 | EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ |
3ca9aeba | 115 | EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ |
31446610 | 116 | EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ |
18aafe64 | 117 | EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ |
d58b4bcc AS |
118 | EHCI_HRTIMER_NUM_EVENTS /* Must come last */ |
119 | }; | |
120 | #define EHCI_HRTIMER_NO_EVENT 99 | |
121 | ||
1da177e4 | 122 | struct ehci_hcd { /* one per controller */ |
d58b4bcc AS |
123 | /* timing support */ |
124 | enum ehci_hrtimer_event next_hrtimer_event; | |
125 | unsigned enabled_hrtimer_events; | |
126 | ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; | |
127 | struct hrtimer hrtimer; | |
128 | ||
3ca9aeba | 129 | int PSS_poll_count; |
31446610 | 130 | int ASS_poll_count; |
bf6387bc | 131 | int died_poll_count; |
3ca9aeba | 132 | |
56c1e26d DB |
133 | /* glue to PCI and HCD framework */ |
134 | struct ehci_caps __iomem *caps; | |
135 | struct ehci_regs __iomem *regs; | |
136 | struct ehci_dbg_port __iomem *debug; | |
137 | ||
138 | __u32 hcs_params; /* cached register copy */ | |
1da177e4 | 139 | spinlock_t lock; |
e8799906 | 140 | enum ehci_rh_state rh_state; |
1da177e4 | 141 | |
df202255 | 142 | /* general schedule support */ |
361aabf3 AS |
143 | bool scanning:1; |
144 | bool need_rescan:1; | |
df202255 | 145 | bool intr_unlinking:1; |
214ac7a0 | 146 | bool iaa_in_progress:1; |
3c273a05 | 147 | bool async_unlinking:1; |
43fe3a99 | 148 | bool shutdown:1; |
569b394f | 149 | struct ehci_qh *qh_scan_next; |
df202255 | 150 | |
1da177e4 LT |
151 | /* async schedule support */ |
152 | struct ehci_qh *async; | |
3d091a6f | 153 | struct ehci_qh *dummy; /* For AMD quirk use */ |
6e018751 | 154 | struct list_head async_unlink; |
214ac7a0 | 155 | struct list_head async_idle; |
32830f20 | 156 | unsigned async_unlink_cycle; |
31446610 | 157 | unsigned async_count; /* async activity count */ |
1da177e4 LT |
158 | |
159 | /* periodic schedule support */ | |
160 | #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ | |
161 | unsigned periodic_size; | |
6dbd682b | 162 | __hc32 *periodic; /* hw periodic table */ |
1da177e4 | 163 | dma_addr_t periodic_dma; |
569b394f | 164 | struct list_head intr_qh_list; |
1da177e4 LT |
165 | unsigned i_thresh; /* uframes HC might cache */ |
166 | ||
167 | union ehci_shadow *pshadow; /* mirror hw periodic table */ | |
9118f9eb | 168 | struct list_head intr_unlink_wait; |
6e018751 | 169 | struct list_head intr_unlink; |
9118f9eb | 170 | unsigned intr_unlink_wait_cycle; |
df202255 | 171 | unsigned intr_unlink_cycle; |
f4289078 | 172 | unsigned now_frame; /* frame from HC hardware */ |
c3ee9b76 | 173 | unsigned last_iso_frame; /* last frame scanned for iso */ |
569b394f AS |
174 | unsigned intr_count; /* intr activity count */ |
175 | unsigned isoc_count; /* isoc activity count */ | |
3ca9aeba | 176 | unsigned periodic_count; /* periodic activity count */ |
cc62a7eb KS |
177 | unsigned uframe_periodic_max; /* max periodic time per uframe */ |
178 | ||
1da177e4 | 179 | |
f4289078 | 180 | /* list of itds & sitds completed while now_frame was still active */ |
9aa09d2f | 181 | struct list_head cached_itd_list; |
55934eb3 | 182 | struct ehci_itd *last_itd_to_free; |
0e5f231b | 183 | struct list_head cached_sitd_list; |
55934eb3 | 184 | struct ehci_sitd *last_sitd_to_free; |
9aa09d2f | 185 | |
1da177e4 LT |
186 | /* per root hub port */ |
187 | unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; | |
383975d7 | 188 | |
57e06c11 AS |
189 | /* bit vectors (one bit per port) */ |
190 | unsigned long bus_suspended; /* which ports were | |
191 | already suspended at the start of a bus suspend */ | |
192 | unsigned long companion_ports; /* which ports are | |
193 | dedicated to the companion controller */ | |
383975d7 AS |
194 | unsigned long owned_ports; /* which ports are |
195 | owned by the companion during a bus suspend */ | |
d1f114d1 AS |
196 | unsigned long port_c_suspend; /* which ports have |
197 | the change-suspend feature turned on */ | |
eafe5b99 AS |
198 | unsigned long suspended_ports; /* which ports are |
199 | suspended */ | |
a448e4dc AS |
200 | unsigned long resuming_ports; /* which ports have |
201 | started to resume */ | |
1da177e4 LT |
202 | |
203 | /* per-HC memory pools (could be per-bus, but ...) */ | |
204 | struct dma_pool *qh_pool; /* qh per active urb */ | |
205 | struct dma_pool *qtd_pool; /* one or more per qh */ | |
206 | struct dma_pool *itd_pool; /* itd per iso urb */ | |
207 | struct dma_pool *sitd_pool; /* sitd per split iso urb */ | |
208 | ||
68335e81 | 209 | unsigned random_frame; |
1da177e4 | 210 | unsigned long next_statechange; |
ee4ecb8a | 211 | ktime_t last_periodic_enable; |
1da177e4 LT |
212 | u32 command; |
213 | ||
8cd42e97 | 214 | /* SILICON QUIRKS */ |
f8aeb3bb | 215 | unsigned no_selective_suspend:1; |
8cd42e97 | 216 | unsigned has_fsl_port_bug:1; /* FreeScale */ |
083522d7 | 217 | unsigned big_endian_mmio:1; |
6dbd682b | 218 | unsigned big_endian_desc:1; |
c430131a | 219 | unsigned big_endian_capbase:1; |
796bcae7 | 220 | unsigned has_amcc_usb23:1; |
403dbd36 | 221 | unsigned need_io_watchdog:1; |
ad93562b | 222 | unsigned amd_pll_fix:1; |
3d091a6f | 223 | unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ |
2f7ac6c1 | 224 | unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ |
68aa95d5 | 225 | unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ |
e6604a7f | 226 | unsigned need_oc_pp_cycle:1; /* MPC834X port power */ |
796bcae7 VB |
227 | |
228 | /* required for usb32 quirk */ | |
229 | #define OHCI_CTRL_HCFS (3 << 6) | |
230 | #define OHCI_USB_OPER (2 << 6) | |
231 | #define OHCI_USB_SUSPEND (3 << 6) | |
232 | ||
233 | #define OHCI_HCCTRL_OFFSET 0x4 | |
234 | #define OHCI_HCCTRL_LEN 0x4 | |
235 | __hc32 *ohci_hcctrl_reg; | |
331ac6b2 | 236 | unsigned has_hostpc:1; |
2cdcec4f | 237 | unsigned has_tdi_phy_lpm:1; |
5a9cdf33 | 238 | unsigned has_ppcd:1; /* support per-port change bits */ |
f8aeb3bb | 239 | u8 sbrn; /* packed release number */ |
1da177e4 | 240 | |
1da177e4 LT |
241 | /* irq statistics */ |
242 | #ifdef EHCI_STATS | |
243 | struct ehci_stats stats; | |
244 | # define COUNT(x) do { (x)++; } while (0) | |
245 | #else | |
246 | # define COUNT(x) do {} while (0) | |
694cc208 TJ |
247 | #endif |
248 | ||
249 | /* debug files */ | |
1512c91f | 250 | #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) |
694cc208 | 251 | struct dentry *debug_dir; |
1da177e4 | 252 | #endif |
9debc179 | 253 | |
d0ce5c6b AS |
254 | /* bandwidth usage */ |
255 | #define EHCI_BANDWIDTH_SIZE 64 | |
256 | #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3) | |
257 | u8 bandwidth[EHCI_BANDWIDTH_SIZE]; | |
258 | /* us allocated per uframe */ | |
259 | ||
9debc179 AS |
260 | /* platform-specific data -- must come last */ |
261 | unsigned long priv[0] __aligned(sizeof(s64)); | |
1da177e4 LT |
262 | }; |
263 | ||
53bd6a60 | 264 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
1da177e4 LT |
265 | static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) |
266 | { | |
267 | return (struct ehci_hcd *) (hcd->hcd_priv); | |
268 | } | |
269 | static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) | |
270 | { | |
271 | return container_of ((void *) ehci, struct usb_hcd, hcd_priv); | |
272 | } | |
273 | ||
1da177e4 LT |
274 | /*-------------------------------------------------------------------------*/ |
275 | ||
0af36739 | 276 | #include <linux/usb/ehci_def.h> |
1da177e4 LT |
277 | |
278 | /*-------------------------------------------------------------------------*/ | |
279 | ||
6dbd682b | 280 | #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) |
1da177e4 LT |
281 | |
282 | /* | |
283 | * EHCI Specification 0.95 Section 3.5 | |
53bd6a60 | 284 | * QTD: describe data transfer components (buffer, direction, ...) |
1da177e4 LT |
285 | * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". |
286 | * | |
287 | * These are associated only with "QH" (Queue Head) structures, | |
288 | * used with control, bulk, and interrupt transfers. | |
289 | */ | |
290 | struct ehci_qtd { | |
291 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
292 | __hc32 hw_next; /* see EHCI 3.5.1 */ |
293 | __hc32 hw_alt_next; /* see EHCI 3.5.2 */ | |
294 | __hc32 hw_token; /* see EHCI 3.5.3 */ | |
1da177e4 LT |
295 | #define QTD_TOGGLE (1 << 31) /* data toggle */ |
296 | #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) | |
297 | #define QTD_IOC (1 << 15) /* interrupt on complete */ | |
298 | #define QTD_CERR(tok) (((tok)>>10) & 0x3) | |
299 | #define QTD_PID(tok) (((tok)>>8) & 0x3) | |
300 | #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
301 | #define QTD_STS_HALT (1 << 6) /* halted on error */ | |
302 | #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
303 | #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ | |
304 | #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ | |
305 | #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
306 | #define QTD_STS_STS (1 << 1) /* split transaction state */ | |
307 | #define QTD_STS_PING (1 << 0) /* issue PING? */ | |
6dbd682b SR |
308 | |
309 | #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) | |
310 | #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) | |
311 | #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) | |
312 | ||
313 | __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ | |
314 | __hc32 hw_buf_hi [5]; /* Appendix B */ | |
1da177e4 LT |
315 | |
316 | /* the rest is HCD-private */ | |
317 | dma_addr_t qtd_dma; /* qtd address */ | |
318 | struct list_head qtd_list; /* sw qtd list */ | |
319 | struct urb *urb; /* qtd's urb */ | |
320 | size_t length; /* length of buffer */ | |
321 | } __attribute__ ((aligned (32))); | |
322 | ||
323 | /* mask NakCnt+T in qh->hw_alt_next */ | |
6dbd682b | 324 | #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) |
1da177e4 LT |
325 | |
326 | #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) | |
327 | ||
328 | /*-------------------------------------------------------------------------*/ | |
329 | ||
330 | /* type tag from {qh,itd,sitd,fstn}->hw_next */ | |
6dbd682b | 331 | #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) |
1da177e4 | 332 | |
6dbd682b SR |
333 | /* |
334 | * Now the following defines are not converted using the | |
551509d2 | 335 | * cpu_to_le32() macro anymore, since we have to support |
6dbd682b SR |
336 | * "dynamic" switching between be and le support, so that the driver |
337 | * can be used on one system with SoC EHCI controller using big-endian | |
338 | * descriptors as well as a normal little-endian PCI EHCI controller. | |
339 | */ | |
1da177e4 | 340 | /* values for that type tag */ |
6dbd682b SR |
341 | #define Q_TYPE_ITD (0 << 1) |
342 | #define Q_TYPE_QH (1 << 1) | |
343 | #define Q_TYPE_SITD (2 << 1) | |
344 | #define Q_TYPE_FSTN (3 << 1) | |
1da177e4 LT |
345 | |
346 | /* next async queue entry, or pointer to interrupt/periodic QH */ | |
6dbd682b | 347 | #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) |
1da177e4 LT |
348 | |
349 | /* for periodic/async schedules and qtd lists, mark end of list */ | |
6dbd682b | 350 | #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ |
1da177e4 LT |
351 | |
352 | /* | |
353 | * Entries in periodic shadow table are pointers to one of four kinds | |
354 | * of data structure. That's dictated by the hardware; a type tag is | |
355 | * encoded in the low bits of the hardware's periodic schedule. Use | |
356 | * Q_NEXT_TYPE to get the tag. | |
357 | * | |
358 | * For entries in the async schedule, the type tag always says "qh". | |
359 | */ | |
360 | union ehci_shadow { | |
53bd6a60 | 361 | struct ehci_qh *qh; /* Q_TYPE_QH */ |
1da177e4 LT |
362 | struct ehci_itd *itd; /* Q_TYPE_ITD */ |
363 | struct ehci_sitd *sitd; /* Q_TYPE_SITD */ | |
364 | struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ | |
6dbd682b | 365 | __hc32 *hw_next; /* (all types) */ |
1da177e4 LT |
366 | void *ptr; |
367 | }; | |
368 | ||
369 | /*-------------------------------------------------------------------------*/ | |
370 | ||
371 | /* | |
372 | * EHCI Specification 0.95 Section 3.6 | |
373 | * QH: describes control/bulk/interrupt endpoints | |
374 | * See Fig 3-7 "Queue Head Structure Layout". | |
375 | * | |
376 | * These appear in both the async and (for interrupt) periodic schedules. | |
377 | */ | |
378 | ||
3807e26d AD |
379 | /* first part defined by EHCI spec */ |
380 | struct ehci_qh_hw { | |
6dbd682b SR |
381 | __hc32 hw_next; /* see EHCI 3.6.1 */ |
382 | __hc32 hw_info1; /* see EHCI 3.6.2 */ | |
4c53de72 AS |
383 | #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ |
384 | #define QH_HEAD (1 << 15) /* Head of async reclamation list */ | |
385 | #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ | |
386 | #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ | |
387 | #define QH_LOW_SPEED (1 << 12) | |
388 | #define QH_FULL_SPEED (0 << 12) | |
389 | #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ | |
6dbd682b | 390 | __hc32 hw_info2; /* see EHCI 3.6.2 */ |
7dedacf4 DB |
391 | #define QH_SMASK 0x000000ff |
392 | #define QH_CMASK 0x0000ff00 | |
393 | #define QH_HUBADDR 0x007f0000 | |
394 | #define QH_HUBPORT 0x3f800000 | |
395 | #define QH_MULT 0xc0000000 | |
6dbd682b | 396 | __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ |
53bd6a60 | 397 | |
1da177e4 | 398 | /* qtd overlay (hardware parts of a struct ehci_qtd) */ |
6dbd682b SR |
399 | __hc32 hw_qtd_next; |
400 | __hc32 hw_alt_next; | |
401 | __hc32 hw_token; | |
402 | __hc32 hw_buf [5]; | |
403 | __hc32 hw_buf_hi [5]; | |
3807e26d | 404 | } __attribute__ ((aligned(32))); |
1da177e4 | 405 | |
3807e26d | 406 | struct ehci_qh { |
8c5bf7be | 407 | struct ehci_qh_hw *hw; /* Must come first */ |
1da177e4 LT |
408 | /* the rest is HCD-private */ |
409 | dma_addr_t qh_dma; /* address of qh */ | |
410 | union ehci_shadow qh_next; /* ptr to qh; or periodic */ | |
411 | struct list_head qtd_list; /* sw qtd list */ | |
569b394f | 412 | struct list_head intr_node; /* list of intr QHs */ |
1da177e4 | 413 | struct ehci_qtd *dummy; |
6e018751 | 414 | struct list_head unlink_node; |
ffa0248e | 415 | struct ehci_per_sched ps; /* scheduling info */ |
1da177e4 | 416 | |
df202255 | 417 | unsigned unlink_cycle; |
1da177e4 LT |
418 | |
419 | u8 qh_state; | |
420 | #define QH_STATE_LINKED 1 /* HC sees this */ | |
421 | #define QH_STATE_UNLINK 2 /* HC may still see this */ | |
422 | #define QH_STATE_IDLE 3 /* HC doesn't see this */ | |
99ac5b1e | 423 | #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ |
1da177e4 LT |
424 | #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ |
425 | ||
a2c2706e AS |
426 | u8 xacterrs; /* XactErr retry counter */ |
427 | #define QH_XACTERR_MAX 32 /* XactErr retry limit */ | |
428 | ||
1da177e4 | 429 | u8 gap_uf; /* uframes split/csplit gap */ |
914b7012 | 430 | |
e04f5f7e | 431 | unsigned is_out:1; /* bulk or intr OUT */ |
914b7012 | 432 | unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ |
7bc782d7 AS |
433 | unsigned dequeue_during_giveback:1; |
434 | unsigned exception:1; /* got a fault, or an unlink | |
435 | was requested */ | |
3807e26d | 436 | }; |
1da177e4 LT |
437 | |
438 | /*-------------------------------------------------------------------------*/ | |
439 | ||
440 | /* description of one iso transaction (up to 3 KB data if highspeed) */ | |
441 | struct ehci_iso_packet { | |
442 | /* These will be copied to iTD when scheduling */ | |
443 | u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ | |
6dbd682b | 444 | __hc32 transaction; /* itd->hw_transaction[i] |= */ |
1da177e4 LT |
445 | u8 cross; /* buf crosses pages */ |
446 | /* for full speed OUT splits */ | |
447 | u32 buf1; | |
448 | }; | |
449 | ||
450 | /* temporary schedule data for packets from iso urbs (both speeds) | |
451 | * each packet is one logical usb transaction to the device (not TT), | |
452 | * beginning at stream->next_uframe | |
453 | */ | |
454 | struct ehci_iso_sched { | |
455 | struct list_head td_list; | |
456 | unsigned span; | |
46c73d1d | 457 | unsigned first_packet; |
1da177e4 LT |
458 | struct ehci_iso_packet packet [0]; |
459 | }; | |
460 | ||
461 | /* | |
462 | * ehci_iso_stream - groups all (s)itds for this endpoint. | |
463 | * acts like a qh would, if EHCI had them for ISO. | |
464 | */ | |
465 | struct ehci_iso_stream { | |
1082f57a CL |
466 | /* first field matches ehci_hq, but is NULL */ |
467 | struct ehci_qh_hw *hw; | |
1da177e4 | 468 | |
1da177e4 LT |
469 | u8 bEndpointAddress; |
470 | u8 highspeed; | |
1da177e4 LT |
471 | struct list_head td_list; /* queued itds/sitds */ |
472 | struct list_head free_list; /* list of unused itds/sitds */ | |
1da177e4 LT |
473 | |
474 | /* output of (re)scheduling */ | |
ffa0248e | 475 | struct ehci_per_sched ps; /* scheduling info */ |
91a99b5e | 476 | unsigned next_uframe; |
6dbd682b | 477 | __hc32 splits; |
1da177e4 LT |
478 | |
479 | /* the rest is derived from the endpoint descriptor, | |
1da177e4 LT |
480 | * including the extra info for hw_bufp[0..2] |
481 | */ | |
ffa0248e | 482 | u16 uperiod; /* period in uframes */ |
1da177e4 | 483 | u16 maxp; |
1da177e4 LT |
484 | unsigned bandwidth; |
485 | ||
486 | /* This is used to initialize iTD's hw_bufp fields */ | |
6dbd682b SR |
487 | __hc32 buf0; |
488 | __hc32 buf1; | |
489 | __hc32 buf2; | |
1da177e4 LT |
490 | |
491 | /* this is used to initialize sITD's tt info */ | |
6dbd682b | 492 | __hc32 address; |
1da177e4 LT |
493 | }; |
494 | ||
495 | /*-------------------------------------------------------------------------*/ | |
496 | ||
497 | /* | |
498 | * EHCI Specification 0.95 Section 3.3 | |
499 | * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" | |
500 | * | |
501 | * Schedule records for high speed iso xfers | |
502 | */ | |
503 | struct ehci_itd { | |
504 | /* first part defined by EHCI spec */ | |
6dbd682b SR |
505 | __hc32 hw_next; /* see EHCI 3.3.1 */ |
506 | __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ | |
1da177e4 LT |
507 | #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ |
508 | #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ | |
509 | #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ | |
510 | #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ | |
511 | #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) | |
512 | #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ | |
513 | ||
6dbd682b | 514 | #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) |
1da177e4 | 515 | |
6dbd682b SR |
516 | __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ |
517 | __hc32 hw_bufp_hi [7]; /* Appendix B */ | |
1da177e4 LT |
518 | |
519 | /* the rest is HCD-private */ | |
520 | dma_addr_t itd_dma; /* for this itd */ | |
521 | union ehci_shadow itd_next; /* ptr to periodic q entry */ | |
522 | ||
523 | struct urb *urb; | |
524 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
525 | struct list_head itd_list; /* list of stream's itds */ | |
526 | ||
527 | /* any/all hw_transactions here may be used by that urb */ | |
528 | unsigned frame; /* where scheduled */ | |
529 | unsigned pg; | |
530 | unsigned index[8]; /* in urb->iso_frame_desc */ | |
1da177e4 LT |
531 | } __attribute__ ((aligned (32))); |
532 | ||
533 | /*-------------------------------------------------------------------------*/ | |
534 | ||
535 | /* | |
53bd6a60 | 536 | * EHCI Specification 0.95 Section 3.4 |
1da177e4 LT |
537 | * siTD, aka split-transaction isochronous Transfer Descriptor |
538 | * ... describe full speed iso xfers through TT in hubs | |
539 | * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) | |
540 | */ | |
541 | struct ehci_sitd { | |
542 | /* first part defined by EHCI spec */ | |
6dbd682b | 543 | __hc32 hw_next; |
1da177e4 | 544 | /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ |
6dbd682b SR |
545 | __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ |
546 | __hc32 hw_uframe; /* EHCI table 3-10 */ | |
547 | __hc32 hw_results; /* EHCI table 3-11 */ | |
1da177e4 LT |
548 | #define SITD_IOC (1 << 31) /* interrupt on completion */ |
549 | #define SITD_PAGE (1 << 30) /* buffer 0/1 */ | |
550 | #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) | |
551 | #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ | |
552 | #define SITD_STS_ERR (1 << 6) /* error from TT */ | |
553 | #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ | |
554 | #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ | |
555 | #define SITD_STS_XACT (1 << 3) /* illegal IN response */ | |
556 | #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ | |
557 | #define SITD_STS_STS (1 << 1) /* split transaction state */ | |
558 | ||
6dbd682b | 559 | #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) |
1da177e4 | 560 | |
6dbd682b SR |
561 | __hc32 hw_buf [2]; /* EHCI table 3-12 */ |
562 | __hc32 hw_backpointer; /* EHCI table 3-13 */ | |
563 | __hc32 hw_buf_hi [2]; /* Appendix B */ | |
1da177e4 LT |
564 | |
565 | /* the rest is HCD-private */ | |
566 | dma_addr_t sitd_dma; | |
567 | union ehci_shadow sitd_next; /* ptr to periodic q entry */ | |
568 | ||
569 | struct urb *urb; | |
570 | struct ehci_iso_stream *stream; /* endpoint's queue */ | |
571 | struct list_head sitd_list; /* list of stream's sitds */ | |
572 | unsigned frame; | |
573 | unsigned index; | |
574 | } __attribute__ ((aligned (32))); | |
575 | ||
576 | /*-------------------------------------------------------------------------*/ | |
577 | ||
578 | /* | |
579 | * EHCI Specification 0.96 Section 3.7 | |
580 | * Periodic Frame Span Traversal Node (FSTN) | |
581 | * | |
582 | * Manages split interrupt transactions (using TT) that span frame boundaries | |
583 | * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN | |
584 | * makes the HC jump (back) to a QH to scan for fs/ls QH completions until | |
585 | * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. | |
586 | */ | |
587 | struct ehci_fstn { | |
6dbd682b SR |
588 | __hc32 hw_next; /* any periodic q entry */ |
589 | __hc32 hw_prev; /* qh or EHCI_LIST_END */ | |
1da177e4 LT |
590 | |
591 | /* the rest is HCD-private */ | |
592 | dma_addr_t fstn_dma; | |
593 | union ehci_shadow fstn_next; /* ptr to periodic q entry */ | |
594 | } __attribute__ ((aligned (32))); | |
595 | ||
596 | /*-------------------------------------------------------------------------*/ | |
597 | ||
16032c4f AS |
598 | /* Prepare the PORTSC wakeup flags during controller suspend/resume */ |
599 | ||
4147200d AS |
600 | #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ |
601 | ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); | |
16032c4f | 602 | |
4147200d AS |
603 | #define ehci_prepare_ports_for_controller_resume(ehci) \ |
604 | ehci_adjust_port_wakeup_flags(ehci, false, false); | |
16032c4f AS |
605 | |
606 | /*-------------------------------------------------------------------------*/ | |
607 | ||
1da177e4 LT |
608 | #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT |
609 | ||
610 | /* | |
611 | * Some EHCI controllers have a Transaction Translator built into the | |
612 | * root hub. This is a non-standard feature. Each controller will need | |
613 | * to add code to the following inline functions, and call them as | |
614 | * needed (mostly in root hub code). | |
615 | */ | |
616 | ||
a8e51775 | 617 | #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) |
1da177e4 LT |
618 | |
619 | /* Returns the speed of a device attached to a port on the root hub. */ | |
620 | static inline unsigned int | |
621 | ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) | |
622 | { | |
623 | if (ehci_is_TDI(ehci)) { | |
331ac6b2 | 624 | switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { |
1da177e4 LT |
625 | case 0: |
626 | return 0; | |
627 | case 1: | |
288ead45 | 628 | return USB_PORT_STAT_LOW_SPEED; |
1da177e4 LT |
629 | case 2: |
630 | default: | |
288ead45 | 631 | return USB_PORT_STAT_HIGH_SPEED; |
1da177e4 LT |
632 | } |
633 | } | |
288ead45 | 634 | return USB_PORT_STAT_HIGH_SPEED; |
1da177e4 LT |
635 | } |
636 | ||
637 | #else | |
638 | ||
639 | #define ehci_is_TDI(e) (0) | |
640 | ||
288ead45 | 641 | #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED |
1da177e4 LT |
642 | #endif |
643 | ||
8cd42e97 KG |
644 | /*-------------------------------------------------------------------------*/ |
645 | ||
646 | #ifdef CONFIG_PPC_83xx | |
647 | /* Some Freescale processors have an erratum in which the TT | |
648 | * port number in the queue head was 0..N-1 instead of 1..N. | |
649 | */ | |
650 | #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) | |
651 | #else | |
652 | #define ehci_has_fsl_portno_bug(e) (0) | |
653 | #endif | |
654 | ||
083522d7 BH |
655 | /* |
656 | * While most USB host controllers implement their registers in | |
657 | * little-endian format, a minority (celleb companion chip) implement | |
658 | * them in big endian format. | |
659 | * | |
660 | * This attempts to support either format at compile time without a | |
661 | * runtime penalty, or both formats with the additional overhead | |
662 | * of checking a flag bit. | |
c430131a JA |
663 | * |
664 | * ehci_big_endian_capbase is a special quirk for controllers that | |
665 | * implement the HC capability registers as separate registers and not | |
666 | * as fields of a 32-bit register. | |
083522d7 BH |
667 | */ |
668 | ||
669 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO | |
670 | #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) | |
c430131a | 671 | #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) |
083522d7 BH |
672 | #else |
673 | #define ehci_big_endian_mmio(e) 0 | |
c430131a | 674 | #define ehci_big_endian_capbase(e) 0 |
083522d7 BH |
675 | #endif |
676 | ||
6dbd682b SR |
677 | /* |
678 | * Big-endian read/write functions are arch-specific. | |
679 | * Other arches can be added if/when they're needed. | |
6dbd682b | 680 | */ |
91bc4d31 VB |
681 | #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) |
682 | #define readl_be(addr) __raw_readl((__force unsigned *)addr) | |
683 | #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) | |
684 | #endif | |
685 | ||
6dbd682b SR |
686 | static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, |
687 | __u32 __iomem * regs) | |
083522d7 | 688 | { |
d728e327 | 689 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 690 | return ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
691 | readl_be(regs) : |
692 | readl(regs); | |
d728e327 | 693 | #else |
68f50e52 | 694 | return readl(regs); |
d728e327 | 695 | #endif |
083522d7 BH |
696 | } |
697 | ||
6dbd682b SR |
698 | static inline void ehci_writel(const struct ehci_hcd *ehci, |
699 | const unsigned int val, __u32 __iomem *regs) | |
083522d7 | 700 | { |
d728e327 | 701 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO |
083522d7 | 702 | ehci_big_endian_mmio(ehci) ? |
68f50e52 AV |
703 | writel_be(val, regs) : |
704 | writel(val, regs); | |
d728e327 | 705 | #else |
68f50e52 | 706 | writel(val, regs); |
d728e327 | 707 | #endif |
083522d7 | 708 | } |
8cd42e97 | 709 | |
796bcae7 VB |
710 | /* |
711 | * On certain ppc-44x SoC there is a HW issue, that could only worked around with | |
712 | * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. | |
25985edc | 713 | * Other common bits are dependent on has_amcc_usb23 quirk flag. |
796bcae7 VB |
714 | */ |
715 | #ifdef CONFIG_44x | |
716 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
717 | { | |
718 | u32 hc_control; | |
719 | ||
720 | hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); | |
721 | if (operational) | |
722 | hc_control |= OHCI_USB_OPER; | |
723 | else | |
724 | hc_control |= OHCI_USB_SUSPEND; | |
725 | ||
726 | writel_be(hc_control, ehci->ohci_hcctrl_reg); | |
727 | (void) readl_be(ehci->ohci_hcctrl_reg); | |
728 | } | |
729 | #else | |
730 | static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) | |
731 | { } | |
732 | #endif | |
733 | ||
1da177e4 LT |
734 | /*-------------------------------------------------------------------------*/ |
735 | ||
6dbd682b SR |
736 | /* |
737 | * The AMCC 440EPx not only implements its EHCI registers in big-endian | |
738 | * format, but also its DMA data structures (descriptors). | |
739 | * | |
740 | * EHCI controllers accessed through PCI work normally (little-endian | |
741 | * everywhere), so we won't bother supporting a BE-only mode for now. | |
742 | */ | |
743 | #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC | |
744 | #define ehci_big_endian_desc(e) ((e)->big_endian_desc) | |
745 | ||
746 | /* cpu to ehci */ | |
747 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
748 | { | |
749 | return ehci_big_endian_desc(ehci) | |
750 | ? (__force __hc32)cpu_to_be32(x) | |
751 | : (__force __hc32)cpu_to_le32(x); | |
752 | } | |
753 | ||
754 | /* ehci to cpu */ | |
755 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
756 | { | |
757 | return ehci_big_endian_desc(ehci) | |
758 | ? be32_to_cpu((__force __be32)x) | |
759 | : le32_to_cpu((__force __le32)x); | |
760 | } | |
761 | ||
762 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
763 | { | |
764 | return ehci_big_endian_desc(ehci) | |
765 | ? be32_to_cpup((__force __be32 *)x) | |
766 | : le32_to_cpup((__force __le32 *)x); | |
767 | } | |
768 | ||
769 | #else | |
770 | ||
771 | /* cpu to ehci */ | |
772 | static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) | |
773 | { | |
774 | return cpu_to_le32(x); | |
775 | } | |
776 | ||
777 | /* ehci to cpu */ | |
778 | static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) | |
779 | { | |
780 | return le32_to_cpu(x); | |
781 | } | |
782 | ||
783 | static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) | |
784 | { | |
785 | return le32_to_cpup(x); | |
786 | } | |
787 | ||
788 | #endif | |
789 | ||
790 | /*-------------------------------------------------------------------------*/ | |
791 | ||
d6064aca AS |
792 | #define ehci_dbg(ehci, fmt, args...) \ |
793 | dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args) | |
794 | #define ehci_err(ehci, fmt, args...) \ | |
795 | dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args) | |
796 | #define ehci_info(ehci, fmt, args...) \ | |
797 | dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args) | |
798 | #define ehci_warn(ehci, fmt, args...) \ | |
799 | dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args) | |
800 | ||
d6064aca | 801 | |
1512c91f | 802 | #if !defined(DEBUG) && !defined(CONFIG_DYNAMIC_DEBUG) |
1da177e4 | 803 | #define STUB_DEBUG_FILES |
1512c91f | 804 | #endif /* !DEBUG && !CONFIG_DYNAMIC_DEBUG */ |
1da177e4 LT |
805 | |
806 | /*-------------------------------------------------------------------------*/ | |
807 | ||
3e023203 AS |
808 | /* Declarations of things exported for use by ehci platform drivers */ |
809 | ||
810 | struct ehci_driver_overrides { | |
3e023203 AS |
811 | size_t extra_priv_size; |
812 | int (*reset)(struct usb_hcd *hcd); | |
813 | }; | |
814 | ||
815 | extern void ehci_init_driver(struct hc_driver *drv, | |
816 | const struct ehci_driver_overrides *over); | |
817 | extern int ehci_setup(struct usb_hcd *hcd); | |
2f3a6b86 MG |
818 | extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, |
819 | u32 mask, u32 done, int usec); | |
3e023203 AS |
820 | |
821 | #ifdef CONFIG_PM | |
822 | extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); | |
823 | extern int ehci_resume(struct usb_hcd *hcd, bool hibernated); | |
824 | #endif /* CONFIG_PM */ | |
825 | ||
1da177e4 | 826 | #endif /* __LINUX_EHCI_HCD_H */ |