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23d3e7a6 MF |
1 | /* |
2 | * Macros and prototypes for i.MX21 | |
3 | * | |
4 | * Copyright (C) 2006 Loping Dog Embedded Systems | |
5 | * Copyright (C) 2009 Martin Fuzzey | |
6 | * Originally written by Jay Monkman <jtm@lopingdog.com> | |
7 | * Ported to 2.6.30, debugged and enhanced by Martin Fuzzey | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software Foundation, | |
21 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #ifndef __LINUX_IMX21_HCD_H__ | |
25 | #define __LINUX_IMX21_HCD_H__ | |
26 | ||
1c20163d ON |
27 | #ifdef CONFIG_DYNAMIC_DEBUG |
28 | #define DEBUG | |
29 | #endif | |
30 | ||
82906b13 | 31 | #include <linux/platform_data/usb-mx2.h> |
23d3e7a6 MF |
32 | |
33 | #define NUM_ISO_ETDS 2 | |
34 | #define USB_NUM_ETD 32 | |
35 | #define DMEM_SIZE 4096 | |
36 | ||
37 | /* Register definitions */ | |
38 | #define USBOTG_HWMODE 0x00 | |
39 | #define USBOTG_HWMODE_ANASDBEN (1 << 14) | |
40 | #define USBOTG_HWMODE_OTGXCVR_SHIFT 6 | |
41 | #define USBOTG_HWMODE_OTGXCVR_MASK (3 << 6) | |
42 | #define USBOTG_HWMODE_OTGXCVR_TD_RD (0 << 6) | |
43 | #define USBOTG_HWMODE_OTGXCVR_TS_RD (2 << 6) | |
44 | #define USBOTG_HWMODE_OTGXCVR_TD_RS (1 << 6) | |
45 | #define USBOTG_HWMODE_OTGXCVR_TS_RS (3 << 6) | |
46 | #define USBOTG_HWMODE_HOSTXCVR_SHIFT 4 | |
47 | #define USBOTG_HWMODE_HOSTXCVR_MASK (3 << 4) | |
48 | #define USBOTG_HWMODE_HOSTXCVR_TD_RD (0 << 4) | |
49 | #define USBOTG_HWMODE_HOSTXCVR_TS_RD (2 << 4) | |
50 | #define USBOTG_HWMODE_HOSTXCVR_TD_RS (1 << 4) | |
51 | #define USBOTG_HWMODE_HOSTXCVR_TS_RS (3 << 4) | |
52 | #define USBOTG_HWMODE_CRECFG_MASK (3 << 0) | |
53 | #define USBOTG_HWMODE_CRECFG_HOST (1 << 0) | |
54 | #define USBOTG_HWMODE_CRECFG_FUNC (2 << 0) | |
55 | #define USBOTG_HWMODE_CRECFG_HNP (3 << 0) | |
56 | ||
57 | #define USBOTG_CINT_STAT 0x04 | |
58 | #define USBOTG_CINT_STEN 0x08 | |
59 | #define USBOTG_ASHNPINT (1 << 5) | |
60 | #define USBOTG_ASFCINT (1 << 4) | |
61 | #define USBOTG_ASHCINT (1 << 3) | |
62 | #define USBOTG_SHNPINT (1 << 2) | |
63 | #define USBOTG_FCINT (1 << 1) | |
64 | #define USBOTG_HCINT (1 << 0) | |
65 | ||
66 | #define USBOTG_CLK_CTRL 0x0c | |
67 | #define USBOTG_CLK_CTRL_FUNC (1 << 2) | |
68 | #define USBOTG_CLK_CTRL_HST (1 << 1) | |
69 | #define USBOTG_CLK_CTRL_MAIN (1 << 0) | |
70 | ||
71 | #define USBOTG_RST_CTRL 0x10 | |
72 | #define USBOTG_RST_RSTI2C (1 << 15) | |
73 | #define USBOTG_RST_RSTCTRL (1 << 5) | |
74 | #define USBOTG_RST_RSTFC (1 << 4) | |
75 | #define USBOTG_RST_RSTFSKE (1 << 3) | |
76 | #define USBOTG_RST_RSTRH (1 << 2) | |
77 | #define USBOTG_RST_RSTHSIE (1 << 1) | |
78 | #define USBOTG_RST_RSTHC (1 << 0) | |
79 | ||
80 | #define USBOTG_FRM_INTVL 0x14 | |
81 | #define USBOTG_FRM_REMAIN 0x18 | |
82 | #define USBOTG_HNP_CSR 0x1c | |
83 | #define USBOTG_HNP_ISR 0x2c | |
84 | #define USBOTG_HNP_IEN 0x30 | |
85 | ||
86 | #define USBOTG_I2C_TXCVR_REG(x) (0x100 + (x)) | |
87 | #define USBOTG_I2C_XCVR_DEVAD 0x118 | |
88 | #define USBOTG_I2C_SEQ_OP_REG 0x119 | |
89 | #define USBOTG_I2C_SEQ_RD_STARTAD 0x11a | |
90 | #define USBOTG_I2C_OP_CTRL_REG 0x11b | |
91 | #define USBOTG_I2C_SCLK_TO_SCK_HPER 0x11e | |
92 | #define USBOTG_I2C_MASTER_INT_REG 0x11f | |
93 | ||
94 | #define USBH_HOST_CTRL 0x80 | |
95 | #define USBH_HOST_CTRL_HCRESET (1 << 31) | |
96 | #define USBH_HOST_CTRL_SCHDOVR(x) ((x) << 16) | |
97 | #define USBH_HOST_CTRL_RMTWUEN (1 << 4) | |
98 | #define USBH_HOST_CTRL_HCUSBSTE_RESET (0 << 2) | |
99 | #define USBH_HOST_CTRL_HCUSBSTE_RESUME (1 << 2) | |
100 | #define USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL (2 << 2) | |
101 | #define USBH_HOST_CTRL_HCUSBSTE_SUSPEND (3 << 2) | |
102 | #define USBH_HOST_CTRL_CTLBLKSR_1 (0 << 0) | |
103 | #define USBH_HOST_CTRL_CTLBLKSR_2 (1 << 0) | |
104 | #define USBH_HOST_CTRL_CTLBLKSR_3 (2 << 0) | |
105 | #define USBH_HOST_CTRL_CTLBLKSR_4 (3 << 0) | |
106 | ||
107 | #define USBH_SYSISR 0x88 | |
108 | #define USBH_SYSISR_PSCINT (1 << 6) | |
109 | #define USBH_SYSISR_FMOFINT (1 << 5) | |
110 | #define USBH_SYSISR_HERRINT (1 << 4) | |
111 | #define USBH_SYSISR_RESDETINT (1 << 3) | |
112 | #define USBH_SYSISR_SOFINT (1 << 2) | |
113 | #define USBH_SYSISR_DONEINT (1 << 1) | |
114 | #define USBH_SYSISR_SORINT (1 << 0) | |
115 | ||
116 | #define USBH_SYSIEN 0x8c | |
117 | #define USBH_SYSIEN_PSCINT (1 << 6) | |
118 | #define USBH_SYSIEN_FMOFINT (1 << 5) | |
119 | #define USBH_SYSIEN_HERRINT (1 << 4) | |
120 | #define USBH_SYSIEN_RESDETINT (1 << 3) | |
121 | #define USBH_SYSIEN_SOFINT (1 << 2) | |
122 | #define USBH_SYSIEN_DONEINT (1 << 1) | |
123 | #define USBH_SYSIEN_SORINT (1 << 0) | |
124 | ||
125 | #define USBH_XBUFSTAT 0x98 | |
126 | #define USBH_YBUFSTAT 0x9c | |
127 | #define USBH_XYINTEN 0xa0 | |
128 | #define USBH_XFILLSTAT 0xa8 | |
129 | #define USBH_YFILLSTAT 0xac | |
130 | #define USBH_ETDENSET 0xc0 | |
131 | #define USBH_ETDENCLR 0xc4 | |
132 | #define USBH_IMMEDINT 0xcc | |
133 | #define USBH_ETDDONESTAT 0xd0 | |
134 | #define USBH_ETDDONEEN 0xd4 | |
135 | #define USBH_FRMNUB 0xe0 | |
136 | #define USBH_LSTHRESH 0xe4 | |
137 | ||
138 | #define USBH_ROOTHUBA 0xe8 | |
139 | #define USBH_ROOTHUBA_PWRTOGOOD_MASK (0xff) | |
140 | #define USBH_ROOTHUBA_PWRTOGOOD_SHIFT (24) | |
141 | #define USBH_ROOTHUBA_NOOVRCURP (1 << 12) | |
142 | #define USBH_ROOTHUBA_OVRCURPM (1 << 11) | |
143 | #define USBH_ROOTHUBA_DEVTYPE (1 << 10) | |
144 | #define USBH_ROOTHUBA_PWRSWTMD (1 << 9) | |
145 | #define USBH_ROOTHUBA_NOPWRSWT (1 << 8) | |
146 | #define USBH_ROOTHUBA_NDNSTMPRT_MASK (0xff) | |
147 | ||
148 | #define USBH_ROOTHUBB 0xec | |
149 | #define USBH_ROOTHUBB_PRTPWRCM(x) (1 << ((x) + 16)) | |
150 | #define USBH_ROOTHUBB_DEVREMOVE(x) (1 << (x)) | |
151 | ||
152 | #define USBH_ROOTSTAT 0xf0 | |
153 | #define USBH_ROOTSTAT_CLRRMTWUE (1 << 31) | |
154 | #define USBH_ROOTSTAT_OVRCURCHG (1 << 17) | |
155 | #define USBH_ROOTSTAT_DEVCONWUE (1 << 15) | |
156 | #define USBH_ROOTSTAT_OVRCURI (1 << 1) | |
157 | #define USBH_ROOTSTAT_LOCPWRS (1 << 0) | |
158 | ||
159 | #define USBH_PORTSTAT(x) (0xf4 + ((x) * 4)) | |
160 | #define USBH_PORTSTAT_PRTRSTSC (1 << 20) | |
161 | #define USBH_PORTSTAT_OVRCURIC (1 << 19) | |
162 | #define USBH_PORTSTAT_PRTSTATSC (1 << 18) | |
163 | #define USBH_PORTSTAT_PRTENBLSC (1 << 17) | |
164 | #define USBH_PORTSTAT_CONNECTSC (1 << 16) | |
165 | #define USBH_PORTSTAT_LSDEVCON (1 << 9) | |
166 | #define USBH_PORTSTAT_PRTPWRST (1 << 8) | |
167 | #define USBH_PORTSTAT_PRTRSTST (1 << 4) | |
168 | #define USBH_PORTSTAT_PRTOVRCURI (1 << 3) | |
169 | #define USBH_PORTSTAT_PRTSUSPST (1 << 2) | |
170 | #define USBH_PORTSTAT_PRTENABST (1 << 1) | |
171 | #define USBH_PORTSTAT_CURCONST (1 << 0) | |
172 | ||
173 | #define USB_DMAREV 0x800 | |
174 | #define USB_DMAINTSTAT 0x804 | |
175 | #define USB_DMAINTSTAT_EPERR (1 << 1) | |
176 | #define USB_DMAINTSTAT_ETDERR (1 << 0) | |
177 | ||
178 | #define USB_DMAINTEN 0x808 | |
179 | #define USB_DMAINTEN_EPERRINTEN (1 << 1) | |
180 | #define USB_DMAINTEN_ETDERRINTEN (1 << 0) | |
181 | ||
182 | #define USB_ETDDMAERSTAT 0x80c | |
183 | #define USB_EPDMAERSTAT 0x810 | |
184 | #define USB_ETDDMAEN 0x820 | |
185 | #define USB_EPDMAEN 0x824 | |
186 | #define USB_ETDDMAXTEN 0x828 | |
187 | #define USB_EPDMAXTEN 0x82c | |
188 | #define USB_ETDDMAENXYT 0x830 | |
189 | #define USB_EPDMAENXYT 0x834 | |
190 | #define USB_ETDDMABST4EN 0x838 | |
191 | #define USB_EPDMABST4EN 0x83c | |
192 | ||
193 | #define USB_MISCCONTROL 0x840 | |
194 | #define USB_MISCCONTROL_ISOPREVFRM (1 << 3) | |
195 | #define USB_MISCCONTROL_SKPRTRY (1 << 2) | |
196 | #define USB_MISCCONTROL_ARBMODE (1 << 1) | |
197 | #define USB_MISCCONTROL_FILTCC (1 << 0) | |
198 | ||
199 | #define USB_ETDDMACHANLCLR 0x848 | |
200 | #define USB_EPDMACHANLCLR 0x84c | |
201 | #define USB_ETDSMSA(x) (0x900 + ((x) * 4)) | |
202 | #define USB_EPSMSA(x) (0x980 + ((x) * 4)) | |
203 | #define USB_ETDDMABUFPTR(x) (0xa00 + ((x) * 4)) | |
204 | #define USB_EPDMABUFPTR(x) (0xa80 + ((x) * 4)) | |
205 | ||
206 | #define USB_ETD_DWORD(x, w) (0x200 + ((x) * 16) + ((w) * 4)) | |
207 | #define DW0_ADDRESS 0 | |
208 | #define DW0_ENDPNT 7 | |
209 | #define DW0_DIRECT 11 | |
210 | #define DW0_SPEED 13 | |
211 | #define DW0_FORMAT 14 | |
212 | #define DW0_MAXPKTSIZ 16 | |
213 | #define DW0_HALTED 27 | |
214 | #define DW0_TOGCRY 28 | |
215 | #define DW0_SNDNAK 30 | |
216 | ||
217 | #define DW1_XBUFSRTAD 0 | |
218 | #define DW1_YBUFSRTAD 16 | |
219 | ||
220 | #define DW2_RTRYDELAY 0 | |
221 | #define DW2_POLINTERV 0 | |
222 | #define DW2_STARTFRM 0 | |
223 | #define DW2_RELPOLPOS 8 | |
224 | #define DW2_DIRPID 16 | |
225 | #define DW2_BUFROUND 18 | |
226 | #define DW2_DELAYINT 19 | |
227 | #define DW2_DATATOG 22 | |
228 | #define DW2_ERRORCNT 24 | |
229 | #define DW2_COMPCODE 28 | |
230 | ||
231 | #define DW3_TOTBYECNT 0 | |
232 | #define DW3_PKTLEN0 0 | |
233 | #define DW3_COMPCODE0 12 | |
234 | #define DW3_PKTLEN1 16 | |
235 | #define DW3_BUFSIZE 21 | |
236 | #define DW3_COMPCODE1 28 | |
237 | ||
238 | #define USBCTRL 0x600 | |
239 | #define USBCTRL_I2C_WU_INT_STAT (1 << 27) | |
240 | #define USBCTRL_OTG_WU_INT_STAT (1 << 26) | |
241 | #define USBCTRL_HOST_WU_INT_STAT (1 << 25) | |
242 | #define USBCTRL_FNT_WU_INT_STAT (1 << 24) | |
243 | #define USBCTRL_I2C_WU_INT_EN (1 << 19) | |
244 | #define USBCTRL_OTG_WU_INT_EN (1 << 18) | |
245 | #define USBCTRL_HOST_WU_INT_EN (1 << 17) | |
246 | #define USBCTRL_FNT_WU_INT_EN (1 << 16) | |
247 | #define USBCTRL_OTC_RCV_RXDP (1 << 13) | |
248 | #define USBCTRL_HOST1_BYP_TLL (1 << 12) | |
249 | #define USBCTRL_OTG_BYP_VAL(x) ((x) << 10) | |
250 | #define USBCTRL_HOST1_BYP_VAL(x) ((x) << 8) | |
251 | #define USBCTRL_OTG_PWR_MASK (1 << 6) | |
252 | #define USBCTRL_HOST1_PWR_MASK (1 << 5) | |
253 | #define USBCTRL_HOST2_PWR_MASK (1 << 4) | |
254 | #define USBCTRL_USB_BYP (1 << 2) | |
255 | #define USBCTRL_HOST1_TXEN_OE (1 << 1) | |
256 | ||
d0cc3d41 | 257 | #define USBOTG_DMEM 0x1000 |
23d3e7a6 MF |
258 | |
259 | /* Values in TD blocks */ | |
260 | #define TD_DIR_SETUP 0 | |
261 | #define TD_DIR_OUT 1 | |
262 | #define TD_DIR_IN 2 | |
263 | #define TD_FORMAT_CONTROL 0 | |
264 | #define TD_FORMAT_ISO 1 | |
265 | #define TD_FORMAT_BULK 2 | |
266 | #define TD_FORMAT_INT 3 | |
267 | #define TD_TOGGLE_CARRY 0 | |
268 | #define TD_TOGGLE_DATA0 2 | |
269 | #define TD_TOGGLE_DATA1 3 | |
270 | ||
271 | /* control transfer states */ | |
272 | #define US_CTRL_SETUP 2 | |
273 | #define US_CTRL_DATA 1 | |
274 | #define US_CTRL_ACK 0 | |
275 | ||
276 | /* bulk transfer main state and 0-length packet */ | |
277 | #define US_BULK 1 | |
278 | #define US_BULK0 0 | |
279 | ||
280 | /*ETD format description*/ | |
281 | #define IMX_FMT_CTRL 0x0 | |
282 | #define IMX_FMT_ISO 0x1 | |
283 | #define IMX_FMT_BULK 0x2 | |
284 | #define IMX_FMT_INT 0x3 | |
285 | ||
286 | static char fmt_urb_to_etd[4] = { | |
287 | /*PIPE_ISOCHRONOUS*/ IMX_FMT_ISO, | |
288 | /*PIPE_INTERRUPT*/ IMX_FMT_INT, | |
289 | /*PIPE_CONTROL*/ IMX_FMT_CTRL, | |
290 | /*PIPE_BULK*/ IMX_FMT_BULK | |
291 | }; | |
292 | ||
293 | /* condition (error) CC codes and mapping (OHCI like) */ | |
294 | ||
295 | #define TD_CC_NOERROR 0x00 | |
296 | #define TD_CC_CRC 0x01 | |
297 | #define TD_CC_BITSTUFFING 0x02 | |
298 | #define TD_CC_DATATOGGLEM 0x03 | |
299 | #define TD_CC_STALL 0x04 | |
300 | #define TD_DEVNOTRESP 0x05 | |
301 | #define TD_PIDCHECKFAIL 0x06 | |
302 | /*#define TD_UNEXPECTEDPID 0x07 - reserved, not active on MX2*/ | |
303 | #define TD_DATAOVERRUN 0x08 | |
304 | #define TD_DATAUNDERRUN 0x09 | |
305 | #define TD_BUFFEROVERRUN 0x0C | |
306 | #define TD_BUFFERUNDERRUN 0x0D | |
307 | #define TD_SCHEDULEOVERRUN 0x0E | |
308 | #define TD_NOTACCESSED 0x0F | |
309 | ||
310 | static const int cc_to_error[16] = { | |
311 | /* No Error */ 0, | |
312 | /* CRC Error */ -EILSEQ, | |
313 | /* Bit Stuff */ -EPROTO, | |
314 | /* Data Togg */ -EILSEQ, | |
315 | /* Stall */ -EPIPE, | |
316 | /* DevNotResp */ -ETIMEDOUT, | |
317 | /* PIDCheck */ -EPROTO, | |
318 | /* UnExpPID */ -EPROTO, | |
319 | /* DataOver */ -EOVERFLOW, | |
320 | /* DataUnder */ -EREMOTEIO, | |
321 | /* (for hw) */ -EIO, | |
322 | /* (for hw) */ -EIO, | |
323 | /* BufferOver */ -ECOMM, | |
324 | /* BuffUnder */ -ENOSR, | |
325 | /* (for HCD) */ -ENOSPC, | |
326 | /* (for HCD) */ -EALREADY | |
327 | }; | |
328 | ||
329 | /* HCD data associated with a usb core URB */ | |
330 | struct urb_priv { | |
331 | struct urb *urb; | |
332 | struct usb_host_endpoint *ep; | |
333 | int active; | |
334 | int state; | |
335 | struct td *isoc_td; | |
336 | int isoc_remaining; | |
337 | int isoc_status; | |
338 | }; | |
339 | ||
340 | /* HCD data associated with a usb core endpoint */ | |
341 | struct ep_priv { | |
342 | struct usb_host_endpoint *ep; | |
343 | struct list_head td_list; | |
344 | struct list_head queue; | |
345 | int etd[NUM_ISO_ETDS]; | |
346 | int waiting_etd; | |
347 | }; | |
348 | ||
349 | /* isoc packet */ | |
350 | struct td { | |
351 | struct list_head list; | |
352 | struct urb *urb; | |
353 | struct usb_host_endpoint *ep; | |
d0cc3d41 MF |
354 | dma_addr_t dma_handle; |
355 | void *cpu_buffer; | |
23d3e7a6 MF |
356 | int len; |
357 | int frame; | |
358 | int isoc_index; | |
359 | }; | |
360 | ||
361 | /* HCD data associated with a hardware ETD */ | |
362 | struct etd_priv { | |
363 | struct usb_host_endpoint *ep; | |
364 | struct urb *urb; | |
365 | struct td *td; | |
366 | struct list_head queue; | |
367 | dma_addr_t dma_handle; | |
d0cc3d41 MF |
368 | void *cpu_buffer; |
369 | void *bounce_buffer; | |
23d3e7a6 MF |
370 | int alloc; |
371 | int len; | |
372 | int dmem_size; | |
373 | int dmem_offset; | |
374 | int active_count; | |
375 | #ifdef DEBUG | |
376 | int activated_frame; | |
377 | int disactivated_frame; | |
378 | int last_int_frame; | |
379 | int last_req_frame; | |
380 | u32 submitted_dwords[4]; | |
381 | #endif | |
382 | }; | |
383 | ||
384 | /* Hardware data memory info */ | |
385 | struct imx21_dmem_area { | |
386 | struct usb_host_endpoint *ep; | |
387 | unsigned int offset; | |
388 | unsigned int size; | |
389 | struct list_head list; | |
390 | }; | |
391 | ||
392 | #ifdef DEBUG | |
393 | struct debug_usage_stats { | |
394 | unsigned int value; | |
395 | unsigned int maximum; | |
396 | }; | |
397 | ||
398 | struct debug_stats { | |
399 | unsigned long submitted; | |
400 | unsigned long completed_ok; | |
401 | unsigned long completed_failed; | |
402 | unsigned long unlinked; | |
403 | unsigned long queue_etd; | |
404 | unsigned long queue_dmem; | |
405 | }; | |
406 | ||
407 | struct debug_isoc_trace { | |
408 | int schedule_frame; | |
409 | int submit_frame; | |
410 | int request_len; | |
411 | int done_frame; | |
412 | int done_len; | |
413 | int cc; | |
414 | struct td *td; | |
415 | }; | |
416 | #endif | |
417 | ||
418 | /* HCD data structure */ | |
419 | struct imx21 { | |
420 | spinlock_t lock; | |
421 | struct device *dev; | |
d0cc3d41 | 422 | struct usb_hcd *hcd; |
23d3e7a6 MF |
423 | struct mx21_usbh_platform_data *pdata; |
424 | struct list_head dmem_list; | |
425 | struct list_head queue_for_etd; /* eps queued due to etd shortage */ | |
426 | struct list_head queue_for_dmem; /* etds queued due to dmem shortage */ | |
427 | struct etd_priv etd[USB_NUM_ETD]; | |
428 | struct clk *clk; | |
429 | void __iomem *regs; | |
430 | #ifdef DEBUG | |
431 | struct dentry *debug_root; | |
432 | struct debug_stats nonisoc_stats; | |
433 | struct debug_stats isoc_stats; | |
434 | struct debug_usage_stats etd_usage; | |
435 | struct debug_usage_stats dmem_usage; | |
436 | struct debug_isoc_trace isoc_trace[20]; | |
437 | struct debug_isoc_trace isoc_trace_failed[20]; | |
438 | unsigned long debug_unblocks; | |
439 | int isoc_trace_index; | |
440 | int isoc_trace_index_failed; | |
441 | #endif | |
442 | }; | |
443 | ||
444 | #endif |