Commit | Line | Data |
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a9d43091 LW |
1 | /* |
2 | * ISP1362 HCD (Host Controller Driver) for USB. | |
3 | * | |
4 | * COPYRIGHT (C) by L. Wassmann <LW@KARO-electronics.de> | |
5 | */ | |
6 | ||
7 | /* ------------------------------------------------------------------------- */ | |
8 | /* | |
9 | * Platform specific compile time options | |
10 | */ | |
10d0ca02 | 11 | #if defined(CONFIG_BLACKFIN) |
a9d43091 LW |
12 | |
13 | #include <linux/io.h> | |
14 | #define USE_32BIT 0 | |
15 | #define MAX_ROOT_PORTS 2 | |
16 | #define USE_PLATFORM_DELAY 0 | |
17 | #define USE_NDELAY 1 | |
18 | ||
19 | #define DUMMY_DELAY_ACCESS \ | |
20 | do { \ | |
21 | bfin_read16(ASYNC_BANK0_BASE); \ | |
22 | bfin_read16(ASYNC_BANK0_BASE); \ | |
23 | bfin_read16(ASYNC_BANK0_BASE); \ | |
24 | } while (0) | |
25 | ||
26 | #undef insw | |
27 | #undef outsw | |
28 | ||
29 | #define insw delayed_insw | |
30 | #define outsw delayed_outsw | |
31 | ||
32 | static inline void delayed_outsw(unsigned int addr, void *buf, int len) | |
33 | { | |
34 | unsigned short *bp = (unsigned short *)buf; | |
35 | while (len--) { | |
36 | DUMMY_DELAY_ACCESS; | |
37 | outw(*bp++, addr); | |
38 | } | |
39 | } | |
40 | ||
41 | static inline void delayed_insw(unsigned int addr, void *buf, int len) | |
42 | { | |
43 | unsigned short *bp = (unsigned short *)buf; | |
44 | while (len--) { | |
45 | DUMMY_DELAY_ACCESS; | |
0c8a32df | 46 | *bp++ = inw(addr); |
a9d43091 LW |
47 | } |
48 | } | |
49 | ||
50 | #else | |
51 | ||
52 | #define MAX_ROOT_PORTS 2 | |
53 | ||
54 | #define USE_32BIT 0 | |
55 | ||
56 | /* These options are mutually eclusive */ | |
57 | #define USE_PLATFORM_DELAY 0 | |
58 | #define USE_NDELAY 0 | |
59 | ||
60 | #define DUMMY_DELAY_ACCESS do {} while (0) | |
61 | ||
62 | #endif | |
63 | ||
64 | ||
65 | /* ------------------------------------------------------------------------- */ | |
66 | ||
67 | #define USB_RESET_WIDTH 50 | |
68 | #define MAX_XFER_SIZE 1023 | |
69 | ||
70 | /* Buffer sizes */ | |
71 | #define ISP1362_BUF_SIZE 4096 | |
72 | #define ISP1362_ISTL_BUFSIZE 512 | |
73 | #define ISP1362_INTL_BLKSIZE 64 | |
74 | #define ISP1362_INTL_BUFFERS 16 | |
75 | #define ISP1362_ATL_BLKSIZE 64 | |
76 | ||
77 | #define ISP1362_REG_WRITE_OFFSET 0x80 | |
78 | ||
a9d43091 LW |
79 | #define REG_WIDTH_16 0x000 |
80 | #define REG_WIDTH_32 0x100 | |
81 | #define REG_WIDTH_MASK 0x100 | |
82 | #define REG_NO_MASK 0x0ff | |
83 | ||
641c86cd GKH |
84 | #ifdef ISP1362_DEBUG |
85 | typedef const unsigned int isp1362_reg_t; | |
86 | ||
a9d43091 LW |
87 | #define REG_ACCESS_R 0x200 |
88 | #define REG_ACCESS_W 0x400 | |
89 | #define REG_ACCESS_RW 0x600 | |
90 | #define REG_ACCESS_MASK 0x600 | |
91 | ||
92 | #define ISP1362_REG_NO(r) ((r) & REG_NO_MASK) | |
93 | ||
a9d43091 LW |
94 | #define ISP1362_REG(name, addr, width, rw) \ |
95 | static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw)) | |
96 | ||
97 | #define REG_ACCESS_TEST(r) BUG_ON(((r) & ISP1362_REG_WRITE_OFFSET) && !((r) & REG_ACCESS_W)) | |
98 | #define REG_WIDTH_TEST(r, w) BUG_ON(((r) & REG_WIDTH_MASK) != (w)) | |
99 | #else | |
100 | typedef const unsigned char isp1362_reg_t; | |
101 | #define ISP1362_REG_NO(r) (r) | |
a9d43091 LW |
102 | |
103 | #define ISP1362_REG(name, addr, width, rw) \ | |
104 | static isp1362_reg_t ISP1362_REG_##name = addr | |
105 | ||
106 | #define REG_ACCESS_TEST(r) do {} while (0) | |
107 | #define REG_WIDTH_TEST(r, w) do {} while (0) | |
108 | #endif | |
109 | ||
110 | /* OHCI compatible registers */ | |
111 | /* | |
112 | * Note: Some of the ISP1362 'OHCI' registers implement only | |
113 | * a subset of the bits defined in the OHCI spec. | |
114 | * | |
115 | * Bitmasks for the individual bits of these registers are defined in "ohci.h" | |
116 | */ | |
117 | ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R); | |
118 | ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW); | |
119 | ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW); | |
120 | ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW); | |
121 | ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW); | |
122 | ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW); | |
123 | ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW); | |
124 | ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW); | |
125 | ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW); | |
126 | ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW); | |
127 | ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW); | |
128 | ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW); | |
129 | ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW); | |
130 | ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW); | |
131 | ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW); | |
132 | ||
133 | /* Philips ISP1362 specific registers */ | |
134 | ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW); | |
135 | #define HCHWCFG_DISABLE_SUSPEND (1 << 15) | |
136 | #define HCHWCFG_GLOBAL_PWRDOWN (1 << 14) | |
7949f4e1 KM |
137 | #define HCHWCFG_PULLDOWN_DS2 (1 << 13) |
138 | #define HCHWCFG_PULLDOWN_DS1 (1 << 12) | |
a9d43091 LW |
139 | #define HCHWCFG_CLKNOTSTOP (1 << 11) |
140 | #define HCHWCFG_ANALOG_OC (1 << 10) | |
141 | #define HCHWCFG_ONEINT (1 << 9) | |
142 | #define HCHWCFG_DACK_MODE (1 << 8) | |
143 | #define HCHWCFG_ONEDMA (1 << 7) | |
144 | #define HCHWCFG_DACK_POL (1 << 6) | |
145 | #define HCHWCFG_DREQ_POL (1 << 5) | |
146 | #define HCHWCFG_DBWIDTH_MASK (0x03 << 3) | |
147 | #define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK) | |
148 | #define HCHWCFG_INT_POL (1 << 2) | |
149 | #define HCHWCFG_INT_TRIGGER (1 << 1) | |
150 | #define HCHWCFG_INT_ENABLE (1 << 0) | |
151 | ||
152 | ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW); | |
153 | #define HCDMACFG_CTR_ENABLE (1 << 7) | |
154 | #define HCDMACFG_BURST_LEN_MASK (0x03 << 5) | |
155 | #define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK) | |
156 | #define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0) | |
157 | #define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1) | |
158 | #define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2) | |
159 | #define HCDMACFG_DMA_ENABLE (1 << 4) | |
160 | #define HCDMACFG_BUF_TYPE_MASK (0x07 << 1) | |
161 | #define HCDMACFG_BUF_TYPE(n) (((n) << 1) & HCDMACFG_BUF_TYPE_MASK) | |
162 | #define HCDMACFG_BUF_ISTL0 HCDMACFG_BUF_TYPE(0) | |
163 | #define HCDMACFG_BUF_ISTL1 HCDMACFG_BUF_TYPE(1) | |
164 | #define HCDMACFG_BUF_INTL HCDMACFG_BUF_TYPE(2) | |
165 | #define HCDMACFG_BUF_ATL HCDMACFG_BUF_TYPE(3) | |
166 | #define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4) | |
167 | #define HCDMACFG_DMA_RW_SELECT (1 << 0) | |
168 | ||
169 | ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW); | |
170 | ||
171 | ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW); | |
172 | #define HCuPINT_SOF (1 << 0) | |
173 | #define HCuPINT_ISTL0 (1 << 1) | |
174 | #define HCuPINT_ISTL1 (1 << 2) | |
175 | #define HCuPINT_EOT (1 << 3) | |
176 | #define HCuPINT_OPR (1 << 4) | |
177 | #define HCuPINT_SUSP (1 << 5) | |
178 | #define HCuPINT_CLKRDY (1 << 6) | |
179 | #define HCuPINT_INTL (1 << 7) | |
180 | #define HCuPINT_ATL (1 << 8) | |
181 | #define HCuPINT_OTG (1 << 9) | |
182 | ||
183 | ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW); | |
184 | /* same bit definitions apply as for HCuPINT */ | |
185 | ||
186 | ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R); | |
187 | #define HCCHIPID_MASK 0xff00 | |
188 | #define HCCHIPID_MAGIC 0x3600 | |
189 | ||
190 | ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW); | |
191 | ||
192 | ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W); | |
193 | #define HCSWRES_MAGIC 0x00f6 | |
194 | ||
195 | ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW); | |
196 | #define HCBUFSTAT_ISTL0_FULL (1 << 0) | |
197 | #define HCBUFSTAT_ISTL1_FULL (1 << 1) | |
198 | #define HCBUFSTAT_INTL_ACTIVE (1 << 2) | |
199 | #define HCBUFSTAT_ATL_ACTIVE (1 << 3) | |
200 | #define HCBUFSTAT_RESET_HWPP (1 << 4) | |
201 | #define HCBUFSTAT_ISTL0_ACTIVE (1 << 5) | |
202 | #define HCBUFSTAT_ISTL1_ACTIVE (1 << 6) | |
203 | #define HCBUFSTAT_ISTL0_DONE (1 << 8) | |
204 | #define HCBUFSTAT_ISTL1_DONE (1 << 9) | |
205 | #define HCBUFSTAT_PAIRED_PTDPP (1 << 10) | |
206 | ||
207 | ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW); | |
208 | #define HCDIRADDR_ADDR_MASK 0x0000ffff | |
209 | #define HCDIRADDR_ADDR(n) (((n) << 0) & HCDIRADDR_ADDR_MASK) | |
210 | #define HCDIRADDR_COUNT_MASK 0xffff0000 | |
211 | #define HCDIRADDR_COUNT(n) (((n) << 16) & HCDIRADDR_COUNT_MASK) | |
212 | ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW); | |
213 | ||
214 | ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW); | |
215 | ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW); | |
216 | ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW); | |
217 | ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW); | |
218 | ||
219 | ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW); | |
220 | ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW); | |
221 | ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW); | |
222 | ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R); | |
223 | ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW); | |
224 | ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW); | |
225 | ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R); | |
226 | ||
227 | ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW); | |
228 | ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW); | |
229 | ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW); | |
230 | ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R); | |
231 | ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW); | |
232 | ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW); | |
233 | ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R); | |
234 | ||
235 | ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW); | |
236 | ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW); | |
237 | ||
238 | ||
239 | ISP1362_REG(OTGCONTROL, 0x62, REG_WIDTH_16, REG_ACCESS_RW); | |
240 | ISP1362_REG(OTGSTATUS, 0x67, REG_WIDTH_16, REG_ACCESS_R); | |
241 | ISP1362_REG(OTGINT, 0x68, REG_WIDTH_16, REG_ACCESS_RW); | |
242 | ISP1362_REG(OTGINTENB, 0x69, REG_WIDTH_16, REG_ACCESS_RW); | |
243 | ISP1362_REG(OTGTIMER, 0x6A, REG_WIDTH_16, REG_ACCESS_RW); | |
244 | ISP1362_REG(OTGALTTMR, 0x6C, REG_WIDTH_16, REG_ACCESS_RW); | |
245 | ||
246 | /* Philips transfer descriptor, cpu-endian */ | |
247 | struct ptd { | |
248 | u16 count; | |
249 | #define PTD_COUNT_MSK (0x3ff << 0) | |
250 | #define PTD_TOGGLE_MSK (1 << 10) | |
251 | #define PTD_ACTIVE_MSK (1 << 11) | |
252 | #define PTD_CC_MSK (0xf << 12) | |
253 | u16 mps; | |
254 | #define PTD_MPS_MSK (0x3ff << 0) | |
255 | #define PTD_SPD_MSK (1 << 10) | |
256 | #define PTD_LAST_MSK (1 << 11) | |
257 | #define PTD_EP_MSK (0xf << 12) | |
258 | u16 len; | |
259 | #define PTD_LEN_MSK (0x3ff << 0) | |
260 | #define PTD_DIR_MSK (3 << 10) | |
261 | #define PTD_DIR_SETUP (0) | |
262 | #define PTD_DIR_OUT (1) | |
263 | #define PTD_DIR_IN (2) | |
264 | u16 faddr; | |
265 | #define PTD_FA_MSK (0x7f << 0) | |
266 | /* PTD Byte 7: [StartingFrame (if ISO PTD) | StartingFrame[0..4], PollingRate[0..2] (if INT PTD)] */ | |
267 | #define PTD_SF_ISO_MSK (0xff << 8) | |
268 | #define PTD_SF_INT_MSK (0x1f << 8) | |
269 | #define PTD_PR_MSK (0x07 << 13) | |
270 | } __attribute__ ((packed, aligned(2))); | |
271 | #define PTD_HEADER_SIZE sizeof(struct ptd) | |
272 | ||
273 | /* ------------------------------------------------------------------------- */ | |
274 | /* Copied from ohci.h: */ | |
275 | /* | |
276 | * Hardware transfer status codes -- CC from PTD | |
277 | */ | |
278 | #define PTD_CC_NOERROR 0x00 | |
279 | #define PTD_CC_CRC 0x01 | |
280 | #define PTD_CC_BITSTUFFING 0x02 | |
281 | #define PTD_CC_DATATOGGLEM 0x03 | |
282 | #define PTD_CC_STALL 0x04 | |
283 | #define PTD_DEVNOTRESP 0x05 | |
284 | #define PTD_PIDCHECKFAIL 0x06 | |
285 | #define PTD_UNEXPECTEDPID 0x07 | |
286 | #define PTD_DATAOVERRUN 0x08 | |
287 | #define PTD_DATAUNDERRUN 0x09 | |
288 | /* 0x0A, 0x0B reserved for hardware */ | |
289 | #define PTD_BUFFEROVERRUN 0x0C | |
290 | #define PTD_BUFFERUNDERRUN 0x0D | |
291 | /* 0x0E, 0x0F reserved for HCD */ | |
292 | #define PTD_NOTACCESSED 0x0F | |
293 | ||
294 | ||
295 | /* map OHCI TD status codes (CC) to errno values */ | |
296 | static const int cc_to_error[16] = { | |
297 | /* No Error */ 0, | |
298 | /* CRC Error */ -EILSEQ, | |
299 | /* Bit Stuff */ -EPROTO, | |
300 | /* Data Togg */ -EILSEQ, | |
301 | /* Stall */ -EPIPE, | |
302 | /* DevNotResp */ -ETIMEDOUT, | |
303 | /* PIDCheck */ -EPROTO, | |
304 | /* UnExpPID */ -EPROTO, | |
305 | /* DataOver */ -EOVERFLOW, | |
306 | /* DataUnder */ -EREMOTEIO, | |
307 | /* (for hw) */ -EIO, | |
308 | /* (for hw) */ -EIO, | |
309 | /* BufferOver */ -ECOMM, | |
310 | /* BuffUnder */ -ENOSR, | |
311 | /* (for HCD) */ -EALREADY, | |
312 | /* (for HCD) */ -EALREADY | |
313 | }; | |
314 | ||
315 | ||
316 | /* | |
317 | * HcControl (control) register masks | |
318 | */ | |
319 | #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ | |
320 | #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ | |
321 | #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ | |
322 | ||
323 | /* pre-shifted values for HCFS */ | |
324 | # define OHCI_USB_RESET (0 << 6) | |
325 | # define OHCI_USB_RESUME (1 << 6) | |
326 | # define OHCI_USB_OPER (2 << 6) | |
327 | # define OHCI_USB_SUSPEND (3 << 6) | |
328 | ||
329 | /* | |
330 | * HcCommandStatus (cmdstatus) register masks | |
331 | */ | |
332 | #define OHCI_HCR (1 << 0) /* host controller reset */ | |
333 | #define OHCI_SOC (3 << 16) /* scheduling overrun count */ | |
334 | ||
335 | /* | |
336 | * masks used with interrupt registers: | |
337 | * HcInterruptStatus (intrstatus) | |
338 | * HcInterruptEnable (intrenable) | |
339 | * HcInterruptDisable (intrdisable) | |
340 | */ | |
341 | #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ | |
342 | #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ | |
343 | #define OHCI_INTR_SF (1 << 2) /* start frame */ | |
344 | #define OHCI_INTR_RD (1 << 3) /* resume detect */ | |
345 | #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ | |
346 | #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ | |
347 | #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ | |
348 | #define OHCI_INTR_OC (1 << 30) /* ownership change */ | |
349 | #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ | |
350 | ||
351 | /* roothub.portstatus [i] bits */ | |
352 | #define RH_PS_CCS 0x00000001 /* current connect status */ | |
353 | #define RH_PS_PES 0x00000002 /* port enable status*/ | |
354 | #define RH_PS_PSS 0x00000004 /* port suspend status */ | |
355 | #define RH_PS_POCI 0x00000008 /* port over current indicator */ | |
356 | #define RH_PS_PRS 0x00000010 /* port reset status */ | |
357 | #define RH_PS_PPS 0x00000100 /* port power status */ | |
358 | #define RH_PS_LSDA 0x00000200 /* low speed device attached */ | |
359 | #define RH_PS_CSC 0x00010000 /* connect status change */ | |
360 | #define RH_PS_PESC 0x00020000 /* port enable status change */ | |
361 | #define RH_PS_PSSC 0x00040000 /* port suspend status change */ | |
362 | #define RH_PS_OCIC 0x00080000 /* over current indicator change */ | |
363 | #define RH_PS_PRSC 0x00100000 /* port reset status change */ | |
364 | ||
365 | /* roothub.status bits */ | |
366 | #define RH_HS_LPS 0x00000001 /* local power status */ | |
367 | #define RH_HS_OCI 0x00000002 /* over current indicator */ | |
368 | #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ | |
369 | #define RH_HS_LPSC 0x00010000 /* local power status change */ | |
370 | #define RH_HS_OCIC 0x00020000 /* over current indicator change */ | |
371 | #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ | |
372 | ||
373 | /* roothub.b masks */ | |
374 | #define RH_B_DR 0x0000ffff /* device removable flags */ | |
375 | #define RH_B_PPCM 0xffff0000 /* port power control mask */ | |
376 | ||
377 | /* roothub.a masks */ | |
378 | #define RH_A_NDP (0xff << 0) /* number of downstream ports */ | |
379 | #define RH_A_PSM (1 << 8) /* power switching mode */ | |
380 | #define RH_A_NPS (1 << 9) /* no power switching */ | |
381 | #define RH_A_DT (1 << 10) /* device type (mbz) */ | |
382 | #define RH_A_OCPM (1 << 11) /* over current protection mode */ | |
383 | #define RH_A_NOCP (1 << 12) /* no over current protection */ | |
384 | #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ | |
385 | ||
386 | #define FI 0x2edf /* 12000 bits per frame (-1) */ | |
387 | #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) | |
388 | #define LSTHRESH 0x628 /* lowspeed bit threshold */ | |
389 | ||
390 | /* ------------------------------------------------------------------------- */ | |
391 | ||
392 | /* PTD accessor macros. */ | |
393 | #define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0) | |
394 | #define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK) | |
395 | #define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10) | |
396 | #define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK) | |
397 | #define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11) | |
398 | #define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK) | |
399 | #define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12) | |
400 | #define PTD_CC(v) (((v) << 12) & PTD_CC_MSK) | |
401 | #define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0) | |
402 | #define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK) | |
403 | #define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10) | |
404 | #define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK) | |
405 | #define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11) | |
406 | #define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK) | |
407 | #define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12) | |
408 | #define PTD_EP(v) (((v) << 12) & PTD_EP_MSK) | |
409 | #define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0) | |
410 | #define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK) | |
411 | #define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10) | |
412 | #define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK) | |
413 | #define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0) | |
414 | #define PTD_FA(v) (((v) << 0) & PTD_FA_MSK) | |
415 | #define PTD_GET_SF_INT(p) (((p)->faddr & PTD_SF_INT_MSK) >> 8) | |
416 | #define PTD_SF_INT(v) (((v) << 8) & PTD_SF_INT_MSK) | |
417 | #define PTD_GET_SF_ISO(p) (((p)->faddr & PTD_SF_ISO_MSK) >> 8) | |
418 | #define PTD_SF_ISO(v) (((v) << 8) & PTD_SF_ISO_MSK) | |
419 | #define PTD_GET_PR(p) (((p)->faddr & PTD_PR_MSK) >> 13) | |
420 | #define PTD_PR(v) (((v) << 13) & PTD_PR_MSK) | |
421 | ||
422 | #define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */ | |
423 | #define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE) | |
424 | ||
425 | struct isp1362_ep { | |
426 | struct usb_host_endpoint *hep; | |
427 | struct usb_device *udev; | |
428 | ||
429 | /* philips transfer descriptor */ | |
430 | struct ptd ptd; | |
431 | ||
432 | u8 maxpacket; | |
433 | u8 epnum; | |
434 | u8 nextpid; | |
435 | u16 error_count; | |
436 | u16 length; /* of current packet */ | |
437 | s16 ptd_offset; /* buffer offset in ISP1362 where | |
438 | PTD has been stored | |
439 | (for access thru HCDIRDATA) */ | |
440 | int ptd_index; | |
441 | int num_ptds; | |
442 | void *data; /* to databuf */ | |
443 | /* queue of active EPs (the ones transmitted to the chip) */ | |
444 | struct list_head active; | |
445 | ||
446 | /* periodic schedule */ | |
447 | u8 branch; | |
448 | u16 interval; | |
449 | u16 load; | |
450 | u16 last_iso; | |
451 | ||
452 | /* async schedule */ | |
453 | struct list_head schedule; /* list of all EPs that need processing */ | |
454 | struct list_head remove_list; | |
455 | int num_req; | |
456 | }; | |
457 | ||
458 | struct isp1362_ep_queue { | |
459 | struct list_head active; /* list of PTDs currently processed by HC */ | |
460 | atomic_t finishing; | |
461 | unsigned long buf_map; | |
462 | unsigned long skip_map; | |
463 | int free_ptd; | |
464 | u16 buf_start; | |
465 | u16 buf_size; | |
466 | u16 blk_size; /* PTD buffer block size for ATL and INTL */ | |
467 | u8 buf_count; | |
468 | u8 buf_avail; | |
469 | char name[16]; | |
470 | ||
471 | /* for statistical tracking */ | |
472 | u8 stat_maxptds; /* Max # of ptds seen simultaneously in fifo */ | |
473 | u8 ptd_count; /* number of ptds submitted to this queue */ | |
474 | }; | |
475 | ||
476 | struct isp1362_hcd { | |
477 | spinlock_t lock; | |
478 | void __iomem *addr_reg; | |
479 | void __iomem *data_reg; | |
480 | ||
481 | struct isp1362_platform_data *board; | |
482 | ||
a6363463 | 483 | struct dentry *debug_file; |
a9d43091 LW |
484 | unsigned long stat1, stat2, stat4, stat8, stat16; |
485 | ||
486 | /* HC registers */ | |
487 | u32 intenb; /* "OHCI" interrupts */ | |
488 | u16 irqenb; /* uP interrupts */ | |
489 | ||
490 | /* Root hub registers */ | |
491 | u32 rhdesca; | |
492 | u32 rhdescb; | |
493 | u32 rhstatus; | |
494 | u32 rhport[MAX_ROOT_PORTS]; | |
495 | unsigned long next_statechange; | |
496 | ||
497 | /* HC control reg shadow copy */ | |
498 | u32 hc_control; | |
499 | ||
500 | /* async schedule: control, bulk */ | |
501 | struct list_head async; | |
502 | ||
503 | /* periodic schedule: int */ | |
504 | u16 load[PERIODIC_SIZE]; | |
505 | struct list_head periodic; | |
506 | u16 fmindex; | |
507 | ||
508 | /* periodic schedule: isochronous */ | |
509 | struct list_head isoc; | |
22a627ba RK |
510 | unsigned int istl_flip:1; |
511 | unsigned int irq_active:1; | |
a9d43091 LW |
512 | |
513 | /* Schedules for the current frame */ | |
514 | struct isp1362_ep_queue atl_queue; | |
515 | struct isp1362_ep_queue intl_queue; | |
516 | struct isp1362_ep_queue istl_queue[2]; | |
517 | ||
518 | /* list of PTDs retrieved from HC */ | |
519 | struct list_head remove_list; | |
520 | enum { | |
521 | ISP1362_INT_SOF, | |
522 | ISP1362_INT_ISTL0, | |
523 | ISP1362_INT_ISTL1, | |
524 | ISP1362_INT_EOT, | |
525 | ISP1362_INT_OPR, | |
526 | ISP1362_INT_SUSP, | |
527 | ISP1362_INT_CLKRDY, | |
528 | ISP1362_INT_INTL, | |
529 | ISP1362_INT_ATL, | |
530 | ISP1362_INT_OTG, | |
531 | NUM_ISP1362_IRQS | |
532 | } IRQ_NAMES; | |
533 | unsigned int irq_stat[NUM_ISP1362_IRQS]; | |
534 | int req_serial; | |
535 | }; | |
536 | ||
537 | static inline const char *ISP1362_INT_NAME(int n) | |
538 | { | |
539 | switch (n) { | |
540 | case ISP1362_INT_SOF: return "SOF"; | |
541 | case ISP1362_INT_ISTL0: return "ISTL0"; | |
542 | case ISP1362_INT_ISTL1: return "ISTL1"; | |
543 | case ISP1362_INT_EOT: return "EOT"; | |
544 | case ISP1362_INT_OPR: return "OPR"; | |
545 | case ISP1362_INT_SUSP: return "SUSP"; | |
546 | case ISP1362_INT_CLKRDY: return "CLKRDY"; | |
547 | case ISP1362_INT_INTL: return "INTL"; | |
548 | case ISP1362_INT_ATL: return "ATL"; | |
549 | case ISP1362_INT_OTG: return "OTG"; | |
550 | default: return "unknown"; | |
551 | } | |
552 | } | |
553 | ||
554 | static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr) | |
555 | { | |
b0a9cf29 | 556 | unsigned long p = (unsigned long)ptr; |
a9d43091 LW |
557 | if (!(p & 0xf)) |
558 | isp1362_hcd->stat16++; | |
559 | else if (!(p & 0x7)) | |
560 | isp1362_hcd->stat8++; | |
561 | else if (!(p & 0x3)) | |
562 | isp1362_hcd->stat4++; | |
563 | else if (!(p & 0x1)) | |
564 | isp1362_hcd->stat2++; | |
565 | else | |
566 | isp1362_hcd->stat1++; | |
567 | } | |
568 | ||
569 | static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd) | |
570 | { | |
571 | return (struct isp1362_hcd *) (hcd->hcd_priv); | |
572 | } | |
573 | ||
574 | static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd) | |
575 | { | |
576 | return container_of((void *)isp1362_hcd, struct usb_hcd, hcd_priv); | |
577 | } | |
578 | ||
579 | #define frame_before(f1, f2) ((s16)((u16)f1 - (u16)f2) < 0) | |
580 | ||
581 | /* | |
582 | * ISP1362 HW Interface | |
583 | */ | |
584 | ||
a9d43091 LW |
585 | #define DBG(level, fmt...) \ |
586 | do { \ | |
587 | if (dbg_level > level) \ | |
588 | pr_debug(fmt); \ | |
589 | } while (0) | |
a9d43091 LW |
590 | |
591 | #ifdef VERBOSE | |
592 | # define VDBG(fmt...) DBG(3, fmt) | |
593 | #else | |
594 | # define VDBG(fmt...) do {} while (0) | |
595 | #endif | |
596 | ||
597 | #ifdef REGISTERS | |
598 | # define RDBG(fmt...) DBG(1, fmt) | |
599 | #else | |
600 | # define RDBG(fmt...) do {} while (0) | |
601 | #endif | |
602 | ||
603 | #ifdef URB_TRACE | |
604 | #define URB_DBG(fmt...) DBG(0, fmt) | |
605 | #else | |
606 | #define URB_DBG(fmt...) do {} while (0) | |
607 | #endif | |
608 | ||
609 | ||
610 | #if USE_PLATFORM_DELAY | |
611 | #if USE_NDELAY | |
612 | #error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously. | |
613 | #endif | |
614 | #define isp1362_delay(h, d) (h)->board->delay(isp1362_hcd_to_hcd(h)->self.controller, d) | |
615 | #elif USE_NDELAY | |
616 | #define isp1362_delay(h, d) ndelay(d) | |
617 | #else | |
618 | #define isp1362_delay(h, d) do {} while (0) | |
619 | #endif | |
620 | ||
621 | #define get_urb(ep) ({ \ | |
622 | BUG_ON(list_empty(&ep->hep->urb_list)); \ | |
623 | container_of(ep->hep->urb_list.next, struct urb, urb_list); \ | |
624 | }) | |
625 | ||
626 | /* basic access functions for ISP1362 chip registers */ | |
627 | /* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure, | |
628 | * that all register accesses are performed with interrupts disabled, since the interrupt | |
629 | * handler has no way of restoring the previous state. | |
630 | */ | |
631 | static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg) | |
632 | { | |
a9d43091 | 633 | REG_ACCESS_TEST(reg); |
a9d43091 LW |
634 | DUMMY_DELAY_ACCESS; |
635 | writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg); | |
636 | DUMMY_DELAY_ACCESS; | |
637 | isp1362_delay(isp1362_hcd, 1); | |
638 | } | |
639 | ||
640 | static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val) | |
641 | { | |
a9d43091 LW |
642 | DUMMY_DELAY_ACCESS; |
643 | writew(val, isp1362_hcd->data_reg); | |
644 | } | |
645 | ||
646 | static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd) | |
647 | { | |
648 | u16 val; | |
649 | ||
a9d43091 LW |
650 | DUMMY_DELAY_ACCESS; |
651 | val = readw(isp1362_hcd->data_reg); | |
652 | ||
653 | return val; | |
654 | } | |
655 | ||
656 | static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val) | |
657 | { | |
a9d43091 LW |
658 | #if USE_32BIT |
659 | DUMMY_DELAY_ACCESS; | |
660 | writel(val, isp1362_hcd->data_reg); | |
661 | #else | |
662 | DUMMY_DELAY_ACCESS; | |
663 | writew((u16)val, isp1362_hcd->data_reg); | |
664 | DUMMY_DELAY_ACCESS; | |
665 | writew(val >> 16, isp1362_hcd->data_reg); | |
666 | #endif | |
667 | } | |
668 | ||
669 | static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd) | |
670 | { | |
671 | u32 val; | |
672 | ||
a9d43091 LW |
673 | #if USE_32BIT |
674 | DUMMY_DELAY_ACCESS; | |
675 | val = readl(isp1362_hcd->data_reg); | |
676 | #else | |
677 | DUMMY_DELAY_ACCESS; | |
678 | val = (u32)readw(isp1362_hcd->data_reg); | |
679 | DUMMY_DELAY_ACCESS; | |
680 | val |= (u32)readw(isp1362_hcd->data_reg) << 16; | |
681 | #endif | |
682 | return val; | |
683 | } | |
684 | ||
685 | /* use readsw/writesw to access the fifo whenever possible */ | |
686 | /* assume HCDIRDATA or XFERCTR & addr_reg have been set up */ | |
687 | static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len) | |
688 | { | |
689 | u8 *dp = buf; | |
690 | u16 data; | |
691 | ||
692 | if (!len) | |
693 | return; | |
694 | ||
a9d43091 LW |
695 | RDBG("%s: Reading %d byte from fifo to mem @ %p\n", __func__, len, buf); |
696 | #if USE_32BIT | |
697 | if (len >= 4) { | |
698 | RDBG("%s: Using readsl for %d dwords\n", __func__, len >> 2); | |
699 | readsl(isp1362_hcd->data_reg, dp, len >> 2); | |
700 | dp += len & ~3; | |
701 | len &= 3; | |
702 | } | |
703 | #endif | |
704 | if (len >= 2) { | |
705 | RDBG("%s: Using readsw for %d words\n", __func__, len >> 1); | |
706 | insw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1); | |
707 | dp += len & ~1; | |
708 | len &= 1; | |
709 | } | |
710 | ||
711 | BUG_ON(len & ~1); | |
712 | if (len > 0) { | |
713 | data = isp1362_read_data16(isp1362_hcd); | |
714 | RDBG("%s: Reading trailing byte %02x to mem @ %08x\n", __func__, | |
715 | (u8)data, (u32)dp); | |
716 | *dp = (u8)data; | |
717 | } | |
718 | } | |
719 | ||
720 | static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len) | |
721 | { | |
722 | u8 *dp = buf; | |
723 | u16 data; | |
724 | ||
725 | if (!len) | |
726 | return; | |
727 | ||
b0a9cf29 | 728 | if ((unsigned long)dp & 0x1) { |
a9d43091 LW |
729 | /* not aligned */ |
730 | for (; len > 1; len -= 2) { | |
731 | data = *dp++; | |
732 | data |= *dp++ << 8; | |
733 | isp1362_write_data16(isp1362_hcd, data); | |
734 | } | |
735 | if (len) | |
736 | isp1362_write_data16(isp1362_hcd, *dp); | |
737 | return; | |
738 | } | |
739 | ||
a9d43091 LW |
740 | RDBG("%s: Writing %d byte to fifo from memory @%p\n", __func__, len, buf); |
741 | #if USE_32BIT | |
742 | if (len >= 4) { | |
743 | RDBG("%s: Using writesl for %d dwords\n", __func__, len >> 2); | |
744 | writesl(isp1362_hcd->data_reg, dp, len >> 2); | |
745 | dp += len & ~3; | |
746 | len &= 3; | |
747 | } | |
748 | #endif | |
749 | if (len >= 2) { | |
750 | RDBG("%s: Using writesw for %d words\n", __func__, len >> 1); | |
751 | outsw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1); | |
752 | dp += len & ~1; | |
753 | len &= 1; | |
754 | } | |
755 | ||
756 | BUG_ON(len & ~1); | |
757 | if (len > 0) { | |
758 | /* finally write any trailing byte; we don't need to care | |
759 | * about the high byte of the last word written | |
760 | */ | |
761 | data = (u16)*dp; | |
762 | RDBG("%s: Sending trailing byte %02x from mem @ %08x\n", __func__, | |
763 | data, (u32)dp); | |
764 | isp1362_write_data16(isp1362_hcd, data); | |
765 | } | |
766 | } | |
767 | ||
768 | #define isp1362_read_reg16(d, r) ({ \ | |
769 | u16 __v; \ | |
770 | REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \ | |
771 | isp1362_write_addr(d, ISP1362_REG_##r); \ | |
772 | __v = isp1362_read_data16(d); \ | |
773 | RDBG("%s: Read %04x from %s[%02x]\n", __func__, __v, #r, \ | |
774 | ISP1362_REG_NO(ISP1362_REG_##r)); \ | |
775 | __v; \ | |
776 | }) | |
777 | ||
778 | #define isp1362_read_reg32(d, r) ({ \ | |
779 | u32 __v; \ | |
780 | REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \ | |
781 | isp1362_write_addr(d, ISP1362_REG_##r); \ | |
782 | __v = isp1362_read_data32(d); \ | |
783 | RDBG("%s: Read %08x from %s[%02x]\n", __func__, __v, #r, \ | |
784 | ISP1362_REG_NO(ISP1362_REG_##r)); \ | |
785 | __v; \ | |
786 | }) | |
787 | ||
788 | #define isp1362_write_reg16(d, r, v) { \ | |
789 | REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \ | |
790 | isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \ | |
791 | isp1362_write_data16(d, (u16)(v)); \ | |
792 | RDBG("%s: Wrote %04x to %s[%02x]\n", __func__, (u16)(v), #r, \ | |
793 | ISP1362_REG_NO(ISP1362_REG_##r)); \ | |
794 | } | |
795 | ||
796 | #define isp1362_write_reg32(d, r, v) { \ | |
797 | REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \ | |
798 | isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \ | |
799 | isp1362_write_data32(d, (u32)(v)); \ | |
800 | RDBG("%s: Wrote %08x to %s[%02x]\n", __func__, (u32)(v), #r, \ | |
801 | ISP1362_REG_NO(ISP1362_REG_##r)); \ | |
802 | } | |
803 | ||
804 | #define isp1362_set_mask16(d, r, m) { \ | |
805 | u16 __v; \ | |
806 | __v = isp1362_read_reg16(d, r); \ | |
807 | if ((__v | m) != __v) \ | |
808 | isp1362_write_reg16(d, r, __v | m); \ | |
809 | } | |
810 | ||
811 | #define isp1362_clr_mask16(d, r, m) { \ | |
812 | u16 __v; \ | |
813 | __v = isp1362_read_reg16(d, r); \ | |
814 | if ((__v & ~m) != __v) \ | |
815 | isp1362_write_reg16(d, r, __v & ~m); \ | |
816 | } | |
817 | ||
818 | #define isp1362_set_mask32(d, r, m) { \ | |
819 | u32 __v; \ | |
820 | __v = isp1362_read_reg32(d, r); \ | |
821 | if ((__v | m) != __v) \ | |
822 | isp1362_write_reg32(d, r, __v | m); \ | |
823 | } | |
824 | ||
825 | #define isp1362_clr_mask32(d, r, m) { \ | |
826 | u32 __v; \ | |
827 | __v = isp1362_read_reg32(d, r); \ | |
828 | if ((__v & ~m) != __v) \ | |
829 | isp1362_write_reg32(d, r, __v & ~m); \ | |
830 | } | |
831 | ||
a9d43091 LW |
832 | #define isp1362_show_reg(d, r) { \ |
833 | if ((ISP1362_REG_##r & REG_WIDTH_MASK) == REG_WIDTH_32) \ | |
834 | DBG(0, "%-12s[%02x]: %08x\n", #r, \ | |
835 | ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg32(d, r)); \ | |
836 | else \ | |
837 | DBG(0, "%-12s[%02x]: %04x\n", #r, \ | |
838 | ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg16(d, r)); \ | |
839 | } | |
a9d43091 LW |
840 | |
841 | static void __attribute__((__unused__)) isp1362_show_regs(struct isp1362_hcd *isp1362_hcd) | |
842 | { | |
843 | isp1362_show_reg(isp1362_hcd, HCREVISION); | |
844 | isp1362_show_reg(isp1362_hcd, HCCONTROL); | |
845 | isp1362_show_reg(isp1362_hcd, HCCMDSTAT); | |
846 | isp1362_show_reg(isp1362_hcd, HCINTSTAT); | |
847 | isp1362_show_reg(isp1362_hcd, HCINTENB); | |
848 | isp1362_show_reg(isp1362_hcd, HCFMINTVL); | |
849 | isp1362_show_reg(isp1362_hcd, HCFMREM); | |
850 | isp1362_show_reg(isp1362_hcd, HCFMNUM); | |
851 | isp1362_show_reg(isp1362_hcd, HCLSTHRESH); | |
852 | isp1362_show_reg(isp1362_hcd, HCRHDESCA); | |
853 | isp1362_show_reg(isp1362_hcd, HCRHDESCB); | |
854 | isp1362_show_reg(isp1362_hcd, HCRHSTATUS); | |
855 | isp1362_show_reg(isp1362_hcd, HCRHPORT1); | |
856 | isp1362_show_reg(isp1362_hcd, HCRHPORT2); | |
857 | ||
858 | isp1362_show_reg(isp1362_hcd, HCHWCFG); | |
859 | isp1362_show_reg(isp1362_hcd, HCDMACFG); | |
860 | isp1362_show_reg(isp1362_hcd, HCXFERCTR); | |
861 | isp1362_show_reg(isp1362_hcd, HCuPINT); | |
862 | ||
863 | if (in_interrupt()) | |
864 | DBG(0, "%-12s[%02x]: %04x\n", "HCuPINTENB", | |
865 | ISP1362_REG_NO(ISP1362_REG_HCuPINTENB), isp1362_hcd->irqenb); | |
866 | else | |
867 | isp1362_show_reg(isp1362_hcd, HCuPINTENB); | |
868 | isp1362_show_reg(isp1362_hcd, HCCHIPID); | |
869 | isp1362_show_reg(isp1362_hcd, HCSCRATCH); | |
870 | isp1362_show_reg(isp1362_hcd, HCBUFSTAT); | |
871 | isp1362_show_reg(isp1362_hcd, HCDIRADDR); | |
872 | /* Access would advance fifo | |
873 | * isp1362_show_reg(isp1362_hcd, HCDIRDATA); | |
874 | */ | |
875 | isp1362_show_reg(isp1362_hcd, HCISTLBUFSZ); | |
876 | isp1362_show_reg(isp1362_hcd, HCISTLRATE); | |
877 | isp1362_show_reg(isp1362_hcd, HCINTLBUFSZ); | |
878 | isp1362_show_reg(isp1362_hcd, HCINTLBLKSZ); | |
879 | isp1362_show_reg(isp1362_hcd, HCINTLDONE); | |
880 | isp1362_show_reg(isp1362_hcd, HCINTLSKIP); | |
881 | isp1362_show_reg(isp1362_hcd, HCINTLLAST); | |
882 | isp1362_show_reg(isp1362_hcd, HCINTLCURR); | |
883 | isp1362_show_reg(isp1362_hcd, HCATLBUFSZ); | |
884 | isp1362_show_reg(isp1362_hcd, HCATLBLKSZ); | |
885 | /* only valid after ATL_DONE interrupt | |
886 | * isp1362_show_reg(isp1362_hcd, HCATLDONE); | |
887 | */ | |
888 | isp1362_show_reg(isp1362_hcd, HCATLSKIP); | |
889 | isp1362_show_reg(isp1362_hcd, HCATLLAST); | |
890 | isp1362_show_reg(isp1362_hcd, HCATLCURR); | |
891 | isp1362_show_reg(isp1362_hcd, HCATLDTC); | |
892 | isp1362_show_reg(isp1362_hcd, HCATLDTCTO); | |
893 | } | |
894 | ||
895 | static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len) | |
896 | { | |
a9d43091 LW |
897 | len = (len + 1) & ~1; |
898 | ||
899 | isp1362_clr_mask16(isp1362_hcd, HCDMACFG, HCDMACFG_CTR_ENABLE); | |
900 | isp1362_write_reg32(isp1362_hcd, HCDIRADDR, | |
901 | HCDIRADDR_ADDR(offset) | HCDIRADDR_COUNT(len)); | |
902 | } | |
903 | ||
904 | static void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len) | |
905 | { | |
a9d43091 LW |
906 | isp1362_write_diraddr(isp1362_hcd, offset, len); |
907 | ||
b0a9cf29 MF |
908 | DBG(3, "%s: Reading %d byte from buffer @%04x to memory @ %p\n", |
909 | __func__, len, offset, buf); | |
a9d43091 LW |
910 | |
911 | isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); | |
a9d43091 LW |
912 | |
913 | isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA); | |
914 | ||
915 | isp1362_read_fifo(isp1362_hcd, buf, len); | |
a9d43091 | 916 | isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); |
a9d43091 LW |
917 | } |
918 | ||
919 | static void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len) | |
920 | { | |
a9d43091 LW |
921 | isp1362_write_diraddr(isp1362_hcd, offset, len); |
922 | ||
b0a9cf29 MF |
923 | DBG(3, "%s: Writing %d byte to buffer @%04x from memory @ %p\n", |
924 | __func__, len, offset, buf); | |
a9d43091 LW |
925 | |
926 | isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); | |
a9d43091 LW |
927 | |
928 | isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA | ISP1362_REG_WRITE_OFFSET); | |
929 | isp1362_write_fifo(isp1362_hcd, buf, len); | |
930 | ||
a9d43091 | 931 | isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); |
a9d43091 LW |
932 | } |
933 | ||
934 | static void __attribute__((unused)) dump_data(char *buf, int len) | |
935 | { | |
936 | if (dbg_level > 0) { | |
937 | int k; | |
938 | int lf = 0; | |
939 | ||
940 | for (k = 0; k < len; ++k) { | |
941 | if (!lf) | |
942 | DBG(0, "%04x:", k); | |
943 | printk(" %02x", ((u8 *) buf)[k]); | |
944 | lf = 1; | |
945 | if (!k) | |
946 | continue; | |
947 | if (k % 16 == 15) { | |
948 | printk("\n"); | |
949 | lf = 0; | |
950 | continue; | |
951 | } | |
952 | if (k % 8 == 7) | |
953 | printk(" "); | |
954 | if (k % 4 == 3) | |
955 | printk(" "); | |
956 | } | |
957 | if (lf) | |
958 | printk("\n"); | |
959 | } | |
960 | } | |
961 | ||
641c86cd | 962 | #if defined(PTD_TRACE) |
a9d43091 LW |
963 | |
964 | static void dump_ptd(struct ptd *ptd) | |
965 | { | |
966 | DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n", | |
967 | container_of(ptd, struct isp1362_ep, ptd), | |
968 | PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd), | |
969 | PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd), | |
970 | PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd), | |
971 | PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd)); | |
972 | DBG(0, " %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr); | |
973 | } | |
974 | ||
975 | static void dump_ptd_out_data(struct ptd *ptd, u8 *buf) | |
976 | { | |
977 | if (dbg_level > 0) { | |
978 | if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) { | |
979 | DBG(0, "--out->\n"); | |
980 | dump_data(buf, PTD_GET_LEN(ptd)); | |
981 | } | |
982 | } | |
983 | } | |
984 | ||
985 | static void dump_ptd_in_data(struct ptd *ptd, u8 *buf) | |
986 | { | |
987 | if (dbg_level > 0) { | |
988 | if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) { | |
989 | DBG(0, "<--in--\n"); | |
990 | dump_data(buf, PTD_GET_COUNT(ptd)); | |
991 | } | |
992 | DBG(0, "-----\n"); | |
993 | } | |
994 | } | |
995 | ||
996 | static void dump_ptd_queue(struct isp1362_ep_queue *epq) | |
997 | { | |
998 | struct isp1362_ep *ep; | |
999 | int dbg = dbg_level; | |
1000 | ||
1001 | dbg_level = 1; | |
1002 | list_for_each_entry(ep, &epq->active, active) { | |
1003 | dump_ptd(&ep->ptd); | |
1004 | dump_data(ep->data, ep->length); | |
1005 | } | |
1006 | dbg_level = dbg; | |
1007 | } | |
1008 | #else | |
1009 | #define dump_ptd(ptd) do {} while (0) | |
1010 | #define dump_ptd_in_data(ptd, buf) do {} while (0) | |
1011 | #define dump_ptd_out_data(ptd, buf) do {} while (0) | |
1012 | #define dump_ptd_data(ptd, buf) do {} while (0) | |
1013 | #define dump_ptd_queue(epq) do {} while (0) | |
1014 | #endif |