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USB: xHCI: adds new cases to trb_comp_code switch
[deliverable/linux.git] / drivers / usb / host / isp1760-hcd.c
CommitLineData
db11e47d
SS		 1/*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/slab.h>
15#include <linux/list.h>
16#include <linux/usb.h>
27729aad 17#include <linux/usb/hcd.h>
db11e47d
SS		 18#include <linux/debugfs.h>
19#include <linux/uaccess.h>
20#include <linux/io.h>
db8516f6 21#include <linux/mm.h>
db11e47d 22#include <asm/unaligned.h>
db8516f6 23#include <asm/cacheflush.h>
db11e47d 24
db11e47d
SS		 25#include "isp1760-hcd.h"
26
27static struct kmem_cache *qtd_cachep;
28static struct kmem_cache *qh_cachep;
29
30struct isp1760_hcd {
31 u32 hcs_params;
32 spinlock_t lock;
33 struct inter_packet_info atl_ints[32];
34 struct inter_packet_info int_ints[32];
35 struct memory_chunk memory_pool[BLOCKS];
36
37 /* periodic schedule support */
38#define DEFAULT_I_TDPS 1024
39 unsigned periodic_size;
40 unsigned i_thresh;
41 unsigned long reset_done;
42 unsigned long next_statechange;
3faefc88 43 unsigned int devflags;
db11e47d
SS		 44};
45
46static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
47{
48 return (struct isp1760_hcd *) (hcd->hcd_priv);
49}
50static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
51{
52 return container_of((void *) priv, struct usb_hcd, hcd_priv);
53}
54
55/* Section 2.2 Host Controller Capability Registers */
56#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
57#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
58#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
59#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
60#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
61#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
62#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
63
64/* Section 2.3 Host Controller Operational Registers */
65#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
66#define CMD_RESET (1<<1) /* reset HC not bus */
67#define CMD_RUN (1<<0) /* start/stop HC */
68#define STS_PCD (1<<2) /* port change detect */
69#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
70
71#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
72#define PORT_POWER (1<<12) /* true: has power (see PPC) */
73#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
74#define PORT_RESET (1<<8) /* reset port */
75#define PORT_SUSPEND (1<<7) /* suspend port */
76#define PORT_RESUME (1<<6) /* resume it */
77#define PORT_PE (1<<2) /* port enable */
78#define PORT_CSC (1<<1) /* connect status change */
79#define PORT_CONNECT (1<<0) /* device connected */
80#define PORT_RWC_BITS (PORT_CSC)
81
82struct isp1760_qtd {
83 struct isp1760_qtd *hw_next;
84 u8 packet_type;
85 u8 toggle;
86
87 void *data_buffer;
88 /* the rest is HCD-private */
89 struct list_head qtd_list;
90 struct urb *urb;
91 size_t length;
92
93 /* isp special*/
94 u32 status;
95#define URB_COMPLETE_NOTIFY (1 << 0)
96#define URB_ENQUEUED (1 << 1)
97#define URB_TYPE_ATL (1 << 2)
98#define URB_TYPE_INT (1 << 3)
99};
100
101struct isp1760_qh {
102 /* first part defined by EHCI spec */
103 struct list_head qtd_list;
104 struct isp1760_hcd *priv;
105
106 /* periodic schedule info */
107 unsigned short period; /* polling interval */
108 struct usb_device *dev;
109
110 u32 toggle;
111 u32 ping;
112};
113
288ead45 114#define ehci_port_speed(priv, portsc) USB_PORT_STAT_HIGH_SPEED
db11e47d
SS		 115
116static unsigned int isp1760_readl(__u32 __iomem *regs)
117{
118 return readl(regs);
119}
120
121static void isp1760_writel(const unsigned int val, __u32 __iomem *regs)
122{
123 writel(val, regs);
124}
125
126/*
127 * The next two copy via MMIO data to/from the device. memcpy_{to|from}io()
128 * doesn't quite work because some people have to enforce 32-bit access
129 */
130static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
3f02a957 131 __u32 __iomem *dst, u32 len)
db11e47d 132{
db11e47d
SS		 133 u32 val;
134 u8 *buff8;
135
136 if (!src) {
137 printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
138 return;
139 }
db11e47d
SS		 140
141 while (len >= 4) {
142 *src = __raw_readl(dst);
143 len -= 4;
144 src++;
145 dst++;
146 }
147
148 if (!len)
149 return;
150
151 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
152 * allocated.
153 */
154 val = isp1760_readl(dst);
155
156 buff8 = (u8 *)src;
157 while (len) {
158
159 *buff8 = val;
160 val >>= 8;
161 len--;
162 buff8++;
163 }
164}
165
166static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src,
167 __u32 __iomem *dst, u32 len)
168{
169 while (len >= 4) {
170 __raw_writel(*src, dst);
171 len -= 4;
172 src++;
173 dst++;
174 }
175
176 if (!len)
177 return;
178 /* in case we have 3, 2 or 1 by left. The buffer is allocated and the
179 * extra bytes should not be read by the HW
180 */
181
182 __raw_writel(*src, dst);
183}
184
185/* memory management of the 60kb on the chip from 0x1000 to 0xffff */
186static void init_memory(struct isp1760_hcd *priv)
187{
188 int i;
189 u32 payload;
190
191 payload = 0x1000;
192 for (i = 0; i < BLOCK_1_NUM; i++) {
193 priv->memory_pool[i].start = payload;
194 priv->memory_pool[i].size = BLOCK_1_SIZE;
195 priv->memory_pool[i].free = 1;
196 payload += priv->memory_pool[i].size;
197 }
198
199
200 for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) {
201 priv->memory_pool[i].start = payload;
202 priv->memory_pool[i].size = BLOCK_2_SIZE;
203 priv->memory_pool[i].free = 1;
204 payload += priv->memory_pool[i].size;
205 }
206
207
208 for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) {
209 priv->memory_pool[i].start = payload;
210 priv->memory_pool[i].size = BLOCK_3_SIZE;
211 priv->memory_pool[i].free = 1;
212 payload += priv->memory_pool[i].size;
213 }
214
215 BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE);
216}
217
218static u32 alloc_mem(struct isp1760_hcd *priv, u32 size)
219{
220 int i;
221
222 if (!size)
223 return ISP1760_NULL_POINTER;
224
225 for (i = 0; i < BLOCKS; i++) {
226 if (priv->memory_pool[i].size >= size &&
227 priv->memory_pool[i].free) {
228
229 priv->memory_pool[i].free = 0;
230 return priv->memory_pool[i].start;
231 }
232 }
233
234 printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n",
235 size);
236 printk(KERN_ERR "Current memory map:\n");
237 for (i = 0; i < BLOCKS; i++) {
238 printk(KERN_ERR "Pool %2d size %4d status: %d\n",
239 i, priv->memory_pool[i].size,
240 priv->memory_pool[i].free);
241 }
242 /* XXX maybe -ENOMEM could be possible */
243 BUG();
244 return 0;
245}
246
247static void free_mem(struct isp1760_hcd *priv, u32 mem)
248{
249 int i;
250
251 if (mem == ISP1760_NULL_POINTER)
252 return;
253
254 for (i = 0; i < BLOCKS; i++) {
255 if (priv->memory_pool[i].start == mem) {
256
257 BUG_ON(priv->memory_pool[i].free);
258
259 priv->memory_pool[i].free = 1;
260 return ;
261 }
262 }
263
264 printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n",
265 mem);
266 BUG();
267}
268
269static void isp1760_init_regs(struct usb_hcd *hcd)
270{
271 isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG);
272 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
273 HC_ATL_PTD_SKIPMAP_REG);
274 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
275 HC_INT_PTD_SKIPMAP_REG);
276 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
277 HC_ISO_PTD_SKIPMAP_REG);
278
279 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
280 HC_ATL_PTD_DONEMAP_REG);
281 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
282 HC_INT_PTD_DONEMAP_REG);
283 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
284 HC_ISO_PTD_DONEMAP_REG);
285}
286
287static int handshake(struct isp1760_hcd *priv, void __iomem *ptr,
288 u32 mask, u32 done, int usec)
289{
290 u32 result;
291
292 do {
293 result = isp1760_readl(ptr);
294 if (result == ~0)
295 return -ENODEV;
296 result &= mask;
297 if (result == done)
298 return 0;
299 udelay(1);
300 usec--;
301 } while (usec > 0);
302 return -ETIMEDOUT;
303}
304
305/* reset a non-running (STS_HALT == 1) controller */
306static int ehci_reset(struct isp1760_hcd *priv)
307{
308 int retval;
309 struct usb_hcd *hcd = priv_to_hcd(priv);
310 u32 command = isp1760_readl(hcd->regs + HC_USBCMD);
311
312 command |= CMD_RESET;
313 isp1760_writel(command, hcd->regs + HC_USBCMD);
314 hcd->state = HC_STATE_HALT;
315 priv->next_statechange = jiffies;
316 retval = handshake(priv, hcd->regs + HC_USBCMD,
317 CMD_RESET, 0, 250 * 1000);
318 return retval;
319}
320
321static void qh_destroy(struct isp1760_qh *qh)
322{
323 BUG_ON(!list_empty(&qh->qtd_list));
324 kmem_cache_free(qh_cachep, qh);
325}
326
327static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv,
328 gfp_t flags)
329{
330 struct isp1760_qh *qh;
331
332 qh = kmem_cache_zalloc(qh_cachep, flags);
333 if (!qh)
334 return qh;
335
336 INIT_LIST_HEAD(&qh->qtd_list);
337 qh->priv = priv;
338 return qh;
339}
340
341/* magic numbers that can affect system performance */
342#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
343#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
344#define EHCI_TUNE_RL_TT 0
345#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
346#define EHCI_TUNE_MULT_TT 1
347#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
348
349/* one-time init, only for memory state */
350static int priv_init(struct usb_hcd *hcd)
351{
352 struct isp1760_hcd *priv = hcd_to_priv(hcd);
353 u32 hcc_params;
354
355 spin_lock_init(&priv->lock);
356
357 /*
358 * hw default: 1K periodic list heads, one per frame.
359 * periodic_size can shrink by USBCMD update if hcc_params allows.
360 */
361 priv->periodic_size = DEFAULT_I_TDPS;
362
363 /* controllers may cache some of the periodic schedule ... */
364 hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS);
365 /* full frame cache */
366 if (HCC_ISOC_CACHE(hcc_params))
367 priv->i_thresh = 8;
368 else /* N microframes cached */
369 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
370
371 return 0;
372}
373
374static int isp1760_hc_setup(struct usb_hcd *hcd)
375{
376 struct isp1760_hcd *priv = hcd_to_priv(hcd);
377 int result;
3faefc88
NC		 378 u32 scratch, hwmode;
379
380 /* Setup HW Mode Control: This assumes a level active-low interrupt */
381 hwmode = HW_DATA_BUS_32BIT;
382
383 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
384 hwmode &= ~HW_DATA_BUS_32BIT;
385 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
386 hwmode |= HW_ANA_DIGI_OC;
387 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
388 hwmode |= HW_DACK_POL_HIGH;
389 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
390 hwmode |= HW_DREQ_POL_HIGH;
9da69c60
MH		 391 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
392 hwmode |= HW_INTR_HIGH_ACT;
393 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
394 hwmode |= HW_INTR_EDGE_TRIG;
3faefc88
NC		 395
396 /*
397 * We have to set this first in case we're in 16-bit mode.
398 * Write it twice to ensure correct upper bits if switching
399 * to 16-bit mode.
400 */
401 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
402 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
db11e47d
SS		 403
404 isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG);
3faefc88
NC		 405 /* Change bus pattern */
406 scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
db11e47d
SS		 407 scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG);
408 if (scratch != 0xdeadbabe) {
409 printk(KERN_ERR "ISP1760: Scratch test failed.\n");
410 return -ENODEV;
411 }
412
413 /* pre reset */
414 isp1760_init_regs(hcd);
415
416 /* reset */
417 isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG);
418 mdelay(100);
419
420 isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG);
421 mdelay(100);
422
423 result = ehci_reset(priv);
424 if (result)
425 return result;
426
427 /* Step 11 passed */
428
3faefc88
NC		 429 isp1760_info(priv, "bus width: %d, oc: %s\n",
430 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
431 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
432 "analog" : "digital");
db11e47d
SS		 433
434 /* ATL reset */
3faefc88 435 isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL);
db11e47d 436 mdelay(10);
3faefc88 437 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
db11e47d 438
3faefc88
NC		 439 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG);
440 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE);
441
442 /*
443 * PORT 1 Control register of the ISP1760 is the OTG control
42c65396
TH		 444 * register on ISP1761. Since there is no OTG or device controller
445 * support in this driver, we use port 1 as a "normal" USB host port on
446 * both chips.
3faefc88 447 */
42c65396
TH		 448 isp1760_writel(PORT1_POWER | PORT1_INIT2,
449 hcd->regs + HC_PORT1_CTRL);
450 mdelay(10);
db11e47d
SS		 451
452 priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS);
453
454 return priv_init(hcd);
455}
456
457static void isp1760_init_maps(struct usb_hcd *hcd)
458{
459 /*set last maps, for iso its only 1, else 32 tds bitmap*/
460 isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG);
461 isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG);
462 isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG);
463}
464
465static void isp1760_enable_interrupts(struct usb_hcd *hcd)
466{
467 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG);
468 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
469 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG);
470 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
471 isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG);
472 isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG);
473 /* step 23 passed */
474}
475
476static int isp1760_run(struct usb_hcd *hcd)
477{
478 struct isp1760_hcd *priv = hcd_to_priv(hcd);
479 int retval;
480 u32 temp;
481 u32 command;
482 u32 chipid;
483
484 hcd->uses_new_polling = 1;
db11e47d
SS		 485
486 hcd->state = HC_STATE_RUNNING;
487 isp1760_enable_interrupts(hcd);
488 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
3faefc88 489 isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
db11e47d
SS		 490
491 command = isp1760_readl(hcd->regs + HC_USBCMD);
492 command &= ~(CMD_LRESET|CMD_RESET);
493 command |= CMD_RUN;
494 isp1760_writel(command, hcd->regs + HC_USBCMD);
495
496 retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN,
497 250 * 1000);
498 if (retval)
499 return retval;
500
501 /*
502 * XXX
503 * Spec says to write FLAG_CF as last config action, priv code grabs
504 * the semaphore while doing so.
505 */
506 down_write(&ehci_cf_port_reset_rwsem);
507 isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG);
508
509 retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF,
510 250 * 1000);
511 up_write(&ehci_cf_port_reset_rwsem);
512 if (retval)
513 return retval;
514
515 chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
516 isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff,
517 chipid >> 16);
518
519 /* PTD Register Init Part 2, Step 28 */
520 /* enable INTs */
521 isp1760_init_maps(hcd);
522
523 /* GRR this is run-once init(), being done every time the HC starts.
524 * So long as they're part of class devices, we can't do it init()
525 * since the class device isn't created that early.
526 */
527 return 0;
528}
529
530static u32 base_to_chip(u32 base)
531{
532 return ((base - 0x400) >> 3);
533}
534
535static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh,
536 struct isp1760_qtd *qtd, struct urb *urb,
537 u32 payload, struct ptd *ptd)
538{
539 u32 dw0;
540 u32 dw1;
541 u32 dw2;
542 u32 dw3;
543 u32 maxpacket;
544 u32 multi;
545 u32 pid_code;
546 u32 rl = RL_COUNTER;
547 u32 nak = NAK_COUNTER;
548
549 /* according to 3.6.2, max packet len can not be > 0x400 */
550 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
551 multi = 1 + ((maxpacket >> 11) & 0x3);
552 maxpacket &= 0x7ff;
553
554 /* DW0 */
555 dw0 = PTD_VALID;
556 dw0 |= PTD_LENGTH(qtd->length);
557 dw0 |= PTD_MAXPACKET(maxpacket);
558 dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe));
559 dw1 = usb_pipeendpoint(urb->pipe) >> 1;
560
561 /* DW1 */
562 dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe));
563
564 pid_code = qtd->packet_type;
565 dw1 |= PTD_PID_TOKEN(pid_code);
566
567 if (usb_pipebulk(urb->pipe))
568 dw1 |= PTD_TRANS_BULK;
569 else if (usb_pipeint(urb->pipe))
570 dw1 |= PTD_TRANS_INT;
571
572 if (urb->dev->speed != USB_SPEED_HIGH) {
573 /* split transaction */
574
575 dw1 |= PTD_TRANS_SPLIT;
576 if (urb->dev->speed == USB_SPEED_LOW)
577 dw1 |= PTD_SE_USB_LOSPEED;
578
579 dw1 |= PTD_PORT_NUM(urb->dev->ttport);
580 dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum);
581
582 /* SE bit for Split INT transfers */
583 if (usb_pipeint(urb->pipe) &&
584 (urb->dev->speed == USB_SPEED_LOW))
585 dw1 |= 2 << 16;
586
587 dw3 = 0;
588 rl = 0;
589 nak = 0;
590 } else {
591 dw0 |= PTD_MULTI(multi);
592 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe))
593 dw3 = qh->ping;
594 else
595 dw3 = 0;
596 }
597 /* DW2 */
598 dw2 = 0;
599 dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload));
600 dw2 |= PTD_RL_CNT(rl);
601 dw3 |= PTD_NAC_CNT(nak);
602
603 /* DW3 */
604 if (usb_pipecontrol(urb->pipe))
605 dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
606 else
607 dw3 |= qh->toggle;
608
609
610 dw3 |= PTD_ACTIVE;
611 /* Cerr */
612 dw3 |= PTD_CERR(ERR_COUNTER);
613
614 memset(ptd, 0, sizeof(*ptd));
615
616 ptd->dw0 = cpu_to_le32(dw0);
617 ptd->dw1 = cpu_to_le32(dw1);
618 ptd->dw2 = cpu_to_le32(dw2);
619 ptd->dw3 = cpu_to_le32(dw3);
620}
621
622static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
623 struct isp1760_qtd *qtd, struct urb *urb,
624 u32 payload, struct ptd *ptd)
625{
626 u32 maxpacket;
627 u32 multi;
628 u32 numberofusofs;
629 u32 i;
630 u32 usofmask, usof;
631 u32 period;
632
633 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
634 multi = 1 + ((maxpacket >> 11) & 0x3);
635 maxpacket &= 0x7ff;
636 /* length of the data per uframe */
637 maxpacket = multi * maxpacket;
638
639 numberofusofs = urb->transfer_buffer_length / maxpacket;
640 if (urb->transfer_buffer_length % maxpacket)
641 numberofusofs += 1;
642
643 usofmask = 1;
644 usof = 0;
645 for (i = 0; i < numberofusofs; i++) {
646 usof |= usofmask;
647 usofmask <<= 1;
648 }
649
650 if (urb->dev->speed != USB_SPEED_HIGH) {
651 /* split */
551509d2 652 ptd->dw5 = cpu_to_le32(0x1c);
db11e47d
SS		 653
654 if (qh->period >= 32)
655 period = qh->period / 2;
656 else
657 period = qh->period;
658
659 } else {
660
661 if (qh->period >= 8)
662 period = qh->period/8;
663 else
664 period = qh->period;
665
666 if (period >= 32)
667 period = 16;
668
669 if (qh->period >= 8) {
670 /* millisecond period */
671 period = (period << 3);
672 } else {
673 /* usof based tranmsfers */
674 /* minimum 4 usofs */
675 usof = 0x11;
676 }
677 }
678
679 ptd->dw2 |= cpu_to_le32(period);
680 ptd->dw4 = cpu_to_le32(usof);
681}
682
683static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
684 struct isp1760_qtd *qtd, struct urb *urb,
685 u32 payload, struct ptd *ptd)
686{
687 transform_into_atl(priv, qh, qtd, urb, payload, ptd);
688 transform_add_int(priv, qh, qtd, urb, payload, ptd);
689}
690
691static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
692 u32 token)
693{
694 int count;
695
696 qtd->data_buffer = databuffer;
697 qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
698 qtd->toggle = GET_DATA_TOGGLE(token);
699
700 if (len > HC_ATL_PL_SIZE)
701 count = HC_ATL_PL_SIZE;
702 else
703 count = len;
704
705 qtd->length = count;
706 return count;
707}
708
709static int check_error(struct ptd *ptd)
710{
711 int error = 0;
712 u32 dw3;
713
714 dw3 = le32_to_cpu(ptd->dw3);
0954e1c2 715 if (dw3 & DW3_HALT_BIT) {
db11e47d
SS		 716 error = -EPIPE;
717
0954e1c2
AV		 718 if (dw3 & DW3_ERROR_BIT)
719 pr_err("error bit is set in DW3\n");
db11e47d
SS		 720 }
721
722 if (dw3 & DW3_QTD_ACTIVE) {
723 printk(KERN_ERR "transfer active bit is set DW3\n");
724 printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf,
725 (le32_to_cpu(ptd->dw2) >> 25) & 0xf);
726 }
727
728 return error;
729}
730
731static void check_int_err_status(u32 dw4)
732{
733 u32 i;
734
735 dw4 >>= 8;
736
737 for (i = 0; i < 8; i++) {
738 switch (dw4 & 0x7) {
739 case INT_UNDERRUN:
740 printk(KERN_ERR "ERROR: under run , %d\n", i);
741 break;
742
743 case INT_EXACT:
744 printk(KERN_ERR "ERROR: transaction error, %d\n", i);
745 break;
746
747 case INT_BABBLE:
748 printk(KERN_ERR "ERROR: babble error, %d\n", i);
749 break;
750 }
751 dw4 >>= 3;
752 }
753}
754
755static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv,
756 u32 payload)
757{
758 u32 token;
759 struct usb_hcd *hcd = priv_to_hcd(priv);
760
761 token = qtd->packet_type;
762
763 if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) {
764 switch (token) {
765 case IN_PID:
766 break;
767 case OUT_PID:
768 case SETUP_PID:
769 priv_write_copy(priv, qtd->data_buffer,
770 hcd->regs + payload,
771 qtd->length);
772 }
773 }
774}
775
776static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload,
777 struct isp1760_hcd *priv, struct isp1760_qh *qh,
778 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
779{
780 struct ptd ptd;
781 struct usb_hcd *hcd = priv_to_hcd(priv);
782
783 transform_into_atl(priv, qh, qtd, urb, payload, &ptd);
784 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd));
785 enqueue_one_qtd(qtd, priv, payload);
786
787 priv->atl_ints[slot].urb = urb;
788 priv->atl_ints[slot].qh = qh;
789 priv->atl_ints[slot].qtd = qtd;
790 priv->atl_ints[slot].data_buffer = qtd->data_buffer;
791 priv->atl_ints[slot].payload = payload;
792 qtd->status |= URB_ENQUEUED | URB_TYPE_ATL;
793 qtd->status |= slot << 16;
794}
795
796static void enqueue_one_int_qtd(u32 int_regs, u32 payload,
797 struct isp1760_hcd *priv, struct isp1760_qh *qh,
798 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
799{
800 struct ptd ptd;
801 struct usb_hcd *hcd = priv_to_hcd(priv);
802
803 transform_into_int(priv, qh, qtd, urb, payload, &ptd);
804 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd));
805 enqueue_one_qtd(qtd, priv, payload);
806
807 priv->int_ints[slot].urb = urb;
808 priv->int_ints[slot].qh = qh;
809 priv->int_ints[slot].qtd = qtd;
810 priv->int_ints[slot].data_buffer = qtd->data_buffer;
811 priv->int_ints[slot].payload = payload;
812 qtd->status |= URB_ENQUEUED | URB_TYPE_INT;
813 qtd->status |= slot << 16;
814}
815
473bca94
AB		 816static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
817 struct isp1760_qtd *qtd)
db11e47d
SS		 818{
819 struct isp1760_hcd *priv = hcd_to_priv(hcd);
820 u32 skip_map, or_map;
821 u32 queue_entry;
822 u32 slot;
823 u32 atl_regs, payload;
824 u32 buffstatus;
825
e6bdfe36
CM		 826 /*
827 * When this function is called from the interrupt handler to enqueue
828 * a follow-up packet, the SKIP register gets written and read back
829 * almost immediately. With ISP1761, this register requires a delay of
830 * 195ns between a write and subsequent read (see section 15.1.1.3).
831 */
832 ndelay(195);
db11e47d
SS		 833 skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
834
835 BUG_ON(!skip_map);
836 slot = __ffs(skip_map);
837 queue_entry = 1 << slot;
838
839 atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd);
840
841 payload = alloc_mem(priv, qtd->length);
842
843 enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd);
844
845 or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
846 or_map |= queue_entry;
847 isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
848
849 skip_map &= ~queue_entry;
850 isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
851
852 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
853 buffstatus |= ATL_BUFFER;
854 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
855}
856
473bca94
AB		 857static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
858 struct isp1760_qtd *qtd)
db11e47d
SS		 859{
860 struct isp1760_hcd *priv = hcd_to_priv(hcd);
861 u32 skip_map, or_map;
862 u32 queue_entry;
863 u32 slot;
864 u32 int_regs, payload;
865 u32 buffstatus;
866
e6bdfe36
CM		 867 /*
868 * When this function is called from the interrupt handler to enqueue
869 * a follow-up packet, the SKIP register gets written and read back
870 * almost immediately. With ISP1761, this register requires a delay of
871 * 195ns between a write and subsequent read (see section 15.1.1.3).
872 */
873 ndelay(195);
db11e47d
SS		 874 skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG);
875
876 BUG_ON(!skip_map);
877 slot = __ffs(skip_map);
878 queue_entry = 1 << slot;
879
880 int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd);
881
882 payload = alloc_mem(priv, qtd->length);
883
884 enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd);
885
886 or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG);
887 or_map |= queue_entry;
888 isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
889
890 skip_map &= ~queue_entry;
891 isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG);
892
893 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
894 buffstatus |= INT_BUFFER;
895 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
896}
897
898static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status)
899__releases(priv->lock)
900__acquires(priv->lock)
901{
902 if (!urb->unlinked) {
903 if (status == -EINPROGRESS)
904 status = 0;
905 }
906
db8516f6
CM		 907 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
908 void *ptr;
909 for (ptr = urb->transfer_buffer;
910 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
911 ptr += PAGE_SIZE)
912 flush_dcache_page(virt_to_page(ptr));
913 }
914
db11e47d
SS		 915 /* complete() can reenter this HCD */
916 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
917 spin_unlock(&priv->lock);
918 usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status);
919 spin_lock(&priv->lock);
920}
921
922static void isp1760_qtd_free(struct isp1760_qtd *qtd)
923{
924 kmem_cache_free(qtd_cachep, qtd);
925}
926
927static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd)
928{
929 struct isp1760_qtd *tmp_qtd;
930
931 tmp_qtd = qtd->hw_next;
932 list_del(&qtd->qtd_list);
933 isp1760_qtd_free(qtd);
934 return tmp_qtd;
935}
936
937/*
938 * Remove this QTD from the QH list and free its memory. If this QTD
939 * isn't the last one than remove also his successor(s).
940 * Returns the QTD which is part of an new URB and should be enqueued.
941 */
942static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd)
943{
944 struct isp1760_qtd *tmp_qtd;
945 int last_one;
946
947 do {
948 tmp_qtd = qtd->hw_next;
949 last_one = qtd->status & URB_COMPLETE_NOTIFY;
950 list_del(&qtd->qtd_list);
951 isp1760_qtd_free(qtd);
952 qtd = tmp_qtd;
953 } while (!last_one && qtd);
954
955 return qtd;
956}
957
958static void do_atl_int(struct usb_hcd *usb_hcd)
959{
960 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
961 u32 done_map, skip_map;
962 struct ptd ptd;
963 struct urb *urb = NULL;
964 u32 atl_regs_base;
965 u32 atl_regs;
966 u32 queue_entry;
967 u32 payload;
968 u32 length;
969 u32 or_map;
970 u32 status = -EINVAL;
971 int error;
972 struct isp1760_qtd *qtd;
973 struct isp1760_qh *qh;
974 u32 rl;
975 u32 nakcount;
976
977 done_map = isp1760_readl(usb_hcd->regs +
978 HC_ATL_PTD_DONEMAP_REG);
979 skip_map = isp1760_readl(usb_hcd->regs +
980 HC_ATL_PTD_SKIPMAP_REG);
981
982 or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
983 or_map &= ~done_map;
984 isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
985
986 atl_regs_base = ATL_REGS_OFFSET;
987 while (done_map) {
988 u32 dw1;
989 u32 dw2;
990 u32 dw3;
991
992 status = 0;
993
994 queue_entry = __ffs(done_map);
995 done_map &= ~(1 << queue_entry);
996 skip_map |= 1 << queue_entry;
997
998 atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd);
999
1000 urb = priv->atl_ints[queue_entry].urb;
1001 qtd = priv->atl_ints[queue_entry].qtd;
1002 qh = priv->atl_ints[queue_entry].qh;
1003 payload = priv->atl_ints[queue_entry].payload;
1004
1005 if (!qh) {
1006 printk(KERN_ERR "qh is 0\n");
1007 continue;
1008 }
3f02a957
ES		 1009 isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs +
1010 HC_MEMORY_REG);
1011 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1012 HC_MEMORY_REG);
1013 /*
1014 * write bank1 address twice to ensure the 90ns delay (time
1015 * between BANK0 write and the priv_read_copy() call is at
380ec678 1016 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns)
3f02a957
ES		 1017 */
1018 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1019 HC_MEMORY_REG);
1020
1021 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs +
1022 ISP_BANK(0), sizeof(ptd));
db11e47d
SS		 1023
1024 dw1 = le32_to_cpu(ptd.dw1);
1025 dw2 = le32_to_cpu(ptd.dw2);
1026 dw3 = le32_to_cpu(ptd.dw3);
1027 rl = (dw2 >> 25) & 0x0f;
1028 nakcount = (dw3 >> 19) & 0xf;
1029
1030 /* Transfer Error, *but* active and no HALT -> reload */
1031 if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) &&
1032 !(dw3 & DW3_HALT_BIT)) {
1033
1034 /* according to ppriv code, we have to
1035 * reload this one if trasfered bytes != requested bytes
1036 * else act like everything went smooth..
1037 * XXX This just doesn't feel right and hasn't
1038 * triggered so far.
1039 */
1040
1041 length = PTD_XFERRED_LENGTH(dw3);
1042 printk(KERN_ERR "Should reload now.... transfered %d "
1043 "of %zu\n", length, qtd->length);
1044 BUG();
1045 }
1046
1047 if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) {
1048 u32 buffstatus;
1049
c0d74142 1050 /*
db11e47d
SS		 1051 * NAKs are handled in HW by the chip. Usually if the
1052 * device is not able to send data fast enough.
c0d74142 1053 * This happens mostly on slower hardware.
db11e47d 1054 */
c0d74142 1055 printk(KERN_NOTICE "Reloading ptd %p/%p... qh %p read: "
22026473 1056 "%d of %zu done: %08x cur: %08x\n", qtd,
db11e47d
SS		 1057 urb, qh, PTD_XFERRED_LENGTH(dw3),
1058 qtd->length, done_map,
1059 (1 << queue_entry));
1060
1061 /* RL counter = ERR counter */
1062 dw3 &= ~(0xf << 19);
1063 dw3 |= rl << 19;
1064 dw3 &= ~(3 << (55 - 32));
1065 dw3 |= ERR_COUNTER << (55 - 32);
1066
1067 /*
1068 * It is not needed to write skip map back because it
1069 * is unchanged. Just make sure that this entry is
1070 * unskipped once it gets written to the HW.
1071 */
1072 skip_map &= ~(1 << queue_entry);
1073 or_map = isp1760_readl(usb_hcd->regs +
1074 HC_ATL_IRQ_MASK_OR_REG);
1075 or_map |= 1 << queue_entry;
1076 isp1760_writel(or_map, usb_hcd->regs +
1077 HC_ATL_IRQ_MASK_OR_REG);
1078
1079 ptd.dw3 = cpu_to_le32(dw3);
1080 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
1081 atl_regs, sizeof(ptd));
1082
551509d2 1083 ptd.dw0 |= cpu_to_le32(PTD_VALID);
db11e47d
SS		 1084 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
1085 atl_regs, sizeof(ptd));
1086
1087 buffstatus = isp1760_readl(usb_hcd->regs +
1088 HC_BUFFER_STATUS_REG);
1089 buffstatus |= ATL_BUFFER;
1090 isp1760_writel(buffstatus, usb_hcd->regs +
1091 HC_BUFFER_STATUS_REG);
1092 continue;
1093 }
1094
1095 error = check_error(&ptd);
1096 if (error) {
1097 status = error;
1098 priv->atl_ints[queue_entry].qh->toggle = 0;
1099 priv->atl_ints[queue_entry].qh->ping = 0;
1100 urb->status = -EPIPE;
1101
1102#if 0
1103 printk(KERN_ERR "Error in %s().\n", __func__);
1104 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1105 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1106 "%08x dw7: %08x\n",
1107 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1108 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1109#endif
1110 } else {
1111 if (usb_pipetype(urb->pipe) == PIPE_BULK) {
1112 priv->atl_ints[queue_entry].qh->toggle = dw3 &
1113 (1 << 25);
1114 priv->atl_ints[queue_entry].qh->ping = dw3 &
1115 (1 << 26);
1116 }
1117 }
1118
1119 length = PTD_XFERRED_LENGTH(dw3);
1120 if (length) {
1121 switch (DW1_GET_PID(dw1)) {
1122 case IN_PID:
1123 priv_read_copy(priv,
1124 priv->atl_ints[queue_entry].data_buffer,
3f02a957 1125 usb_hcd->regs + payload + ISP_BANK(1),
db11e47d
SS		 1126 length);
1127
1128 case OUT_PID:
1129
1130 urb->actual_length += length;
1131
1132 case SETUP_PID:
1133 break;
1134 }
1135 }
1136
1137 priv->atl_ints[queue_entry].data_buffer = NULL;
1138 priv->atl_ints[queue_entry].urb = NULL;
1139 priv->atl_ints[queue_entry].qtd = NULL;
1140 priv->atl_ints[queue_entry].qh = NULL;
1141
1142 free_mem(priv, payload);
1143
1144 isp1760_writel(skip_map, usb_hcd->regs +
1145 HC_ATL_PTD_SKIPMAP_REG);
1146
1147 if (urb->status == -EPIPE) {
1148 /* HALT was received */
1149
1150 qtd = clean_up_qtdlist(qtd);
1151 isp1760_urb_done(priv, urb, urb->status);
1152
1153 } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) {
1154 /* short BULK received */
1155
db11e47d
SS		 1156 if (urb->transfer_flags & URB_SHORT_NOT_OK) {
1157 urb->status = -EREMOTEIO;
7839b516
SS		 1158 isp1760_dbg(priv, "short bulk, %d instead %zu "
1159 "with URB_SHORT_NOT_OK flag.\n",
1160 length, qtd->length);
db11e47d
SS		 1161 }
1162
1163 if (urb->status == -EINPROGRESS)
1164 urb->status = 0;
1165
1166 qtd = clean_up_qtdlist(qtd);
1167
1168 isp1760_urb_done(priv, urb, urb->status);
1169
1170 } else if (qtd->status & URB_COMPLETE_NOTIFY) {
1171 /* that was the last qtd of that URB */
1172
1173 if (urb->status == -EINPROGRESS)
1174 urb->status = 0;
1175
1176 qtd = clean_this_qtd(qtd);
1177 isp1760_urb_done(priv, urb, urb->status);
1178
1179 } else {
1180 /* next QTD of this URB */
1181
1182 qtd = clean_this_qtd(qtd);
1183 BUG_ON(!qtd);
1184 }
1185
1186 if (qtd)
1187 enqueue_an_ATL_packet(usb_hcd, qh, qtd);
1188
1189 skip_map = isp1760_readl(usb_hcd->regs +
1190 HC_ATL_PTD_SKIPMAP_REG);
1191 }
1192}
1193
1194static void do_intl_int(struct usb_hcd *usb_hcd)
1195{
1196 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
1197 u32 done_map, skip_map;
1198 struct ptd ptd;
1199 struct urb *urb = NULL;
1200 u32 int_regs;
1201 u32 int_regs_base;
1202 u32 payload;
1203 u32 length;
1204 u32 or_map;
1205 int error;
1206 u32 queue_entry;
1207 struct isp1760_qtd *qtd;
1208 struct isp1760_qh *qh;
1209
1210 done_map = isp1760_readl(usb_hcd->regs +
1211 HC_INT_PTD_DONEMAP_REG);
1212 skip_map = isp1760_readl(usb_hcd->regs +
1213 HC_INT_PTD_SKIPMAP_REG);
1214
1215 or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
1216 or_map &= ~done_map;
1217 isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
1218
1219 int_regs_base = INT_REGS_OFFSET;
1220
1221 while (done_map) {
1222 u32 dw1;
1223 u32 dw3;
1224
1225 queue_entry = __ffs(done_map);
1226 done_map &= ~(1 << queue_entry);
1227 skip_map |= 1 << queue_entry;
1228
1229 int_regs = int_regs_base + queue_entry * sizeof(struct ptd);
1230 urb = priv->int_ints[queue_entry].urb;
1231 qtd = priv->int_ints[queue_entry].qtd;
1232 qh = priv->int_ints[queue_entry].qh;
1233 payload = priv->int_ints[queue_entry].payload;
1234
1235 if (!qh) {
1236 printk(KERN_ERR "(INT) qh is 0\n");
1237 continue;
1238 }
1239
3f02a957
ES		 1240 isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs +
1241 HC_MEMORY_REG);
1242 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1243 HC_MEMORY_REG);
1244 /*
1245 * write bank1 address twice to ensure the 90ns delay (time
1246 * between BANK0 write and the priv_read_copy() call is at
1247 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
1248 */
1249 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1250 HC_MEMORY_REG);
1251
1252 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs +
1253 ISP_BANK(0), sizeof(ptd));
db11e47d
SS		 1254 dw1 = le32_to_cpu(ptd.dw1);
1255 dw3 = le32_to_cpu(ptd.dw3);
1256 check_int_err_status(le32_to_cpu(ptd.dw4));
1257
1258 error = check_error(&ptd);
1259 if (error) {
1260#if 0
1261 printk(KERN_ERR "Error in %s().\n", __func__);
1262 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1263 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1264 "%08x dw7: %08x\n",
1265 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1266 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1267#endif
1268 urb->status = -EPIPE;
1269 priv->int_ints[queue_entry].qh->toggle = 0;
1270 priv->int_ints[queue_entry].qh->ping = 0;
1271
1272 } else {
1273 priv->int_ints[queue_entry].qh->toggle =
1274 dw3 & (1 << 25);
1275 priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26);
1276 }
1277
1278 if (urb->dev->speed != USB_SPEED_HIGH)
1279 length = PTD_XFERRED_LENGTH_LO(dw3);
1280 else
1281 length = PTD_XFERRED_LENGTH(dw3);
1282
1283 if (length) {
1284 switch (DW1_GET_PID(dw1)) {
1285 case IN_PID:
1286 priv_read_copy(priv,
1287 priv->int_ints[queue_entry].data_buffer,
3f02a957 1288 usb_hcd->regs + payload + ISP_BANK(1),
db11e47d
SS		 1289 length);
1290 case OUT_PID:
1291
1292 urb->actual_length += length;
1293
1294 case SETUP_PID:
1295 break;
1296 }
1297 }
1298
1299 priv->int_ints[queue_entry].data_buffer = NULL;
1300 priv->int_ints[queue_entry].urb = NULL;
1301 priv->int_ints[queue_entry].qtd = NULL;
1302 priv->int_ints[queue_entry].qh = NULL;
1303
1304 isp1760_writel(skip_map, usb_hcd->regs +
1305 HC_INT_PTD_SKIPMAP_REG);
1306 free_mem(priv, payload);
1307
1308 if (urb->status == -EPIPE) {
1309 /* HALT received */
1310
1311 qtd = clean_up_qtdlist(qtd);
1312 isp1760_urb_done(priv, urb, urb->status);
1313
1314 } else if (qtd->status & URB_COMPLETE_NOTIFY) {
1315
1316 if (urb->status == -EINPROGRESS)
1317 urb->status = 0;
1318
1319 qtd = clean_this_qtd(qtd);
1320 isp1760_urb_done(priv, urb, urb->status);
1321
1322 } else {
1323 /* next QTD of this URB */
1324
1325 qtd = clean_this_qtd(qtd);
1326 BUG_ON(!qtd);
1327 }
1328
1329 if (qtd)
1330 enqueue_an_INT_packet(usb_hcd, qh, qtd);
1331
1332 skip_map = isp1760_readl(usb_hcd->regs +
1333 HC_INT_PTD_SKIPMAP_REG);
1334 }
1335}
1336
1337#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1338static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
1339 gfp_t flags)
1340{
1341 struct isp1760_qh *qh;
1342 int is_input, type;
1343
1344 qh = isp1760_qh_alloc(priv, flags);
1345 if (!qh)
1346 return qh;
1347
1348 /*
1349 * init endpoint/device data for this QH
1350 */
1351 is_input = usb_pipein(urb->pipe);
1352 type = usb_pipetype(urb->pipe);
1353
1354 if (type == PIPE_INTERRUPT) {
1355
1356 if (urb->dev->speed == USB_SPEED_HIGH) {
1357
1358 qh->period = urb->interval >> 3;
1359 if (qh->period == 0 && urb->interval != 1) {
1360 /* NOTE interval 2 or 4 uframes could work.
1361 * But interval 1 scheduling is simpler, and
1362 * includes high bandwidth.
1363 */
1364 printk(KERN_ERR "intr period %d uframes, NYET!",
1365 urb->interval);
1366 qh_destroy(qh);
1367 return NULL;
1368 }
1369 } else {
1370 qh->period = urb->interval;
1371 }
1372 }
1373
1374 /* support for tt scheduling, and access to toggles */
1375 qh->dev = urb->dev;
1376
1377 if (!usb_pipecontrol(urb->pipe))
1378 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1379 1);
1380 return qh;
1381}
1382
1383/*
1384 * For control/bulk/interrupt, return QH with these TDs appended.
1385 * Allocates and initializes the QH if necessary.
1386 * Returns null if it can't allocate a QH it needs to.
1387 * If the QH has TDs (urbs) already, that's great.
1388 */
1389static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv,
1390 struct urb *urb, struct list_head *qtd_list, int epnum,
1391 void **ptr)
1392{
1393 struct isp1760_qh *qh;
1394 struct isp1760_qtd *qtd;
1395 struct isp1760_qtd *prev_qtd;
1396
1397 qh = (struct isp1760_qh *)*ptr;
1398 if (!qh) {
1399 /* can't sleep here, we have priv->lock... */
1400 qh = qh_make(priv, urb, GFP_ATOMIC);
1401 if (!qh)
1402 return qh;
1403 *ptr = qh;
1404 }
1405
1406 qtd = list_entry(qtd_list->next, struct isp1760_qtd,
1407 qtd_list);
1408 if (!list_empty(&qh->qtd_list))
1409 prev_qtd = list_entry(qh->qtd_list.prev,
1410 struct isp1760_qtd, qtd_list);
1411 else
1412 prev_qtd = NULL;
1413
1414 list_splice(qtd_list, qh->qtd_list.prev);
1415 if (prev_qtd) {
1416 BUG_ON(prev_qtd->hw_next);
1417 prev_qtd->hw_next = qtd;
1418 }
1419
1420 urb->hcpriv = qh;
1421 return qh;
1422}
1423
1424static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb,
1425 struct list_head *qtd_list)
1426{
1427 struct list_head *entry, *temp;
1428
1429 list_for_each_safe(entry, temp, qtd_list) {
1430 struct isp1760_qtd *qtd;
1431
1432 qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
1433 list_del(&qtd->qtd_list);
1434 isp1760_qtd_free(qtd);
1435 }
1436}
1437
1438static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
1439 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1440{
1441 struct isp1760_qtd *qtd;
1442 int epnum;
1443 unsigned long flags;
1444 struct isp1760_qh *qh = NULL;
1445 int rc;
1446 int qh_busy;
1447
1448 qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
1449 epnum = urb->ep->desc.bEndpointAddress;
1450
1451 spin_lock_irqsave(&priv->lock, flags);
541c7d43 1452 if (!HCD_HW_ACCESSIBLE(priv_to_hcd(priv))) {
db11e47d
SS		 1453 rc = -ESHUTDOWN;
1454 goto done;
1455 }
1456 rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb);
1457 if (rc)
1458 goto done;
1459
1460 qh = urb->ep->hcpriv;
1461 if (qh)
1462 qh_busy = !list_empty(&qh->qtd_list);
1463 else
1464 qh_busy = 0;
1465
1466 qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv);
1467 if (!qh) {
1468 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
1469 rc = -ENOMEM;
1470 goto done;
1471 }
1472
1473 if (!qh_busy)
1474 p(priv_to_hcd(priv), qh, qtd);
1475
1476done:
1477 spin_unlock_irqrestore(&priv->lock, flags);
1478 if (!qh)
1479 qtd_list_free(priv, urb, qtd_list);
1480 return rc;
1481}
1482
1483static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv,
1484 gfp_t flags)
1485{
1486 struct isp1760_qtd *qtd;
1487
1488 qtd = kmem_cache_zalloc(qtd_cachep, flags);
1489 if (qtd)
1490 INIT_LIST_HEAD(&qtd->qtd_list);
1491
1492 return qtd;
1493}
1494
1495/*
1496 * create a list of filled qtds for this URB; won't link into qh.
1497 */
1498static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1499 struct urb *urb, struct list_head *head, gfp_t flags)
1500{
1501 struct isp1760_qtd *qtd, *qtd_prev;
1502 void *buf;
1503 int len, maxpacket;
1504 int is_input;
1505 u32 token;
1506
1507 /*
1508 * URBs map to sequences of QTDs: one logical transaction
1509 */
1510 qtd = isp1760_qtd_alloc(priv, flags);
1511 if (!qtd)
1512 return NULL;
1513
1514 list_add_tail(&qtd->qtd_list, head);
1515 qtd->urb = urb;
1516 urb->status = -EINPROGRESS;
1517
1518 token = 0;
1519 /* for split transactions, SplitXState initialized to zero */
1520
1521 len = urb->transfer_buffer_length;
1522 is_input = usb_pipein(urb->pipe);
1523 if (usb_pipecontrol(urb->pipe)) {
1524 /* SETUP pid */
1525 qtd_fill(qtd, urb->setup_packet,
1526 sizeof(struct usb_ctrlrequest),
1527 token | SETUP_PID);
1528
1529 /* ... and always at least one more pid */
1530 token ^= DATA_TOGGLE;
1531 qtd_prev = qtd;
1532 qtd = isp1760_qtd_alloc(priv, flags);
1533 if (!qtd)
1534 goto cleanup;
1535 qtd->urb = urb;
1536 qtd_prev->hw_next = qtd;
1537 list_add_tail(&qtd->qtd_list, head);
1538
1539 /* for zero length DATA stages, STATUS is always IN */
1540 if (len == 0)
1541 token |= IN_PID;
1542 }
1543
1544 /*
1545 * data transfer stage: buffer setup
1546 */
1547 buf = urb->transfer_buffer;
1548
1549 if (is_input)
1550 token |= IN_PID;
1551 else
1552 token |= OUT_PID;
1553
1554 maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1555
1556 /*
1557 * buffer gets wrapped in one or more qtds;
1558 * last one may be "short" (including zero len)
1559 * and may serve as a control status ack
1560 */
1561 for (;;) {
1562 int this_qtd_len;
1563
1564 if (!buf && len) {
1565 /* XXX This looks like usb storage / SCSI bug */
1566 printk(KERN_ERR "buf is null, dma is %08lx len is %d\n",
1567 (long unsigned)urb->transfer_dma, len);
1568 WARN_ON(1);
1569 }
1570
1571 this_qtd_len = qtd_fill(qtd, buf, len, token);
1572 len -= this_qtd_len;
1573 buf += this_qtd_len;
1574
1575 /* qh makes control packets use qtd toggle; maybe switch it */
1576 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1577 token ^= DATA_TOGGLE;
1578
1579 if (len <= 0)
1580 break;
1581
1582 qtd_prev = qtd;
1583 qtd = isp1760_qtd_alloc(priv, flags);
1584 if (!qtd)
1585 goto cleanup;
1586 qtd->urb = urb;
1587 qtd_prev->hw_next = qtd;
1588 list_add_tail(&qtd->qtd_list, head);
1589 }
1590
1591 /*
1592 * control requests may need a terminating data "status" ack;
1593 * bulk ones may need a terminating short packet (zero length).
1594 */
1595 if (urb->transfer_buffer_length != 0) {
1596 int one_more = 0;
1597
1598 if (usb_pipecontrol(urb->pipe)) {
1599 one_more = 1;
1600 /* "in" <--> "out" */
1601 token ^= IN_PID;
1602 /* force DATA1 */
1603 token |= DATA_TOGGLE;
1604 } else if (usb_pipebulk(urb->pipe)
1605 && (urb->transfer_flags & URB_ZERO_PACKET)
1606 && !(urb->transfer_buffer_length % maxpacket)) {
1607 one_more = 1;
1608 }
1609 if (one_more) {
1610 qtd_prev = qtd;
1611 qtd = isp1760_qtd_alloc(priv, flags);
1612 if (!qtd)
1613 goto cleanup;
1614 qtd->urb = urb;
1615 qtd_prev->hw_next = qtd;
1616 list_add_tail(&qtd->qtd_list, head);
1617
1618 /* never any data in such packets */
1619 qtd_fill(qtd, NULL, 0, token);
1620 }
1621 }
1622
1623 qtd->status = URB_COMPLETE_NOTIFY;
1624 return head;
1625
1626cleanup:
1627 qtd_list_free(priv, urb, head);
1628 return NULL;
1629}
1630
1631static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1632 gfp_t mem_flags)
1633{
1634 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1635 struct list_head qtd_list;
1636 packet_enqueue *pe;
1637
1638 INIT_LIST_HEAD(&qtd_list);
1639
1640 switch (usb_pipetype(urb->pipe)) {
1641 case PIPE_CONTROL:
1642 case PIPE_BULK:
1643
1644 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1645 return -ENOMEM;
1646 pe = enqueue_an_ATL_packet;
1647 break;
1648
1649 case PIPE_INTERRUPT:
1650 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1651 return -ENOMEM;
1652 pe = enqueue_an_INT_packet;
1653 break;
1654
1655 case PIPE_ISOCHRONOUS:
1656 printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n");
1657 default:
1658 return -EPIPE;
1659 }
1660
a36c27df 1661 return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe);
db11e47d
SS		 1662}
1663
1664static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1665 int status)
1666{
1667 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1668 struct inter_packet_info *ints;
1669 u32 i;
1670 u32 reg_base, or_reg, skip_reg;
d249afdd 1671 unsigned long flags;
db11e47d 1672 struct ptd ptd;
0afb20e0 1673 packet_enqueue *pe;
db11e47d
SS		 1674
1675 switch (usb_pipetype(urb->pipe)) {
1676 case PIPE_ISOCHRONOUS:
1677 return -EPIPE;
1678 break;
1679
1680 case PIPE_INTERRUPT:
1681 ints = priv->int_ints;
1682 reg_base = INT_REGS_OFFSET;
1683 or_reg = HC_INT_IRQ_MASK_OR_REG;
1684 skip_reg = HC_INT_PTD_SKIPMAP_REG;
0afb20e0 1685 pe = enqueue_an_INT_packet;
db11e47d
SS		 1686 break;
1687
1688 default:
1689 ints = priv->atl_ints;
1690 reg_base = ATL_REGS_OFFSET;
1691 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1692 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
0afb20e0 1693 pe = enqueue_an_ATL_packet;
db11e47d
SS		 1694 break;
1695 }
1696
1697 memset(&ptd, 0, sizeof(ptd));
1698 spin_lock_irqsave(&priv->lock, flags);
1699
1700 for (i = 0; i < 32; i++) {
1701 if (ints->urb == urb) {
1702 u32 skip_map;
1703 u32 or_map;
1704 struct isp1760_qtd *qtd;
0afb20e0 1705 struct isp1760_qh *qh = ints->qh;
db11e47d
SS		 1706
1707 skip_map = isp1760_readl(hcd->regs + skip_reg);
1708 skip_map |= 1 << i;
1709 isp1760_writel(skip_map, hcd->regs + skip_reg);
1710
1711 or_map = isp1760_readl(hcd->regs + or_reg);
1712 or_map &= ~(1 << i);
1713 isp1760_writel(or_map, hcd->regs + or_reg);
1714
1715 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base
1716 + i * sizeof(ptd), sizeof(ptd));
1717 qtd = ints->qtd;
0afb20e0 1718 qtd = clean_up_qtdlist(qtd);
db11e47d
SS		 1719
1720 free_mem(priv, ints->payload);
1721
1722 ints->urb = NULL;
1723 ints->qh = NULL;
1724 ints->qtd = NULL;
1725 ints->data_buffer = NULL;
1726 ints->payload = 0;
1727
1728 isp1760_urb_done(priv, urb, status);
0afb20e0
WF		 1729 if (qtd)
1730 pe(hcd, qh, qtd);
db11e47d 1731 break;
0afb20e0
WF		 1732
1733 } else if (ints->qtd) {
1734 struct isp1760_qtd *qtd, *prev_qtd = ints->qtd;
1735
1736 for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) {
1737 if (qtd->urb == urb) {
1738 prev_qtd->hw_next = clean_up_qtdlist(qtd);
1739 isp1760_urb_done(priv, urb, status);
1740 break;
1741 }
1742 prev_qtd = qtd;
1743 }
1744 /* we found the urb before the end of the list */
1745 if (qtd)
1746 break;
db11e47d
SS		 1747 }
1748 ints++;
1749 }
1750
1751 spin_unlock_irqrestore(&priv->lock, flags);
1752 return 0;
1753}
1754
1755static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd)
1756{
1757 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
1758 u32 imask;
1759 irqreturn_t irqret = IRQ_NONE;
1760
1761 spin_lock(&priv->lock);
1762
1763 if (!(usb_hcd->state & HC_STATE_RUNNING))
1764 goto leave;
1765
1766 imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG);
1767 if (unlikely(!imask))
1768 goto leave;
1769
1770 isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG);
1771 if (imask & HC_ATL_INT)
1772 do_atl_int(usb_hcd);
1773
1774 if (imask & HC_INTL_INT)
1775 do_intl_int(usb_hcd);
1776
1777 irqret = IRQ_HANDLED;
1778leave:
1779 spin_unlock(&priv->lock);
1780 return irqret;
1781}
1782
1783static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1784{
1785 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1786 u32 temp, status = 0;
1787 u32 mask;
1788 int retval = 1;
1789 unsigned long flags;
1790
1791 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1792 if (!HC_IS_RUNNING(hcd->state))
1793 return 0;
1794
1795 /* init status to no-changes */
1796 buf[0] = 0;
1797 mask = PORT_CSC;
1798
1799 spin_lock_irqsave(&priv->lock, flags);
1800 temp = isp1760_readl(hcd->regs + HC_PORTSC1);
1801
1802 if (temp & PORT_OWNER) {
1803 if (temp & PORT_CSC) {
1804 temp &= ~PORT_CSC;
1805 isp1760_writel(temp, hcd->regs + HC_PORTSC1);
1806 goto done;
1807 }
1808 }
1809
1810 /*
1811 * Return status information even for ports with OWNER set.
1812 * Otherwise khubd wouldn't see the disconnect event when a
1813 * high-speed device is switched over to the companion
1814 * controller by the user.
1815 */
1816
1817 if ((temp & mask) != 0
1818 || ((temp & PORT_RESUME) != 0
1819 && time_after_eq(jiffies,
1820 priv->reset_done))) {
1821 buf [0] |= 1 << (0 + 1);
1822 status = STS_PCD;
1823 }
1824 /* FIXME autosuspend idle root hubs */
1825done:
1826 spin_unlock_irqrestore(&priv->lock, flags);
1827 return status ? retval : 0;
1828}
1829
1830static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1831 struct usb_hub_descriptor *desc)
1832{
1833 int ports = HCS_N_PORTS(priv->hcs_params);
1834 u16 temp;
1835
1836 desc->bDescriptorType = 0x29;
1837 /* priv 1.0, 2.3.9 says 20ms max */
1838 desc->bPwrOn2PwrGood = 10;
1839 desc->bHubContrCurrent = 0;
1840
1841 desc->bNbrPorts = ports;
1842 temp = 1 + (ports / 8);
1843 desc->bDescLength = 7 + 2 * temp;
1844
1845 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1846 memset(&desc->bitmap[0], 0, temp);
1847 memset(&desc->bitmap[temp], 0xff, temp);
1848
1849 /* per-port overcurrent reporting */
1850 temp = 0x0008;
1851 if (HCS_PPC(priv->hcs_params))
1852 /* per-port power control */
1853 temp |= 0x0001;
1854 else
1855 /* no power switching */
1856 temp |= 0x0002;
1857 desc->wHubCharacteristics = cpu_to_le16(temp);
1858}
1859
1860#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1861
1862static int check_reset_complete(struct isp1760_hcd *priv, int index,
1863 u32 __iomem *status_reg, int port_status)
1864{
1865 if (!(port_status & PORT_CONNECT))
1866 return port_status;
1867
1868 /* if reset finished and it's still not enabled -- handoff */
1869 if (!(port_status & PORT_PE)) {
1870
1871 printk(KERN_ERR "port %d full speed --> companion\n",
1872 index + 1);
1873
1874 port_status |= PORT_OWNER;
1875 port_status &= ~PORT_RWC_BITS;
1876 isp1760_writel(port_status, status_reg);
1877
1878 } else
1879 printk(KERN_ERR "port %d high speed\n", index + 1);
1880
1881 return port_status;
1882}
1883
1884static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1885 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1886{
1887 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1888 int ports = HCS_N_PORTS(priv->hcs_params);
1889 u32 __iomem *status_reg = hcd->regs + HC_PORTSC1;
1890 u32 temp, status;
1891 unsigned long flags;
1892 int retval = 0;
1893 unsigned selector;
1894
1895 /*
1896 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1897 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1898 * (track current state ourselves) ... blink for diagnostics,
1899 * power, "this is the one", etc. EHCI spec supports this.
1900 */
1901
1902 spin_lock_irqsave(&priv->lock, flags);
1903 switch (typeReq) {
1904 case ClearHubFeature:
1905 switch (wValue) {
1906 case C_HUB_LOCAL_POWER:
1907 case C_HUB_OVER_CURRENT:
1908 /* no hub-wide feature/status flags */
1909 break;
1910 default:
1911 goto error;
1912 }
1913 break;
1914 case ClearPortFeature:
1915 if (!wIndex || wIndex > ports)
1916 goto error;
1917 wIndex--;
1918 temp = isp1760_readl(status_reg);
1919
1920 /*
1921 * Even if OWNER is set, so the port is owned by the
1922 * companion controller, khubd needs to be able to clear
1923 * the port-change status bits (especially
749da5f8 1924 * USB_PORT_STAT_C_CONNECTION).
db11e47d
SS		 1925 */
1926
1927 switch (wValue) {
1928 case USB_PORT_FEAT_ENABLE:
1929 isp1760_writel(temp & ~PORT_PE, status_reg);
1930 break;
1931 case USB_PORT_FEAT_C_ENABLE:
1932 /* XXX error? */
1933 break;
1934 case USB_PORT_FEAT_SUSPEND:
1935 if (temp & PORT_RESET)
1936 goto error;
1937
1938 if (temp & PORT_SUSPEND) {
1939 if ((temp & PORT_PE) == 0)
1940 goto error;
1941 /* resume signaling for 20 msec */
1942 temp &= ~(PORT_RWC_BITS);
1943 isp1760_writel(temp | PORT_RESUME,
1944 status_reg);
1945 priv->reset_done = jiffies +
1946 msecs_to_jiffies(20);
1947 }
1948 break;
1949 case USB_PORT_FEAT_C_SUSPEND:
1950 /* we auto-clear this feature */
1951 break;
1952 case USB_PORT_FEAT_POWER:
1953 if (HCS_PPC(priv->hcs_params))
1954 isp1760_writel(temp & ~PORT_POWER, status_reg);
1955 break;
1956 case USB_PORT_FEAT_C_CONNECTION:
1957 isp1760_writel(temp | PORT_CSC,
1958 status_reg);
1959 break;
1960 case USB_PORT_FEAT_C_OVER_CURRENT:
1961 /* XXX error ?*/
1962 break;
1963 case USB_PORT_FEAT_C_RESET:
1964 /* GetPortStatus clears reset */
1965 break;
1966 default:
1967 goto error;
1968 }
1969 isp1760_readl(hcd->regs + HC_USBCMD);
1970 break;
1971 case GetHubDescriptor:
1972 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1973 buf);
1974 break;
1975 case GetHubStatus:
1976 /* no hub-wide feature/status flags */
1977 memset(buf, 0, 4);
1978 break;
1979 case GetPortStatus:
1980 if (!wIndex || wIndex > ports)
1981 goto error;
1982 wIndex--;
1983 status = 0;
1984 temp = isp1760_readl(status_reg);
1985
1986 /* wPortChange bits */
1987 if (temp & PORT_CSC)
749da5f8 1988 status |= USB_PORT_STAT_C_CONNECTION << 16;
db11e47d
SS		 1989
1990
1991 /* whoever resumes must GetPortStatus to complete it!! */
1992 if (temp & PORT_RESUME) {
1993 printk(KERN_ERR "Port resume should be skipped.\n");
1994
1995 /* Remote Wakeup received? */
1996 if (!priv->reset_done) {
1997 /* resume signaling for 20 msec */
1998 priv->reset_done = jiffies
1999 + msecs_to_jiffies(20);
2000 /* check the port again */
2001 mod_timer(&priv_to_hcd(priv)->rh_timer,
2002 priv->reset_done);
2003 }
2004
2005 /* resume completed? */
2006 else if (time_after_eq(jiffies,
2007 priv->reset_done)) {
749da5f8 2008 status |= USB_PORT_STAT_C_SUSPEND << 16;
db11e47d
SS		 2009 priv->reset_done = 0;
2010
2011 /* stop resume signaling */
2012 temp = isp1760_readl(status_reg);
2013 isp1760_writel(
2014 temp & ~(PORT_RWC_BITS | PORT_RESUME),
2015 status_reg);
2016 retval = handshake(priv, status_reg,
2017 PORT_RESUME, 0, 2000 /* 2msec */);
2018 if (retval != 0) {
2019 isp1760_err(priv,
2020 "port %d resume error %d\n",
2021 wIndex + 1, retval);
2022 goto error;
2023 }
2024 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
2025 }
2026 }
2027
2028 /* whoever resets must GetPortStatus to complete it!! */
2029 if ((temp & PORT_RESET)
2030 && time_after_eq(jiffies,
2031 priv->reset_done)) {
749da5f8 2032 status |= USB_PORT_STAT_C_RESET << 16;
db11e47d
SS		 2033 priv->reset_done = 0;
2034
2035 /* force reset to complete */
2036 isp1760_writel(temp & ~PORT_RESET,
2037 status_reg);
2038 /* REVISIT: some hardware needs 550+ usec to clear
2039 * this bit; seems too long to spin routinely...
2040 */
2041 retval = handshake(priv, status_reg,
2042 PORT_RESET, 0, 750);
2043 if (retval != 0) {
2044 isp1760_err(priv, "port %d reset error %d\n",
2045 wIndex + 1, retval);
2046 goto error;
2047 }
2048
2049 /* see what we found out */
2050 temp = check_reset_complete(priv, wIndex, status_reg,
2051 isp1760_readl(status_reg));
2052 }
2053 /*
2054 * Even if OWNER is set, there's no harm letting khubd
2055 * see the wPortStatus values (they should all be 0 except
2056 * for PORT_POWER anyway).
2057 */
2058
2059 if (temp & PORT_OWNER)
2060 printk(KERN_ERR "Warning: PORT_OWNER is set\n");
2061
2062 if (temp & PORT_CONNECT) {
749da5f8 2063 status |= USB_PORT_STAT_CONNECTION;
db11e47d
SS		 2064 /* status may be from integrated TT */
2065 status |= ehci_port_speed(priv, temp);
2066 }
2067 if (temp & PORT_PE)
749da5f8 2068 status |= USB_PORT_STAT_ENABLE;
db11e47d 2069 if (temp & (PORT_SUSPEND|PORT_RESUME))
749da5f8 2070 status |= USB_PORT_STAT_SUSPEND;
db11e47d 2071 if (temp & PORT_RESET)
749da5f8 2072 status |= USB_PORT_STAT_RESET;
db11e47d 2073 if (temp & PORT_POWER)
749da5f8 2074 status |= USB_PORT_STAT_POWER;
db11e47d
SS		 2075
2076 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2077 break;
2078 case SetHubFeature:
2079 switch (wValue) {
2080 case C_HUB_LOCAL_POWER:
2081 case C_HUB_OVER_CURRENT:
2082 /* no hub-wide feature/status flags */
2083 break;
2084 default:
2085 goto error;
2086 }
2087 break;
2088 case SetPortFeature:
2089 selector = wIndex >> 8;
2090 wIndex &= 0xff;
2091 if (!wIndex || wIndex > ports)
2092 goto error;
2093 wIndex--;
2094 temp = isp1760_readl(status_reg);
2095 if (temp & PORT_OWNER)
2096 break;
2097
2098/* temp &= ~PORT_RWC_BITS; */
2099 switch (wValue) {
2100 case USB_PORT_FEAT_ENABLE:
2101 isp1760_writel(temp | PORT_PE, status_reg);
2102 break;
2103
2104 case USB_PORT_FEAT_SUSPEND:
2105 if ((temp & PORT_PE) == 0
2106 || (temp & PORT_RESET) != 0)
2107 goto error;
2108
2109 isp1760_writel(temp | PORT_SUSPEND, status_reg);
2110 break;
2111 case USB_PORT_FEAT_POWER:
2112 if (HCS_PPC(priv->hcs_params))
2113 isp1760_writel(temp | PORT_POWER,
2114 status_reg);
2115 break;
2116 case USB_PORT_FEAT_RESET:
2117 if (temp & PORT_RESUME)
2118 goto error;
2119 /* line status bits may report this as low speed,
2120 * which can be fine if this root hub has a
2121 * transaction translator built in.
2122 */
2123 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2124 && PORT_USB11(temp)) {
2125 temp |= PORT_OWNER;
2126 } else {
2127 temp |= PORT_RESET;
2128 temp &= ~PORT_PE;
2129
2130 /*
2131 * caller must wait, then call GetPortStatus
2132 * usb 2.0 spec says 50 ms resets on root
2133 */
2134 priv->reset_done = jiffies +
2135 msecs_to_jiffies(50);
2136 }
2137 isp1760_writel(temp, status_reg);
2138 break;
2139 default:
2140 goto error;
2141 }
2142 isp1760_readl(hcd->regs + HC_USBCMD);
2143 break;
2144
2145 default:
2146error:
2147 /* "stall" on error */
2148 retval = -EPIPE;
2149 }
2150 spin_unlock_irqrestore(&priv->lock, flags);
2151 return retval;
2152}
2153
2154static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd,
2155 struct usb_host_endpoint *ep)
2156{
2157 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
2158 struct isp1760_qh *qh;
2159 struct isp1760_qtd *qtd;
d249afdd 2160 unsigned long flags;
db11e47d
SS		 2161
2162 spin_lock_irqsave(&priv->lock, flags);
2163 qh = ep->hcpriv;
2164 if (!qh)
2165 goto out;
2166
2167 ep->hcpriv = NULL;
2168 do {
2169 /* more than entry might get removed */
2170 if (list_empty(&qh->qtd_list))
2171 break;
2172
2173 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
2174 qtd_list);
2175
2176 if (qtd->status & URB_ENQUEUED) {
2177
2178 spin_unlock_irqrestore(&priv->lock, flags);
2179 isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET);
2180 spin_lock_irqsave(&priv->lock, flags);
2181 } else {
2182 struct urb *urb;
2183
2184 urb = qtd->urb;
2185 clean_up_qtdlist(qtd);
2186 isp1760_urb_done(priv, urb, -ECONNRESET);
2187 }
2188 } while (1);
2189
2190 qh_destroy(qh);
2191 /* remove requests and leak them.
2192 * ATL are pretty fast done, INT could take a while...
2193 * The latter shoule be removed
2194 */
2195out:
2196 spin_unlock_irqrestore(&priv->lock, flags);
2197}
2198
2199static int isp1760_get_frame(struct usb_hcd *hcd)
2200{
2201 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2202 u32 fr;
2203
2204 fr = isp1760_readl(hcd->regs + HC_FRINDEX);
2205 return (fr >> 3) % priv->periodic_size;
2206}
2207
2208static void isp1760_stop(struct usb_hcd *hcd)
2209{
2210 struct isp1760_hcd *priv = hcd_to_priv(hcd);
3faefc88 2211 u32 temp;
db11e47d
SS		 2212
2213 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2214 NULL, 0);
2215 mdelay(20);
2216
2217 spin_lock_irq(&priv->lock);
2218 ehci_reset(priv);
2219 /* Disable IRQ */
3faefc88
NC		 2220 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
2221 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
db11e47d
SS		 2222 spin_unlock_irq(&priv->lock);
2223
2224 isp1760_writel(0, hcd->regs + HC_CONFIGFLAG);
2225}
2226
2227static void isp1760_shutdown(struct usb_hcd *hcd)
2228{
3faefc88 2229 u32 command, temp;
db11e47d
SS		 2230
2231 isp1760_stop(hcd);
3faefc88
NC		 2232 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
2233 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
db11e47d
SS		 2234
2235 command = isp1760_readl(hcd->regs + HC_USBCMD);
2236 command &= ~CMD_RUN;
2237 isp1760_writel(command, hcd->regs + HC_USBCMD);
2238}
2239
2240static const struct hc_driver isp1760_hc_driver = {
2241 .description = "isp1760-hcd",
2242 .product_desc = "NXP ISP1760 USB Host Controller",
2243 .hcd_priv_size = sizeof(struct isp1760_hcd),
2244 .irq = isp1760_irq,
2245 .flags = HCD_MEMORY | HCD_USB2,
2246 .reset = isp1760_hc_setup,
2247 .start = isp1760_run,
2248 .stop = isp1760_stop,
2249 .shutdown = isp1760_shutdown,
2250 .urb_enqueue = isp1760_urb_enqueue,
2251 .urb_dequeue = isp1760_urb_dequeue,
2252 .endpoint_disable = isp1760_endpoint_disable,
2253 .get_frame_number = isp1760_get_frame,
2254 .hub_status_data = isp1760_hub_status_data,
2255 .hub_control = isp1760_hub_control,
2256};
2257
2258int __init init_kmem_once(void)
2259{
2260 qtd_cachep = kmem_cache_create("isp1760_qtd",
2261 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2262 SLAB_MEM_SPREAD, NULL);
2263
2264 if (!qtd_cachep)
2265 return -ENOMEM;
2266
2267 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2268 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2269
2270 if (!qh_cachep) {
2271 kmem_cache_destroy(qtd_cachep);
2272 return -ENOMEM;
2273 }
2274
2275 return 0;
2276}
2277
2278void deinit_kmem_cache(void)
2279{
2280 kmem_cache_destroy(qtd_cachep);
2281 kmem_cache_destroy(qh_cachep);
2282}
2283
f9031f2c
CM		 2284struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2285 int irq, unsigned long irqflags,
2286 struct device *dev, const char *busname,
2287 unsigned int devflags)
db11e47d
SS		 2288{
2289 struct usb_hcd *hcd;
2290 struct isp1760_hcd *priv;
2291 int ret;
2292
2293 if (usb_disabled())
2294 return ERR_PTR(-ENODEV);
2295
2296 /* prevent usb-core allocating DMA pages */
2297 dev->dma_mask = NULL;
2298
0031a06e 2299 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
db11e47d
SS		 2300 if (!hcd)
2301 return ERR_PTR(-ENOMEM);
2302
2303 priv = hcd_to_priv(hcd);
3faefc88 2304 priv->devflags = devflags;
db11e47d
SS		 2305 init_memory(priv);
2306 hcd->regs = ioremap(res_start, res_len);
2307 if (!hcd->regs) {
2308 ret = -EIO;
2309 goto err_put;
2310 }
2311
db11e47d
SS		 2312 hcd->irq = irq;
2313 hcd->rsrc_start = res_start;
2314 hcd->rsrc_len = res_len;
2315
e6942d63
NC		 2316 ret = usb_add_hcd(hcd, irq, irqflags);
2317 if (ret)
2318 goto err_unmap;
2319
db11e47d
SS		 2320 return hcd;
2321
2322err_unmap:
2323 iounmap(hcd->regs);
2324
2325err_put:
2326 usb_put_hcd(hcd);
2327
2328 return ERR_PTR(ret);
2329}
2330
2331MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2332MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2333MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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