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Merge commit 'v2.6.35-rc1' into amd-iommu/2.6.35
[deliverable/linux.git] / drivers / usb / host / isp1760-hcd.c
CommitLineData
db11e47d
SS		 1/*
2 * Driver for the NXP ISP1760 chip
3 *
4 * However, the code might contain some bugs. What doesn't work for sure is:
5 * - ISO
6 * - OTG
7 e The interrupt line is configured as active low, level.
8 *
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
10 *
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/slab.h>
15#include <linux/list.h>
16#include <linux/usb.h>
27729aad 17#include <linux/usb/hcd.h>
db11e47d
SS		 18#include <linux/debugfs.h>
19#include <linux/uaccess.h>
20#include <linux/io.h>
db8516f6 21#include <linux/mm.h>
db11e47d 22#include <asm/unaligned.h>
db8516f6 23#include <asm/cacheflush.h>
db11e47d 24
db11e47d
SS		 25#include "isp1760-hcd.h"
26
27static struct kmem_cache *qtd_cachep;
28static struct kmem_cache *qh_cachep;
29
30struct isp1760_hcd {
31 u32 hcs_params;
32 spinlock_t lock;
33 struct inter_packet_info atl_ints[32];
34 struct inter_packet_info int_ints[32];
35 struct memory_chunk memory_pool[BLOCKS];
36
37 /* periodic schedule support */
38#define DEFAULT_I_TDPS 1024
39 unsigned periodic_size;
40 unsigned i_thresh;
41 unsigned long reset_done;
42 unsigned long next_statechange;
3faefc88 43 unsigned int devflags;
db11e47d
SS		 44};
45
46static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
47{
48 return (struct isp1760_hcd *) (hcd->hcd_priv);
49}
50static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
51{
52 return container_of((void *) priv, struct usb_hcd, hcd_priv);
53}
54
55/* Section 2.2 Host Controller Capability Registers */
56#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
57#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
58#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
59#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
60#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
61#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
62#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
63
64/* Section 2.3 Host Controller Operational Registers */
65#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
66#define CMD_RESET (1<<1) /* reset HC not bus */
67#define CMD_RUN (1<<0) /* start/stop HC */
68#define STS_PCD (1<<2) /* port change detect */
69#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
70
71#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
72#define PORT_POWER (1<<12) /* true: has power (see PPC) */
73#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
74#define PORT_RESET (1<<8) /* reset port */
75#define PORT_SUSPEND (1<<7) /* suspend port */
76#define PORT_RESUME (1<<6) /* resume it */
77#define PORT_PE (1<<2) /* port enable */
78#define PORT_CSC (1<<1) /* connect status change */
79#define PORT_CONNECT (1<<0) /* device connected */
80#define PORT_RWC_BITS (PORT_CSC)
81
82struct isp1760_qtd {
83 struct isp1760_qtd *hw_next;
84 u8 packet_type;
85 u8 toggle;
86
87 void *data_buffer;
88 /* the rest is HCD-private */
89 struct list_head qtd_list;
90 struct urb *urb;
91 size_t length;
92
93 /* isp special*/
94 u32 status;
95#define URB_COMPLETE_NOTIFY (1 << 0)
96#define URB_ENQUEUED (1 << 1)
97#define URB_TYPE_ATL (1 << 2)
98#define URB_TYPE_INT (1 << 3)
99};
100
101struct isp1760_qh {
102 /* first part defined by EHCI spec */
103 struct list_head qtd_list;
104 struct isp1760_hcd *priv;
105
106 /* periodic schedule info */
107 unsigned short period; /* polling interval */
108 struct usb_device *dev;
109
110 u32 toggle;
111 u32 ping;
112};
113
288ead45 114#define ehci_port_speed(priv, portsc) USB_PORT_STAT_HIGH_SPEED
db11e47d
SS		 115
116static unsigned int isp1760_readl(__u32 __iomem *regs)
117{
118 return readl(regs);
119}
120
121static void isp1760_writel(const unsigned int val, __u32 __iomem *regs)
122{
123 writel(val, regs);
124}
125
126/*
127 * The next two copy via MMIO data to/from the device. memcpy_{to|from}io()
128 * doesn't quite work because some people have to enforce 32-bit access
129 */
130static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
3f02a957 131 __u32 __iomem *dst, u32 len)
db11e47d 132{
db11e47d
SS		 133 u32 val;
134 u8 *buff8;
135
136 if (!src) {
137 printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
138 return;
139 }
db11e47d
SS		 140
141 while (len >= 4) {
142 *src = __raw_readl(dst);
143 len -= 4;
144 src++;
145 dst++;
146 }
147
148 if (!len)
149 return;
150
151 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
152 * allocated.
153 */
154 val = isp1760_readl(dst);
155
156 buff8 = (u8 *)src;
157 while (len) {
158
159 *buff8 = val;
160 val >>= 8;
161 len--;
162 buff8++;
163 }
164}
165
166static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src,
167 __u32 __iomem *dst, u32 len)
168{
169 while (len >= 4) {
170 __raw_writel(*src, dst);
171 len -= 4;
172 src++;
173 dst++;
174 }
175
176 if (!len)
177 return;
178 /* in case we have 3, 2 or 1 by left. The buffer is allocated and the
179 * extra bytes should not be read by the HW
180 */
181
182 __raw_writel(*src, dst);
183}
184
185/* memory management of the 60kb on the chip from 0x1000 to 0xffff */
186static void init_memory(struct isp1760_hcd *priv)
187{
188 int i;
189 u32 payload;
190
191 payload = 0x1000;
192 for (i = 0; i < BLOCK_1_NUM; i++) {
193 priv->memory_pool[i].start = payload;
194 priv->memory_pool[i].size = BLOCK_1_SIZE;
195 priv->memory_pool[i].free = 1;
196 payload += priv->memory_pool[i].size;
197 }
198
199
200 for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) {
201 priv->memory_pool[i].start = payload;
202 priv->memory_pool[i].size = BLOCK_2_SIZE;
203 priv->memory_pool[i].free = 1;
204 payload += priv->memory_pool[i].size;
205 }
206
207
208 for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) {
209 priv->memory_pool[i].start = payload;
210 priv->memory_pool[i].size = BLOCK_3_SIZE;
211 priv->memory_pool[i].free = 1;
212 payload += priv->memory_pool[i].size;
213 }
214
215 BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE);
216}
217
218static u32 alloc_mem(struct isp1760_hcd *priv, u32 size)
219{
220 int i;
221
222 if (!size)
223 return ISP1760_NULL_POINTER;
224
225 for (i = 0; i < BLOCKS; i++) {
226 if (priv->memory_pool[i].size >= size &&
227 priv->memory_pool[i].free) {
228
229 priv->memory_pool[i].free = 0;
230 return priv->memory_pool[i].start;
231 }
232 }
233
234 printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n",
235 size);
236 printk(KERN_ERR "Current memory map:\n");
237 for (i = 0; i < BLOCKS; i++) {
238 printk(KERN_ERR "Pool %2d size %4d status: %d\n",
239 i, priv->memory_pool[i].size,
240 priv->memory_pool[i].free);
241 }
242 /* XXX maybe -ENOMEM could be possible */
243 BUG();
244 return 0;
245}
246
247static void free_mem(struct isp1760_hcd *priv, u32 mem)
248{
249 int i;
250
251 if (mem == ISP1760_NULL_POINTER)
252 return;
253
254 for (i = 0; i < BLOCKS; i++) {
255 if (priv->memory_pool[i].start == mem) {
256
257 BUG_ON(priv->memory_pool[i].free);
258
259 priv->memory_pool[i].free = 1;
260 return ;
261 }
262 }
263
264 printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n",
265 mem);
266 BUG();
267}
268
269static void isp1760_init_regs(struct usb_hcd *hcd)
270{
271 isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG);
272 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
273 HC_ATL_PTD_SKIPMAP_REG);
274 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
275 HC_INT_PTD_SKIPMAP_REG);
276 isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
277 HC_ISO_PTD_SKIPMAP_REG);
278
279 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
280 HC_ATL_PTD_DONEMAP_REG);
281 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
282 HC_INT_PTD_DONEMAP_REG);
283 isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
284 HC_ISO_PTD_DONEMAP_REG);
285}
286
287static int handshake(struct isp1760_hcd *priv, void __iomem *ptr,
288 u32 mask, u32 done, int usec)
289{
290 u32 result;
291
292 do {
293 result = isp1760_readl(ptr);
294 if (result == ~0)
295 return -ENODEV;
296 result &= mask;
297 if (result == done)
298 return 0;
299 udelay(1);
300 usec--;
301 } while (usec > 0);
302 return -ETIMEDOUT;
303}
304
305/* reset a non-running (STS_HALT == 1) controller */
306static int ehci_reset(struct isp1760_hcd *priv)
307{
308 int retval;
309 struct usb_hcd *hcd = priv_to_hcd(priv);
310 u32 command = isp1760_readl(hcd->regs + HC_USBCMD);
311
312 command |= CMD_RESET;
313 isp1760_writel(command, hcd->regs + HC_USBCMD);
314 hcd->state = HC_STATE_HALT;
315 priv->next_statechange = jiffies;
316 retval = handshake(priv, hcd->regs + HC_USBCMD,
317 CMD_RESET, 0, 250 * 1000);
318 return retval;
319}
320
321static void qh_destroy(struct isp1760_qh *qh)
322{
323 BUG_ON(!list_empty(&qh->qtd_list));
324 kmem_cache_free(qh_cachep, qh);
325}
326
327static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv,
328 gfp_t flags)
329{
330 struct isp1760_qh *qh;
331
332 qh = kmem_cache_zalloc(qh_cachep, flags);
333 if (!qh)
334 return qh;
335
336 INIT_LIST_HEAD(&qh->qtd_list);
337 qh->priv = priv;
338 return qh;
339}
340
341/* magic numbers that can affect system performance */
342#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
343#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
344#define EHCI_TUNE_RL_TT 0
345#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
346#define EHCI_TUNE_MULT_TT 1
347#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
348
349/* one-time init, only for memory state */
350static int priv_init(struct usb_hcd *hcd)
351{
352 struct isp1760_hcd *priv = hcd_to_priv(hcd);
353 u32 hcc_params;
354
355 spin_lock_init(&priv->lock);
356
357 /*
358 * hw default: 1K periodic list heads, one per frame.
359 * periodic_size can shrink by USBCMD update if hcc_params allows.
360 */
361 priv->periodic_size = DEFAULT_I_TDPS;
362
363 /* controllers may cache some of the periodic schedule ... */
364 hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS);
365 /* full frame cache */
366 if (HCC_ISOC_CACHE(hcc_params))
367 priv->i_thresh = 8;
368 else /* N microframes cached */
369 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
370
371 return 0;
372}
373
374static int isp1760_hc_setup(struct usb_hcd *hcd)
375{
376 struct isp1760_hcd *priv = hcd_to_priv(hcd);
377 int result;
3faefc88
NC		 378 u32 scratch, hwmode;
379
380 /* Setup HW Mode Control: This assumes a level active-low interrupt */
381 hwmode = HW_DATA_BUS_32BIT;
382
383 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
384 hwmode &= ~HW_DATA_BUS_32BIT;
385 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
386 hwmode |= HW_ANA_DIGI_OC;
387 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
388 hwmode |= HW_DACK_POL_HIGH;
389 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
390 hwmode |= HW_DREQ_POL_HIGH;
9da69c60
MH		 391 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
392 hwmode |= HW_INTR_HIGH_ACT;
393 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
394 hwmode |= HW_INTR_EDGE_TRIG;
3faefc88
NC		 395
396 /*
397 * We have to set this first in case we're in 16-bit mode.
398 * Write it twice to ensure correct upper bits if switching
399 * to 16-bit mode.
400 */
401 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
402 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
db11e47d
SS		 403
404 isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG);
3faefc88
NC		 405 /* Change bus pattern */
406 scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
db11e47d
SS		 407 scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG);
408 if (scratch != 0xdeadbabe) {
409 printk(KERN_ERR "ISP1760: Scratch test failed.\n");
410 return -ENODEV;
411 }
412
413 /* pre reset */
414 isp1760_init_regs(hcd);
415
416 /* reset */
417 isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG);
418 mdelay(100);
419
420 isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG);
421 mdelay(100);
422
423 result = ehci_reset(priv);
424 if (result)
425 return result;
426
427 /* Step 11 passed */
428
3faefc88
NC		 429 isp1760_info(priv, "bus width: %d, oc: %s\n",
430 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
431 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
432 "analog" : "digital");
db11e47d
SS		 433
434 /* ATL reset */
3faefc88 435 isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL);
db11e47d 436 mdelay(10);
3faefc88 437 isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
db11e47d 438
3faefc88
NC		 439 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG);
440 isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE);
441
442 /*
443 * PORT 1 Control register of the ISP1760 is the OTG control
42c65396
TH		 444 * register on ISP1761. Since there is no OTG or device controller
445 * support in this driver, we use port 1 as a "normal" USB host port on
446 * both chips.
3faefc88 447 */
42c65396
TH		 448 isp1760_writel(PORT1_POWER | PORT1_INIT2,
449 hcd->regs + HC_PORT1_CTRL);
450 mdelay(10);
db11e47d
SS		 451
452 priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS);
453
454 return priv_init(hcd);
455}
456
457static void isp1760_init_maps(struct usb_hcd *hcd)
458{
459 /*set last maps, for iso its only 1, else 32 tds bitmap*/
460 isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG);
461 isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG);
462 isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG);
463}
464
465static void isp1760_enable_interrupts(struct usb_hcd *hcd)
466{
467 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG);
468 isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
469 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG);
470 isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
471 isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG);
472 isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG);
473 /* step 23 passed */
474}
475
476static int isp1760_run(struct usb_hcd *hcd)
477{
478 struct isp1760_hcd *priv = hcd_to_priv(hcd);
479 int retval;
480 u32 temp;
481 u32 command;
482 u32 chipid;
483
484 hcd->uses_new_polling = 1;
485 hcd->poll_rh = 0;
486
487 hcd->state = HC_STATE_RUNNING;
488 isp1760_enable_interrupts(hcd);
489 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
3faefc88 490 isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
db11e47d
SS		 491
492 command = isp1760_readl(hcd->regs + HC_USBCMD);
493 command &= ~(CMD_LRESET|CMD_RESET);
494 command |= CMD_RUN;
495 isp1760_writel(command, hcd->regs + HC_USBCMD);
496
497 retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN,
498 250 * 1000);
499 if (retval)
500 return retval;
501
502 /*
503 * XXX
504 * Spec says to write FLAG_CF as last config action, priv code grabs
505 * the semaphore while doing so.
506 */
507 down_write(&ehci_cf_port_reset_rwsem);
508 isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG);
509
510 retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF,
511 250 * 1000);
512 up_write(&ehci_cf_port_reset_rwsem);
513 if (retval)
514 return retval;
515
516 chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
517 isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff,
518 chipid >> 16);
519
520 /* PTD Register Init Part 2, Step 28 */
521 /* enable INTs */
522 isp1760_init_maps(hcd);
523
524 /* GRR this is run-once init(), being done every time the HC starts.
525 * So long as they're part of class devices, we can't do it init()
526 * since the class device isn't created that early.
527 */
528 return 0;
529}
530
531static u32 base_to_chip(u32 base)
532{
533 return ((base - 0x400) >> 3);
534}
535
536static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh,
537 struct isp1760_qtd *qtd, struct urb *urb,
538 u32 payload, struct ptd *ptd)
539{
540 u32 dw0;
541 u32 dw1;
542 u32 dw2;
543 u32 dw3;
544 u32 maxpacket;
545 u32 multi;
546 u32 pid_code;
547 u32 rl = RL_COUNTER;
548 u32 nak = NAK_COUNTER;
549
550 /* according to 3.6.2, max packet len can not be > 0x400 */
551 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
552 multi = 1 + ((maxpacket >> 11) & 0x3);
553 maxpacket &= 0x7ff;
554
555 /* DW0 */
556 dw0 = PTD_VALID;
557 dw0 |= PTD_LENGTH(qtd->length);
558 dw0 |= PTD_MAXPACKET(maxpacket);
559 dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe));
560 dw1 = usb_pipeendpoint(urb->pipe) >> 1;
561
562 /* DW1 */
563 dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe));
564
565 pid_code = qtd->packet_type;
566 dw1 |= PTD_PID_TOKEN(pid_code);
567
568 if (usb_pipebulk(urb->pipe))
569 dw1 |= PTD_TRANS_BULK;
570 else if (usb_pipeint(urb->pipe))
571 dw1 |= PTD_TRANS_INT;
572
573 if (urb->dev->speed != USB_SPEED_HIGH) {
574 /* split transaction */
575
576 dw1 |= PTD_TRANS_SPLIT;
577 if (urb->dev->speed == USB_SPEED_LOW)
578 dw1 |= PTD_SE_USB_LOSPEED;
579
580 dw1 |= PTD_PORT_NUM(urb->dev->ttport);
581 dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum);
582
583 /* SE bit for Split INT transfers */
584 if (usb_pipeint(urb->pipe) &&
585 (urb->dev->speed == USB_SPEED_LOW))
586 dw1 |= 2 << 16;
587
588 dw3 = 0;
589 rl = 0;
590 nak = 0;
591 } else {
592 dw0 |= PTD_MULTI(multi);
593 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe))
594 dw3 = qh->ping;
595 else
596 dw3 = 0;
597 }
598 /* DW2 */
599 dw2 = 0;
600 dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload));
601 dw2 |= PTD_RL_CNT(rl);
602 dw3 |= PTD_NAC_CNT(nak);
603
604 /* DW3 */
605 if (usb_pipecontrol(urb->pipe))
606 dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
607 else
608 dw3 |= qh->toggle;
609
610
611 dw3 |= PTD_ACTIVE;
612 /* Cerr */
613 dw3 |= PTD_CERR(ERR_COUNTER);
614
615 memset(ptd, 0, sizeof(*ptd));
616
617 ptd->dw0 = cpu_to_le32(dw0);
618 ptd->dw1 = cpu_to_le32(dw1);
619 ptd->dw2 = cpu_to_le32(dw2);
620 ptd->dw3 = cpu_to_le32(dw3);
621}
622
623static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
624 struct isp1760_qtd *qtd, struct urb *urb,
625 u32 payload, struct ptd *ptd)
626{
627 u32 maxpacket;
628 u32 multi;
629 u32 numberofusofs;
630 u32 i;
631 u32 usofmask, usof;
632 u32 period;
633
634 maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
635 multi = 1 + ((maxpacket >> 11) & 0x3);
636 maxpacket &= 0x7ff;
637 /* length of the data per uframe */
638 maxpacket = multi * maxpacket;
639
640 numberofusofs = urb->transfer_buffer_length / maxpacket;
641 if (urb->transfer_buffer_length % maxpacket)
642 numberofusofs += 1;
643
644 usofmask = 1;
645 usof = 0;
646 for (i = 0; i < numberofusofs; i++) {
647 usof |= usofmask;
648 usofmask <<= 1;
649 }
650
651 if (urb->dev->speed != USB_SPEED_HIGH) {
652 /* split */
551509d2 653 ptd->dw5 = cpu_to_le32(0x1c);
db11e47d
SS		 654
655 if (qh->period >= 32)
656 period = qh->period / 2;
657 else
658 period = qh->period;
659
660 } else {
661
662 if (qh->period >= 8)
663 period = qh->period/8;
664 else
665 period = qh->period;
666
667 if (period >= 32)
668 period = 16;
669
670 if (qh->period >= 8) {
671 /* millisecond period */
672 period = (period << 3);
673 } else {
674 /* usof based tranmsfers */
675 /* minimum 4 usofs */
676 usof = 0x11;
677 }
678 }
679
680 ptd->dw2 |= cpu_to_le32(period);
681 ptd->dw4 = cpu_to_le32(usof);
682}
683
684static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
685 struct isp1760_qtd *qtd, struct urb *urb,
686 u32 payload, struct ptd *ptd)
687{
688 transform_into_atl(priv, qh, qtd, urb, payload, ptd);
689 transform_add_int(priv, qh, qtd, urb, payload, ptd);
690}
691
692static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
693 u32 token)
694{
695 int count;
696
697 qtd->data_buffer = databuffer;
698 qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
699 qtd->toggle = GET_DATA_TOGGLE(token);
700
701 if (len > HC_ATL_PL_SIZE)
702 count = HC_ATL_PL_SIZE;
703 else
704 count = len;
705
706 qtd->length = count;
707 return count;
708}
709
710static int check_error(struct ptd *ptd)
711{
712 int error = 0;
713 u32 dw3;
714
715 dw3 = le32_to_cpu(ptd->dw3);
0954e1c2 716 if (dw3 & DW3_HALT_BIT) {
db11e47d
SS		 717 error = -EPIPE;
718
0954e1c2
AV		 719 if (dw3 & DW3_ERROR_BIT)
720 pr_err("error bit is set in DW3\n");
db11e47d
SS		 721 }
722
723 if (dw3 & DW3_QTD_ACTIVE) {
724 printk(KERN_ERR "transfer active bit is set DW3\n");
725 printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf,
726 (le32_to_cpu(ptd->dw2) >> 25) & 0xf);
727 }
728
729 return error;
730}
731
732static void check_int_err_status(u32 dw4)
733{
734 u32 i;
735
736 dw4 >>= 8;
737
738 for (i = 0; i < 8; i++) {
739 switch (dw4 & 0x7) {
740 case INT_UNDERRUN:
741 printk(KERN_ERR "ERROR: under run , %d\n", i);
742 break;
743
744 case INT_EXACT:
745 printk(KERN_ERR "ERROR: transaction error, %d\n", i);
746 break;
747
748 case INT_BABBLE:
749 printk(KERN_ERR "ERROR: babble error, %d\n", i);
750 break;
751 }
752 dw4 >>= 3;
753 }
754}
755
756static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv,
757 u32 payload)
758{
759 u32 token;
760 struct usb_hcd *hcd = priv_to_hcd(priv);
761
762 token = qtd->packet_type;
763
764 if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) {
765 switch (token) {
766 case IN_PID:
767 break;
768 case OUT_PID:
769 case SETUP_PID:
770 priv_write_copy(priv, qtd->data_buffer,
771 hcd->regs + payload,
772 qtd->length);
773 }
774 }
775}
776
777static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload,
778 struct isp1760_hcd *priv, struct isp1760_qh *qh,
779 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
780{
781 struct ptd ptd;
782 struct usb_hcd *hcd = priv_to_hcd(priv);
783
784 transform_into_atl(priv, qh, qtd, urb, payload, &ptd);
785 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd));
786 enqueue_one_qtd(qtd, priv, payload);
787
788 priv->atl_ints[slot].urb = urb;
789 priv->atl_ints[slot].qh = qh;
790 priv->atl_ints[slot].qtd = qtd;
791 priv->atl_ints[slot].data_buffer = qtd->data_buffer;
792 priv->atl_ints[slot].payload = payload;
793 qtd->status |= URB_ENQUEUED | URB_TYPE_ATL;
794 qtd->status |= slot << 16;
795}
796
797static void enqueue_one_int_qtd(u32 int_regs, u32 payload,
798 struct isp1760_hcd *priv, struct isp1760_qh *qh,
799 struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
800{
801 struct ptd ptd;
802 struct usb_hcd *hcd = priv_to_hcd(priv);
803
804 transform_into_int(priv, qh, qtd, urb, payload, &ptd);
805 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd));
806 enqueue_one_qtd(qtd, priv, payload);
807
808 priv->int_ints[slot].urb = urb;
809 priv->int_ints[slot].qh = qh;
810 priv->int_ints[slot].qtd = qtd;
811 priv->int_ints[slot].data_buffer = qtd->data_buffer;
812 priv->int_ints[slot].payload = payload;
813 qtd->status |= URB_ENQUEUED | URB_TYPE_INT;
814 qtd->status |= slot << 16;
815}
816
473bca94
AB		 817static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
818 struct isp1760_qtd *qtd)
db11e47d
SS		 819{
820 struct isp1760_hcd *priv = hcd_to_priv(hcd);
821 u32 skip_map, or_map;
822 u32 queue_entry;
823 u32 slot;
824 u32 atl_regs, payload;
825 u32 buffstatus;
826
e6bdfe36
CM		 827 /*
828 * When this function is called from the interrupt handler to enqueue
829 * a follow-up packet, the SKIP register gets written and read back
830 * almost immediately. With ISP1761, this register requires a delay of
831 * 195ns between a write and subsequent read (see section 15.1.1.3).
832 */
833 ndelay(195);
db11e47d
SS		 834 skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
835
836 BUG_ON(!skip_map);
837 slot = __ffs(skip_map);
838 queue_entry = 1 << slot;
839
840 atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd);
841
842 payload = alloc_mem(priv, qtd->length);
843
844 enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd);
845
846 or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
847 or_map |= queue_entry;
848 isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
849
850 skip_map &= ~queue_entry;
851 isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
852
853 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
854 buffstatus |= ATL_BUFFER;
855 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
856}
857
473bca94
AB		 858static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
859 struct isp1760_qtd *qtd)
db11e47d
SS		 860{
861 struct isp1760_hcd *priv = hcd_to_priv(hcd);
862 u32 skip_map, or_map;
863 u32 queue_entry;
864 u32 slot;
865 u32 int_regs, payload;
866 u32 buffstatus;
867
e6bdfe36
CM		 868 /*
869 * When this function is called from the interrupt handler to enqueue
870 * a follow-up packet, the SKIP register gets written and read back
871 * almost immediately. With ISP1761, this register requires a delay of
872 * 195ns between a write and subsequent read (see section 15.1.1.3).
873 */
874 ndelay(195);
db11e47d
SS		 875 skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG);
876
877 BUG_ON(!skip_map);
878 slot = __ffs(skip_map);
879 queue_entry = 1 << slot;
880
881 int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd);
882
883 payload = alloc_mem(priv, qtd->length);
884
885 enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd);
886
887 or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG);
888 or_map |= queue_entry;
889 isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
890
891 skip_map &= ~queue_entry;
892 isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG);
893
894 buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
895 buffstatus |= INT_BUFFER;
896 isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
897}
898
899static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status)
900__releases(priv->lock)
901__acquires(priv->lock)
902{
903 if (!urb->unlinked) {
904 if (status == -EINPROGRESS)
905 status = 0;
906 }
907
db8516f6
CM		 908 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
909 void *ptr;
910 for (ptr = urb->transfer_buffer;
911 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
912 ptr += PAGE_SIZE)
913 flush_dcache_page(virt_to_page(ptr));
914 }
915
db11e47d
SS		 916 /* complete() can reenter this HCD */
917 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
918 spin_unlock(&priv->lock);
919 usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status);
920 spin_lock(&priv->lock);
921}
922
923static void isp1760_qtd_free(struct isp1760_qtd *qtd)
924{
925 kmem_cache_free(qtd_cachep, qtd);
926}
927
928static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd)
929{
930 struct isp1760_qtd *tmp_qtd;
931
932 tmp_qtd = qtd->hw_next;
933 list_del(&qtd->qtd_list);
934 isp1760_qtd_free(qtd);
935 return tmp_qtd;
936}
937
938/*
939 * Remove this QTD from the QH list and free its memory. If this QTD
940 * isn't the last one than remove also his successor(s).
941 * Returns the QTD which is part of an new URB and should be enqueued.
942 */
943static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd)
944{
945 struct isp1760_qtd *tmp_qtd;
946 int last_one;
947
948 do {
949 tmp_qtd = qtd->hw_next;
950 last_one = qtd->status & URB_COMPLETE_NOTIFY;
951 list_del(&qtd->qtd_list);
952 isp1760_qtd_free(qtd);
953 qtd = tmp_qtd;
954 } while (!last_one && qtd);
955
956 return qtd;
957}
958
959static void do_atl_int(struct usb_hcd *usb_hcd)
960{
961 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
962 u32 done_map, skip_map;
963 struct ptd ptd;
964 struct urb *urb = NULL;
965 u32 atl_regs_base;
966 u32 atl_regs;
967 u32 queue_entry;
968 u32 payload;
969 u32 length;
970 u32 or_map;
971 u32 status = -EINVAL;
972 int error;
973 struct isp1760_qtd *qtd;
974 struct isp1760_qh *qh;
975 u32 rl;
976 u32 nakcount;
977
978 done_map = isp1760_readl(usb_hcd->regs +
979 HC_ATL_PTD_DONEMAP_REG);
980 skip_map = isp1760_readl(usb_hcd->regs +
981 HC_ATL_PTD_SKIPMAP_REG);
982
983 or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
984 or_map &= ~done_map;
985 isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
986
987 atl_regs_base = ATL_REGS_OFFSET;
988 while (done_map) {
989 u32 dw1;
990 u32 dw2;
991 u32 dw3;
992
993 status = 0;
994
995 queue_entry = __ffs(done_map);
996 done_map &= ~(1 << queue_entry);
997 skip_map |= 1 << queue_entry;
998
999 atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd);
1000
1001 urb = priv->atl_ints[queue_entry].urb;
1002 qtd = priv->atl_ints[queue_entry].qtd;
1003 qh = priv->atl_ints[queue_entry].qh;
1004 payload = priv->atl_ints[queue_entry].payload;
1005
1006 if (!qh) {
1007 printk(KERN_ERR "qh is 0\n");
1008 continue;
1009 }
3f02a957
ES		 1010 isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs +
1011 HC_MEMORY_REG);
1012 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1013 HC_MEMORY_REG);
1014 /*
1015 * write bank1 address twice to ensure the 90ns delay (time
1016 * between BANK0 write and the priv_read_copy() call is at
380ec678 1017 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns)
3f02a957
ES		 1018 */
1019 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1020 HC_MEMORY_REG);
1021
1022 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs +
1023 ISP_BANK(0), sizeof(ptd));
db11e47d
SS		 1024
1025 dw1 = le32_to_cpu(ptd.dw1);
1026 dw2 = le32_to_cpu(ptd.dw2);
1027 dw3 = le32_to_cpu(ptd.dw3);
1028 rl = (dw2 >> 25) & 0x0f;
1029 nakcount = (dw3 >> 19) & 0xf;
1030
1031 /* Transfer Error, *but* active and no HALT -> reload */
1032 if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) &&
1033 !(dw3 & DW3_HALT_BIT)) {
1034
1035 /* according to ppriv code, we have to
1036 * reload this one if trasfered bytes != requested bytes
1037 * else act like everything went smooth..
1038 * XXX This just doesn't feel right and hasn't
1039 * triggered so far.
1040 */
1041
1042 length = PTD_XFERRED_LENGTH(dw3);
1043 printk(KERN_ERR "Should reload now.... transfered %d "
1044 "of %zu\n", length, qtd->length);
1045 BUG();
1046 }
1047
1048 if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) {
1049 u32 buffstatus;
1050
c0d74142 1051 /*
db11e47d
SS		 1052 * NAKs are handled in HW by the chip. Usually if the
1053 * device is not able to send data fast enough.
c0d74142 1054 * This happens mostly on slower hardware.
db11e47d 1055 */
c0d74142 1056 printk(KERN_NOTICE "Reloading ptd %p/%p... qh %p read: "
22026473 1057 "%d of %zu done: %08x cur: %08x\n", qtd,
db11e47d
SS		 1058 urb, qh, PTD_XFERRED_LENGTH(dw3),
1059 qtd->length, done_map,
1060 (1 << queue_entry));
1061
1062 /* RL counter = ERR counter */
1063 dw3 &= ~(0xf << 19);
1064 dw3 |= rl << 19;
1065 dw3 &= ~(3 << (55 - 32));
1066 dw3 |= ERR_COUNTER << (55 - 32);
1067
1068 /*
1069 * It is not needed to write skip map back because it
1070 * is unchanged. Just make sure that this entry is
1071 * unskipped once it gets written to the HW.
1072 */
1073 skip_map &= ~(1 << queue_entry);
1074 or_map = isp1760_readl(usb_hcd->regs +
1075 HC_ATL_IRQ_MASK_OR_REG);
1076 or_map |= 1 << queue_entry;
1077 isp1760_writel(or_map, usb_hcd->regs +
1078 HC_ATL_IRQ_MASK_OR_REG);
1079
1080 ptd.dw3 = cpu_to_le32(dw3);
1081 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
1082 atl_regs, sizeof(ptd));
1083
551509d2 1084 ptd.dw0 |= cpu_to_le32(PTD_VALID);
db11e47d
SS		 1085 priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
1086 atl_regs, sizeof(ptd));
1087
1088 buffstatus = isp1760_readl(usb_hcd->regs +
1089 HC_BUFFER_STATUS_REG);
1090 buffstatus |= ATL_BUFFER;
1091 isp1760_writel(buffstatus, usb_hcd->regs +
1092 HC_BUFFER_STATUS_REG);
1093 continue;
1094 }
1095
1096 error = check_error(&ptd);
1097 if (error) {
1098 status = error;
1099 priv->atl_ints[queue_entry].qh->toggle = 0;
1100 priv->atl_ints[queue_entry].qh->ping = 0;
1101 urb->status = -EPIPE;
1102
1103#if 0
1104 printk(KERN_ERR "Error in %s().\n", __func__);
1105 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1106 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1107 "%08x dw7: %08x\n",
1108 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1109 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1110#endif
1111 } else {
1112 if (usb_pipetype(urb->pipe) == PIPE_BULK) {
1113 priv->atl_ints[queue_entry].qh->toggle = dw3 &
1114 (1 << 25);
1115 priv->atl_ints[queue_entry].qh->ping = dw3 &
1116 (1 << 26);
1117 }
1118 }
1119
1120 length = PTD_XFERRED_LENGTH(dw3);
1121 if (length) {
1122 switch (DW1_GET_PID(dw1)) {
1123 case IN_PID:
1124 priv_read_copy(priv,
1125 priv->atl_ints[queue_entry].data_buffer,
3f02a957 1126 usb_hcd->regs + payload + ISP_BANK(1),
db11e47d
SS		 1127 length);
1128
1129 case OUT_PID:
1130
1131 urb->actual_length += length;
1132
1133 case SETUP_PID:
1134 break;
1135 }
1136 }
1137
1138 priv->atl_ints[queue_entry].data_buffer = NULL;
1139 priv->atl_ints[queue_entry].urb = NULL;
1140 priv->atl_ints[queue_entry].qtd = NULL;
1141 priv->atl_ints[queue_entry].qh = NULL;
1142
1143 free_mem(priv, payload);
1144
1145 isp1760_writel(skip_map, usb_hcd->regs +
1146 HC_ATL_PTD_SKIPMAP_REG);
1147
1148 if (urb->status == -EPIPE) {
1149 /* HALT was received */
1150
1151 qtd = clean_up_qtdlist(qtd);
1152 isp1760_urb_done(priv, urb, urb->status);
1153
1154 } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) {
1155 /* short BULK received */
1156
db11e47d
SS		 1157 if (urb->transfer_flags & URB_SHORT_NOT_OK) {
1158 urb->status = -EREMOTEIO;
7839b516
SS		 1159 isp1760_dbg(priv, "short bulk, %d instead %zu "
1160 "with URB_SHORT_NOT_OK flag.\n",
1161 length, qtd->length);
db11e47d
SS		 1162 }
1163
1164 if (urb->status == -EINPROGRESS)
1165 urb->status = 0;
1166
1167 qtd = clean_up_qtdlist(qtd);
1168
1169 isp1760_urb_done(priv, urb, urb->status);
1170
1171 } else if (qtd->status & URB_COMPLETE_NOTIFY) {
1172 /* that was the last qtd of that URB */
1173
1174 if (urb->status == -EINPROGRESS)
1175 urb->status = 0;
1176
1177 qtd = clean_this_qtd(qtd);
1178 isp1760_urb_done(priv, urb, urb->status);
1179
1180 } else {
1181 /* next QTD of this URB */
1182
1183 qtd = clean_this_qtd(qtd);
1184 BUG_ON(!qtd);
1185 }
1186
1187 if (qtd)
1188 enqueue_an_ATL_packet(usb_hcd, qh, qtd);
1189
1190 skip_map = isp1760_readl(usb_hcd->regs +
1191 HC_ATL_PTD_SKIPMAP_REG);
1192 }
1193}
1194
1195static void do_intl_int(struct usb_hcd *usb_hcd)
1196{
1197 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
1198 u32 done_map, skip_map;
1199 struct ptd ptd;
1200 struct urb *urb = NULL;
1201 u32 int_regs;
1202 u32 int_regs_base;
1203 u32 payload;
1204 u32 length;
1205 u32 or_map;
1206 int error;
1207 u32 queue_entry;
1208 struct isp1760_qtd *qtd;
1209 struct isp1760_qh *qh;
1210
1211 done_map = isp1760_readl(usb_hcd->regs +
1212 HC_INT_PTD_DONEMAP_REG);
1213 skip_map = isp1760_readl(usb_hcd->regs +
1214 HC_INT_PTD_SKIPMAP_REG);
1215
1216 or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
1217 or_map &= ~done_map;
1218 isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
1219
1220 int_regs_base = INT_REGS_OFFSET;
1221
1222 while (done_map) {
1223 u32 dw1;
1224 u32 dw3;
1225
1226 queue_entry = __ffs(done_map);
1227 done_map &= ~(1 << queue_entry);
1228 skip_map |= 1 << queue_entry;
1229
1230 int_regs = int_regs_base + queue_entry * sizeof(struct ptd);
1231 urb = priv->int_ints[queue_entry].urb;
1232 qtd = priv->int_ints[queue_entry].qtd;
1233 qh = priv->int_ints[queue_entry].qh;
1234 payload = priv->int_ints[queue_entry].payload;
1235
1236 if (!qh) {
1237 printk(KERN_ERR "(INT) qh is 0\n");
1238 continue;
1239 }
1240
3f02a957
ES		 1241 isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs +
1242 HC_MEMORY_REG);
1243 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1244 HC_MEMORY_REG);
1245 /*
1246 * write bank1 address twice to ensure the 90ns delay (time
1247 * between BANK0 write and the priv_read_copy() call is at
1248 * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
1249 */
1250 isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
1251 HC_MEMORY_REG);
1252
1253 priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs +
1254 ISP_BANK(0), sizeof(ptd));
db11e47d
SS		 1255 dw1 = le32_to_cpu(ptd.dw1);
1256 dw3 = le32_to_cpu(ptd.dw3);
1257 check_int_err_status(le32_to_cpu(ptd.dw4));
1258
1259 error = check_error(&ptd);
1260 if (error) {
1261#if 0
1262 printk(KERN_ERR "Error in %s().\n", __func__);
1263 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1264 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1265 "%08x dw7: %08x\n",
1266 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1267 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1268#endif
1269 urb->status = -EPIPE;
1270 priv->int_ints[queue_entry].qh->toggle = 0;
1271 priv->int_ints[queue_entry].qh->ping = 0;
1272
1273 } else {
1274 priv->int_ints[queue_entry].qh->toggle =
1275 dw3 & (1 << 25);
1276 priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26);
1277 }
1278
1279 if (urb->dev->speed != USB_SPEED_HIGH)
1280 length = PTD_XFERRED_LENGTH_LO(dw3);
1281 else
1282 length = PTD_XFERRED_LENGTH(dw3);
1283
1284 if (length) {
1285 switch (DW1_GET_PID(dw1)) {
1286 case IN_PID:
1287 priv_read_copy(priv,
1288 priv->int_ints[queue_entry].data_buffer,
3f02a957 1289 usb_hcd->regs + payload + ISP_BANK(1),
db11e47d
SS		 1290 length);
1291 case OUT_PID:
1292
1293 urb->actual_length += length;
1294
1295 case SETUP_PID:
1296 break;
1297 }
1298 }
1299
1300 priv->int_ints[queue_entry].data_buffer = NULL;
1301 priv->int_ints[queue_entry].urb = NULL;
1302 priv->int_ints[queue_entry].qtd = NULL;
1303 priv->int_ints[queue_entry].qh = NULL;
1304
1305 isp1760_writel(skip_map, usb_hcd->regs +
1306 HC_INT_PTD_SKIPMAP_REG);
1307 free_mem(priv, payload);
1308
1309 if (urb->status == -EPIPE) {
1310 /* HALT received */
1311
1312 qtd = clean_up_qtdlist(qtd);
1313 isp1760_urb_done(priv, urb, urb->status);
1314
1315 } else if (qtd->status & URB_COMPLETE_NOTIFY) {
1316
1317 if (urb->status == -EINPROGRESS)
1318 urb->status = 0;
1319
1320 qtd = clean_this_qtd(qtd);
1321 isp1760_urb_done(priv, urb, urb->status);
1322
1323 } else {
1324 /* next QTD of this URB */
1325
1326 qtd = clean_this_qtd(qtd);
1327 BUG_ON(!qtd);
1328 }
1329
1330 if (qtd)
1331 enqueue_an_INT_packet(usb_hcd, qh, qtd);
1332
1333 skip_map = isp1760_readl(usb_hcd->regs +
1334 HC_INT_PTD_SKIPMAP_REG);
1335 }
1336}
1337
1338#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1339static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
1340 gfp_t flags)
1341{
1342 struct isp1760_qh *qh;
1343 int is_input, type;
1344
1345 qh = isp1760_qh_alloc(priv, flags);
1346 if (!qh)
1347 return qh;
1348
1349 /*
1350 * init endpoint/device data for this QH
1351 */
1352 is_input = usb_pipein(urb->pipe);
1353 type = usb_pipetype(urb->pipe);
1354
1355 if (type == PIPE_INTERRUPT) {
1356
1357 if (urb->dev->speed == USB_SPEED_HIGH) {
1358
1359 qh->period = urb->interval >> 3;
1360 if (qh->period == 0 && urb->interval != 1) {
1361 /* NOTE interval 2 or 4 uframes could work.
1362 * But interval 1 scheduling is simpler, and
1363 * includes high bandwidth.
1364 */
1365 printk(KERN_ERR "intr period %d uframes, NYET!",
1366 urb->interval);
1367 qh_destroy(qh);
1368 return NULL;
1369 }
1370 } else {
1371 qh->period = urb->interval;
1372 }
1373 }
1374
1375 /* support for tt scheduling, and access to toggles */
1376 qh->dev = urb->dev;
1377
1378 if (!usb_pipecontrol(urb->pipe))
1379 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1380 1);
1381 return qh;
1382}
1383
1384/*
1385 * For control/bulk/interrupt, return QH with these TDs appended.
1386 * Allocates and initializes the QH if necessary.
1387 * Returns null if it can't allocate a QH it needs to.
1388 * If the QH has TDs (urbs) already, that's great.
1389 */
1390static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv,
1391 struct urb *urb, struct list_head *qtd_list, int epnum,
1392 void **ptr)
1393{
1394 struct isp1760_qh *qh;
1395 struct isp1760_qtd *qtd;
1396 struct isp1760_qtd *prev_qtd;
1397
1398 qh = (struct isp1760_qh *)*ptr;
1399 if (!qh) {
1400 /* can't sleep here, we have priv->lock... */
1401 qh = qh_make(priv, urb, GFP_ATOMIC);
1402 if (!qh)
1403 return qh;
1404 *ptr = qh;
1405 }
1406
1407 qtd = list_entry(qtd_list->next, struct isp1760_qtd,
1408 qtd_list);
1409 if (!list_empty(&qh->qtd_list))
1410 prev_qtd = list_entry(qh->qtd_list.prev,
1411 struct isp1760_qtd, qtd_list);
1412 else
1413 prev_qtd = NULL;
1414
1415 list_splice(qtd_list, qh->qtd_list.prev);
1416 if (prev_qtd) {
1417 BUG_ON(prev_qtd->hw_next);
1418 prev_qtd->hw_next = qtd;
1419 }
1420
1421 urb->hcpriv = qh;
1422 return qh;
1423}
1424
1425static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb,
1426 struct list_head *qtd_list)
1427{
1428 struct list_head *entry, *temp;
1429
1430 list_for_each_safe(entry, temp, qtd_list) {
1431 struct isp1760_qtd *qtd;
1432
1433 qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
1434 list_del(&qtd->qtd_list);
1435 isp1760_qtd_free(qtd);
1436 }
1437}
1438
1439static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
1440 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1441{
1442 struct isp1760_qtd *qtd;
1443 int epnum;
1444 unsigned long flags;
1445 struct isp1760_qh *qh = NULL;
1446 int rc;
1447 int qh_busy;
1448
1449 qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
1450 epnum = urb->ep->desc.bEndpointAddress;
1451
1452 spin_lock_irqsave(&priv->lock, flags);
1453 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &priv_to_hcd(priv)->flags)) {
1454 rc = -ESHUTDOWN;
1455 goto done;
1456 }
1457 rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb);
1458 if (rc)
1459 goto done;
1460
1461 qh = urb->ep->hcpriv;
1462 if (qh)
1463 qh_busy = !list_empty(&qh->qtd_list);
1464 else
1465 qh_busy = 0;
1466
1467 qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv);
1468 if (!qh) {
1469 usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
1470 rc = -ENOMEM;
1471 goto done;
1472 }
1473
1474 if (!qh_busy)
1475 p(priv_to_hcd(priv), qh, qtd);
1476
1477done:
1478 spin_unlock_irqrestore(&priv->lock, flags);
1479 if (!qh)
1480 qtd_list_free(priv, urb, qtd_list);
1481 return rc;
1482}
1483
1484static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv,
1485 gfp_t flags)
1486{
1487 struct isp1760_qtd *qtd;
1488
1489 qtd = kmem_cache_zalloc(qtd_cachep, flags);
1490 if (qtd)
1491 INIT_LIST_HEAD(&qtd->qtd_list);
1492
1493 return qtd;
1494}
1495
1496/*
1497 * create a list of filled qtds for this URB; won't link into qh.
1498 */
1499static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
1500 struct urb *urb, struct list_head *head, gfp_t flags)
1501{
1502 struct isp1760_qtd *qtd, *qtd_prev;
1503 void *buf;
1504 int len, maxpacket;
1505 int is_input;
1506 u32 token;
1507
1508 /*
1509 * URBs map to sequences of QTDs: one logical transaction
1510 */
1511 qtd = isp1760_qtd_alloc(priv, flags);
1512 if (!qtd)
1513 return NULL;
1514
1515 list_add_tail(&qtd->qtd_list, head);
1516 qtd->urb = urb;
1517 urb->status = -EINPROGRESS;
1518
1519 token = 0;
1520 /* for split transactions, SplitXState initialized to zero */
1521
1522 len = urb->transfer_buffer_length;
1523 is_input = usb_pipein(urb->pipe);
1524 if (usb_pipecontrol(urb->pipe)) {
1525 /* SETUP pid */
1526 qtd_fill(qtd, urb->setup_packet,
1527 sizeof(struct usb_ctrlrequest),
1528 token | SETUP_PID);
1529
1530 /* ... and always at least one more pid */
1531 token ^= DATA_TOGGLE;
1532 qtd_prev = qtd;
1533 qtd = isp1760_qtd_alloc(priv, flags);
1534 if (!qtd)
1535 goto cleanup;
1536 qtd->urb = urb;
1537 qtd_prev->hw_next = qtd;
1538 list_add_tail(&qtd->qtd_list, head);
1539
1540 /* for zero length DATA stages, STATUS is always IN */
1541 if (len == 0)
1542 token |= IN_PID;
1543 }
1544
1545 /*
1546 * data transfer stage: buffer setup
1547 */
1548 buf = urb->transfer_buffer;
1549
1550 if (is_input)
1551 token |= IN_PID;
1552 else
1553 token |= OUT_PID;
1554
1555 maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1556
1557 /*
1558 * buffer gets wrapped in one or more qtds;
1559 * last one may be "short" (including zero len)
1560 * and may serve as a control status ack
1561 */
1562 for (;;) {
1563 int this_qtd_len;
1564
1565 if (!buf && len) {
1566 /* XXX This looks like usb storage / SCSI bug */
1567 printk(KERN_ERR "buf is null, dma is %08lx len is %d\n",
1568 (long unsigned)urb->transfer_dma, len);
1569 WARN_ON(1);
1570 }
1571
1572 this_qtd_len = qtd_fill(qtd, buf, len, token);
1573 len -= this_qtd_len;
1574 buf += this_qtd_len;
1575
1576 /* qh makes control packets use qtd toggle; maybe switch it */
1577 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1578 token ^= DATA_TOGGLE;
1579
1580 if (len <= 0)
1581 break;
1582
1583 qtd_prev = qtd;
1584 qtd = isp1760_qtd_alloc(priv, flags);
1585 if (!qtd)
1586 goto cleanup;
1587 qtd->urb = urb;
1588 qtd_prev->hw_next = qtd;
1589 list_add_tail(&qtd->qtd_list, head);
1590 }
1591
1592 /*
1593 * control requests may need a terminating data "status" ack;
1594 * bulk ones may need a terminating short packet (zero length).
1595 */
1596 if (urb->transfer_buffer_length != 0) {
1597 int one_more = 0;
1598
1599 if (usb_pipecontrol(urb->pipe)) {
1600 one_more = 1;
1601 /* "in" <--> "out" */
1602 token ^= IN_PID;
1603 /* force DATA1 */
1604 token |= DATA_TOGGLE;
1605 } else if (usb_pipebulk(urb->pipe)
1606 && (urb->transfer_flags & URB_ZERO_PACKET)
1607 && !(urb->transfer_buffer_length % maxpacket)) {
1608 one_more = 1;
1609 }
1610 if (one_more) {
1611 qtd_prev = qtd;
1612 qtd = isp1760_qtd_alloc(priv, flags);
1613 if (!qtd)
1614 goto cleanup;
1615 qtd->urb = urb;
1616 qtd_prev->hw_next = qtd;
1617 list_add_tail(&qtd->qtd_list, head);
1618
1619 /* never any data in such packets */
1620 qtd_fill(qtd, NULL, 0, token);
1621 }
1622 }
1623
1624 qtd->status = URB_COMPLETE_NOTIFY;
1625 return head;
1626
1627cleanup:
1628 qtd_list_free(priv, urb, head);
1629 return NULL;
1630}
1631
1632static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1633 gfp_t mem_flags)
1634{
1635 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1636 struct list_head qtd_list;
1637 packet_enqueue *pe;
1638
1639 INIT_LIST_HEAD(&qtd_list);
1640
1641 switch (usb_pipetype(urb->pipe)) {
1642 case PIPE_CONTROL:
1643 case PIPE_BULK:
1644
1645 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1646 return -ENOMEM;
1647 pe = enqueue_an_ATL_packet;
1648 break;
1649
1650 case PIPE_INTERRUPT:
1651 if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
1652 return -ENOMEM;
1653 pe = enqueue_an_INT_packet;
1654 break;
1655
1656 case PIPE_ISOCHRONOUS:
1657 printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n");
1658 default:
1659 return -EPIPE;
1660 }
1661
a36c27df 1662 return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe);
db11e47d
SS		 1663}
1664
1665static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
1666 int status)
1667{
1668 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1669 struct inter_packet_info *ints;
1670 u32 i;
1671 u32 reg_base, or_reg, skip_reg;
d249afdd 1672 unsigned long flags;
db11e47d 1673 struct ptd ptd;
0afb20e0 1674 packet_enqueue *pe;
db11e47d
SS		 1675
1676 switch (usb_pipetype(urb->pipe)) {
1677 case PIPE_ISOCHRONOUS:
1678 return -EPIPE;
1679 break;
1680
1681 case PIPE_INTERRUPT:
1682 ints = priv->int_ints;
1683 reg_base = INT_REGS_OFFSET;
1684 or_reg = HC_INT_IRQ_MASK_OR_REG;
1685 skip_reg = HC_INT_PTD_SKIPMAP_REG;
0afb20e0 1686 pe = enqueue_an_INT_packet;
db11e47d
SS		 1687 break;
1688
1689 default:
1690 ints = priv->atl_ints;
1691 reg_base = ATL_REGS_OFFSET;
1692 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1693 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
0afb20e0 1694 pe = enqueue_an_ATL_packet;
db11e47d
SS		 1695 break;
1696 }
1697
1698 memset(&ptd, 0, sizeof(ptd));
1699 spin_lock_irqsave(&priv->lock, flags);
1700
1701 for (i = 0; i < 32; i++) {
1702 if (ints->urb == urb) {
1703 u32 skip_map;
1704 u32 or_map;
1705 struct isp1760_qtd *qtd;
0afb20e0 1706 struct isp1760_qh *qh = ints->qh;
db11e47d
SS		 1707
1708 skip_map = isp1760_readl(hcd->regs + skip_reg);
1709 skip_map |= 1 << i;
1710 isp1760_writel(skip_map, hcd->regs + skip_reg);
1711
1712 or_map = isp1760_readl(hcd->regs + or_reg);
1713 or_map &= ~(1 << i);
1714 isp1760_writel(or_map, hcd->regs + or_reg);
1715
1716 priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base
1717 + i * sizeof(ptd), sizeof(ptd));
1718 qtd = ints->qtd;
0afb20e0 1719 qtd = clean_up_qtdlist(qtd);
db11e47d
SS		 1720
1721 free_mem(priv, ints->payload);
1722
1723 ints->urb = NULL;
1724 ints->qh = NULL;
1725 ints->qtd = NULL;
1726 ints->data_buffer = NULL;
1727 ints->payload = 0;
1728
1729 isp1760_urb_done(priv, urb, status);
0afb20e0
WF		 1730 if (qtd)
1731 pe(hcd, qh, qtd);
db11e47d 1732 break;
0afb20e0
WF		 1733
1734 } else if (ints->qtd) {
1735 struct isp1760_qtd *qtd, *prev_qtd = ints->qtd;
1736
1737 for (qtd = ints->qtd->hw_next; qtd; qtd = qtd->hw_next) {
1738 if (qtd->urb == urb) {
1739 prev_qtd->hw_next = clean_up_qtdlist(qtd);
1740 isp1760_urb_done(priv, urb, status);
1741 break;
1742 }
1743 prev_qtd = qtd;
1744 }
1745 /* we found the urb before the end of the list */
1746 if (qtd)
1747 break;
db11e47d
SS		 1748 }
1749 ints++;
1750 }
1751
1752 spin_unlock_irqrestore(&priv->lock, flags);
1753 return 0;
1754}
1755
1756static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd)
1757{
1758 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
1759 u32 imask;
1760 irqreturn_t irqret = IRQ_NONE;
1761
1762 spin_lock(&priv->lock);
1763
1764 if (!(usb_hcd->state & HC_STATE_RUNNING))
1765 goto leave;
1766
1767 imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG);
1768 if (unlikely(!imask))
1769 goto leave;
1770
1771 isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG);
1772 if (imask & HC_ATL_INT)
1773 do_atl_int(usb_hcd);
1774
1775 if (imask & HC_INTL_INT)
1776 do_intl_int(usb_hcd);
1777
1778 irqret = IRQ_HANDLED;
1779leave:
1780 spin_unlock(&priv->lock);
1781 return irqret;
1782}
1783
1784static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1785{
1786 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1787 u32 temp, status = 0;
1788 u32 mask;
1789 int retval = 1;
1790 unsigned long flags;
1791
1792 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1793 if (!HC_IS_RUNNING(hcd->state))
1794 return 0;
1795
1796 /* init status to no-changes */
1797 buf[0] = 0;
1798 mask = PORT_CSC;
1799
1800 spin_lock_irqsave(&priv->lock, flags);
1801 temp = isp1760_readl(hcd->regs + HC_PORTSC1);
1802
1803 if (temp & PORT_OWNER) {
1804 if (temp & PORT_CSC) {
1805 temp &= ~PORT_CSC;
1806 isp1760_writel(temp, hcd->regs + HC_PORTSC1);
1807 goto done;
1808 }
1809 }
1810
1811 /*
1812 * Return status information even for ports with OWNER set.
1813 * Otherwise khubd wouldn't see the disconnect event when a
1814 * high-speed device is switched over to the companion
1815 * controller by the user.
1816 */
1817
1818 if ((temp & mask) != 0
1819 || ((temp & PORT_RESUME) != 0
1820 && time_after_eq(jiffies,
1821 priv->reset_done))) {
1822 buf [0] |= 1 << (0 + 1);
1823 status = STS_PCD;
1824 }
1825 /* FIXME autosuspend idle root hubs */
1826done:
1827 spin_unlock_irqrestore(&priv->lock, flags);
1828 return status ? retval : 0;
1829}
1830
1831static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1832 struct usb_hub_descriptor *desc)
1833{
1834 int ports = HCS_N_PORTS(priv->hcs_params);
1835 u16 temp;
1836
1837 desc->bDescriptorType = 0x29;
1838 /* priv 1.0, 2.3.9 says 20ms max */
1839 desc->bPwrOn2PwrGood = 10;
1840 desc->bHubContrCurrent = 0;
1841
1842 desc->bNbrPorts = ports;
1843 temp = 1 + (ports / 8);
1844 desc->bDescLength = 7 + 2 * temp;
1845
1846 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1847 memset(&desc->bitmap[0], 0, temp);
1848 memset(&desc->bitmap[temp], 0xff, temp);
1849
1850 /* per-port overcurrent reporting */
1851 temp = 0x0008;
1852 if (HCS_PPC(priv->hcs_params))
1853 /* per-port power control */
1854 temp |= 0x0001;
1855 else
1856 /* no power switching */
1857 temp |= 0x0002;
1858 desc->wHubCharacteristics = cpu_to_le16(temp);
1859}
1860
1861#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1862
1863static int check_reset_complete(struct isp1760_hcd *priv, int index,
1864 u32 __iomem *status_reg, int port_status)
1865{
1866 if (!(port_status & PORT_CONNECT))
1867 return port_status;
1868
1869 /* if reset finished and it's still not enabled -- handoff */
1870 if (!(port_status & PORT_PE)) {
1871
1872 printk(KERN_ERR "port %d full speed --> companion\n",
1873 index + 1);
1874
1875 port_status |= PORT_OWNER;
1876 port_status &= ~PORT_RWC_BITS;
1877 isp1760_writel(port_status, status_reg);
1878
1879 } else
1880 printk(KERN_ERR "port %d high speed\n", index + 1);
1881
1882 return port_status;
1883}
1884
1885static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1886 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1887{
1888 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1889 int ports = HCS_N_PORTS(priv->hcs_params);
1890 u32 __iomem *status_reg = hcd->regs + HC_PORTSC1;
1891 u32 temp, status;
1892 unsigned long flags;
1893 int retval = 0;
1894 unsigned selector;
1895
1896 /*
1897 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1898 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1899 * (track current state ourselves) ... blink for diagnostics,
1900 * power, "this is the one", etc. EHCI spec supports this.
1901 */
1902
1903 spin_lock_irqsave(&priv->lock, flags);
1904 switch (typeReq) {
1905 case ClearHubFeature:
1906 switch (wValue) {
1907 case C_HUB_LOCAL_POWER:
1908 case C_HUB_OVER_CURRENT:
1909 /* no hub-wide feature/status flags */
1910 break;
1911 default:
1912 goto error;
1913 }
1914 break;
1915 case ClearPortFeature:
1916 if (!wIndex || wIndex > ports)
1917 goto error;
1918 wIndex--;
1919 temp = isp1760_readl(status_reg);
1920
1921 /*
1922 * Even if OWNER is set, so the port is owned by the
1923 * companion controller, khubd needs to be able to clear
1924 * the port-change status bits (especially
749da5f8 1925 * USB_PORT_STAT_C_CONNECTION).
db11e47d
SS		 1926 */
1927
1928 switch (wValue) {
1929 case USB_PORT_FEAT_ENABLE:
1930 isp1760_writel(temp & ~PORT_PE, status_reg);
1931 break;
1932 case USB_PORT_FEAT_C_ENABLE:
1933 /* XXX error? */
1934 break;
1935 case USB_PORT_FEAT_SUSPEND:
1936 if (temp & PORT_RESET)
1937 goto error;
1938
1939 if (temp & PORT_SUSPEND) {
1940 if ((temp & PORT_PE) == 0)
1941 goto error;
1942 /* resume signaling for 20 msec */
1943 temp &= ~(PORT_RWC_BITS);
1944 isp1760_writel(temp | PORT_RESUME,
1945 status_reg);
1946 priv->reset_done = jiffies +
1947 msecs_to_jiffies(20);
1948 }
1949 break;
1950 case USB_PORT_FEAT_C_SUSPEND:
1951 /* we auto-clear this feature */
1952 break;
1953 case USB_PORT_FEAT_POWER:
1954 if (HCS_PPC(priv->hcs_params))
1955 isp1760_writel(temp & ~PORT_POWER, status_reg);
1956 break;
1957 case USB_PORT_FEAT_C_CONNECTION:
1958 isp1760_writel(temp | PORT_CSC,
1959 status_reg);
1960 break;
1961 case USB_PORT_FEAT_C_OVER_CURRENT:
1962 /* XXX error ?*/
1963 break;
1964 case USB_PORT_FEAT_C_RESET:
1965 /* GetPortStatus clears reset */
1966 break;
1967 default:
1968 goto error;
1969 }
1970 isp1760_readl(hcd->regs + HC_USBCMD);
1971 break;
1972 case GetHubDescriptor:
1973 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1974 buf);
1975 break;
1976 case GetHubStatus:
1977 /* no hub-wide feature/status flags */
1978 memset(buf, 0, 4);
1979 break;
1980 case GetPortStatus:
1981 if (!wIndex || wIndex > ports)
1982 goto error;
1983 wIndex--;
1984 status = 0;
1985 temp = isp1760_readl(status_reg);
1986
1987 /* wPortChange bits */
1988 if (temp & PORT_CSC)
749da5f8 1989 status |= USB_PORT_STAT_C_CONNECTION << 16;
db11e47d
SS		 1990
1991
1992 /* whoever resumes must GetPortStatus to complete it!! */
1993 if (temp & PORT_RESUME) {
1994 printk(KERN_ERR "Port resume should be skipped.\n");
1995
1996 /* Remote Wakeup received? */
1997 if (!priv->reset_done) {
1998 /* resume signaling for 20 msec */
1999 priv->reset_done = jiffies
2000 + msecs_to_jiffies(20);
2001 /* check the port again */
2002 mod_timer(&priv_to_hcd(priv)->rh_timer,
2003 priv->reset_done);
2004 }
2005
2006 /* resume completed? */
2007 else if (time_after_eq(jiffies,
2008 priv->reset_done)) {
749da5f8 2009 status |= USB_PORT_STAT_C_SUSPEND << 16;
db11e47d
SS		 2010 priv->reset_done = 0;
2011
2012 /* stop resume signaling */
2013 temp = isp1760_readl(status_reg);
2014 isp1760_writel(
2015 temp & ~(PORT_RWC_BITS | PORT_RESUME),
2016 status_reg);
2017 retval = handshake(priv, status_reg,
2018 PORT_RESUME, 0, 2000 /* 2msec */);
2019 if (retval != 0) {
2020 isp1760_err(priv,
2021 "port %d resume error %d\n",
2022 wIndex + 1, retval);
2023 goto error;
2024 }
2025 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
2026 }
2027 }
2028
2029 /* whoever resets must GetPortStatus to complete it!! */
2030 if ((temp & PORT_RESET)
2031 && time_after_eq(jiffies,
2032 priv->reset_done)) {
749da5f8 2033 status |= USB_PORT_STAT_C_RESET << 16;
db11e47d
SS		 2034 priv->reset_done = 0;
2035
2036 /* force reset to complete */
2037 isp1760_writel(temp & ~PORT_RESET,
2038 status_reg);
2039 /* REVISIT: some hardware needs 550+ usec to clear
2040 * this bit; seems too long to spin routinely...
2041 */
2042 retval = handshake(priv, status_reg,
2043 PORT_RESET, 0, 750);
2044 if (retval != 0) {
2045 isp1760_err(priv, "port %d reset error %d\n",
2046 wIndex + 1, retval);
2047 goto error;
2048 }
2049
2050 /* see what we found out */
2051 temp = check_reset_complete(priv, wIndex, status_reg,
2052 isp1760_readl(status_reg));
2053 }
2054 /*
2055 * Even if OWNER is set, there's no harm letting khubd
2056 * see the wPortStatus values (they should all be 0 except
2057 * for PORT_POWER anyway).
2058 */
2059
2060 if (temp & PORT_OWNER)
2061 printk(KERN_ERR "Warning: PORT_OWNER is set\n");
2062
2063 if (temp & PORT_CONNECT) {
749da5f8 2064 status |= USB_PORT_STAT_CONNECTION;
db11e47d
SS		 2065 /* status may be from integrated TT */
2066 status |= ehci_port_speed(priv, temp);
2067 }
2068 if (temp & PORT_PE)
749da5f8 2069 status |= USB_PORT_STAT_ENABLE;
db11e47d 2070 if (temp & (PORT_SUSPEND|PORT_RESUME))
749da5f8 2071 status |= USB_PORT_STAT_SUSPEND;
db11e47d 2072 if (temp & PORT_RESET)
749da5f8 2073 status |= USB_PORT_STAT_RESET;
db11e47d 2074 if (temp & PORT_POWER)
749da5f8 2075 status |= USB_PORT_STAT_POWER;
db11e47d
SS		 2076
2077 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2078 break;
2079 case SetHubFeature:
2080 switch (wValue) {
2081 case C_HUB_LOCAL_POWER:
2082 case C_HUB_OVER_CURRENT:
2083 /* no hub-wide feature/status flags */
2084 break;
2085 default:
2086 goto error;
2087 }
2088 break;
2089 case SetPortFeature:
2090 selector = wIndex >> 8;
2091 wIndex &= 0xff;
2092 if (!wIndex || wIndex > ports)
2093 goto error;
2094 wIndex--;
2095 temp = isp1760_readl(status_reg);
2096 if (temp & PORT_OWNER)
2097 break;
2098
2099/* temp &= ~PORT_RWC_BITS; */
2100 switch (wValue) {
2101 case USB_PORT_FEAT_ENABLE:
2102 isp1760_writel(temp | PORT_PE, status_reg);
2103 break;
2104
2105 case USB_PORT_FEAT_SUSPEND:
2106 if ((temp & PORT_PE) == 0
2107 || (temp & PORT_RESET) != 0)
2108 goto error;
2109
2110 isp1760_writel(temp | PORT_SUSPEND, status_reg);
2111 break;
2112 case USB_PORT_FEAT_POWER:
2113 if (HCS_PPC(priv->hcs_params))
2114 isp1760_writel(temp | PORT_POWER,
2115 status_reg);
2116 break;
2117 case USB_PORT_FEAT_RESET:
2118 if (temp & PORT_RESUME)
2119 goto error;
2120 /* line status bits may report this as low speed,
2121 * which can be fine if this root hub has a
2122 * transaction translator built in.
2123 */
2124 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2125 && PORT_USB11(temp)) {
2126 temp |= PORT_OWNER;
2127 } else {
2128 temp |= PORT_RESET;
2129 temp &= ~PORT_PE;
2130
2131 /*
2132 * caller must wait, then call GetPortStatus
2133 * usb 2.0 spec says 50 ms resets on root
2134 */
2135 priv->reset_done = jiffies +
2136 msecs_to_jiffies(50);
2137 }
2138 isp1760_writel(temp, status_reg);
2139 break;
2140 default:
2141 goto error;
2142 }
2143 isp1760_readl(hcd->regs + HC_USBCMD);
2144 break;
2145
2146 default:
2147error:
2148 /* "stall" on error */
2149 retval = -EPIPE;
2150 }
2151 spin_unlock_irqrestore(&priv->lock, flags);
2152 return retval;
2153}
2154
2155static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd,
2156 struct usb_host_endpoint *ep)
2157{
2158 struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
2159 struct isp1760_qh *qh;
2160 struct isp1760_qtd *qtd;
d249afdd 2161 unsigned long flags;
db11e47d
SS		 2162
2163 spin_lock_irqsave(&priv->lock, flags);
2164 qh = ep->hcpriv;
2165 if (!qh)
2166 goto out;
2167
2168 ep->hcpriv = NULL;
2169 do {
2170 /* more than entry might get removed */
2171 if (list_empty(&qh->qtd_list))
2172 break;
2173
2174 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
2175 qtd_list);
2176
2177 if (qtd->status & URB_ENQUEUED) {
2178
2179 spin_unlock_irqrestore(&priv->lock, flags);
2180 isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET);
2181 spin_lock_irqsave(&priv->lock, flags);
2182 } else {
2183 struct urb *urb;
2184
2185 urb = qtd->urb;
2186 clean_up_qtdlist(qtd);
2187 isp1760_urb_done(priv, urb, -ECONNRESET);
2188 }
2189 } while (1);
2190
2191 qh_destroy(qh);
2192 /* remove requests and leak them.
2193 * ATL are pretty fast done, INT could take a while...
2194 * The latter shoule be removed
2195 */
2196out:
2197 spin_unlock_irqrestore(&priv->lock, flags);
2198}
2199
2200static int isp1760_get_frame(struct usb_hcd *hcd)
2201{
2202 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2203 u32 fr;
2204
2205 fr = isp1760_readl(hcd->regs + HC_FRINDEX);
2206 return (fr >> 3) % priv->periodic_size;
2207}
2208
2209static void isp1760_stop(struct usb_hcd *hcd)
2210{
2211 struct isp1760_hcd *priv = hcd_to_priv(hcd);
3faefc88 2212 u32 temp;
db11e47d
SS		 2213
2214 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2215 NULL, 0);
2216 mdelay(20);
2217
2218 spin_lock_irq(&priv->lock);
2219 ehci_reset(priv);
2220 /* Disable IRQ */
3faefc88
NC		 2221 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
2222 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
db11e47d
SS		 2223 spin_unlock_irq(&priv->lock);
2224
2225 isp1760_writel(0, hcd->regs + HC_CONFIGFLAG);
2226}
2227
2228static void isp1760_shutdown(struct usb_hcd *hcd)
2229{
3faefc88 2230 u32 command, temp;
db11e47d
SS		 2231
2232 isp1760_stop(hcd);
3faefc88
NC		 2233 temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
2234 isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
db11e47d
SS		 2235
2236 command = isp1760_readl(hcd->regs + HC_USBCMD);
2237 command &= ~CMD_RUN;
2238 isp1760_writel(command, hcd->regs + HC_USBCMD);
2239}
2240
2241static const struct hc_driver isp1760_hc_driver = {
2242 .description = "isp1760-hcd",
2243 .product_desc = "NXP ISP1760 USB Host Controller",
2244 .hcd_priv_size = sizeof(struct isp1760_hcd),
2245 .irq = isp1760_irq,
2246 .flags = HCD_MEMORY | HCD_USB2,
2247 .reset = isp1760_hc_setup,
2248 .start = isp1760_run,
2249 .stop = isp1760_stop,
2250 .shutdown = isp1760_shutdown,
2251 .urb_enqueue = isp1760_urb_enqueue,
2252 .urb_dequeue = isp1760_urb_dequeue,
2253 .endpoint_disable = isp1760_endpoint_disable,
2254 .get_frame_number = isp1760_get_frame,
2255 .hub_status_data = isp1760_hub_status_data,
2256 .hub_control = isp1760_hub_control,
2257};
2258
2259int __init init_kmem_once(void)
2260{
2261 qtd_cachep = kmem_cache_create("isp1760_qtd",
2262 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2263 SLAB_MEM_SPREAD, NULL);
2264
2265 if (!qtd_cachep)
2266 return -ENOMEM;
2267
2268 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2269 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2270
2271 if (!qh_cachep) {
2272 kmem_cache_destroy(qtd_cachep);
2273 return -ENOMEM;
2274 }
2275
2276 return 0;
2277}
2278
2279void deinit_kmem_cache(void)
2280{
2281 kmem_cache_destroy(qtd_cachep);
2282 kmem_cache_destroy(qh_cachep);
2283}
2284
f9031f2c
CM		 2285struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2286 int irq, unsigned long irqflags,
2287 struct device *dev, const char *busname,
2288 unsigned int devflags)
db11e47d
SS		 2289{
2290 struct usb_hcd *hcd;
2291 struct isp1760_hcd *priv;
2292 int ret;
2293
2294 if (usb_disabled())
2295 return ERR_PTR(-ENODEV);
2296
2297 /* prevent usb-core allocating DMA pages */
2298 dev->dma_mask = NULL;
2299
0031a06e 2300 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
db11e47d
SS		 2301 if (!hcd)
2302 return ERR_PTR(-ENOMEM);
2303
2304 priv = hcd_to_priv(hcd);
3faefc88 2305 priv->devflags = devflags;
db11e47d
SS		 2306 init_memory(priv);
2307 hcd->regs = ioremap(res_start, res_len);
2308 if (!hcd->regs) {
2309 ret = -EIO;
2310 goto err_put;
2311 }
2312
db11e47d
SS		 2313 hcd->irq = irq;
2314 hcd->rsrc_start = res_start;
2315 hcd->rsrc_len = res_len;
2316
e6942d63
NC		 2317 ret = usb_add_hcd(hcd, irq, irqflags);
2318 if (ret)
2319 goto err_unmap;
2320
db11e47d
SS		 2321 return hcd;
2322
2323err_unmap:
2324 iounmap(hcd->regs);
2325
2326err_put:
2327 usb_put_hcd(hcd);
2328
2329 return ERR_PTR(ret);
2330}
2331
2332MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2333MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2334MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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