Commit | Line | Data |
---|---|---|
db11e47d SS |
1 | /* |
2 | * Driver for the NXP ISP1760 chip | |
3 | * | |
4 | * However, the code might contain some bugs. What doesn't work for sure is: | |
5 | * - ISO | |
6 | * - OTG | |
7 | e The interrupt line is configured as active low, level. | |
8 | * | |
9 | * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de> | |
10 | * | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/list.h> | |
16 | #include <linux/usb.h> | |
27729aad | 17 | #include <linux/usb/hcd.h> |
db11e47d SS |
18 | #include <linux/debugfs.h> |
19 | #include <linux/uaccess.h> | |
20 | #include <linux/io.h> | |
db8516f6 | 21 | #include <linux/mm.h> |
db11e47d | 22 | #include <asm/unaligned.h> |
db8516f6 | 23 | #include <asm/cacheflush.h> |
db11e47d | 24 | |
db11e47d SS |
25 | #include "isp1760-hcd.h" |
26 | ||
27 | static struct kmem_cache *qtd_cachep; | |
28 | static struct kmem_cache *qh_cachep; | |
29 | ||
30 | struct isp1760_hcd { | |
31 | u32 hcs_params; | |
32 | spinlock_t lock; | |
33 | struct inter_packet_info atl_ints[32]; | |
34 | struct inter_packet_info int_ints[32]; | |
35 | struct memory_chunk memory_pool[BLOCKS]; | |
b14e840d | 36 | u32 atl_queued; |
db11e47d SS |
37 | |
38 | /* periodic schedule support */ | |
39 | #define DEFAULT_I_TDPS 1024 | |
40 | unsigned periodic_size; | |
41 | unsigned i_thresh; | |
42 | unsigned long reset_done; | |
43 | unsigned long next_statechange; | |
3faefc88 | 44 | unsigned int devflags; |
db11e47d SS |
45 | }; |
46 | ||
47 | static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) | |
48 | { | |
49 | return (struct isp1760_hcd *) (hcd->hcd_priv); | |
50 | } | |
db11e47d SS |
51 | |
52 | /* Section 2.2 Host Controller Capability Registers */ | |
53 | #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ | |
54 | #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ | |
55 | #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ | |
56 | #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ | |
57 | #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ | |
58 | #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ | |
59 | #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ | |
60 | ||
61 | /* Section 2.3 Host Controller Operational Registers */ | |
62 | #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ | |
63 | #define CMD_RESET (1<<1) /* reset HC not bus */ | |
64 | #define CMD_RUN (1<<0) /* start/stop HC */ | |
65 | #define STS_PCD (1<<2) /* port change detect */ | |
66 | #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ | |
67 | ||
68 | #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ | |
69 | #define PORT_POWER (1<<12) /* true: has power (see PPC) */ | |
70 | #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ | |
71 | #define PORT_RESET (1<<8) /* reset port */ | |
72 | #define PORT_SUSPEND (1<<7) /* suspend port */ | |
73 | #define PORT_RESUME (1<<6) /* resume it */ | |
74 | #define PORT_PE (1<<2) /* port enable */ | |
75 | #define PORT_CSC (1<<1) /* connect status change */ | |
76 | #define PORT_CONNECT (1<<0) /* device connected */ | |
77 | #define PORT_RWC_BITS (PORT_CSC) | |
78 | ||
79 | struct isp1760_qtd { | |
db11e47d | 80 | u8 packet_type; |
db11e47d | 81 | void *data_buffer; |
a041d8e4 AB |
82 | u32 payload_addr; |
83 | ||
db11e47d SS |
84 | /* the rest is HCD-private */ |
85 | struct list_head qtd_list; | |
86 | struct urb *urb; | |
87 | size_t length; | |
88 | ||
89 | /* isp special*/ | |
90 | u32 status; | |
db11e47d | 91 | #define URB_ENQUEUED (1 << 1) |
db11e47d SS |
92 | }; |
93 | ||
94 | struct isp1760_qh { | |
95 | /* first part defined by EHCI spec */ | |
96 | struct list_head qtd_list; | |
db11e47d | 97 | |
db11e47d SS |
98 | u32 toggle; |
99 | u32 ping; | |
100 | }; | |
101 | ||
bedc0c31 AB |
102 | /* |
103 | * Access functions for isp176x registers (addresses 0..0x03FF). | |
104 | */ | |
105 | static u32 reg_read32(void __iomem *base, u32 reg) | |
db11e47d | 106 | { |
bedc0c31 | 107 | return readl(base + reg); |
db11e47d SS |
108 | } |
109 | ||
bedc0c31 | 110 | static void reg_write32(void __iomem *base, u32 reg, u32 val) |
db11e47d | 111 | { |
bedc0c31 | 112 | writel(val, base + reg); |
db11e47d SS |
113 | } |
114 | ||
115 | /* | |
bedc0c31 AB |
116 | * Access functions for isp176x memory (offset >= 0x0400). |
117 | * | |
118 | * bank_reads8() reads memory locations prefetched by an earlier write to | |
119 | * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- | |
120 | * bank optimizations, you should use the more generic mem_reads8() below. | |
121 | * | |
122 | * For access to ptd memory, use the specialized ptd_read() and ptd_write() | |
123 | * below. | |
124 | * | |
125 | * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() | |
db11e47d SS |
126 | * doesn't quite work because some people have to enforce 32-bit access |
127 | */ | |
bedc0c31 AB |
128 | static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, |
129 | __u32 *dst, u32 bytes) | |
db11e47d | 130 | { |
bedc0c31 | 131 | __u32 __iomem *src; |
db11e47d | 132 | u32 val; |
bedc0c31 AB |
133 | __u8 *src_byteptr; |
134 | __u8 *dst_byteptr; | |
db11e47d | 135 | |
bedc0c31 | 136 | src = src_base + (bank_addr | src_offset); |
db11e47d | 137 | |
bedc0c31 AB |
138 | if (src_offset < PAYLOAD_OFFSET) { |
139 | while (bytes >= 4) { | |
140 | *dst = le32_to_cpu(__raw_readl(src)); | |
141 | bytes -= 4; | |
142 | src++; | |
143 | dst++; | |
144 | } | |
145 | } else { | |
146 | while (bytes >= 4) { | |
147 | *dst = __raw_readl(src); | |
148 | bytes -= 4; | |
149 | src++; | |
150 | dst++; | |
151 | } | |
db11e47d SS |
152 | } |
153 | ||
bedc0c31 | 154 | if (!bytes) |
db11e47d SS |
155 | return; |
156 | ||
157 | /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully | |
158 | * allocated. | |
159 | */ | |
bedc0c31 AB |
160 | if (src_offset < PAYLOAD_OFFSET) |
161 | val = le32_to_cpu(__raw_readl(src)); | |
162 | else | |
163 | val = __raw_readl(src); | |
164 | ||
165 | dst_byteptr = (void *) dst; | |
166 | src_byteptr = (void *) &val; | |
167 | while (bytes > 0) { | |
168 | *dst_byteptr = *src_byteptr; | |
169 | dst_byteptr++; | |
170 | src_byteptr++; | |
171 | bytes--; | |
db11e47d SS |
172 | } |
173 | } | |
174 | ||
bedc0c31 AB |
175 | static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst, |
176 | u32 bytes) | |
db11e47d | 177 | { |
bedc0c31 AB |
178 | reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0)); |
179 | ndelay(90); | |
180 | bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes); | |
181 | } | |
182 | ||
183 | static void mem_writes8(void __iomem *dst_base, u32 dst_offset, | |
184 | __u32 const *src, u32 bytes) | |
185 | { | |
186 | __u32 __iomem *dst; | |
187 | ||
188 | dst = dst_base + dst_offset; | |
189 | ||
190 | if (dst_offset < PAYLOAD_OFFSET) { | |
191 | while (bytes >= 4) { | |
192 | __raw_writel(cpu_to_le32(*src), dst); | |
193 | bytes -= 4; | |
194 | src++; | |
195 | dst++; | |
196 | } | |
197 | } else { | |
198 | while (bytes >= 4) { | |
199 | __raw_writel(*src, dst); | |
200 | bytes -= 4; | |
201 | src++; | |
202 | dst++; | |
203 | } | |
db11e47d SS |
204 | } |
205 | ||
bedc0c31 | 206 | if (!bytes) |
db11e47d | 207 | return; |
bedc0c31 AB |
208 | /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the |
209 | * extra bytes should not be read by the HW. | |
db11e47d SS |
210 | */ |
211 | ||
bedc0c31 AB |
212 | if (dst_offset < PAYLOAD_OFFSET) |
213 | __raw_writel(cpu_to_le32(*src), dst); | |
214 | else | |
215 | __raw_writel(*src, dst); | |
db11e47d SS |
216 | } |
217 | ||
bedc0c31 AB |
218 | /* |
219 | * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, | |
220 | * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. | |
221 | */ | |
222 | static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot, | |
223 | struct ptd *ptd) | |
224 | { | |
225 | reg_write32(base, HC_MEMORY_REG, | |
226 | ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd)); | |
227 | ndelay(90); | |
228 | bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0), | |
229 | (void *) ptd, sizeof(*ptd)); | |
230 | } | |
231 | ||
232 | static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, | |
233 | struct ptd *ptd) | |
234 | { | |
235 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0), | |
236 | &ptd->dw1, 7*sizeof(ptd->dw1)); | |
237 | /* Make sure dw0 gets written last (after other dw's and after payload) | |
238 | since it contains the enable bit */ | |
239 | wmb(); | |
240 | mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0, | |
241 | sizeof(ptd->dw0)); | |
242 | } | |
243 | ||
244 | ||
db11e47d SS |
245 | /* memory management of the 60kb on the chip from 0x1000 to 0xffff */ |
246 | static void init_memory(struct isp1760_hcd *priv) | |
247 | { | |
a041d8e4 AB |
248 | int i, curr; |
249 | u32 payload_addr; | |
db11e47d | 250 | |
a041d8e4 | 251 | payload_addr = PAYLOAD_OFFSET; |
db11e47d | 252 | for (i = 0; i < BLOCK_1_NUM; i++) { |
a041d8e4 | 253 | priv->memory_pool[i].start = payload_addr; |
db11e47d SS |
254 | priv->memory_pool[i].size = BLOCK_1_SIZE; |
255 | priv->memory_pool[i].free = 1; | |
a041d8e4 | 256 | payload_addr += priv->memory_pool[i].size; |
db11e47d SS |
257 | } |
258 | ||
a041d8e4 AB |
259 | curr = i; |
260 | for (i = 0; i < BLOCK_2_NUM; i++) { | |
261 | priv->memory_pool[curr + i].start = payload_addr; | |
262 | priv->memory_pool[curr + i].size = BLOCK_2_SIZE; | |
263 | priv->memory_pool[curr + i].free = 1; | |
264 | payload_addr += priv->memory_pool[curr + i].size; | |
db11e47d SS |
265 | } |
266 | ||
a041d8e4 AB |
267 | curr = i; |
268 | for (i = 0; i < BLOCK_3_NUM; i++) { | |
269 | priv->memory_pool[curr + i].start = payload_addr; | |
270 | priv->memory_pool[curr + i].size = BLOCK_3_SIZE; | |
271 | priv->memory_pool[curr + i].free = 1; | |
272 | payload_addr += priv->memory_pool[curr + i].size; | |
db11e47d SS |
273 | } |
274 | ||
34537731 | 275 | WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE); |
db11e47d SS |
276 | } |
277 | ||
6bda21bc | 278 | static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
db11e47d | 279 | { |
6bda21bc | 280 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d SS |
281 | int i; |
282 | ||
34537731 | 283 | WARN_ON(qtd->payload_addr); |
a041d8e4 AB |
284 | |
285 | if (!qtd->length) | |
286 | return; | |
db11e47d SS |
287 | |
288 | for (i = 0; i < BLOCKS; i++) { | |
a041d8e4 | 289 | if (priv->memory_pool[i].size >= qtd->length && |
db11e47d | 290 | priv->memory_pool[i].free) { |
db11e47d | 291 | priv->memory_pool[i].free = 0; |
a041d8e4 AB |
292 | qtd->payload_addr = priv->memory_pool[i].start; |
293 | return; | |
db11e47d SS |
294 | } |
295 | } | |
296 | ||
6bda21bc | 297 | dev_err(hcd->self.controller, |
d06847fe | 298 | "%s: Cannot allocate %zu bytes of memory\n" |
6bda21bc AB |
299 | "Current memory map:\n", |
300 | __func__, qtd->length); | |
db11e47d | 301 | for (i = 0; i < BLOCKS; i++) { |
6bda21bc | 302 | dev_err(hcd->self.controller, "Pool %2d size %4d status: %d\n", |
db11e47d SS |
303 | i, priv->memory_pool[i].size, |
304 | priv->memory_pool[i].free); | |
305 | } | |
306 | /* XXX maybe -ENOMEM could be possible */ | |
307 | BUG(); | |
a041d8e4 | 308 | return; |
db11e47d SS |
309 | } |
310 | ||
6bda21bc | 311 | static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
db11e47d | 312 | { |
6bda21bc | 313 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d SS |
314 | int i; |
315 | ||
a041d8e4 | 316 | if (!qtd->payload_addr) |
db11e47d SS |
317 | return; |
318 | ||
319 | for (i = 0; i < BLOCKS; i++) { | |
a041d8e4 | 320 | if (priv->memory_pool[i].start == qtd->payload_addr) { |
34537731 | 321 | WARN_ON(priv->memory_pool[i].free); |
db11e47d | 322 | priv->memory_pool[i].free = 1; |
a041d8e4 AB |
323 | qtd->payload_addr = 0; |
324 | return; | |
db11e47d SS |
325 | } |
326 | } | |
327 | ||
6bda21bc AB |
328 | dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n", |
329 | __func__, qtd->payload_addr); | |
db11e47d SS |
330 | BUG(); |
331 | } | |
332 | ||
333 | static void isp1760_init_regs(struct usb_hcd *hcd) | |
334 | { | |
bedc0c31 AB |
335 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0); |
336 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | |
337 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | |
338 | reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE); | |
db11e47d SS |
339 | } |
340 | ||
bedc0c31 | 341 | static int handshake(struct usb_hcd *hcd, u32 reg, |
db11e47d SS |
342 | u32 mask, u32 done, int usec) |
343 | { | |
344 | u32 result; | |
345 | ||
346 | do { | |
bedc0c31 | 347 | result = reg_read32(hcd->regs, reg); |
db11e47d SS |
348 | if (result == ~0) |
349 | return -ENODEV; | |
350 | result &= mask; | |
351 | if (result == done) | |
352 | return 0; | |
353 | udelay(1); | |
354 | usec--; | |
355 | } while (usec > 0); | |
356 | return -ETIMEDOUT; | |
357 | } | |
358 | ||
359 | /* reset a non-running (STS_HALT == 1) controller */ | |
6bda21bc | 360 | static int ehci_reset(struct usb_hcd *hcd) |
db11e47d SS |
361 | { |
362 | int retval; | |
6bda21bc AB |
363 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
364 | ||
bedc0c31 | 365 | u32 command = reg_read32(hcd->regs, HC_USBCMD); |
db11e47d SS |
366 | |
367 | command |= CMD_RESET; | |
bedc0c31 | 368 | reg_write32(hcd->regs, HC_USBCMD, command); |
db11e47d SS |
369 | hcd->state = HC_STATE_HALT; |
370 | priv->next_statechange = jiffies; | |
bedc0c31 | 371 | retval = handshake(hcd, HC_USBCMD, |
db11e47d SS |
372 | CMD_RESET, 0, 250 * 1000); |
373 | return retval; | |
374 | } | |
375 | ||
376 | static void qh_destroy(struct isp1760_qh *qh) | |
377 | { | |
34537731 | 378 | WARN_ON(!list_empty(&qh->qtd_list)); |
db11e47d SS |
379 | kmem_cache_free(qh_cachep, qh); |
380 | } | |
381 | ||
6bda21bc | 382 | static struct isp1760_qh *isp1760_qh_alloc(gfp_t flags) |
db11e47d SS |
383 | { |
384 | struct isp1760_qh *qh; | |
385 | ||
386 | qh = kmem_cache_zalloc(qh_cachep, flags); | |
387 | if (!qh) | |
388 | return qh; | |
389 | ||
390 | INIT_LIST_HEAD(&qh->qtd_list); | |
db11e47d SS |
391 | return qh; |
392 | } | |
393 | ||
394 | /* magic numbers that can affect system performance */ | |
395 | #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ | |
396 | #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ | |
397 | #define EHCI_TUNE_RL_TT 0 | |
398 | #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ | |
399 | #define EHCI_TUNE_MULT_TT 1 | |
400 | #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ | |
401 | ||
402 | /* one-time init, only for memory state */ | |
403 | static int priv_init(struct usb_hcd *hcd) | |
404 | { | |
405 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
406 | u32 hcc_params; | |
407 | ||
408 | spin_lock_init(&priv->lock); | |
409 | ||
410 | /* | |
411 | * hw default: 1K periodic list heads, one per frame. | |
412 | * periodic_size can shrink by USBCMD update if hcc_params allows. | |
413 | */ | |
414 | priv->periodic_size = DEFAULT_I_TDPS; | |
415 | ||
416 | /* controllers may cache some of the periodic schedule ... */ | |
bedc0c31 | 417 | hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS); |
db11e47d SS |
418 | /* full frame cache */ |
419 | if (HCC_ISOC_CACHE(hcc_params)) | |
420 | priv->i_thresh = 8; | |
421 | else /* N microframes cached */ | |
422 | priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); | |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
427 | static int isp1760_hc_setup(struct usb_hcd *hcd) | |
428 | { | |
429 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
430 | int result; | |
3faefc88 NC |
431 | u32 scratch, hwmode; |
432 | ||
433 | /* Setup HW Mode Control: This assumes a level active-low interrupt */ | |
434 | hwmode = HW_DATA_BUS_32BIT; | |
435 | ||
436 | if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) | |
437 | hwmode &= ~HW_DATA_BUS_32BIT; | |
438 | if (priv->devflags & ISP1760_FLAG_ANALOG_OC) | |
439 | hwmode |= HW_ANA_DIGI_OC; | |
440 | if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH) | |
441 | hwmode |= HW_DACK_POL_HIGH; | |
442 | if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH) | |
443 | hwmode |= HW_DREQ_POL_HIGH; | |
9da69c60 MH |
444 | if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH) |
445 | hwmode |= HW_INTR_HIGH_ACT; | |
446 | if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG) | |
447 | hwmode |= HW_INTR_EDGE_TRIG; | |
3faefc88 NC |
448 | |
449 | /* | |
450 | * We have to set this first in case we're in 16-bit mode. | |
451 | * Write it twice to ensure correct upper bits if switching | |
452 | * to 16-bit mode. | |
453 | */ | |
bedc0c31 AB |
454 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
455 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); | |
db11e47d | 456 | |
bedc0c31 | 457 | reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe); |
3faefc88 | 458 | /* Change bus pattern */ |
bedc0c31 AB |
459 | scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
460 | scratch = reg_read32(hcd->regs, HC_SCRATCH_REG); | |
db11e47d | 461 | if (scratch != 0xdeadbabe) { |
6bda21bc | 462 | dev_err(hcd->self.controller, "Scratch test failed.\n"); |
db11e47d SS |
463 | return -ENODEV; |
464 | } | |
465 | ||
466 | /* pre reset */ | |
467 | isp1760_init_regs(hcd); | |
468 | ||
469 | /* reset */ | |
bedc0c31 | 470 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL); |
db11e47d SS |
471 | mdelay(100); |
472 | ||
bedc0c31 | 473 | reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC); |
db11e47d SS |
474 | mdelay(100); |
475 | ||
6bda21bc | 476 | result = ehci_reset(hcd); |
db11e47d SS |
477 | if (result) |
478 | return result; | |
479 | ||
480 | /* Step 11 passed */ | |
481 | ||
6bda21bc | 482 | dev_info(hcd->self.controller, "bus width: %d, oc: %s\n", |
3faefc88 NC |
483 | (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ? |
484 | 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ? | |
485 | "analog" : "digital"); | |
db11e47d SS |
486 | |
487 | /* ATL reset */ | |
bedc0c31 | 488 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET); |
db11e47d | 489 | mdelay(10); |
bedc0c31 | 490 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode); |
db11e47d | 491 | |
bedc0c31 AB |
492 | reg_write32(hcd->regs, HC_INTERRUPT_REG, INTERRUPT_ENABLE_MASK); |
493 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK); | |
3faefc88 NC |
494 | |
495 | /* | |
496 | * PORT 1 Control register of the ISP1760 is the OTG control | |
42c65396 TH |
497 | * register on ISP1761. Since there is no OTG or device controller |
498 | * support in this driver, we use port 1 as a "normal" USB host port on | |
499 | * both chips. | |
3faefc88 | 500 | */ |
bedc0c31 | 501 | reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2); |
42c65396 | 502 | mdelay(10); |
db11e47d | 503 | |
bedc0c31 | 504 | priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS); |
db11e47d SS |
505 | |
506 | return priv_init(hcd); | |
507 | } | |
508 | ||
509 | static void isp1760_init_maps(struct usb_hcd *hcd) | |
510 | { | |
511 | /*set last maps, for iso its only 1, else 32 tds bitmap*/ | |
bedc0c31 AB |
512 | reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000); |
513 | reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000); | |
514 | reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001); | |
eb1a7968 AB |
515 | |
516 | reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, | |
517 | ATL_BUF_FILL | INT_BUF_FILL); | |
db11e47d SS |
518 | } |
519 | ||
520 | static void isp1760_enable_interrupts(struct usb_hcd *hcd) | |
521 | { | |
bedc0c31 | 522 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0); |
eb1a7968 | 523 | reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff); |
bedc0c31 | 524 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0); |
eb1a7968 | 525 | reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff); |
bedc0c31 AB |
526 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0); |
527 | reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff); | |
db11e47d SS |
528 | /* step 23 passed */ |
529 | } | |
530 | ||
531 | static int isp1760_run(struct usb_hcd *hcd) | |
532 | { | |
db11e47d SS |
533 | int retval; |
534 | u32 temp; | |
535 | u32 command; | |
536 | u32 chipid; | |
537 | ||
538 | hcd->uses_new_polling = 1; | |
db11e47d SS |
539 | |
540 | hcd->state = HC_STATE_RUNNING; | |
541 | isp1760_enable_interrupts(hcd); | |
bedc0c31 AB |
542 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
543 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN); | |
db11e47d | 544 | |
bedc0c31 | 545 | command = reg_read32(hcd->regs, HC_USBCMD); |
db11e47d SS |
546 | command &= ~(CMD_LRESET|CMD_RESET); |
547 | command |= CMD_RUN; | |
bedc0c31 | 548 | reg_write32(hcd->regs, HC_USBCMD, command); |
db11e47d | 549 | |
bedc0c31 | 550 | retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, |
db11e47d SS |
551 | 250 * 1000); |
552 | if (retval) | |
553 | return retval; | |
554 | ||
555 | /* | |
556 | * XXX | |
557 | * Spec says to write FLAG_CF as last config action, priv code grabs | |
558 | * the semaphore while doing so. | |
559 | */ | |
560 | down_write(&ehci_cf_port_reset_rwsem); | |
bedc0c31 | 561 | reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF); |
db11e47d | 562 | |
bedc0c31 | 563 | retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000); |
db11e47d SS |
564 | up_write(&ehci_cf_port_reset_rwsem); |
565 | if (retval) | |
566 | return retval; | |
567 | ||
bedc0c31 | 568 | chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG); |
6bda21bc AB |
569 | dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n", |
570 | chipid & 0xffff, chipid >> 16); | |
db11e47d SS |
571 | |
572 | /* PTD Register Init Part 2, Step 28 */ | |
573 | /* enable INTs */ | |
574 | isp1760_init_maps(hcd); | |
575 | ||
576 | /* GRR this is run-once init(), being done every time the HC starts. | |
577 | * So long as they're part of class devices, we can't do it init() | |
578 | * since the class device isn't created that early. | |
579 | */ | |
580 | return 0; | |
581 | } | |
582 | ||
583 | static u32 base_to_chip(u32 base) | |
584 | { | |
585 | return ((base - 0x400) >> 3); | |
586 | } | |
587 | ||
7adc14b1 AB |
588 | static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) |
589 | { | |
590 | struct urb *urb; | |
591 | ||
592 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) | |
593 | return 1; | |
594 | ||
595 | urb = qtd->urb; | |
596 | qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); | |
597 | return (qtd->urb != urb); | |
598 | } | |
599 | ||
6bda21bc | 600 | static void transform_into_atl(struct isp1760_qh *qh, |
a041d8e4 | 601 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 602 | { |
db11e47d SS |
603 | u32 maxpacket; |
604 | u32 multi; | |
605 | u32 pid_code; | |
606 | u32 rl = RL_COUNTER; | |
607 | u32 nak = NAK_COUNTER; | |
608 | ||
bedc0c31 AB |
609 | memset(ptd, 0, sizeof(*ptd)); |
610 | ||
db11e47d | 611 | /* according to 3.6.2, max packet len can not be > 0x400 */ |
a041d8e4 AB |
612 | maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe, |
613 | usb_pipeout(qtd->urb->pipe)); | |
db11e47d SS |
614 | multi = 1 + ((maxpacket >> 11) & 0x3); |
615 | maxpacket &= 0x7ff; | |
616 | ||
617 | /* DW0 */ | |
bedc0c31 AB |
618 | ptd->dw0 = PTD_VALID; |
619 | ptd->dw0 |= PTD_LENGTH(qtd->length); | |
620 | ptd->dw0 |= PTD_MAXPACKET(maxpacket); | |
a041d8e4 | 621 | ptd->dw0 |= PTD_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); |
db11e47d SS |
622 | |
623 | /* DW1 */ | |
a041d8e4 AB |
624 | ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1; |
625 | ptd->dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); | |
db11e47d SS |
626 | |
627 | pid_code = qtd->packet_type; | |
bedc0c31 | 628 | ptd->dw1 |= PTD_PID_TOKEN(pid_code); |
db11e47d | 629 | |
a041d8e4 | 630 | if (usb_pipebulk(qtd->urb->pipe)) |
bedc0c31 | 631 | ptd->dw1 |= PTD_TRANS_BULK; |
a041d8e4 | 632 | else if (usb_pipeint(qtd->urb->pipe)) |
bedc0c31 | 633 | ptd->dw1 |= PTD_TRANS_INT; |
db11e47d | 634 | |
a041d8e4 | 635 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) { |
db11e47d SS |
636 | /* split transaction */ |
637 | ||
bedc0c31 | 638 | ptd->dw1 |= PTD_TRANS_SPLIT; |
a041d8e4 | 639 | if (qtd->urb->dev->speed == USB_SPEED_LOW) |
bedc0c31 | 640 | ptd->dw1 |= PTD_SE_USB_LOSPEED; |
db11e47d | 641 | |
a041d8e4 AB |
642 | ptd->dw1 |= PTD_PORT_NUM(qtd->urb->dev->ttport); |
643 | ptd->dw1 |= PTD_HUB_NUM(qtd->urb->dev->tt->hub->devnum); | |
db11e47d SS |
644 | |
645 | /* SE bit for Split INT transfers */ | |
a041d8e4 AB |
646 | if (usb_pipeint(qtd->urb->pipe) && |
647 | (qtd->urb->dev->speed == USB_SPEED_LOW)) | |
bedc0c31 | 648 | ptd->dw1 |= 2 << 16; |
db11e47d | 649 | |
bedc0c31 | 650 | ptd->dw3 = 0; |
db11e47d SS |
651 | rl = 0; |
652 | nak = 0; | |
653 | } else { | |
bedc0c31 | 654 | ptd->dw0 |= PTD_MULTI(multi); |
a041d8e4 AB |
655 | if (usb_pipecontrol(qtd->urb->pipe) || |
656 | usb_pipebulk(qtd->urb->pipe)) | |
bedc0c31 | 657 | ptd->dw3 = qh->ping; |
db11e47d | 658 | else |
bedc0c31 | 659 | ptd->dw3 = 0; |
db11e47d SS |
660 | } |
661 | /* DW2 */ | |
bedc0c31 | 662 | ptd->dw2 = 0; |
a041d8e4 | 663 | ptd->dw2 |= PTD_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); |
bedc0c31 AB |
664 | ptd->dw2 |= PTD_RL_CNT(rl); |
665 | ptd->dw3 |= PTD_NAC_CNT(nak); | |
db11e47d SS |
666 | |
667 | /* DW3 */ | |
7adc14b1 AB |
668 | ptd->dw3 |= qh->toggle; |
669 | if (usb_pipecontrol(qtd->urb->pipe)) { | |
670 | if (qtd->data_buffer == qtd->urb->setup_packet) | |
671 | ptd->dw3 &= ~PTD_DATA_TOGGLE(1); | |
672 | else if (last_qtd_of_urb(qtd, qh)) | |
673 | ptd->dw3 |= PTD_DATA_TOGGLE(1); | |
674 | } | |
db11e47d | 675 | |
bedc0c31 | 676 | ptd->dw3 |= PTD_ACTIVE; |
db11e47d | 677 | /* Cerr */ |
bedc0c31 | 678 | ptd->dw3 |= PTD_CERR(ERR_COUNTER); |
db11e47d SS |
679 | } |
680 | ||
6bda21bc | 681 | static void transform_add_int(struct isp1760_qh *qh, |
a041d8e4 | 682 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 683 | { |
65f1b525 | 684 | u32 usof; |
db11e47d SS |
685 | u32 period; |
686 | ||
65f1b525 AB |
687 | /* |
688 | * Most of this is guessing. ISP1761 datasheet is quite unclear, and | |
689 | * the algorithm from the original Philips driver code, which was | |
690 | * pretty much used in this driver before as well, is quite horrendous | |
691 | * and, i believe, incorrect. The code below follows the datasheet and | |
692 | * USB2.0 spec as far as I can tell, and plug/unplug seems to be much | |
693 | * more reliable this way (fingers crossed...). | |
694 | */ | |
db11e47d | 695 | |
65f1b525 AB |
696 | if (qtd->urb->dev->speed == USB_SPEED_HIGH) { |
697 | /* urb->interval is in units of microframes (1/8 ms) */ | |
698 | period = qtd->urb->interval >> 3; | |
699 | ||
700 | if (qtd->urb->interval > 4) | |
701 | usof = 0x01; /* One bit set => | |
702 | interval 1 ms * uFrame-match */ | |
703 | else if (qtd->urb->interval > 2) | |
704 | usof = 0x22; /* Two bits set => interval 1/2 ms */ | |
705 | else if (qtd->urb->interval > 1) | |
706 | usof = 0x55; /* Four bits set => interval 1/4 ms */ | |
db11e47d | 707 | else |
65f1b525 | 708 | usof = 0xff; /* All bits set => interval 1/8 ms */ |
db11e47d | 709 | } else { |
65f1b525 AB |
710 | /* urb->interval is in units of frames (1 ms) */ |
711 | period = qtd->urb->interval; | |
712 | usof = 0x0f; /* Execute Start Split on any of the | |
713 | four first uFrames */ | |
714 | ||
715 | /* | |
716 | * First 8 bits in dw5 is uSCS and "specifies which uSOF the | |
717 | * complete split needs to be sent. Valid only for IN." Also, | |
718 | * "All bits can be set to one for every transfer." (p 82, | |
719 | * ISP1761 data sheet.) 0x1c is from Philips driver. Where did | |
720 | * that number come from? 0xff seems to work fine... | |
721 | */ | |
722 | /* ptd->dw5 = 0x1c; */ | |
723 | ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */ | |
db11e47d SS |
724 | } |
725 | ||
65f1b525 AB |
726 | period = period >> 1;/* Ensure equal or shorter period than requested */ |
727 | period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */ | |
728 | ||
bedc0c31 AB |
729 | ptd->dw2 |= period; |
730 | ptd->dw4 = usof; | |
db11e47d SS |
731 | } |
732 | ||
6bda21bc | 733 | static void transform_into_int(struct isp1760_qh *qh, |
a041d8e4 | 734 | struct isp1760_qtd *qtd, struct ptd *ptd) |
db11e47d | 735 | { |
6bda21bc AB |
736 | transform_into_atl(qh, qtd, ptd); |
737 | transform_add_int(qh, qtd, ptd); | |
db11e47d SS |
738 | } |
739 | ||
6bda21bc | 740 | static int check_error(struct usb_hcd *hcd, struct ptd *ptd) |
db11e47d SS |
741 | { |
742 | int error = 0; | |
db11e47d | 743 | |
bedc0c31 | 744 | if (ptd->dw3 & DW3_HALT_BIT) { |
db11e47d SS |
745 | error = -EPIPE; |
746 | ||
bedc0c31 | 747 | if (ptd->dw3 & DW3_ERROR_BIT) |
0954e1c2 | 748 | pr_err("error bit is set in DW3\n"); |
db11e47d SS |
749 | } |
750 | ||
bedc0c31 | 751 | if (ptd->dw3 & DW3_QTD_ACTIVE) { |
6bda21bc AB |
752 | dev_err(hcd->self.controller, "Transfer active bit is set DW3\n" |
753 | "nak counter: %d, rl: %d\n", | |
754 | (ptd->dw3 >> 19) & 0xf, (ptd->dw2 >> 25) & 0xf); | |
db11e47d SS |
755 | } |
756 | ||
757 | return error; | |
758 | } | |
759 | ||
6bda21bc | 760 | static void check_int_err_status(struct usb_hcd *hcd, u32 dw4) |
db11e47d SS |
761 | { |
762 | u32 i; | |
763 | ||
764 | dw4 >>= 8; | |
765 | ||
766 | for (i = 0; i < 8; i++) { | |
767 | switch (dw4 & 0x7) { | |
768 | case INT_UNDERRUN: | |
6bda21bc | 769 | dev_err(hcd->self.controller, "Underrun (%d)\n", i); |
db11e47d SS |
770 | break; |
771 | ||
772 | case INT_EXACT: | |
6bda21bc AB |
773 | dev_err(hcd->self.controller, |
774 | "Transaction error (%d)\n", i); | |
db11e47d SS |
775 | break; |
776 | ||
777 | case INT_BABBLE: | |
6bda21bc | 778 | dev_err(hcd->self.controller, "Babble error (%d)\n", i); |
db11e47d SS |
779 | break; |
780 | } | |
781 | dw4 >>= 3; | |
782 | } | |
783 | } | |
784 | ||
6bda21bc | 785 | static void enqueue_one_qtd(struct usb_hcd *hcd, struct isp1760_qtd *qtd) |
db11e47d | 786 | { |
a041d8e4 AB |
787 | if (qtd->length && (qtd->length <= MAX_PAYLOAD_SIZE)) { |
788 | switch (qtd->packet_type) { | |
db11e47d SS |
789 | case IN_PID: |
790 | break; | |
791 | case OUT_PID: | |
792 | case SETUP_PID: | |
a041d8e4 AB |
793 | mem_writes8(hcd->regs, qtd->payload_addr, |
794 | qtd->data_buffer, qtd->length); | |
db11e47d SS |
795 | } |
796 | } | |
797 | } | |
798 | ||
6bda21bc AB |
799 | static void enqueue_one_atl_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, |
800 | u32 slot, struct isp1760_qtd *qtd) | |
db11e47d | 801 | { |
6bda21bc | 802 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d | 803 | struct ptd ptd; |
db11e47d | 804 | |
6bda21bc AB |
805 | alloc_mem(hcd, qtd); |
806 | transform_into_atl(qh, qtd, &ptd); | |
bedc0c31 | 807 | ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); |
6bda21bc | 808 | enqueue_one_qtd(hcd, qtd); |
db11e47d | 809 | |
db11e47d SS |
810 | priv->atl_ints[slot].qh = qh; |
811 | priv->atl_ints[slot].qtd = qtd; | |
fd436aee | 812 | qtd->status |= URB_ENQUEUED; |
db11e47d SS |
813 | qtd->status |= slot << 16; |
814 | } | |
815 | ||
6bda21bc AB |
816 | static void enqueue_one_int_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, |
817 | u32 slot, struct isp1760_qtd *qtd) | |
db11e47d | 818 | { |
6bda21bc | 819 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d | 820 | struct ptd ptd; |
db11e47d | 821 | |
6bda21bc AB |
822 | alloc_mem(hcd, qtd); |
823 | transform_into_int(qh, qtd, &ptd); | |
bedc0c31 | 824 | ptd_write(hcd->regs, INT_PTD_OFFSET, slot, &ptd); |
6bda21bc | 825 | enqueue_one_qtd(hcd, qtd); |
db11e47d | 826 | |
db11e47d SS |
827 | priv->int_ints[slot].qh = qh; |
828 | priv->int_ints[slot].qtd = qtd; | |
fd436aee | 829 | qtd->status |= URB_ENQUEUED; |
db11e47d SS |
830 | qtd->status |= slot << 16; |
831 | } | |
832 | ||
473bca94 AB |
833 | static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, |
834 | struct isp1760_qtd *qtd) | |
db11e47d SS |
835 | { |
836 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
eb1a7968 | 837 | u32 skip_map; |
db11e47d | 838 | u32 slot; |
db11e47d | 839 | |
e6bdfe36 CM |
840 | /* |
841 | * When this function is called from the interrupt handler to enqueue | |
842 | * a follow-up packet, the SKIP register gets written and read back | |
843 | * almost immediately. With ISP1761, this register requires a delay of | |
844 | * 195ns between a write and subsequent read (see section 15.1.1.3). | |
845 | */ | |
ebb8a4e4 | 846 | mmiowb(); |
e6bdfe36 | 847 | ndelay(195); |
bedc0c31 | 848 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); |
db11e47d SS |
849 | |
850 | BUG_ON(!skip_map); | |
851 | slot = __ffs(skip_map); | |
db11e47d | 852 | |
6bda21bc | 853 | enqueue_one_atl_qtd(hcd, qh, slot, qtd); |
db11e47d | 854 | |
6bda21bc | 855 | skip_map &= ~(1 << slot); |
bedc0c31 | 856 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); |
db11e47d | 857 | |
b14e840d SAS |
858 | priv->atl_queued++; |
859 | if (priv->atl_queued == 2) | |
bedc0c31 AB |
860 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, |
861 | INTERRUPT_ENABLE_SOT_MASK); | |
db11e47d SS |
862 | } |
863 | ||
473bca94 AB |
864 | static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh, |
865 | struct isp1760_qtd *qtd) | |
db11e47d | 866 | { |
eb1a7968 | 867 | u32 skip_map; |
db11e47d | 868 | u32 slot; |
db11e47d | 869 | |
e6bdfe36 CM |
870 | /* |
871 | * When this function is called from the interrupt handler to enqueue | |
872 | * a follow-up packet, the SKIP register gets written and read back | |
873 | * almost immediately. With ISP1761, this register requires a delay of | |
874 | * 195ns between a write and subsequent read (see section 15.1.1.3). | |
875 | */ | |
ebb8a4e4 | 876 | mmiowb(); |
e6bdfe36 | 877 | ndelay(195); |
bedc0c31 | 878 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
db11e47d SS |
879 | |
880 | BUG_ON(!skip_map); | |
881 | slot = __ffs(skip_map); | |
db11e47d | 882 | |
6bda21bc | 883 | enqueue_one_int_qtd(hcd, qh, slot, qtd); |
db11e47d | 884 | |
6bda21bc | 885 | skip_map &= ~(1 << slot); |
bedc0c31 | 886 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); |
db11e47d SS |
887 | } |
888 | ||
6bda21bc | 889 | static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) |
db11e47d SS |
890 | __releases(priv->lock) |
891 | __acquires(priv->lock) | |
892 | { | |
6bda21bc AB |
893 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
894 | ||
db11e47d | 895 | if (!urb->unlinked) { |
6bda21bc AB |
896 | if (urb->status == -EINPROGRESS) |
897 | urb->status = 0; | |
db11e47d SS |
898 | } |
899 | ||
db8516f6 CM |
900 | if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { |
901 | void *ptr; | |
902 | for (ptr = urb->transfer_buffer; | |
903 | ptr < urb->transfer_buffer + urb->transfer_buffer_length; | |
904 | ptr += PAGE_SIZE) | |
905 | flush_dcache_page(virt_to_page(ptr)); | |
906 | } | |
907 | ||
db11e47d | 908 | /* complete() can reenter this HCD */ |
6bda21bc | 909 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
db11e47d | 910 | spin_unlock(&priv->lock); |
6bda21bc | 911 | usb_hcd_giveback_urb(hcd, urb, urb->status); |
db11e47d SS |
912 | spin_lock(&priv->lock); |
913 | } | |
914 | ||
34537731 AB |
915 | static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, |
916 | u8 packet_type) | |
db11e47d | 917 | { |
34537731 AB |
918 | struct isp1760_qtd *qtd; |
919 | ||
920 | qtd = kmem_cache_zalloc(qtd_cachep, flags); | |
921 | if (!qtd) | |
922 | return NULL; | |
923 | ||
924 | INIT_LIST_HEAD(&qtd->qtd_list); | |
925 | qtd->urb = urb; | |
926 | qtd->packet_type = packet_type; | |
927 | ||
928 | return qtd; | |
929 | } | |
930 | ||
931 | static void qtd_free(struct isp1760_qtd *qtd) | |
932 | { | |
933 | WARN_ON(qtd->payload_addr); | |
db11e47d SS |
934 | kmem_cache_free(qtd_cachep, qtd); |
935 | } | |
936 | ||
fd436aee AB |
937 | static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd, |
938 | struct isp1760_qh *qh) | |
db11e47d SS |
939 | { |
940 | struct isp1760_qtd *tmp_qtd; | |
941 | ||
fd436aee AB |
942 | if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) |
943 | tmp_qtd = NULL; | |
944 | else | |
945 | tmp_qtd = list_entry(qtd->qtd_list.next, struct isp1760_qtd, | |
946 | qtd_list); | |
db11e47d | 947 | list_del(&qtd->qtd_list); |
34537731 | 948 | qtd_free(qtd); |
db11e47d SS |
949 | return tmp_qtd; |
950 | } | |
951 | ||
952 | /* | |
953 | * Remove this QTD from the QH list and free its memory. If this QTD | |
954 | * isn't the last one than remove also his successor(s). | |
955 | * Returns the QTD which is part of an new URB and should be enqueued. | |
956 | */ | |
fd436aee AB |
957 | static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd, |
958 | struct isp1760_qh *qh) | |
db11e47d | 959 | { |
fd436aee | 960 | struct urb *urb; |
db11e47d | 961 | |
fd436aee | 962 | urb = qtd->urb; |
db11e47d | 963 | do { |
fd436aee AB |
964 | qtd = clean_this_qtd(qtd, qh); |
965 | } while (qtd && (qtd->urb == urb)); | |
db11e47d SS |
966 | |
967 | return qtd; | |
968 | } | |
969 | ||
bedc0c31 | 970 | static void do_atl_int(struct usb_hcd *hcd) |
db11e47d | 971 | { |
bedc0c31 | 972 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d SS |
973 | u32 done_map, skip_map; |
974 | struct ptd ptd; | |
6bda21bc AB |
975 | struct urb *urb; |
976 | u32 slot; | |
db11e47d | 977 | u32 length; |
db11e47d SS |
978 | u32 status = -EINVAL; |
979 | int error; | |
980 | struct isp1760_qtd *qtd; | |
981 | struct isp1760_qh *qh; | |
982 | u32 rl; | |
983 | u32 nakcount; | |
984 | ||
bedc0c31 AB |
985 | done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG); |
986 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); | |
db11e47d | 987 | |
db11e47d | 988 | while (done_map) { |
db11e47d | 989 | status = 0; |
b14e840d | 990 | priv->atl_queued--; |
db11e47d | 991 | |
6bda21bc AB |
992 | slot = __ffs(done_map); |
993 | done_map &= ~(1 << slot); | |
994 | skip_map |= (1 << slot); | |
db11e47d | 995 | |
6bda21bc AB |
996 | qtd = priv->atl_ints[slot].qtd; |
997 | qh = priv->atl_ints[slot].qh; | |
db11e47d | 998 | |
847ed3e8 AB |
999 | /* urb unlinked? */ |
1000 | if (!qh) | |
db11e47d | 1001 | continue; |
847ed3e8 | 1002 | |
6bda21bc | 1003 | ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); |
3f02a957 | 1004 | |
bedc0c31 AB |
1005 | rl = (ptd.dw2 >> 25) & 0x0f; |
1006 | nakcount = (ptd.dw3 >> 19) & 0xf; | |
db11e47d SS |
1007 | |
1008 | /* Transfer Error, *but* active and no HALT -> reload */ | |
bedc0c31 AB |
1009 | if ((ptd.dw3 & DW3_ERROR_BIT) && (ptd.dw3 & DW3_QTD_ACTIVE) && |
1010 | !(ptd.dw3 & DW3_HALT_BIT)) { | |
db11e47d SS |
1011 | |
1012 | /* according to ppriv code, we have to | |
1013 | * reload this one if trasfered bytes != requested bytes | |
1014 | * else act like everything went smooth.. | |
1015 | * XXX This just doesn't feel right and hasn't | |
1016 | * triggered so far. | |
1017 | */ | |
1018 | ||
bedc0c31 | 1019 | length = PTD_XFERRED_LENGTH(ptd.dw3); |
6bda21bc AB |
1020 | dev_err(hcd->self.controller, |
1021 | "Should reload now... transferred %d " | |
db11e47d SS |
1022 | "of %zu\n", length, qtd->length); |
1023 | BUG(); | |
1024 | } | |
1025 | ||
bedc0c31 | 1026 | if (!nakcount && (ptd.dw3 & DW3_QTD_ACTIVE)) { |
c0d74142 | 1027 | /* |
db11e47d SS |
1028 | * NAKs are handled in HW by the chip. Usually if the |
1029 | * device is not able to send data fast enough. | |
c0d74142 | 1030 | * This happens mostly on slower hardware. |
db11e47d | 1031 | */ |
db11e47d SS |
1032 | |
1033 | /* RL counter = ERR counter */ | |
bedc0c31 AB |
1034 | ptd.dw3 &= ~(0xf << 19); |
1035 | ptd.dw3 |= rl << 19; | |
1036 | ptd.dw3 &= ~(3 << (55 - 32)); | |
1037 | ptd.dw3 |= ERR_COUNTER << (55 - 32); | |
db11e47d SS |
1038 | |
1039 | /* | |
1040 | * It is not needed to write skip map back because it | |
1041 | * is unchanged. Just make sure that this entry is | |
1042 | * unskipped once it gets written to the HW. | |
1043 | */ | |
6bda21bc | 1044 | skip_map &= ~(1 << slot); |
db11e47d | 1045 | |
bedc0c31 | 1046 | ptd.dw0 |= PTD_VALID; |
6bda21bc | 1047 | ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd); |
db11e47d | 1048 | |
b14e840d SAS |
1049 | priv->atl_queued++; |
1050 | if (priv->atl_queued == 2) | |
bedc0c31 AB |
1051 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, |
1052 | INTERRUPT_ENABLE_SOT_MASK); | |
db11e47d SS |
1053 | continue; |
1054 | } | |
1055 | ||
6bda21bc | 1056 | error = check_error(hcd, &ptd); |
db11e47d SS |
1057 | if (error) { |
1058 | status = error; | |
6bda21bc AB |
1059 | priv->atl_ints[slot].qh->toggle = 0; |
1060 | priv->atl_ints[slot].qh->ping = 0; | |
1061 | qtd->urb->status = -EPIPE; | |
db11e47d SS |
1062 | |
1063 | #if 0 | |
1064 | printk(KERN_ERR "Error in %s().\n", __func__); | |
1065 | printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x " | |
1066 | "dw3: %08x dw4: %08x dw5: %08x dw6: " | |
1067 | "%08x dw7: %08x\n", | |
1068 | ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, | |
1069 | ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); | |
1070 | #endif | |
1071 | } else { | |
7adc14b1 AB |
1072 | priv->atl_ints[slot].qh->toggle = ptd.dw3 & (1 << 25); |
1073 | priv->atl_ints[slot].qh->ping = ptd.dw3 & (1 << 26); | |
db11e47d SS |
1074 | } |
1075 | ||
bedc0c31 | 1076 | length = PTD_XFERRED_LENGTH(ptd.dw3); |
db11e47d | 1077 | if (length) { |
bedc0c31 | 1078 | switch (DW1_GET_PID(ptd.dw1)) { |
db11e47d | 1079 | case IN_PID: |
a041d8e4 | 1080 | mem_reads8(hcd->regs, qtd->payload_addr, |
bbaa3876 | 1081 | qtd->data_buffer, length); |
db11e47d SS |
1082 | |
1083 | case OUT_PID: | |
1084 | ||
6bda21bc | 1085 | qtd->urb->actual_length += length; |
db11e47d SS |
1086 | |
1087 | case SETUP_PID: | |
1088 | break; | |
1089 | } | |
1090 | } | |
1091 | ||
6bda21bc AB |
1092 | priv->atl_ints[slot].qtd = NULL; |
1093 | priv->atl_ints[slot].qh = NULL; | |
db11e47d | 1094 | |
6bda21bc | 1095 | free_mem(hcd, qtd); |
db11e47d | 1096 | |
bedc0c31 | 1097 | reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map); |
db11e47d | 1098 | |
6bda21bc | 1099 | if (qtd->urb->status == -EPIPE) { |
db11e47d SS |
1100 | /* HALT was received */ |
1101 | ||
6bda21bc | 1102 | urb = qtd->urb; |
fd436aee | 1103 | qtd = clean_up_qtdlist(qtd, qh); |
6bda21bc | 1104 | isp1760_urb_done(hcd, urb); |
db11e47d | 1105 | |
6bda21bc AB |
1106 | } else if (usb_pipebulk(qtd->urb->pipe) && |
1107 | (length < qtd->length)) { | |
db11e47d SS |
1108 | /* short BULK received */ |
1109 | ||
6bda21bc AB |
1110 | if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) { |
1111 | qtd->urb->status = -EREMOTEIO; | |
1112 | dev_dbg(hcd->self.controller, | |
1113 | "short bulk, %d instead %zu " | |
1114 | "with URB_SHORT_NOT_OK flag.\n", | |
1115 | length, qtd->length); | |
db11e47d SS |
1116 | } |
1117 | ||
6bda21bc AB |
1118 | if (qtd->urb->status == -EINPROGRESS) |
1119 | qtd->urb->status = 0; | |
db11e47d | 1120 | |
6bda21bc | 1121 | urb = qtd->urb; |
fd436aee | 1122 | qtd = clean_up_qtdlist(qtd, qh); |
6bda21bc | 1123 | isp1760_urb_done(hcd, urb); |
db11e47d | 1124 | |
fd436aee | 1125 | } else if (last_qtd_of_urb(qtd, qh)) { |
db11e47d SS |
1126 | /* that was the last qtd of that URB */ |
1127 | ||
6bda21bc AB |
1128 | if (qtd->urb->status == -EINPROGRESS) |
1129 | qtd->urb->status = 0; | |
db11e47d | 1130 | |
6bda21bc AB |
1131 | urb = qtd->urb; |
1132 | qtd = clean_up_qtdlist(qtd, qh); | |
1133 | isp1760_urb_done(hcd, urb); | |
db11e47d SS |
1134 | |
1135 | } else { | |
1136 | /* next QTD of this URB */ | |
1137 | ||
fd436aee | 1138 | qtd = clean_this_qtd(qtd, qh); |
db11e47d SS |
1139 | BUG_ON(!qtd); |
1140 | } | |
1141 | ||
1142 | if (qtd) | |
bedc0c31 | 1143 | enqueue_an_ATL_packet(hcd, qh, qtd); |
db11e47d | 1144 | |
bedc0c31 | 1145 | skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG); |
db11e47d | 1146 | } |
b14e840d | 1147 | if (priv->atl_queued <= 1) |
bedc0c31 AB |
1148 | reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, |
1149 | INTERRUPT_ENABLE_MASK); | |
db11e47d SS |
1150 | } |
1151 | ||
bedc0c31 | 1152 | static void do_intl_int(struct usb_hcd *hcd) |
db11e47d | 1153 | { |
bedc0c31 | 1154 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d SS |
1155 | u32 done_map, skip_map; |
1156 | struct ptd ptd; | |
6bda21bc | 1157 | struct urb *urb; |
db11e47d | 1158 | u32 length; |
db11e47d | 1159 | int error; |
6bda21bc | 1160 | u32 slot; |
db11e47d SS |
1161 | struct isp1760_qtd *qtd; |
1162 | struct isp1760_qh *qh; | |
1163 | ||
bedc0c31 AB |
1164 | done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG); |
1165 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); | |
db11e47d | 1166 | |
db11e47d | 1167 | while (done_map) { |
6bda21bc AB |
1168 | slot = __ffs(done_map); |
1169 | done_map &= ~(1 << slot); | |
1170 | skip_map |= (1 << slot); | |
db11e47d | 1171 | |
6bda21bc AB |
1172 | qtd = priv->int_ints[slot].qtd; |
1173 | qh = priv->int_ints[slot].qh; | |
db11e47d | 1174 | |
847ed3e8 AB |
1175 | /* urb unlinked? */ |
1176 | if (!qh) | |
db11e47d | 1177 | continue; |
db11e47d | 1178 | |
6bda21bc AB |
1179 | ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd); |
1180 | check_int_err_status(hcd, ptd.dw4); | |
db11e47d | 1181 | |
6bda21bc | 1182 | error = check_error(hcd, &ptd); |
db11e47d SS |
1183 | if (error) { |
1184 | #if 0 | |
1185 | printk(KERN_ERR "Error in %s().\n", __func__); | |
1186 | printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x " | |
1187 | "dw3: %08x dw4: %08x dw5: %08x dw6: " | |
1188 | "%08x dw7: %08x\n", | |
1189 | ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3, | |
1190 | ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7); | |
1191 | #endif | |
6bda21bc AB |
1192 | qtd->urb->status = -EPIPE; |
1193 | priv->int_ints[slot].qh->toggle = 0; | |
1194 | priv->int_ints[slot].qh->ping = 0; | |
db11e47d SS |
1195 | |
1196 | } else { | |
6bda21bc AB |
1197 | priv->int_ints[slot].qh->toggle = ptd.dw3 & (1 << 25); |
1198 | priv->int_ints[slot].qh->ping = ptd.dw3 & (1 << 26); | |
db11e47d SS |
1199 | } |
1200 | ||
6bda21bc | 1201 | if (qtd->urb->dev->speed != USB_SPEED_HIGH) |
bedc0c31 | 1202 | length = PTD_XFERRED_LENGTH_LO(ptd.dw3); |
db11e47d | 1203 | else |
bedc0c31 | 1204 | length = PTD_XFERRED_LENGTH(ptd.dw3); |
db11e47d SS |
1205 | |
1206 | if (length) { | |
bedc0c31 | 1207 | switch (DW1_GET_PID(ptd.dw1)) { |
db11e47d | 1208 | case IN_PID: |
a041d8e4 | 1209 | mem_reads8(hcd->regs, qtd->payload_addr, |
bbaa3876 | 1210 | qtd->data_buffer, length); |
db11e47d SS |
1211 | case OUT_PID: |
1212 | ||
6bda21bc | 1213 | qtd->urb->actual_length += length; |
db11e47d SS |
1214 | |
1215 | case SETUP_PID: | |
1216 | break; | |
1217 | } | |
1218 | } | |
1219 | ||
6bda21bc AB |
1220 | priv->int_ints[slot].qtd = NULL; |
1221 | priv->int_ints[slot].qh = NULL; | |
db11e47d | 1222 | |
bedc0c31 | 1223 | reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map); |
6bda21bc | 1224 | free_mem(hcd, qtd); |
db11e47d | 1225 | |
6bda21bc | 1226 | if (qtd->urb->status == -EPIPE) { |
db11e47d SS |
1227 | /* HALT received */ |
1228 | ||
6bda21bc AB |
1229 | urb = qtd->urb; |
1230 | qtd = clean_up_qtdlist(qtd, qh); | |
1231 | isp1760_urb_done(hcd, urb); | |
db11e47d | 1232 | |
fd436aee | 1233 | } else if (last_qtd_of_urb(qtd, qh)) { |
db11e47d | 1234 | |
6bda21bc AB |
1235 | if (qtd->urb->status == -EINPROGRESS) |
1236 | qtd->urb->status = 0; | |
db11e47d | 1237 | |
6bda21bc AB |
1238 | urb = qtd->urb; |
1239 | qtd = clean_up_qtdlist(qtd, qh); | |
1240 | isp1760_urb_done(hcd, urb); | |
db11e47d SS |
1241 | |
1242 | } else { | |
1243 | /* next QTD of this URB */ | |
1244 | ||
fd436aee | 1245 | qtd = clean_this_qtd(qtd, qh); |
db11e47d SS |
1246 | BUG_ON(!qtd); |
1247 | } | |
1248 | ||
1249 | if (qtd) | |
bedc0c31 | 1250 | enqueue_an_INT_packet(hcd, qh, qtd); |
db11e47d | 1251 | |
bedc0c31 | 1252 | skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG); |
db11e47d SS |
1253 | } |
1254 | } | |
1255 | ||
34537731 | 1256 | static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) |
db11e47d | 1257 | { |
34537731 | 1258 | qtd->data_buffer = databuffer; |
db11e47d | 1259 | |
34537731 AB |
1260 | if (len > MAX_PAYLOAD_SIZE) |
1261 | len = MAX_PAYLOAD_SIZE; | |
1262 | qtd->length = len; | |
db11e47d | 1263 | |
34537731 | 1264 | return qtd->length; |
db11e47d SS |
1265 | } |
1266 | ||
34537731 | 1267 | static void qtd_list_free(struct list_head *qtd_list) |
db11e47d | 1268 | { |
34537731 | 1269 | struct isp1760_qtd *qtd, *qtd_next; |
db11e47d | 1270 | |
34537731 | 1271 | list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { |
db11e47d | 1272 | list_del(&qtd->qtd_list); |
34537731 | 1273 | qtd_free(qtd); |
db11e47d SS |
1274 | } |
1275 | } | |
1276 | ||
db11e47d | 1277 | /* |
34537731 AB |
1278 | * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. |
1279 | * Also calculate the PID type (SETUP/IN/OUT) for each packet. | |
db11e47d | 1280 | */ |
6bda21bc | 1281 | #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) |
34537731 | 1282 | static void packetize_urb(struct usb_hcd *hcd, |
db11e47d SS |
1283 | struct urb *urb, struct list_head *head, gfp_t flags) |
1284 | { | |
fd436aee | 1285 | struct isp1760_qtd *qtd; |
db11e47d | 1286 | void *buf; |
34537731 AB |
1287 | int len, maxpacketsize; |
1288 | u8 packet_type; | |
db11e47d SS |
1289 | |
1290 | /* | |
1291 | * URBs map to sequences of QTDs: one logical transaction | |
1292 | */ | |
db11e47d | 1293 | |
34537731 AB |
1294 | if (!urb->transfer_buffer && urb->transfer_buffer_length) { |
1295 | /* XXX This looks like usb storage / SCSI bug */ | |
1296 | dev_err(hcd->self.controller, | |
1297 | "buf is null, dma is %08lx len is %d\n", | |
1298 | (long unsigned)urb->transfer_dma, | |
1299 | urb->transfer_buffer_length); | |
1300 | WARN_ON(1); | |
1301 | } | |
db11e47d | 1302 | |
34537731 AB |
1303 | if (usb_pipein(urb->pipe)) |
1304 | packet_type = IN_PID; | |
1305 | else | |
1306 | packet_type = OUT_PID; | |
db11e47d | 1307 | |
db11e47d | 1308 | if (usb_pipecontrol(urb->pipe)) { |
34537731 | 1309 | qtd = qtd_alloc(flags, urb, SETUP_PID); |
db11e47d SS |
1310 | if (!qtd) |
1311 | goto cleanup; | |
34537731 | 1312 | qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); |
db11e47d SS |
1313 | list_add_tail(&qtd->qtd_list, head); |
1314 | ||
1315 | /* for zero length DATA stages, STATUS is always IN */ | |
34537731 AB |
1316 | if (urb->transfer_buffer_length == 0) |
1317 | packet_type = IN_PID; | |
db11e47d SS |
1318 | } |
1319 | ||
34537731 AB |
1320 | maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, |
1321 | usb_pipeout(urb->pipe))); | |
db11e47d SS |
1322 | |
1323 | /* | |
1324 | * buffer gets wrapped in one or more qtds; | |
1325 | * last one may be "short" (including zero len) | |
1326 | * and may serve as a control status ack | |
1327 | */ | |
34537731 AB |
1328 | buf = urb->transfer_buffer; |
1329 | len = urb->transfer_buffer_length; | |
1330 | ||
db11e47d SS |
1331 | for (;;) { |
1332 | int this_qtd_len; | |
1333 | ||
34537731 AB |
1334 | qtd = qtd_alloc(flags, urb, packet_type); |
1335 | if (!qtd) | |
1336 | goto cleanup; | |
1337 | this_qtd_len = qtd_fill(qtd, buf, len); | |
1338 | list_add_tail(&qtd->qtd_list, head); | |
db11e47d | 1339 | |
db11e47d SS |
1340 | len -= this_qtd_len; |
1341 | buf += this_qtd_len; | |
1342 | ||
db11e47d SS |
1343 | if (len <= 0) |
1344 | break; | |
db11e47d SS |
1345 | } |
1346 | ||
1347 | /* | |
1348 | * control requests may need a terminating data "status" ack; | |
1349 | * bulk ones may need a terminating short packet (zero length). | |
1350 | */ | |
1351 | if (urb->transfer_buffer_length != 0) { | |
1352 | int one_more = 0; | |
1353 | ||
1354 | if (usb_pipecontrol(urb->pipe)) { | |
1355 | one_more = 1; | |
34537731 AB |
1356 | if (packet_type == IN_PID) |
1357 | packet_type = OUT_PID; | |
1358 | else | |
1359 | packet_type = IN_PID; | |
db11e47d SS |
1360 | } else if (usb_pipebulk(urb->pipe) |
1361 | && (urb->transfer_flags & URB_ZERO_PACKET) | |
34537731 AB |
1362 | && !(urb->transfer_buffer_length % |
1363 | maxpacketsize)) { | |
db11e47d SS |
1364 | one_more = 1; |
1365 | } | |
1366 | if (one_more) { | |
34537731 | 1367 | qtd = qtd_alloc(flags, urb, packet_type); |
db11e47d SS |
1368 | if (!qtd) |
1369 | goto cleanup; | |
db11e47d SS |
1370 | |
1371 | /* never any data in such packets */ | |
34537731 AB |
1372 | qtd_fill(qtd, NULL, 0); |
1373 | list_add_tail(&qtd->qtd_list, head); | |
db11e47d SS |
1374 | } |
1375 | } | |
1376 | ||
34537731 | 1377 | return; |
db11e47d SS |
1378 | |
1379 | cleanup: | |
34537731 AB |
1380 | qtd_list_free(head); |
1381 | } | |
1382 | ||
1383 | static int enqueue_qtdlist(struct usb_hcd *hcd, struct urb *urb, | |
1384 | struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p) | |
1385 | { | |
1386 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1387 | struct isp1760_qtd *qtd; | |
1388 | struct isp1760_qh *qh = NULL; | |
1389 | unsigned long flags; | |
1390 | int qh_empty; | |
1391 | int rc; | |
1392 | ||
1393 | spin_lock_irqsave(&priv->lock, flags); | |
1394 | if (!HCD_HW_ACCESSIBLE(hcd)) { | |
1395 | rc = -ESHUTDOWN; | |
1396 | goto done; | |
1397 | } | |
1398 | rc = usb_hcd_link_urb_to_ep(hcd, urb); | |
1399 | if (rc) | |
1400 | goto done; | |
1401 | ||
1402 | qh = urb->ep->hcpriv; | |
1403 | if (!qh) { | |
1404 | qh = isp1760_qh_alloc(GFP_ATOMIC); | |
1405 | if (!qh) { | |
1406 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
1407 | rc = -ENOMEM; | |
1408 | goto done; | |
1409 | } | |
1410 | if (!usb_pipecontrol(urb->pipe)) | |
1411 | usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), | |
1412 | !usb_pipein(urb->pipe), 1); | |
1413 | urb->ep->hcpriv = qh; | |
1414 | } | |
1415 | ||
1416 | qh_empty = list_empty(&qh->qtd_list); | |
1417 | list_splice_tail(qtd_list, &qh->qtd_list); | |
1418 | if (qh_empty) { | |
1419 | qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list); | |
1420 | p(hcd, qh, qtd); | |
1421 | } | |
1422 | ||
1423 | done: | |
1424 | spin_unlock_irqrestore(&priv->lock, flags); | |
1425 | if (!qh) | |
1426 | qtd_list_free(qtd_list); | |
1427 | return rc; | |
db11e47d SS |
1428 | } |
1429 | ||
1430 | static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, | |
1431 | gfp_t mem_flags) | |
1432 | { | |
db11e47d SS |
1433 | struct list_head qtd_list; |
1434 | packet_enqueue *pe; | |
1435 | ||
1436 | INIT_LIST_HEAD(&qtd_list); | |
1437 | ||
1438 | switch (usb_pipetype(urb->pipe)) { | |
1439 | case PIPE_CONTROL: | |
1440 | case PIPE_BULK: | |
34537731 | 1441 | pe = enqueue_an_ATL_packet; |
db11e47d SS |
1442 | break; |
1443 | ||
1444 | case PIPE_INTERRUPT: | |
db11e47d SS |
1445 | pe = enqueue_an_INT_packet; |
1446 | break; | |
1447 | ||
1448 | case PIPE_ISOCHRONOUS: | |
6bda21bc | 1449 | dev_err(hcd->self.controller, "PIPE_ISOCHRONOUS ain't supported\n"); |
db11e47d SS |
1450 | default: |
1451 | return -EPIPE; | |
1452 | } | |
1453 | ||
34537731 AB |
1454 | packetize_urb(hcd, urb, &qtd_list, mem_flags); |
1455 | if (list_empty(&qtd_list)) | |
1456 | return -ENOMEM; | |
1457 | ||
1458 | return enqueue_qtdlist(hcd, urb, &qtd_list, mem_flags, pe); | |
db11e47d SS |
1459 | } |
1460 | ||
6bda21bc | 1461 | static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
db11e47d SS |
1462 | { |
1463 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1464 | struct inter_packet_info *ints; | |
1465 | u32 i; | |
eb1a7968 | 1466 | u32 reg_base, skip_reg; |
d249afdd | 1467 | unsigned long flags; |
db11e47d | 1468 | struct ptd ptd; |
0afb20e0 | 1469 | packet_enqueue *pe; |
db11e47d SS |
1470 | |
1471 | switch (usb_pipetype(urb->pipe)) { | |
1472 | case PIPE_ISOCHRONOUS: | |
1473 | return -EPIPE; | |
1474 | break; | |
1475 | ||
1476 | case PIPE_INTERRUPT: | |
1477 | ints = priv->int_ints; | |
bedc0c31 | 1478 | reg_base = INT_PTD_OFFSET; |
db11e47d | 1479 | skip_reg = HC_INT_PTD_SKIPMAP_REG; |
0afb20e0 | 1480 | pe = enqueue_an_INT_packet; |
db11e47d SS |
1481 | break; |
1482 | ||
1483 | default: | |
1484 | ints = priv->atl_ints; | |
bedc0c31 | 1485 | reg_base = ATL_PTD_OFFSET; |
db11e47d | 1486 | skip_reg = HC_ATL_PTD_SKIPMAP_REG; |
0afb20e0 | 1487 | pe = enqueue_an_ATL_packet; |
db11e47d SS |
1488 | break; |
1489 | } | |
1490 | ||
1491 | memset(&ptd, 0, sizeof(ptd)); | |
1492 | spin_lock_irqsave(&priv->lock, flags); | |
1493 | ||
1494 | for (i = 0; i < 32; i++) { | |
fd436aee AB |
1495 | if (!ints[i].qh) |
1496 | continue; | |
34537731 | 1497 | WARN_ON(!ints[i].qtd); |
fd436aee AB |
1498 | |
1499 | if (ints[i].qtd->urb == urb) { | |
db11e47d | 1500 | u32 skip_map; |
db11e47d | 1501 | struct isp1760_qtd *qtd; |
fd436aee | 1502 | struct isp1760_qh *qh; |
db11e47d | 1503 | |
bedc0c31 | 1504 | skip_map = reg_read32(hcd->regs, skip_reg); |
db11e47d | 1505 | skip_map |= 1 << i; |
bedc0c31 | 1506 | reg_write32(hcd->regs, skip_reg, skip_map); |
db11e47d | 1507 | |
bedc0c31 | 1508 | ptd_write(hcd->regs, reg_base, i, &ptd); |
db11e47d | 1509 | |
d3cf2a8d | 1510 | qtd = ints[i].qtd; |
fd436aee | 1511 | qh = ints[i].qh; |
db11e47d | 1512 | |
6bda21bc | 1513 | free_mem(hcd, qtd); |
a041d8e4 | 1514 | qtd = clean_up_qtdlist(qtd, qh); |
db11e47d | 1515 | |
d3cf2a8d AB |
1516 | ints[i].qh = NULL; |
1517 | ints[i].qtd = NULL; | |
db11e47d | 1518 | |
22bea9ce | 1519 | urb->status = status; |
6bda21bc | 1520 | isp1760_urb_done(hcd, urb); |
0afb20e0 WF |
1521 | if (qtd) |
1522 | pe(hcd, qh, qtd); | |
db11e47d | 1523 | break; |
0afb20e0 | 1524 | |
fd436aee AB |
1525 | } else { |
1526 | struct isp1760_qtd *qtd; | |
0afb20e0 | 1527 | |
fd436aee AB |
1528 | list_for_each_entry(qtd, &ints[i].qtd->qtd_list, |
1529 | qtd_list) { | |
0afb20e0 | 1530 | if (qtd->urb == urb) { |
fd436aee | 1531 | clean_up_qtdlist(qtd, ints[i].qh); |
6bda21bc | 1532 | isp1760_urb_done(hcd, urb); |
fd436aee | 1533 | qtd = NULL; |
0afb20e0 WF |
1534 | break; |
1535 | } | |
0afb20e0 | 1536 | } |
fd436aee AB |
1537 | |
1538 | /* We found the urb before the last slot */ | |
1539 | if (!qtd) | |
0afb20e0 | 1540 | break; |
db11e47d | 1541 | } |
db11e47d SS |
1542 | } |
1543 | ||
1544 | spin_unlock_irqrestore(&priv->lock, flags); | |
1545 | return 0; | |
1546 | } | |
1547 | ||
6bda21bc | 1548 | static irqreturn_t isp1760_irq(struct usb_hcd *hcd) |
db11e47d | 1549 | { |
6bda21bc | 1550 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d SS |
1551 | u32 imask; |
1552 | irqreturn_t irqret = IRQ_NONE; | |
1553 | ||
1554 | spin_lock(&priv->lock); | |
1555 | ||
6bda21bc | 1556 | if (!(hcd->state & HC_STATE_RUNNING)) |
db11e47d SS |
1557 | goto leave; |
1558 | ||
6bda21bc | 1559 | imask = reg_read32(hcd->regs, HC_INTERRUPT_REG); |
db11e47d SS |
1560 | if (unlikely(!imask)) |
1561 | goto leave; | |
1562 | ||
753d8534 | 1563 | reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); |
b14e840d | 1564 | if (imask & (HC_ATL_INT | HC_SOT_INT)) |
6bda21bc | 1565 | do_atl_int(hcd); |
db11e47d SS |
1566 | |
1567 | if (imask & HC_INTL_INT) | |
6bda21bc | 1568 | do_intl_int(hcd); |
db11e47d SS |
1569 | |
1570 | irqret = IRQ_HANDLED; | |
1571 | leave: | |
1572 | spin_unlock(&priv->lock); | |
1573 | return irqret; | |
1574 | } | |
1575 | ||
1576 | static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf) | |
1577 | { | |
1578 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1579 | u32 temp, status = 0; | |
1580 | u32 mask; | |
1581 | int retval = 1; | |
1582 | unsigned long flags; | |
1583 | ||
1584 | /* if !USB_SUSPEND, root hub timers won't get shut down ... */ | |
1585 | if (!HC_IS_RUNNING(hcd->state)) | |
1586 | return 0; | |
1587 | ||
1588 | /* init status to no-changes */ | |
1589 | buf[0] = 0; | |
1590 | mask = PORT_CSC; | |
1591 | ||
1592 | spin_lock_irqsave(&priv->lock, flags); | |
bedc0c31 | 1593 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
db11e47d SS |
1594 | |
1595 | if (temp & PORT_OWNER) { | |
1596 | if (temp & PORT_CSC) { | |
1597 | temp &= ~PORT_CSC; | |
bedc0c31 | 1598 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
db11e47d SS |
1599 | goto done; |
1600 | } | |
1601 | } | |
1602 | ||
1603 | /* | |
1604 | * Return status information even for ports with OWNER set. | |
1605 | * Otherwise khubd wouldn't see the disconnect event when a | |
1606 | * high-speed device is switched over to the companion | |
1607 | * controller by the user. | |
1608 | */ | |
1609 | ||
1610 | if ((temp & mask) != 0 | |
1611 | || ((temp & PORT_RESUME) != 0 | |
1612 | && time_after_eq(jiffies, | |
1613 | priv->reset_done))) { | |
1614 | buf [0] |= 1 << (0 + 1); | |
1615 | status = STS_PCD; | |
1616 | } | |
1617 | /* FIXME autosuspend idle root hubs */ | |
1618 | done: | |
1619 | spin_unlock_irqrestore(&priv->lock, flags); | |
1620 | return status ? retval : 0; | |
1621 | } | |
1622 | ||
1623 | static void isp1760_hub_descriptor(struct isp1760_hcd *priv, | |
1624 | struct usb_hub_descriptor *desc) | |
1625 | { | |
1626 | int ports = HCS_N_PORTS(priv->hcs_params); | |
1627 | u16 temp; | |
1628 | ||
1629 | desc->bDescriptorType = 0x29; | |
1630 | /* priv 1.0, 2.3.9 says 20ms max */ | |
1631 | desc->bPwrOn2PwrGood = 10; | |
1632 | desc->bHubContrCurrent = 0; | |
1633 | ||
1634 | desc->bNbrPorts = ports; | |
1635 | temp = 1 + (ports / 8); | |
1636 | desc->bDescLength = 7 + 2 * temp; | |
1637 | ||
da13051c | 1638 | /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ |
dbe79bbe JY |
1639 | memset(&desc->u.hs.DeviceRemovable[0], 0, temp); |
1640 | memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); | |
db11e47d SS |
1641 | |
1642 | /* per-port overcurrent reporting */ | |
1643 | temp = 0x0008; | |
1644 | if (HCS_PPC(priv->hcs_params)) | |
1645 | /* per-port power control */ | |
1646 | temp |= 0x0001; | |
1647 | else | |
1648 | /* no power switching */ | |
1649 | temp |= 0x0002; | |
1650 | desc->wHubCharacteristics = cpu_to_le16(temp); | |
1651 | } | |
1652 | ||
1653 | #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E) | |
1654 | ||
bedc0c31 AB |
1655 | static int check_reset_complete(struct usb_hcd *hcd, int index, |
1656 | int port_status) | |
db11e47d SS |
1657 | { |
1658 | if (!(port_status & PORT_CONNECT)) | |
1659 | return port_status; | |
1660 | ||
1661 | /* if reset finished and it's still not enabled -- handoff */ | |
1662 | if (!(port_status & PORT_PE)) { | |
1663 | ||
6bda21bc AB |
1664 | dev_err(hcd->self.controller, |
1665 | "port %d full speed --> companion\n", | |
1666 | index + 1); | |
db11e47d SS |
1667 | |
1668 | port_status |= PORT_OWNER; | |
1669 | port_status &= ~PORT_RWC_BITS; | |
bedc0c31 | 1670 | reg_write32(hcd->regs, HC_PORTSC1, port_status); |
db11e47d SS |
1671 | |
1672 | } else | |
6bda21bc AB |
1673 | dev_err(hcd->self.controller, "port %d high speed\n", |
1674 | index + 1); | |
db11e47d SS |
1675 | |
1676 | return port_status; | |
1677 | } | |
1678 | ||
1679 | static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq, | |
1680 | u16 wValue, u16 wIndex, char *buf, u16 wLength) | |
1681 | { | |
1682 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1683 | int ports = HCS_N_PORTS(priv->hcs_params); | |
db11e47d SS |
1684 | u32 temp, status; |
1685 | unsigned long flags; | |
1686 | int retval = 0; | |
1687 | unsigned selector; | |
1688 | ||
1689 | /* | |
1690 | * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. | |
1691 | * HCS_INDICATOR may say we can change LEDs to off/amber/green. | |
1692 | * (track current state ourselves) ... blink for diagnostics, | |
1693 | * power, "this is the one", etc. EHCI spec supports this. | |
1694 | */ | |
1695 | ||
1696 | spin_lock_irqsave(&priv->lock, flags); | |
1697 | switch (typeReq) { | |
1698 | case ClearHubFeature: | |
1699 | switch (wValue) { | |
1700 | case C_HUB_LOCAL_POWER: | |
1701 | case C_HUB_OVER_CURRENT: | |
1702 | /* no hub-wide feature/status flags */ | |
1703 | break; | |
1704 | default: | |
1705 | goto error; | |
1706 | } | |
1707 | break; | |
1708 | case ClearPortFeature: | |
1709 | if (!wIndex || wIndex > ports) | |
1710 | goto error; | |
1711 | wIndex--; | |
bedc0c31 | 1712 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
db11e47d SS |
1713 | |
1714 | /* | |
1715 | * Even if OWNER is set, so the port is owned by the | |
1716 | * companion controller, khubd needs to be able to clear | |
1717 | * the port-change status bits (especially | |
749da5f8 | 1718 | * USB_PORT_STAT_C_CONNECTION). |
db11e47d SS |
1719 | */ |
1720 | ||
1721 | switch (wValue) { | |
1722 | case USB_PORT_FEAT_ENABLE: | |
bedc0c31 | 1723 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE); |
db11e47d SS |
1724 | break; |
1725 | case USB_PORT_FEAT_C_ENABLE: | |
1726 | /* XXX error? */ | |
1727 | break; | |
1728 | case USB_PORT_FEAT_SUSPEND: | |
1729 | if (temp & PORT_RESET) | |
1730 | goto error; | |
1731 | ||
1732 | if (temp & PORT_SUSPEND) { | |
1733 | if ((temp & PORT_PE) == 0) | |
1734 | goto error; | |
1735 | /* resume signaling for 20 msec */ | |
1736 | temp &= ~(PORT_RWC_BITS); | |
bedc0c31 AB |
1737 | reg_write32(hcd->regs, HC_PORTSC1, |
1738 | temp | PORT_RESUME); | |
db11e47d SS |
1739 | priv->reset_done = jiffies + |
1740 | msecs_to_jiffies(20); | |
1741 | } | |
1742 | break; | |
1743 | case USB_PORT_FEAT_C_SUSPEND: | |
1744 | /* we auto-clear this feature */ | |
1745 | break; | |
1746 | case USB_PORT_FEAT_POWER: | |
1747 | if (HCS_PPC(priv->hcs_params)) | |
bedc0c31 AB |
1748 | reg_write32(hcd->regs, HC_PORTSC1, |
1749 | temp & ~PORT_POWER); | |
db11e47d SS |
1750 | break; |
1751 | case USB_PORT_FEAT_C_CONNECTION: | |
bedc0c31 | 1752 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC); |
db11e47d SS |
1753 | break; |
1754 | case USB_PORT_FEAT_C_OVER_CURRENT: | |
1755 | /* XXX error ?*/ | |
1756 | break; | |
1757 | case USB_PORT_FEAT_C_RESET: | |
1758 | /* GetPortStatus clears reset */ | |
1759 | break; | |
1760 | default: | |
1761 | goto error; | |
1762 | } | |
bedc0c31 | 1763 | reg_read32(hcd->regs, HC_USBCMD); |
db11e47d SS |
1764 | break; |
1765 | case GetHubDescriptor: | |
1766 | isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *) | |
1767 | buf); | |
1768 | break; | |
1769 | case GetHubStatus: | |
1770 | /* no hub-wide feature/status flags */ | |
1771 | memset(buf, 0, 4); | |
1772 | break; | |
1773 | case GetPortStatus: | |
1774 | if (!wIndex || wIndex > ports) | |
1775 | goto error; | |
1776 | wIndex--; | |
1777 | status = 0; | |
bedc0c31 | 1778 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
db11e47d SS |
1779 | |
1780 | /* wPortChange bits */ | |
1781 | if (temp & PORT_CSC) | |
749da5f8 | 1782 | status |= USB_PORT_STAT_C_CONNECTION << 16; |
db11e47d SS |
1783 | |
1784 | ||
1785 | /* whoever resumes must GetPortStatus to complete it!! */ | |
1786 | if (temp & PORT_RESUME) { | |
6bda21bc | 1787 | dev_err(hcd->self.controller, "Port resume should be skipped.\n"); |
db11e47d SS |
1788 | |
1789 | /* Remote Wakeup received? */ | |
1790 | if (!priv->reset_done) { | |
1791 | /* resume signaling for 20 msec */ | |
1792 | priv->reset_done = jiffies | |
1793 | + msecs_to_jiffies(20); | |
1794 | /* check the port again */ | |
6bda21bc | 1795 | mod_timer(&hcd->rh_timer, priv->reset_done); |
db11e47d SS |
1796 | } |
1797 | ||
1798 | /* resume completed? */ | |
1799 | else if (time_after_eq(jiffies, | |
1800 | priv->reset_done)) { | |
749da5f8 | 1801 | status |= USB_PORT_STAT_C_SUSPEND << 16; |
db11e47d SS |
1802 | priv->reset_done = 0; |
1803 | ||
1804 | /* stop resume signaling */ | |
bedc0c31 AB |
1805 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
1806 | reg_write32(hcd->regs, HC_PORTSC1, | |
1807 | temp & ~(PORT_RWC_BITS | PORT_RESUME)); | |
1808 | retval = handshake(hcd, HC_PORTSC1, | |
db11e47d SS |
1809 | PORT_RESUME, 0, 2000 /* 2msec */); |
1810 | if (retval != 0) { | |
6bda21bc | 1811 | dev_err(hcd->self.controller, |
db11e47d SS |
1812 | "port %d resume error %d\n", |
1813 | wIndex + 1, retval); | |
1814 | goto error; | |
1815 | } | |
1816 | temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10)); | |
1817 | } | |
1818 | } | |
1819 | ||
1820 | /* whoever resets must GetPortStatus to complete it!! */ | |
1821 | if ((temp & PORT_RESET) | |
1822 | && time_after_eq(jiffies, | |
1823 | priv->reset_done)) { | |
749da5f8 | 1824 | status |= USB_PORT_STAT_C_RESET << 16; |
db11e47d SS |
1825 | priv->reset_done = 0; |
1826 | ||
1827 | /* force reset to complete */ | |
bedc0c31 | 1828 | reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET); |
db11e47d SS |
1829 | /* REVISIT: some hardware needs 550+ usec to clear |
1830 | * this bit; seems too long to spin routinely... | |
1831 | */ | |
bedc0c31 | 1832 | retval = handshake(hcd, HC_PORTSC1, |
db11e47d SS |
1833 | PORT_RESET, 0, 750); |
1834 | if (retval != 0) { | |
6bda21bc | 1835 | dev_err(hcd->self.controller, "port %d reset error %d\n", |
db11e47d SS |
1836 | wIndex + 1, retval); |
1837 | goto error; | |
1838 | } | |
1839 | ||
1840 | /* see what we found out */ | |
bedc0c31 AB |
1841 | temp = check_reset_complete(hcd, wIndex, |
1842 | reg_read32(hcd->regs, HC_PORTSC1)); | |
db11e47d SS |
1843 | } |
1844 | /* | |
1845 | * Even if OWNER is set, there's no harm letting khubd | |
1846 | * see the wPortStatus values (they should all be 0 except | |
1847 | * for PORT_POWER anyway). | |
1848 | */ | |
1849 | ||
1850 | if (temp & PORT_OWNER) | |
6bda21bc | 1851 | dev_err(hcd->self.controller, "PORT_OWNER is set\n"); |
db11e47d SS |
1852 | |
1853 | if (temp & PORT_CONNECT) { | |
749da5f8 | 1854 | status |= USB_PORT_STAT_CONNECTION; |
db11e47d | 1855 | /* status may be from integrated TT */ |
6bda21bc | 1856 | status |= USB_PORT_STAT_HIGH_SPEED; |
db11e47d SS |
1857 | } |
1858 | if (temp & PORT_PE) | |
749da5f8 | 1859 | status |= USB_PORT_STAT_ENABLE; |
db11e47d | 1860 | if (temp & (PORT_SUSPEND|PORT_RESUME)) |
749da5f8 | 1861 | status |= USB_PORT_STAT_SUSPEND; |
db11e47d | 1862 | if (temp & PORT_RESET) |
749da5f8 | 1863 | status |= USB_PORT_STAT_RESET; |
db11e47d | 1864 | if (temp & PORT_POWER) |
749da5f8 | 1865 | status |= USB_PORT_STAT_POWER; |
db11e47d SS |
1866 | |
1867 | put_unaligned(cpu_to_le32(status), (__le32 *) buf); | |
1868 | break; | |
1869 | case SetHubFeature: | |
1870 | switch (wValue) { | |
1871 | case C_HUB_LOCAL_POWER: | |
1872 | case C_HUB_OVER_CURRENT: | |
1873 | /* no hub-wide feature/status flags */ | |
1874 | break; | |
1875 | default: | |
1876 | goto error; | |
1877 | } | |
1878 | break; | |
1879 | case SetPortFeature: | |
1880 | selector = wIndex >> 8; | |
1881 | wIndex &= 0xff; | |
1882 | if (!wIndex || wIndex > ports) | |
1883 | goto error; | |
1884 | wIndex--; | |
bedc0c31 | 1885 | temp = reg_read32(hcd->regs, HC_PORTSC1); |
db11e47d SS |
1886 | if (temp & PORT_OWNER) |
1887 | break; | |
1888 | ||
1889 | /* temp &= ~PORT_RWC_BITS; */ | |
1890 | switch (wValue) { | |
1891 | case USB_PORT_FEAT_ENABLE: | |
bedc0c31 | 1892 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE); |
db11e47d SS |
1893 | break; |
1894 | ||
1895 | case USB_PORT_FEAT_SUSPEND: | |
1896 | if ((temp & PORT_PE) == 0 | |
1897 | || (temp & PORT_RESET) != 0) | |
1898 | goto error; | |
1899 | ||
bedc0c31 | 1900 | reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND); |
db11e47d SS |
1901 | break; |
1902 | case USB_PORT_FEAT_POWER: | |
1903 | if (HCS_PPC(priv->hcs_params)) | |
bedc0c31 AB |
1904 | reg_write32(hcd->regs, HC_PORTSC1, |
1905 | temp | PORT_POWER); | |
db11e47d SS |
1906 | break; |
1907 | case USB_PORT_FEAT_RESET: | |
1908 | if (temp & PORT_RESUME) | |
1909 | goto error; | |
1910 | /* line status bits may report this as low speed, | |
1911 | * which can be fine if this root hub has a | |
1912 | * transaction translator built in. | |
1913 | */ | |
1914 | if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT | |
1915 | && PORT_USB11(temp)) { | |
1916 | temp |= PORT_OWNER; | |
1917 | } else { | |
1918 | temp |= PORT_RESET; | |
1919 | temp &= ~PORT_PE; | |
1920 | ||
1921 | /* | |
1922 | * caller must wait, then call GetPortStatus | |
1923 | * usb 2.0 spec says 50 ms resets on root | |
1924 | */ | |
1925 | priv->reset_done = jiffies + | |
1926 | msecs_to_jiffies(50); | |
1927 | } | |
bedc0c31 | 1928 | reg_write32(hcd->regs, HC_PORTSC1, temp); |
db11e47d SS |
1929 | break; |
1930 | default: | |
1931 | goto error; | |
1932 | } | |
bedc0c31 | 1933 | reg_read32(hcd->regs, HC_USBCMD); |
db11e47d SS |
1934 | break; |
1935 | ||
1936 | default: | |
1937 | error: | |
1938 | /* "stall" on error */ | |
1939 | retval = -EPIPE; | |
1940 | } | |
1941 | spin_unlock_irqrestore(&priv->lock, flags); | |
1942 | return retval; | |
1943 | } | |
1944 | ||
6bda21bc | 1945 | static void isp1760_endpoint_disable(struct usb_hcd *hcd, |
db11e47d SS |
1946 | struct usb_host_endpoint *ep) |
1947 | { | |
6bda21bc | 1948 | struct isp1760_hcd *priv = hcd_to_priv(hcd); |
db11e47d SS |
1949 | struct isp1760_qh *qh; |
1950 | struct isp1760_qtd *qtd; | |
d249afdd | 1951 | unsigned long flags; |
db11e47d SS |
1952 | |
1953 | spin_lock_irqsave(&priv->lock, flags); | |
1954 | qh = ep->hcpriv; | |
1955 | if (!qh) | |
1956 | goto out; | |
1957 | ||
1958 | ep->hcpriv = NULL; | |
1959 | do { | |
1960 | /* more than entry might get removed */ | |
1961 | if (list_empty(&qh->qtd_list)) | |
1962 | break; | |
1963 | ||
1964 | qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd, | |
1965 | qtd_list); | |
1966 | ||
1967 | if (qtd->status & URB_ENQUEUED) { | |
db11e47d | 1968 | spin_unlock_irqrestore(&priv->lock, flags); |
6bda21bc | 1969 | isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET); |
db11e47d SS |
1970 | spin_lock_irqsave(&priv->lock, flags); |
1971 | } else { | |
1972 | struct urb *urb; | |
1973 | ||
1974 | urb = qtd->urb; | |
fd436aee | 1975 | clean_up_qtdlist(qtd, qh); |
6bda21bc AB |
1976 | urb->status = -ECONNRESET; |
1977 | isp1760_urb_done(hcd, urb); | |
db11e47d SS |
1978 | } |
1979 | } while (1); | |
1980 | ||
1981 | qh_destroy(qh); | |
1982 | /* remove requests and leak them. | |
1983 | * ATL are pretty fast done, INT could take a while... | |
1984 | * The latter shoule be removed | |
1985 | */ | |
1986 | out: | |
1987 | spin_unlock_irqrestore(&priv->lock, flags); | |
1988 | } | |
1989 | ||
1990 | static int isp1760_get_frame(struct usb_hcd *hcd) | |
1991 | { | |
1992 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
1993 | u32 fr; | |
1994 | ||
bedc0c31 | 1995 | fr = reg_read32(hcd->regs, HC_FRINDEX); |
db11e47d SS |
1996 | return (fr >> 3) % priv->periodic_size; |
1997 | } | |
1998 | ||
1999 | static void isp1760_stop(struct usb_hcd *hcd) | |
2000 | { | |
2001 | struct isp1760_hcd *priv = hcd_to_priv(hcd); | |
3faefc88 | 2002 | u32 temp; |
db11e47d SS |
2003 | |
2004 | isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1, | |
2005 | NULL, 0); | |
2006 | mdelay(20); | |
2007 | ||
2008 | spin_lock_irq(&priv->lock); | |
6bda21bc | 2009 | ehci_reset(hcd); |
db11e47d | 2010 | /* Disable IRQ */ |
bedc0c31 AB |
2011 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
2012 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); | |
db11e47d SS |
2013 | spin_unlock_irq(&priv->lock); |
2014 | ||
bedc0c31 | 2015 | reg_write32(hcd->regs, HC_CONFIGFLAG, 0); |
db11e47d SS |
2016 | } |
2017 | ||
2018 | static void isp1760_shutdown(struct usb_hcd *hcd) | |
2019 | { | |
3faefc88 | 2020 | u32 command, temp; |
db11e47d SS |
2021 | |
2022 | isp1760_stop(hcd); | |
bedc0c31 AB |
2023 | temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL); |
2024 | reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN); | |
db11e47d | 2025 | |
bedc0c31 | 2026 | command = reg_read32(hcd->regs, HC_USBCMD); |
db11e47d | 2027 | command &= ~CMD_RUN; |
bedc0c31 | 2028 | reg_write32(hcd->regs, HC_USBCMD, command); |
db11e47d SS |
2029 | } |
2030 | ||
2031 | static const struct hc_driver isp1760_hc_driver = { | |
2032 | .description = "isp1760-hcd", | |
2033 | .product_desc = "NXP ISP1760 USB Host Controller", | |
2034 | .hcd_priv_size = sizeof(struct isp1760_hcd), | |
2035 | .irq = isp1760_irq, | |
2036 | .flags = HCD_MEMORY | HCD_USB2, | |
2037 | .reset = isp1760_hc_setup, | |
2038 | .start = isp1760_run, | |
2039 | .stop = isp1760_stop, | |
2040 | .shutdown = isp1760_shutdown, | |
2041 | .urb_enqueue = isp1760_urb_enqueue, | |
2042 | .urb_dequeue = isp1760_urb_dequeue, | |
2043 | .endpoint_disable = isp1760_endpoint_disable, | |
2044 | .get_frame_number = isp1760_get_frame, | |
2045 | .hub_status_data = isp1760_hub_status_data, | |
2046 | .hub_control = isp1760_hub_control, | |
2047 | }; | |
2048 | ||
2049 | int __init init_kmem_once(void) | |
2050 | { | |
2051 | qtd_cachep = kmem_cache_create("isp1760_qtd", | |
2052 | sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY | | |
2053 | SLAB_MEM_SPREAD, NULL); | |
2054 | ||
2055 | if (!qtd_cachep) | |
2056 | return -ENOMEM; | |
2057 | ||
2058 | qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), | |
2059 | 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); | |
2060 | ||
2061 | if (!qh_cachep) { | |
2062 | kmem_cache_destroy(qtd_cachep); | |
2063 | return -ENOMEM; | |
2064 | } | |
2065 | ||
2066 | return 0; | |
2067 | } | |
2068 | ||
2069 | void deinit_kmem_cache(void) | |
2070 | { | |
2071 | kmem_cache_destroy(qtd_cachep); | |
2072 | kmem_cache_destroy(qh_cachep); | |
2073 | } | |
2074 | ||
f9031f2c CM |
2075 | struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len, |
2076 | int irq, unsigned long irqflags, | |
2077 | struct device *dev, const char *busname, | |
2078 | unsigned int devflags) | |
db11e47d SS |
2079 | { |
2080 | struct usb_hcd *hcd; | |
2081 | struct isp1760_hcd *priv; | |
2082 | int ret; | |
2083 | ||
2084 | if (usb_disabled()) | |
2085 | return ERR_PTR(-ENODEV); | |
2086 | ||
2087 | /* prevent usb-core allocating DMA pages */ | |
2088 | dev->dma_mask = NULL; | |
2089 | ||
0031a06e | 2090 | hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev)); |
db11e47d SS |
2091 | if (!hcd) |
2092 | return ERR_PTR(-ENOMEM); | |
2093 | ||
2094 | priv = hcd_to_priv(hcd); | |
3faefc88 | 2095 | priv->devflags = devflags; |
db11e47d SS |
2096 | init_memory(priv); |
2097 | hcd->regs = ioremap(res_start, res_len); | |
2098 | if (!hcd->regs) { | |
2099 | ret = -EIO; | |
2100 | goto err_put; | |
2101 | } | |
2102 | ||
db11e47d SS |
2103 | hcd->irq = irq; |
2104 | hcd->rsrc_start = res_start; | |
2105 | hcd->rsrc_len = res_len; | |
2106 | ||
e6942d63 NC |
2107 | ret = usb_add_hcd(hcd, irq, irqflags); |
2108 | if (ret) | |
2109 | goto err_unmap; | |
2110 | ||
db11e47d SS |
2111 | return hcd; |
2112 | ||
2113 | err_unmap: | |
2114 | iounmap(hcd->regs); | |
2115 | ||
2116 | err_put: | |
2117 | usb_put_hcd(hcd); | |
2118 | ||
2119 | return ERR_PTR(ret); | |
2120 | } | |
2121 | ||
2122 | MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP"); | |
2123 | MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>"); | |
2124 | MODULE_LICENSE("GPL v2"); |