Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
578333ab AS |
2 | * Open Host Controller Interface (OHCI) driver for USB. |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
1da177e4 LT |
5 | * |
6 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
7 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 8 | * |
1da177e4 LT |
9 | * [ Initialisation is based on Linus' ] |
10 | * [ uhci code and gregs ohci fragments ] | |
11 | * [ (C) Copyright 1999 Linus Torvalds ] | |
12 | * [ (C) Copyright 1999 Gregory P. Smith] | |
dd9048af DB |
13 | * |
14 | * | |
1da177e4 LT |
15 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
16 | * interfaces (though some non-x86 Intel chips use it). It supports | |
17 | * smarter hardware than UHCI. A download link for the spec available | |
18 | * through the http://www.usb.org website. | |
19 | * | |
1da177e4 LT |
20 | * This file is licenced under the GPL. |
21 | */ | |
dd9048af | 22 | |
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/sched.h> | |
30 | #include <linux/slab.h> | |
1da177e4 LT |
31 | #include <linux/errno.h> |
32 | #include <linux/init.h> | |
33 | #include <linux/timer.h> | |
34 | #include <linux/list.h> | |
1da177e4 | 35 | #include <linux/usb.h> |
3a16f7b4 | 36 | #include <linux/usb/otg.h> |
27729aad | 37 | #include <linux/usb/hcd.h> |
dd9048af | 38 | #include <linux/dma-mapping.h> |
f4df0e33 | 39 | #include <linux/dmapool.h> |
d576bb9f | 40 | #include <linux/workqueue.h> |
684c19e0 | 41 | #include <linux/debugfs.h> |
1da177e4 LT |
42 | |
43 | #include <asm/io.h> | |
44 | #include <asm/irq.h> | |
1da177e4 LT |
45 | #include <asm/unaligned.h> |
46 | #include <asm/byteorder.h> | |
47 | ||
48 | ||
1da177e4 LT |
49 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
50 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
51 | ||
52 | /*-------------------------------------------------------------------------*/ | |
53 | ||
1da177e4 | 54 | /* For initializing controller (mask in an HCFS mode too) */ |
d413984a | 55 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 56 | #define OHCI_INTR_INIT \ |
d413984a DB |
57 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
58 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
59 | |
60 | #ifdef __hppa__ | |
61 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
62 | #define IR_DISABLE | |
63 | #endif | |
64 | ||
65 | #ifdef CONFIG_ARCH_OMAP | |
66 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
67 | #define IR_DISABLE | |
68 | #endif | |
69 | ||
70 | /*-------------------------------------------------------------------------*/ | |
71 | ||
72 | static const char hcd_name [] = "ohci_hcd"; | |
73 | ||
d413984a | 74 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
499b3803 | 75 | #define IO_WATCHDOG_DELAY msecs_to_jiffies(250) |
d413984a | 76 | |
1da177e4 | 77 | #include "ohci.h" |
ad93562b | 78 | #include "pci-quirks.h" |
1da177e4 | 79 | |
256dbcd8 AS |
80 | static void ohci_dump(struct ohci_hcd *ohci); |
81 | static void ohci_stop(struct usb_hcd *hcd); | |
81e38333 | 82 | static void io_watchdog_func(unsigned long _ohci); |
ab1666c1 | 83 | |
1da177e4 LT |
84 | #include "ohci-hub.c" |
85 | #include "ohci-dbg.c" | |
86 | #include "ohci-mem.c" | |
87 | #include "ohci-q.c" | |
88 | ||
89 | ||
90 | /* | |
91 | * On architectures with edge-triggered interrupts we must never return | |
92 | * IRQ_NONE. | |
93 | */ | |
94 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
95 | #define IRQ_NOTMINE IRQ_HANDLED | |
96 | #else | |
97 | #define IRQ_NOTMINE IRQ_NONE | |
98 | #endif | |
99 | ||
100 | ||
101 | /* Some boards misreport power switching/overcurrent */ | |
900937c0 | 102 | static bool distrust_firmware = true; |
1da177e4 LT |
103 | module_param (distrust_firmware, bool, 0); |
104 | MODULE_PARM_DESC (distrust_firmware, | |
105 | "true to distrust firmware power/overcurrent setup"); | |
106 | ||
107 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
900937c0 | 108 | static bool no_handshake; |
1da177e4 LT |
109 | module_param (no_handshake, bool, 0); |
110 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
111 | ||
112 | /*-------------------------------------------------------------------------*/ | |
113 | ||
6f65126c AS |
114 | static int number_of_tds(struct urb *urb) |
115 | { | |
116 | int len, i, num, this_sg_len; | |
117 | struct scatterlist *sg; | |
118 | ||
119 | len = urb->transfer_buffer_length; | |
120 | i = urb->num_mapped_sgs; | |
121 | ||
122 | if (len > 0 && i > 0) { /* Scatter-gather transfer */ | |
123 | num = 0; | |
124 | sg = urb->sg; | |
125 | for (;;) { | |
126 | this_sg_len = min_t(int, sg_dma_len(sg), len); | |
127 | num += DIV_ROUND_UP(this_sg_len, 4096); | |
128 | len -= this_sg_len; | |
129 | if (--i <= 0 || len <= 0) | |
130 | break; | |
131 | sg = sg_next(sg); | |
132 | } | |
133 | ||
134 | } else { /* Non-SG transfer */ | |
135 | /* one TD for every 4096 Bytes (could be up to 8K) */ | |
136 | num = DIV_ROUND_UP(len, 4096); | |
137 | } | |
138 | return num; | |
139 | } | |
140 | ||
1da177e4 LT |
141 | /* |
142 | * queue up an urb for anything except the root hub | |
143 | */ | |
144 | static int ohci_urb_enqueue ( | |
145 | struct usb_hcd *hcd, | |
1da177e4 | 146 | struct urb *urb, |
55016f10 | 147 | gfp_t mem_flags |
1da177e4 LT |
148 | ) { |
149 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
150 | struct ed *ed; | |
151 | urb_priv_t *urb_priv; | |
152 | unsigned int pipe = urb->pipe; | |
153 | int i, size = 0; | |
154 | unsigned long flags; | |
155 | int retval = 0; | |
dd9048af | 156 | |
1da177e4 | 157 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
71f46340 GKH |
158 | ed = ed_get(ohci, urb->ep, urb->dev, pipe, urb->interval); |
159 | if (! ed) | |
1da177e4 LT |
160 | return -ENOMEM; |
161 | ||
162 | /* for the private part of the URB we need the number of TDs (size) */ | |
163 | switch (ed->type) { | |
164 | case PIPE_CONTROL: | |
165 | /* td_submit_urb() doesn't yet handle these */ | |
166 | if (urb->transfer_buffer_length > 4096) | |
167 | return -EMSGSIZE; | |
168 | ||
169 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
170 | size = 2; | |
171 | /* FALLTHROUGH */ | |
172 | // case PIPE_INTERRUPT: | |
173 | // case PIPE_BULK: | |
174 | default: | |
6f65126c AS |
175 | size += number_of_tds(urb); |
176 | /* maybe a zero-length packet to wrap it up */ | |
1da177e4 LT |
177 | if (size == 0) |
178 | size++; | |
179 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
180 | && (urb->transfer_buffer_length | |
181 | % usb_maxpacket (urb->dev, pipe, | |
182 | usb_pipeout (pipe))) == 0) | |
183 | size++; | |
184 | break; | |
185 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
186 | size = urb->number_of_packets; | |
187 | break; | |
188 | } | |
189 | ||
190 | /* allocate the private part of the URB */ | |
dd00cc48 | 191 | urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), |
1da177e4 LT |
192 | mem_flags); |
193 | if (!urb_priv) | |
194 | return -ENOMEM; | |
1da177e4 LT |
195 | INIT_LIST_HEAD (&urb_priv->pending); |
196 | urb_priv->length = size; | |
dd9048af | 197 | urb_priv->ed = ed; |
1da177e4 LT |
198 | |
199 | /* allocate the TDs (deferring hash chain updates) */ | |
200 | for (i = 0; i < size; i++) { | |
201 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
202 | if (!urb_priv->td [i]) { | |
203 | urb_priv->length = i; | |
204 | urb_free_priv (ohci, urb_priv); | |
205 | return -ENOMEM; | |
206 | } | |
dd9048af | 207 | } |
1da177e4 LT |
208 | |
209 | spin_lock_irqsave (&ohci->lock, flags); | |
210 | ||
211 | /* don't submit to a dead HC */ | |
541c7d43 | 212 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
8de98402 BH |
213 | retval = -ENODEV; |
214 | goto fail; | |
215 | } | |
b7463c71 | 216 | if (ohci->rh_state != OHCI_RH_RUNNING) { |
1da177e4 LT |
217 | retval = -ENODEV; |
218 | goto fail; | |
219 | } | |
e9df41c5 AS |
220 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
221 | if (retval) | |
1da177e4 | 222 | goto fail; |
1da177e4 LT |
223 | |
224 | /* schedule the ed if needed */ | |
225 | if (ed->state == ED_IDLE) { | |
226 | retval = ed_schedule (ohci, ed); | |
e9df41c5 AS |
227 | if (retval < 0) { |
228 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
229 | goto fail; | |
230 | } | |
81e38333 AS |
231 | |
232 | /* Start up the I/O watchdog timer, if it's not running */ | |
233 | if (!timer_pending(&ohci->io_watchdog) && | |
499b3803 AS |
234 | list_empty(&ohci->eds_in_use)) { |
235 | ohci->prev_frame_no = ohci_frame_no(ohci); | |
81e38333 AS |
236 | mod_timer(&ohci->io_watchdog, |
237 | jiffies + IO_WATCHDOG_DELAY); | |
499b3803 | 238 | } |
81e38333 AS |
239 | list_add(&ed->in_use_list, &ohci->eds_in_use); |
240 | ||
1da177e4 LT |
241 | if (ed->type == PIPE_ISOCHRONOUS) { |
242 | u16 frame = ohci_frame_no(ohci); | |
243 | ||
244 | /* delay a few frames before the first TD */ | |
245 | frame += max_t (u16, 8, ed->interval); | |
246 | frame &= ~(ed->interval - 1); | |
247 | frame |= ed->branch; | |
248 | urb->start_frame = frame; | |
a8693424 | 249 | ed->last_iso = frame + ed->interval * (size - 1); |
6a41b4d3 AS |
250 | } |
251 | } else if (ed->type == PIPE_ISOCHRONOUS) { | |
e1944017 | 252 | u16 next = ohci_frame_no(ohci) + 1; |
6a41b4d3 | 253 | u16 frame = ed->last_iso + ed->interval; |
a8693424 | 254 | u16 length = ed->interval * (size - 1); |
6a41b4d3 AS |
255 | |
256 | /* Behind the scheduling threshold? */ | |
257 | if (unlikely(tick_before(frame, next))) { | |
258 | ||
a8693424 | 259 | /* URB_ISO_ASAP: Round up to the first available slot */ |
815fa7b9 | 260 | if (urb->transfer_flags & URB_ISO_ASAP) { |
6a41b4d3 AS |
261 | frame += (next - frame + ed->interval - 1) & |
262 | -ed->interval; | |
1da177e4 | 263 | |
6a41b4d3 | 264 | /* |
a8693424 AS |
265 | * Not ASAP: Use the next slot in the stream, |
266 | * no matter what. | |
1da177e4 | 267 | */ |
815fa7b9 | 268 | } else { |
815fa7b9 AS |
269 | /* |
270 | * Some OHCI hardware doesn't handle late TDs | |
271 | * correctly. After retiring them it proceeds | |
272 | * to the next ED instead of the next TD. | |
273 | * Therefore we have to omit the late TDs | |
274 | * entirely. | |
275 | */ | |
276 | urb_priv->td_cnt = DIV_ROUND_UP( | |
277 | (u16) (next - frame), | |
278 | ed->interval); | |
a8693424 AS |
279 | if (urb_priv->td_cnt >= urb_priv->length) { |
280 | ++urb_priv->td_cnt; /* Mark it */ | |
281 | ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n", | |
282 | urb, frame, length, | |
283 | next); | |
284 | } | |
6a41b4d3 | 285 | } |
1da177e4 | 286 | } |
6a41b4d3 | 287 | urb->start_frame = frame; |
a8693424 | 288 | ed->last_iso = frame + length; |
6a41b4d3 | 289 | } |
1da177e4 LT |
290 | |
291 | /* fill the TDs and link them to the ed; and | |
292 | * enable that part of the schedule, if needed | |
293 | * and update count of queued periodic urbs | |
294 | */ | |
295 | urb->hcpriv = urb_priv; | |
296 | td_submit_urb (ohci, urb); | |
297 | ||
1da177e4 LT |
298 | fail: |
299 | if (retval) | |
300 | urb_free_priv (ohci, urb_priv); | |
301 | spin_unlock_irqrestore (&ohci->lock, flags); | |
302 | return retval; | |
303 | } | |
304 | ||
305 | /* | |
55d84968 AS |
306 | * decouple the URB from the HC queues (TDs, urb_priv). |
307 | * reporting is always done | |
1da177e4 LT |
308 | * asynchronously, and we might be dealing with an urb that's |
309 | * partially transferred, or an ED with other urbs being unlinked. | |
310 | */ | |
e9df41c5 | 311 | static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
312 | { |
313 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
314 | unsigned long flags; | |
e9df41c5 | 315 | int rc; |
8b3ab0ed | 316 | urb_priv_t *urb_priv; |
dd9048af | 317 | |
1da177e4 | 318 | spin_lock_irqsave (&ohci->lock, flags); |
e9df41c5 | 319 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
8b3ab0ed | 320 | if (rc == 0) { |
1da177e4 LT |
321 | |
322 | /* Unless an IRQ completed the unlink while it was being | |
323 | * handed to us, flag it for unlink and giveback, and force | |
324 | * some upcoming INTR_SF to call finish_unlinks() | |
325 | */ | |
326 | urb_priv = urb->hcpriv; | |
8b3ab0ed AS |
327 | if (urb_priv->ed->state == ED_OPER) |
328 | start_ed_unlink(ohci, urb_priv->ed); | |
329 | ||
330 | if (ohci->rh_state != OHCI_RH_RUNNING) { | |
331 | /* With HC dead, we can clean up right away */ | |
cdb4dd15 | 332 | ohci_work(ohci); |
1da177e4 | 333 | } |
1da177e4 LT |
334 | } |
335 | spin_unlock_irqrestore (&ohci->lock, flags); | |
e9df41c5 | 336 | return rc; |
1da177e4 LT |
337 | } |
338 | ||
339 | /*-------------------------------------------------------------------------*/ | |
340 | ||
341 | /* frees config/altsetting state for endpoints, | |
342 | * including ED memory, dummy TD, and bulk/intr data toggle | |
343 | */ | |
344 | ||
345 | static void | |
346 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
347 | { | |
348 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
349 | unsigned long flags; | |
350 | struct ed *ed = ep->hcpriv; | |
351 | unsigned limit = 1000; | |
352 | ||
353 | /* ASSERT: any requests/urbs are being unlinked */ | |
354 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
355 | ||
356 | if (!ed) | |
357 | return; | |
358 | ||
359 | rescan: | |
360 | spin_lock_irqsave (&ohci->lock, flags); | |
361 | ||
b7463c71 | 362 | if (ohci->rh_state != OHCI_RH_RUNNING) { |
1da177e4 LT |
363 | sanitize: |
364 | ed->state = ED_IDLE; | |
cdb4dd15 | 365 | ohci_work(ohci); |
1da177e4 LT |
366 | } |
367 | ||
368 | switch (ed->state) { | |
369 | case ED_UNLINK: /* wait for hw to finish? */ | |
370 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
371 | if (limit-- == 0) { | |
89a0fd18 | 372 | ohci_warn(ohci, "ED unlink timeout\n"); |
1da177e4 LT |
373 | goto sanitize; |
374 | } | |
375 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 376 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
377 | goto rescan; |
378 | case ED_IDLE: /* fully unlinked */ | |
379 | if (list_empty (&ed->td_list)) { | |
380 | td_free (ohci, ed->dummy); | |
381 | ed_free (ohci, ed); | |
382 | break; | |
383 | } | |
384 | /* else FALL THROUGH */ | |
385 | default: | |
386 | /* caller was supposed to have unlinked any requests; | |
387 | * that's not our job. can't recover; must leak ed. | |
388 | */ | |
389 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
390 | ed, ep->desc.bEndpointAddress, ed->state, | |
391 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
392 | td_free (ohci, ed->dummy); | |
393 | break; | |
394 | } | |
395 | ep->hcpriv = NULL; | |
396 | spin_unlock_irqrestore (&ohci->lock, flags); | |
1da177e4 LT |
397 | } |
398 | ||
399 | static int ohci_get_frame (struct usb_hcd *hcd) | |
400 | { | |
401 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
402 | ||
403 | return ohci_frame_no(ohci); | |
404 | } | |
405 | ||
406 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
407 | { | |
408 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
409 | ohci->hc_control &= OHCI_CTRL_RWC; | |
410 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
b7463c71 | 411 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 LT |
412 | } |
413 | ||
64a21d02 | 414 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
415 | * other cases where the next software may expect clean state from the |
416 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
417 | */ | |
64a21d02 AG |
418 | static void |
419 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
420 | { |
421 | struct ohci_hcd *ohci; | |
422 | ||
64a21d02 | 423 | ohci = hcd_to_ohci (hcd); |
c6187597 | 424 | ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable); |
3df7169e | 425 | |
c6187597 AS |
426 | /* Software reset, after which the controller goes into SUSPEND */ |
427 | ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
428 | ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */ | |
429 | udelay(10); | |
3df7169e | 430 | |
c6187597 | 431 | ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval); |
81e38333 | 432 | ohci->rh_state = OHCI_RH_HALTED; |
f4df0e33 DB |
433 | } |
434 | ||
1da177e4 LT |
435 | /*-------------------------------------------------------------------------* |
436 | * HC functions | |
437 | *-------------------------------------------------------------------------*/ | |
438 | ||
439 | /* init memory, and kick BIOS/SMM off */ | |
440 | ||
441 | static int ohci_init (struct ohci_hcd *ohci) | |
442 | { | |
443 | int ret; | |
6a9062f3 | 444 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 445 | |
6f65126c AS |
446 | /* Accept arbitrarily long scatter-gather lists */ |
447 | hcd->self.sg_tablesize = ~0; | |
448 | ||
1133cd8a DB |
449 | if (distrust_firmware) |
450 | ohci->flags |= OHCI_QUIRK_HUB_POWER; | |
451 | ||
b7463c71 | 452 | ohci->rh_state = OHCI_RH_HALTED; |
6a9062f3 | 453 | ohci->regs = hcd->regs; |
1da177e4 | 454 | |
6a9062f3 DB |
455 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
456 | * was never needed for most non-PCI systems ... remove the code? | |
457 | */ | |
458 | ||
1da177e4 LT |
459 | #ifndef IR_DISABLE |
460 | /* SMM owns the HC? not for long! */ | |
461 | if (!no_handshake && ohci_readl (ohci, | |
462 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
463 | u32 temp; | |
464 | ||
465 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
466 | ||
467 | /* this timeout is arbitrary. we make it long, so systems | |
468 | * depending on usb keyboards may be usable even if the | |
469 | * BIOS/SMM code seems pretty broken. | |
470 | */ | |
471 | temp = 500; /* arbitrary: five seconds */ | |
472 | ||
473 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
474 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
475 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
476 | msleep (10); | |
477 | if (--temp == 0) { | |
478 | ohci_err (ohci, "USB HC takeover failed!" | |
479 | " (BIOS/SMM bug)\n"); | |
480 | return -EBUSY; | |
481 | } | |
482 | } | |
483 | ohci_usb_reset (ohci); | |
484 | } | |
485 | #endif | |
486 | ||
487 | /* Disable HC interrupts */ | |
488 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
489 | |
490 | /* flush the writes, and save key bits like RWC */ | |
491 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
492 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 493 | |
fdd13b36 DB |
494 | /* Read the number of ports unless overridden */ |
495 | if (ohci->num_ports == 0) | |
496 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
497 | ||
1da177e4 LT |
498 | if (ohci->hcca) |
499 | return 0; | |
500 | ||
81e38333 AS |
501 | setup_timer(&ohci->io_watchdog, io_watchdog_func, |
502 | (unsigned long) ohci); | |
503 | set_timer_slack(&ohci->io_watchdog, msecs_to_jiffies(20)); | |
504 | ||
6a9062f3 | 505 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
4428524d | 506 | sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL); |
1da177e4 LT |
507 | if (!ohci->hcca) |
508 | return -ENOMEM; | |
509 | ||
510 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
511 | ohci_stop (hcd); |
512 | else { | |
6a9062f3 DB |
513 | create_debug_files (ohci); |
514 | } | |
1da177e4 LT |
515 | |
516 | return ret; | |
1da177e4 LT |
517 | } |
518 | ||
519 | /*-------------------------------------------------------------------------*/ | |
520 | ||
521 | /* Start an OHCI controller, set the BUS operational | |
522 | * resets USB and controller | |
dd9048af | 523 | * enable interrupts |
1da177e4 LT |
524 | */ |
525 | static int ohci_run (struct ohci_hcd *ohci) | |
526 | { | |
96f90a8b | 527 | u32 mask, val; |
1da177e4 | 528 | int first = ohci->fminterval == 0; |
6a9062f3 | 529 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 530 | |
b7463c71 | 531 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 LT |
532 | |
533 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
534 | if (first) { | |
535 | ||
96f90a8b HS |
536 | val = ohci_readl (ohci, &ohci->regs->fminterval); |
537 | ohci->fminterval = val & 0x3fff; | |
1da177e4 LT |
538 | if (ohci->fminterval != FI) |
539 | ohci_dbg (ohci, "fminterval delta %d\n", | |
540 | ohci->fminterval - FI); | |
541 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
542 | /* also: power/overcurrent flags in roothub.a */ | |
543 | } | |
544 | ||
6fd9086a AS |
545 | /* Reset USB nearly "by the book". RemoteWakeupConnected has |
546 | * to be checked in case boot firmware (BIOS/SMM/...) has set up | |
547 | * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). | |
548 | * If the bus glue detected wakeup capability then it should | |
bcca06ef | 549 | * already be enabled; if so we'll just enable it again. |
1da177e4 | 550 | */ |
bcca06ef AS |
551 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) |
552 | device_set_wakeup_capable(hcd->self.controller, 1); | |
1da177e4 LT |
553 | |
554 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
555 | case OHCI_USB_OPER: | |
96f90a8b | 556 | val = 0; |
1da177e4 LT |
557 | break; |
558 | case OHCI_USB_SUSPEND: | |
559 | case OHCI_USB_RESUME: | |
560 | ohci->hc_control &= OHCI_CTRL_RWC; | |
561 | ohci->hc_control |= OHCI_USB_RESUME; | |
96f90a8b | 562 | val = 10 /* msec wait */; |
1da177e4 LT |
563 | break; |
564 | // case OHCI_USB_RESET: | |
565 | default: | |
566 | ohci->hc_control &= OHCI_CTRL_RWC; | |
567 | ohci->hc_control |= OHCI_USB_RESET; | |
96f90a8b | 568 | val = 50 /* msec wait */; |
1da177e4 LT |
569 | break; |
570 | } | |
571 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
572 | // flush the writes | |
573 | (void) ohci_readl (ohci, &ohci->regs->control); | |
96f90a8b | 574 | msleep(val); |
383975d7 | 575 | |
1da177e4 LT |
576 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); |
577 | ||
578 | /* 2msec timelimit here means no irqs/preempt */ | |
579 | spin_lock_irq (&ohci->lock); | |
580 | ||
581 | retry: | |
582 | /* HC Reset requires max 10 us delay */ | |
583 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
96f90a8b | 584 | val = 30; /* ... allow extra time */ |
1da177e4 | 585 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { |
96f90a8b | 586 | if (--val == 0) { |
1da177e4 LT |
587 | spin_unlock_irq (&ohci->lock); |
588 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
589 | return -1; | |
590 | } | |
591 | udelay (1); | |
592 | } | |
593 | ||
594 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
595 | * within 2msec else HC enters RESUME | |
596 | * | |
597 | * ... but some hardware won't init fmInterval "by the book" | |
598 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
599 | * this if we write fmInterval after we're OPERATIONAL. | |
600 | * Unclear about ALi, ServerWorks, and others ... this could | |
601 | * easily be a longstanding bug in chip init on Linux. | |
602 | */ | |
603 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
604 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
605 | // flush those writes | |
606 | (void) ohci_readl (ohci, &ohci->regs->control); | |
607 | } | |
608 | ||
609 | /* Tell the controller where the control and bulk lists are | |
610 | * The lists are empty now. */ | |
611 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
612 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
613 | ||
614 | /* a reset clears this */ | |
615 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
616 | ||
617 | periodic_reinit (ohci); | |
618 | ||
619 | /* some OHCI implementations are finicky about how they init. | |
620 | * bogus values here mean not even enumeration could work. | |
621 | */ | |
622 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
623 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
624 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
625 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
626 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
627 | goto retry; | |
628 | } | |
629 | spin_unlock_irq (&ohci->lock); | |
630 | ohci_err (ohci, "init err (%08x %04x)\n", | |
631 | ohci_readl (ohci, &ohci->regs->fminterval), | |
632 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
633 | return -EOVERFLOW; | |
634 | } | |
635 | ||
37ebb549 | 636 | /* use rhsc irqs after hub_wq is allocated */ |
541c7d43 | 637 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
d413984a DB |
638 | hcd->uses_new_polling = 1; |
639 | ||
640 | /* start controller operations */ | |
1da177e4 | 641 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
642 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
643 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
b7463c71 | 644 | ohci->rh_state = OHCI_RH_RUNNING; |
1da177e4 LT |
645 | |
646 | /* wake on ConnectStatusChange, matching external hubs */ | |
647 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
648 | ||
649 | /* Choose the interrupts we care about now, others later on demand */ | |
650 | mask = OHCI_INTR_INIT; | |
d413984a | 651 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
652 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
653 | ||
654 | /* handle root hub init quirks ... */ | |
96f90a8b HS |
655 | val = roothub_a (ohci); |
656 | val &= ~(RH_A_PSM | RH_A_OCPM); | |
1da177e4 LT |
657 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { |
658 | /* NSC 87560 and maybe others */ | |
96f90a8b HS |
659 | val |= RH_A_NOCP; |
660 | val &= ~(RH_A_POTPGT | RH_A_NPS); | |
661 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1133cd8a DB |
662 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || |
663 | (ohci->flags & OHCI_QUIRK_HUB_POWER)) { | |
1da177e4 LT |
664 | /* hub power always on; required for AMD-756 and some |
665 | * Mac platforms. ganged overcurrent reporting, if any. | |
666 | */ | |
96f90a8b HS |
667 | val |= RH_A_NPS; |
668 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1da177e4 LT |
669 | } |
670 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
96f90a8b | 671 | ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, |
1da177e4 LT |
672 | &ohci->regs->roothub.b); |
673 | // flush those writes | |
674 | (void) ohci_readl (ohci, &ohci->regs->control); | |
675 | ||
d413984a | 676 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
677 | spin_unlock_irq (&ohci->lock); |
678 | ||
679 | // POTPGT delay is bits 24-31, in 2 ms units. | |
96f90a8b | 680 | mdelay ((val >> 23) & 0x1fe); |
1da177e4 | 681 | |
256dbcd8 | 682 | ohci_dump(ohci); |
1da177e4 | 683 | |
1da177e4 LT |
684 | return 0; |
685 | } | |
686 | ||
95e44d44 MG |
687 | /* ohci_setup routine for generic controller initialization */ |
688 | ||
689 | int ohci_setup(struct usb_hcd *hcd) | |
690 | { | |
691 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | |
692 | ||
693 | ohci_hcd_init(ohci); | |
694 | ||
695 | return ohci_init(ohci); | |
696 | } | |
697 | EXPORT_SYMBOL_GPL(ohci_setup); | |
698 | ||
699 | /* ohci_start routine for generic controller start of all OHCI bus glue */ | |
700 | static int ohci_start(struct usb_hcd *hcd) | |
701 | { | |
702 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | |
703 | int ret; | |
704 | ||
705 | ret = ohci_run(ohci); | |
706 | if (ret < 0) { | |
707 | ohci_err(ohci, "can't start\n"); | |
708 | ohci_stop(hcd); | |
709 | } | |
710 | return ret; | |
711 | } | |
712 | ||
1da177e4 LT |
713 | /*-------------------------------------------------------------------------*/ |
714 | ||
81e38333 AS |
715 | /* |
716 | * Some OHCI controllers are known to lose track of completed TDs. They | |
717 | * don't add the TDs to the hardware done queue, which means we never see | |
718 | * them as being completed. | |
719 | * | |
720 | * This watchdog routine checks for such problems. Without some way to | |
721 | * tell when those TDs have completed, we would never take their EDs off | |
722 | * the unlink list. As a result, URBs could never be dequeued and | |
723 | * endpoints could never be released. | |
724 | */ | |
725 | static void io_watchdog_func(unsigned long _ohci) | |
726 | { | |
727 | struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; | |
728 | bool takeback_all_pending = false; | |
729 | u32 status; | |
730 | u32 head; | |
731 | struct ed *ed; | |
732 | struct td *td, *td_start, *td_next; | |
499b3803 | 733 | unsigned frame_no; |
81e38333 AS |
734 | unsigned long flags; |
735 | ||
736 | spin_lock_irqsave(&ohci->lock, flags); | |
737 | ||
738 | /* | |
739 | * One way to lose track of completed TDs is if the controller | |
740 | * never writes back the done queue head. If it hasn't been | |
741 | * written back since the last time this function ran and if it | |
742 | * was non-empty at that time, something is badly wrong with the | |
743 | * hardware. | |
744 | */ | |
745 | status = ohci_readl(ohci, &ohci->regs->intrstatus); | |
746 | if (!(status & OHCI_INTR_WDH) && ohci->wdh_cnt == ohci->prev_wdh_cnt) { | |
747 | if (ohci->prev_donehead) { | |
748 | ohci_err(ohci, "HcDoneHead not written back; disabled\n"); | |
499b3803 | 749 | died: |
81e38333 AS |
750 | usb_hc_died(ohci_to_hcd(ohci)); |
751 | ohci_dump(ohci); | |
752 | ohci_shutdown(ohci_to_hcd(ohci)); | |
753 | goto done; | |
754 | } else { | |
755 | /* No write back because the done queue was empty */ | |
756 | takeback_all_pending = true; | |
757 | } | |
758 | } | |
759 | ||
760 | /* Check every ED which might have pending TDs */ | |
761 | list_for_each_entry(ed, &ohci->eds_in_use, in_use_list) { | |
762 | if (ed->pending_td) { | |
763 | if (takeback_all_pending || | |
764 | OKAY_TO_TAKEBACK(ohci, ed)) { | |
765 | unsigned tmp = hc32_to_cpu(ohci, ed->hwINFO); | |
766 | ||
767 | ohci_dbg(ohci, "takeback pending TD for dev %d ep 0x%x\n", | |
768 | 0x007f & tmp, | |
769 | (0x000f & (tmp >> 7)) + | |
770 | ((tmp & ED_IN) >> 5)); | |
771 | add_to_done_list(ohci, ed->pending_td); | |
772 | } | |
773 | } | |
774 | ||
775 | /* Starting from the latest pending TD, */ | |
776 | td = ed->pending_td; | |
777 | ||
778 | /* or the last TD on the done list, */ | |
779 | if (!td) { | |
780 | list_for_each_entry(td_next, &ed->td_list, td_list) { | |
781 | if (!td_next->next_dl_td) | |
782 | break; | |
783 | td = td_next; | |
784 | } | |
785 | } | |
786 | ||
787 | /* find the last TD processed by the controller. */ | |
788 | head = hc32_to_cpu(ohci, ACCESS_ONCE(ed->hwHeadP)) & TD_MASK; | |
789 | td_start = td; | |
790 | td_next = list_prepare_entry(td, &ed->td_list, td_list); | |
791 | list_for_each_entry_continue(td_next, &ed->td_list, td_list) { | |
792 | if (head == (u32) td_next->td_dma) | |
793 | break; | |
794 | td = td_next; /* head pointer has passed this TD */ | |
795 | } | |
796 | if (td != td_start) { | |
797 | /* | |
798 | * In case a WDH cycle is in progress, we will wait | |
799 | * for the next two cycles to complete before assuming | |
800 | * this TD will never get on the done queue. | |
801 | */ | |
802 | ed->takeback_wdh_cnt = ohci->wdh_cnt + 2; | |
803 | ed->pending_td = td; | |
804 | } | |
805 | } | |
806 | ||
807 | ohci_work(ohci); | |
808 | ||
809 | if (ohci->rh_state == OHCI_RH_RUNNING) { | |
499b3803 AS |
810 | |
811 | /* | |
812 | * Sometimes a controller just stops working. We can tell | |
813 | * by checking that the frame counter has advanced since | |
814 | * the last time we ran. | |
815 | * | |
816 | * But be careful: Some controllers violate the spec by | |
817 | * stopping their frame counter when no ports are active. | |
818 | */ | |
819 | frame_no = ohci_frame_no(ohci); | |
820 | if (frame_no == ohci->prev_frame_no) { | |
821 | int active_cnt = 0; | |
822 | int i; | |
823 | unsigned tmp; | |
824 | ||
825 | for (i = 0; i < ohci->num_ports; ++i) { | |
826 | tmp = roothub_portstatus(ohci, i); | |
827 | /* Enabled and not suspended? */ | |
828 | if ((tmp & RH_PS_PES) && !(tmp & RH_PS_PSS)) | |
829 | ++active_cnt; | |
830 | } | |
831 | ||
832 | if (active_cnt > 0) { | |
833 | ohci_err(ohci, "frame counter not updating; disabled\n"); | |
834 | goto died; | |
835 | } | |
836 | } | |
81e38333 | 837 | if (!list_empty(&ohci->eds_in_use)) { |
499b3803 | 838 | ohci->prev_frame_no = frame_no; |
81e38333 AS |
839 | ohci->prev_wdh_cnt = ohci->wdh_cnt; |
840 | ohci->prev_donehead = ohci_readl(ohci, | |
841 | &ohci->regs->donehead); | |
842 | mod_timer(&ohci->io_watchdog, | |
843 | jiffies + IO_WATCHDOG_DELAY); | |
844 | } | |
845 | } | |
846 | ||
847 | done: | |
848 | spin_unlock_irqrestore(&ohci->lock, flags); | |
849 | } | |
850 | ||
1da177e4 LT |
851 | /* an interrupt happens */ |
852 | ||
7d12e780 | 853 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
854 | { |
855 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
856 | struct ohci_regs __iomem *regs = ohci->regs; | |
89a0fd18 | 857 | int ints; |
1da177e4 | 858 | |
565227c0 BH |
859 | /* Read interrupt status (and flush pending writes). We ignore the |
860 | * optimization of checking the LSB of hcca->done_head; it doesn't | |
861 | * work on all systems (edge triggering for OHCI can be a factor). | |
89a0fd18 | 862 | */ |
565227c0 | 863 | ints = ohci_readl(ohci, ®s->intrstatus); |
1da177e4 | 864 | |
565227c0 BH |
865 | /* Check for an all 1's result which is a typical consequence |
866 | * of dead, unclocked, or unplugged (CardBus...) devices | |
867 | */ | |
868 | if (ints == ~(u32)0) { | |
b7463c71 | 869 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 | 870 | ohci_dbg (ohci, "device removed!\n"); |
69fff59d | 871 | usb_hc_died(hcd); |
1da177e4 | 872 | return IRQ_HANDLED; |
565227c0 BH |
873 | } |
874 | ||
875 | /* We only care about interrupts that are enabled */ | |
876 | ints &= ohci_readl(ohci, ®s->intrenable); | |
1da177e4 LT |
877 | |
878 | /* interrupt for some other device? */ | |
b7463c71 | 879 | if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED)) |
1da177e4 | 880 | return IRQ_NOTMINE; |
d413984a | 881 | |
1da177e4 | 882 | if (ints & OHCI_INTR_UE) { |
1da177e4 | 883 | // e.g. due to PCI Master/Target Abort |
89a0fd18 | 884 | if (quirk_nec(ohci)) { |
d576bb9f MH |
885 | /* Workaround for a silicon bug in some NEC chips used |
886 | * in Apple's PowerBooks. Adapted from Darwin code. | |
887 | */ | |
888 | ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); | |
889 | ||
890 | ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); | |
891 | ||
892 | schedule_work (&ohci->nec_work); | |
893 | } else { | |
d576bb9f | 894 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); |
b7463c71 | 895 | ohci->rh_state = OHCI_RH_HALTED; |
69fff59d | 896 | usb_hc_died(hcd); |
d576bb9f | 897 | } |
1da177e4 | 898 | |
256dbcd8 | 899 | ohci_dump(ohci); |
1da177e4 LT |
900 | ohci_usb_reset (ohci); |
901 | } | |
902 | ||
583ceada | 903 | if (ints & OHCI_INTR_RHSC) { |
d2c4254f | 904 | ohci_dbg(ohci, "rhsc\n"); |
583ceada AS |
905 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
906 | ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, | |
907 | ®s->intrstatus); | |
052ac01a AS |
908 | |
909 | /* NOTE: Vendors didn't always make the same implementation | |
910 | * choices for RHSC. Many followed the spec; RHSC triggers | |
911 | * on an edge, like setting and maybe clearing a port status | |
912 | * change bit. With others it's level-triggered, active | |
37ebb549 PM |
913 | * until hub_wq clears all the port status change bits. We'll |
914 | * always disable it here and rely on polling until hub_wq | |
052ac01a AS |
915 | * re-enables it. |
916 | */ | |
917 | ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); | |
583ceada AS |
918 | usb_hcd_poll_rh_status(hcd); |
919 | } | |
920 | ||
921 | /* For connect and disconnect events, we expect the controller | |
922 | * to turn on RHSC along with RD. But for remote wakeup events | |
923 | * this might not happen. | |
924 | */ | |
925 | else if (ints & OHCI_INTR_RD) { | |
d2c4254f | 926 | ohci_dbg(ohci, "resume detect\n"); |
583ceada | 927 | ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); |
541c7d43 | 928 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
8d1a243b AS |
929 | if (ohci->autostop) { |
930 | spin_lock (&ohci->lock); | |
931 | ohci_rh_resume (ohci); | |
932 | spin_unlock (&ohci->lock); | |
933 | } else | |
f197b2c5 | 934 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
935 | } |
936 | ||
c6fcb85e AS |
937 | spin_lock(&ohci->lock); |
938 | if (ints & OHCI_INTR_WDH) | |
939 | update_done_list(ohci); | |
dd9048af | 940 | |
1da177e4 LT |
941 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
942 | ||
943 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
944 | * when there's still unlinking to be done (next frame). | |
945 | */ | |
cdb4dd15 | 946 | ohci_work(ohci); |
95d9a01d | 947 | if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list |
b7463c71 | 948 | && ohci->rh_state == OHCI_RH_RUNNING) |
dd9048af | 949 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
1da177e4 | 950 | |
b7463c71 | 951 | if (ohci->rh_state == OHCI_RH_RUNNING) { |
1da177e4 | 952 | ohci_writel (ohci, ints, ®s->intrstatus); |
81e38333 AS |
953 | if (ints & OHCI_INTR_WDH) |
954 | ++ohci->wdh_cnt; | |
955 | ||
dd9048af | 956 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
1da177e4 LT |
957 | // flush those writes |
958 | (void) ohci_readl (ohci, &ohci->regs->control); | |
959 | } | |
c6fcb85e | 960 | spin_unlock(&ohci->lock); |
1da177e4 LT |
961 | |
962 | return IRQ_HANDLED; | |
963 | } | |
964 | ||
965 | /*-------------------------------------------------------------------------*/ | |
966 | ||
967 | static void ohci_stop (struct usb_hcd *hcd) | |
dd9048af | 968 | { |
1da177e4 LT |
969 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
970 | ||
256dbcd8 | 971 | ohci_dump(ohci); |
1da177e4 | 972 | |
569ff2de | 973 | if (quirk_nec(ohci)) |
43829731 | 974 | flush_work(&ohci->nec_work); |
81e38333 | 975 | del_timer_sync(&ohci->io_watchdog); |
1da177e4 | 976 | |
1da177e4 | 977 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
435932f2 | 978 | ohci_usb_reset(ohci); |
71795c1d | 979 | free_irq(hcd->irq, hcd); |
cd70469d | 980 | hcd->irq = 0; |
71795c1d | 981 | |
ab1666c1 | 982 | if (quirk_amdiso(ohci)) |
ad93562b | 983 | usb_amd_dev_put(); |
89a0fd18 | 984 | |
1da177e4 LT |
985 | remove_debug_files (ohci); |
986 | ohci_mem_cleanup (ohci); | |
987 | if (ohci->hcca) { | |
dd9048af DB |
988 | dma_free_coherent (hcd->self.controller, |
989 | sizeof *ohci->hcca, | |
1da177e4 LT |
990 | ohci->hcca, ohci->hcca_dma); |
991 | ohci->hcca = NULL; | |
992 | ohci->hcca_dma = 0; | |
993 | } | |
994 | } | |
995 | ||
996 | /*-------------------------------------------------------------------------*/ | |
997 | ||
da6fb570 DB |
998 | #if defined(CONFIG_PM) || defined(CONFIG_PCI) |
999 | ||
1da177e4 | 1000 | /* must not be called from interrupt context */ |
95e44d44 | 1001 | int ohci_restart(struct ohci_hcd *ohci) |
1da177e4 LT |
1002 | { |
1003 | int temp; | |
1004 | int i; | |
1005 | struct urb_priv *priv; | |
1da177e4 | 1006 | |
95e44d44 | 1007 | ohci_init(ohci); |
1da177e4 | 1008 | spin_lock_irq(&ohci->lock); |
b7463c71 | 1009 | ohci->rh_state = OHCI_RH_HALTED; |
d576bb9f MH |
1010 | |
1011 | /* Recycle any "live" eds/tds (and urbs). */ | |
1da177e4 LT |
1012 | if (!list_empty (&ohci->pending)) |
1013 | ohci_dbg(ohci, "abort schedule...\n"); | |
1014 | list_for_each_entry (priv, &ohci->pending, pending) { | |
1015 | struct urb *urb = priv->td[0]->urb; | |
1016 | struct ed *ed = priv->ed; | |
1017 | ||
1018 | switch (ed->state) { | |
1019 | case ED_OPER: | |
1020 | ed->state = ED_UNLINK; | |
1021 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
1022 | ed_deschedule (ohci, ed); | |
1023 | ||
1024 | ed->ed_next = ohci->ed_rm_list; | |
1025 | ed->ed_prev = NULL; | |
1026 | ohci->ed_rm_list = ed; | |
1027 | /* FALLTHROUGH */ | |
1028 | case ED_UNLINK: | |
1029 | break; | |
1030 | default: | |
1031 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
1032 | ed, ed->state); | |
1033 | } | |
1034 | ||
55d84968 AS |
1035 | if (!urb->unlinked) |
1036 | urb->unlinked = -ESHUTDOWN; | |
1da177e4 | 1037 | } |
cdb4dd15 | 1038 | ohci_work(ohci); |
1da177e4 LT |
1039 | spin_unlock_irq(&ohci->lock); |
1040 | ||
1041 | /* paranoia, in case that didn't work: */ | |
1042 | ||
1043 | /* empty the interrupt branches */ | |
1044 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
1045 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
dd9048af | 1046 | |
1da177e4 LT |
1047 | /* no EDs to remove */ |
1048 | ohci->ed_rm_list = NULL; | |
1049 | ||
dd9048af | 1050 | /* empty control and bulk lists */ |
1da177e4 LT |
1051 | ohci->ed_controltail = NULL; |
1052 | ohci->ed_bulktail = NULL; | |
1053 | ||
1054 | if ((temp = ohci_run (ohci)) < 0) { | |
1055 | ohci_err (ohci, "can't restart, %d\n", temp); | |
1056 | return temp; | |
1da177e4 | 1057 | } |
383975d7 | 1058 | ohci_dbg(ohci, "restart complete\n"); |
1da177e4 LT |
1059 | return 0; |
1060 | } | |
95e44d44 | 1061 | EXPORT_SYMBOL_GPL(ohci_restart); |
d576bb9f | 1062 | |
da6fb570 DB |
1063 | #endif |
1064 | ||
cd1965db FF |
1065 | #ifdef CONFIG_PM |
1066 | ||
95e44d44 | 1067 | int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
cd1965db FF |
1068 | { |
1069 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
1070 | unsigned long flags; | |
e1bffbf6 | 1071 | int rc = 0; |
cd1965db | 1072 | |
d4ae47dc | 1073 | /* Disable irq emission and mark HW unaccessible. Use |
cd1965db FF |
1074 | * the spinlock to properly synchronize with possible pending |
1075 | * RH suspend or resume activity. | |
1076 | */ | |
1077 | spin_lock_irqsave (&ohci->lock, flags); | |
cd1965db FF |
1078 | ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
1079 | (void)ohci_readl(ohci, &ohci->regs->intrdisable); | |
1080 | ||
1081 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
cd1965db FF |
1082 | spin_unlock_irqrestore (&ohci->lock, flags); |
1083 | ||
e1bffbf6 MG |
1084 | synchronize_irq(hcd->irq); |
1085 | ||
1086 | if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) { | |
1087 | ohci_resume(hcd, false); | |
1088 | rc = -EBUSY; | |
1089 | } | |
1090 | return rc; | |
cd1965db | 1091 | } |
95e44d44 | 1092 | EXPORT_SYMBOL_GPL(ohci_suspend); |
cd1965db FF |
1093 | |
1094 | ||
95e44d44 | 1095 | int ohci_resume(struct usb_hcd *hcd, bool hibernated) |
cd1965db | 1096 | { |
cfa49b4b FF |
1097 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); |
1098 | int port; | |
1099 | bool need_reinit = false; | |
1100 | ||
cd1965db FF |
1101 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
1102 | ||
1103 | /* Make sure resume from hibernation re-enumerates everything */ | |
1104 | if (hibernated) | |
cfa49b4b FF |
1105 | ohci_usb_reset(ohci); |
1106 | ||
1107 | /* See if the controller is already running or has been reset */ | |
1108 | ohci->hc_control = ohci_readl(ohci, &ohci->regs->control); | |
1109 | if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) { | |
1110 | need_reinit = true; | |
1111 | } else { | |
1112 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
1113 | case OHCI_USB_OPER: | |
1114 | case OHCI_USB_RESET: | |
1115 | need_reinit = true; | |
1116 | } | |
1117 | } | |
1118 | ||
1119 | /* If needed, reinitialize and suspend the root hub */ | |
1120 | if (need_reinit) { | |
1121 | spin_lock_irq(&ohci->lock); | |
1122 | ohci_rh_resume(ohci); | |
1123 | ohci_rh_suspend(ohci, 0); | |
1124 | spin_unlock_irq(&ohci->lock); | |
1125 | } | |
1126 | ||
1127 | /* Normally just turn on port power and enable interrupts */ | |
1128 | else { | |
1129 | ohci_dbg(ohci, "powerup ports\n"); | |
1130 | for (port = 0; port < ohci->num_ports; port++) | |
1131 | ohci_writel(ohci, RH_PS_PPS, | |
1132 | &ohci->regs->roothub.portstatus[port]); | |
1133 | ||
1134 | ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable); | |
1135 | ohci_readl(ohci, &ohci->regs->intrenable); | |
1136 | msleep(20); | |
1137 | } | |
1138 | ||
1139 | usb_hcd_resume_root_hub(hcd); | |
cd1965db | 1140 | |
cd1965db FF |
1141 | return 0; |
1142 | } | |
95e44d44 MG |
1143 | EXPORT_SYMBOL_GPL(ohci_resume); |
1144 | ||
1145 | #endif | |
1146 | ||
1147 | /*-------------------------------------------------------------------------*/ | |
1148 | ||
1149 | /* | |
1150 | * Generic structure: This gets copied for platform drivers so that | |
1151 | * individual entries can be overridden as needed. | |
1152 | */ | |
cd1965db | 1153 | |
95e44d44 MG |
1154 | static const struct hc_driver ohci_hc_driver = { |
1155 | .description = hcd_name, | |
1156 | .product_desc = "OHCI Host Controller", | |
1157 | .hcd_priv_size = sizeof(struct ohci_hcd), | |
1158 | ||
1159 | /* | |
1160 | * generic hardware linkage | |
1161 | */ | |
1162 | .irq = ohci_irq, | |
1163 | .flags = HCD_MEMORY | HCD_USB11, | |
1164 | ||
1165 | /* | |
1166 | * basic lifecycle operations | |
1167 | */ | |
1168 | .reset = ohci_setup, | |
1169 | .start = ohci_start, | |
1170 | .stop = ohci_stop, | |
1171 | .shutdown = ohci_shutdown, | |
1172 | ||
1173 | /* | |
1174 | * managing i/o requests and associated device resources | |
1175 | */ | |
1176 | .urb_enqueue = ohci_urb_enqueue, | |
1177 | .urb_dequeue = ohci_urb_dequeue, | |
1178 | .endpoint_disable = ohci_endpoint_disable, | |
1179 | ||
1180 | /* | |
1181 | * scheduling support | |
1182 | */ | |
1183 | .get_frame_number = ohci_get_frame, | |
1184 | ||
1185 | /* | |
1186 | * root hub support | |
1187 | */ | |
1188 | .hub_status_data = ohci_hub_status_data, | |
1189 | .hub_control = ohci_hub_control, | |
1190 | #ifdef CONFIG_PM | |
1191 | .bus_suspend = ohci_bus_suspend, | |
1192 | .bus_resume = ohci_bus_resume, | |
cd1965db | 1193 | #endif |
95e44d44 MG |
1194 | .start_port_reset = ohci_start_port_reset, |
1195 | }; | |
1196 | ||
1197 | void ohci_init_driver(struct hc_driver *drv, | |
1198 | const struct ohci_driver_overrides *over) | |
1199 | { | |
1200 | /* Copy the generic table to drv and then apply the overrides */ | |
1201 | *drv = ohci_hc_driver; | |
1202 | ||
c80ad6d1 KH |
1203 | if (over) { |
1204 | drv->product_desc = over->product_desc; | |
1205 | drv->hcd_priv_size += over->extra_priv_size; | |
1206 | if (over->reset) | |
1207 | drv->reset = over->reset; | |
1208 | } | |
95e44d44 MG |
1209 | } |
1210 | EXPORT_SYMBOL_GPL(ohci_init_driver); | |
cd1965db | 1211 | |
d576bb9f MH |
1212 | /*-------------------------------------------------------------------------*/ |
1213 | ||
1da177e4 | 1214 | MODULE_AUTHOR (DRIVER_AUTHOR); |
2b70f073 | 1215 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1216 | MODULE_LICENSE ("GPL"); |
1217 | ||
6381fad7 | 1218 | #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) |
1da177e4 | 1219 | #include "ohci-sa1111.c" |
5e16fabe | 1220 | #define SA1111_DRIVER ohci_hcd_sa1111_driver |
1da177e4 LT |
1221 | #endif |
1222 | ||
068413e9 | 1223 | #ifdef CONFIG_USB_OHCI_HCD_DAVINCI |
efe7daf2 | 1224 | #include "ohci-da8xx.c" |
8097804e | 1225 | #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver |
efe7daf2 SS |
1226 | #endif |
1227 | ||
495a678f SM |
1228 | #ifdef CONFIG_USB_OHCI_HCD_PPC_OF |
1229 | #include "ohci-ppc-of.c" | |
1230 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | |
1231 | #endif | |
1232 | ||
6a6c957e GL |
1233 | #ifdef CONFIG_PPC_PS3 |
1234 | #include "ohci-ps3.c" | |
7a4eb7fd | 1235 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver |
6a6c957e GL |
1236 | #endif |
1237 | ||
f54aab6e MD |
1238 | #ifdef CONFIG_MFD_SM501 |
1239 | #include "ohci-sm501.c" | |
3ee38d8b | 1240 | #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver |
f54aab6e MD |
1241 | #endif |
1242 | ||
78c73414 DB |
1243 | #ifdef CONFIG_MFD_TC6393XB |
1244 | #include "ohci-tmio.c" | |
1245 | #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver | |
2249071b LPC |
1246 | #endif |
1247 | ||
1248 | #ifdef CONFIG_MACH_JZ4740 | |
1249 | #include "ohci-jz4740.c" | |
1250 | #define PLATFORM_DRIVER ohci_hcd_jz4740_driver | |
1643accd DD |
1251 | #endif |
1252 | ||
47fc28bf CM |
1253 | #ifdef CONFIG_TILE_USB |
1254 | #include "ohci-tilegx.c" | |
1255 | #define PLATFORM_DRIVER ohci_hcd_tilegx_driver | |
1256 | #endif | |
1257 | ||
5e16fabe SM |
1258 | static int __init ohci_hcd_mod_init(void) |
1259 | { | |
1260 | int retval = 0; | |
5e16fabe SM |
1261 | |
1262 | if (usb_disabled()) | |
1263 | return -ENODEV; | |
1264 | ||
2b70f073 | 1265 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); |
5e16fabe SM |
1266 | pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, |
1267 | sizeof (struct ed), sizeof (struct td)); | |
9beeee65 | 1268 | set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe | 1269 | |
485f4f39 | 1270 | ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); |
684c19e0 TJ |
1271 | if (!ohci_debug_root) { |
1272 | retval = -ENOENT; | |
1273 | goto error_debug; | |
1274 | } | |
684c19e0 | 1275 | |
6a6c957e | 1276 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd GL |
1277 | retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
1278 | if (retval < 0) | |
1279 | goto error_ps3; | |
6a6c957e GL |
1280 | #endif |
1281 | ||
5e16fabe SM |
1282 | #ifdef PLATFORM_DRIVER |
1283 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
1284 | if (retval < 0) | |
de44743b | 1285 | goto error_platform; |
5e16fabe SM |
1286 | #endif |
1287 | ||
495a678f | 1288 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1289 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
495a678f | 1290 | if (retval < 0) |
de44743b | 1291 | goto error_of_platform; |
495a678f SM |
1292 | #endif |
1293 | ||
5e16fabe SM |
1294 | #ifdef SA1111_DRIVER |
1295 | retval = sa1111_driver_register(&SA1111_DRIVER); | |
1296 | if (retval < 0) | |
de44743b | 1297 | goto error_sa1111; |
5e16fabe SM |
1298 | #endif |
1299 | ||
3ee38d8b BD |
1300 | #ifdef SM501_OHCI_DRIVER |
1301 | retval = platform_driver_register(&SM501_OHCI_DRIVER); | |
1302 | if (retval < 0) | |
1303 | goto error_sm501; | |
1304 | #endif | |
1305 | ||
78c73414 DB |
1306 | #ifdef TMIO_OHCI_DRIVER |
1307 | retval = platform_driver_register(&TMIO_OHCI_DRIVER); | |
1308 | if (retval < 0) | |
1309 | goto error_tmio; | |
1310 | #endif | |
1311 | ||
8097804e AB |
1312 | #ifdef DAVINCI_PLATFORM_DRIVER |
1313 | retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER); | |
1314 | if (retval < 0) | |
1315 | goto error_davinci; | |
1316 | #endif | |
1317 | ||
5e16fabe SM |
1318 | return retval; |
1319 | ||
1320 | /* Error path */ | |
8097804e AB |
1321 | #ifdef DAVINCI_PLATFORM_DRIVER |
1322 | platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER); | |
1323 | error_davinci: | |
1324 | #endif | |
78c73414 DB |
1325 | #ifdef TMIO_OHCI_DRIVER |
1326 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1327 | error_tmio: | |
1328 | #endif | |
3ee38d8b | 1329 | #ifdef SM501_OHCI_DRIVER |
78c73414 | 1330 | platform_driver_unregister(&SM501_OHCI_DRIVER); |
3ee38d8b BD |
1331 | error_sm501: |
1332 | #endif | |
de44743b BH |
1333 | #ifdef SA1111_DRIVER |
1334 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1335 | error_sa1111: | |
5e16fabe | 1336 | #endif |
495a678f | 1337 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1338 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
de44743b | 1339 | error_of_platform: |
495a678f | 1340 | #endif |
8097804e AB |
1341 | #ifdef PLATFORM_DRIVER |
1342 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1343 | error_platform: | |
968b448b | 1344 | #endif |
6a6c957e | 1345 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1346 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1347 | error_ps3: |
5e16fabe | 1348 | #endif |
684c19e0 TJ |
1349 | debugfs_remove(ohci_debug_root); |
1350 | ohci_debug_root = NULL; | |
1351 | error_debug: | |
684c19e0 | 1352 | |
9beeee65 | 1353 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1354 | return retval; |
1355 | } | |
1356 | module_init(ohci_hcd_mod_init); | |
1357 | ||
1358 | static void __exit ohci_hcd_mod_exit(void) | |
1359 | { | |
8097804e AB |
1360 | #ifdef DAVINCI_PLATFORM_DRIVER |
1361 | platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER); | |
1362 | #endif | |
78c73414 DB |
1363 | #ifdef TMIO_OHCI_DRIVER |
1364 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1365 | #endif | |
3ee38d8b BD |
1366 | #ifdef SM501_OHCI_DRIVER |
1367 | platform_driver_unregister(&SM501_OHCI_DRIVER); | |
1368 | #endif | |
5e16fabe SM |
1369 | #ifdef SA1111_DRIVER |
1370 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1371 | #endif | |
495a678f | 1372 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1373 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
495a678f | 1374 | #endif |
8097804e AB |
1375 | #ifdef PLATFORM_DRIVER |
1376 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1377 | #endif | |
6a6c957e | 1378 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1379 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1380 | #endif |
684c19e0 | 1381 | debugfs_remove(ohci_debug_root); |
9beeee65 | 1382 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1383 | } |
1384 | module_exit(ohci_hcd_mod_exit); | |
1385 |