Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
578333ab AS |
2 | * Open Host Controller Interface (OHCI) driver for USB. |
3 | * | |
4 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
1da177e4 LT |
5 | * |
6 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> | |
7 | * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> | |
dd9048af | 8 | * |
1da177e4 LT |
9 | * [ Initialisation is based on Linus' ] |
10 | * [ uhci code and gregs ohci fragments ] | |
11 | * [ (C) Copyright 1999 Linus Torvalds ] | |
12 | * [ (C) Copyright 1999 Gregory P. Smith] | |
dd9048af DB |
13 | * |
14 | * | |
1da177e4 LT |
15 | * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller |
16 | * interfaces (though some non-x86 Intel chips use it). It supports | |
17 | * smarter hardware than UHCI. A download link for the spec available | |
18 | * through the http://www.usb.org website. | |
19 | * | |
1da177e4 LT |
20 | * This file is licenced under the GPL. |
21 | */ | |
dd9048af | 22 | |
1da177e4 LT |
23 | #include <linux/module.h> |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/sched.h> | |
30 | #include <linux/slab.h> | |
1da177e4 LT |
31 | #include <linux/errno.h> |
32 | #include <linux/init.h> | |
33 | #include <linux/timer.h> | |
34 | #include <linux/list.h> | |
1da177e4 | 35 | #include <linux/usb.h> |
3a16f7b4 | 36 | #include <linux/usb/otg.h> |
27729aad | 37 | #include <linux/usb/hcd.h> |
dd9048af | 38 | #include <linux/dma-mapping.h> |
f4df0e33 | 39 | #include <linux/dmapool.h> |
d576bb9f | 40 | #include <linux/workqueue.h> |
684c19e0 | 41 | #include <linux/debugfs.h> |
1da177e4 LT |
42 | |
43 | #include <asm/io.h> | |
44 | #include <asm/irq.h> | |
1da177e4 LT |
45 | #include <asm/unaligned.h> |
46 | #include <asm/byteorder.h> | |
47 | ||
48 | ||
1da177e4 LT |
49 | #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" |
50 | #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" | |
51 | ||
52 | /*-------------------------------------------------------------------------*/ | |
53 | ||
8de98402 | 54 | #undef OHCI_VERBOSE_DEBUG /* not always helpful */ |
1da177e4 LT |
55 | |
56 | /* For initializing controller (mask in an HCFS mode too) */ | |
d413984a | 57 | #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR |
1da177e4 | 58 | #define OHCI_INTR_INIT \ |
d413984a DB |
59 | (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ |
60 | | OHCI_INTR_RD | OHCI_INTR_WDH) | |
1da177e4 LT |
61 | |
62 | #ifdef __hppa__ | |
63 | /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ | |
64 | #define IR_DISABLE | |
65 | #endif | |
66 | ||
67 | #ifdef CONFIG_ARCH_OMAP | |
68 | /* OMAP doesn't support IR (no SMM; not needed) */ | |
69 | #define IR_DISABLE | |
70 | #endif | |
71 | ||
72 | /*-------------------------------------------------------------------------*/ | |
73 | ||
74 | static const char hcd_name [] = "ohci_hcd"; | |
75 | ||
d413984a DB |
76 | #define STATECHANGE_DELAY msecs_to_jiffies(300) |
77 | ||
1da177e4 | 78 | #include "ohci.h" |
ad93562b | 79 | #include "pci-quirks.h" |
1da177e4 LT |
80 | |
81 | static void ohci_dump (struct ohci_hcd *ohci, int verbose); | |
1da177e4 | 82 | static void ohci_stop (struct usb_hcd *hcd); |
ab1666c1 | 83 | |
1da177e4 LT |
84 | #include "ohci-hub.c" |
85 | #include "ohci-dbg.c" | |
86 | #include "ohci-mem.c" | |
87 | #include "ohci-q.c" | |
88 | ||
89 | ||
90 | /* | |
91 | * On architectures with edge-triggered interrupts we must never return | |
92 | * IRQ_NONE. | |
93 | */ | |
94 | #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ | |
95 | #define IRQ_NOTMINE IRQ_HANDLED | |
96 | #else | |
97 | #define IRQ_NOTMINE IRQ_NONE | |
98 | #endif | |
99 | ||
100 | ||
101 | /* Some boards misreport power switching/overcurrent */ | |
90ab5ee9 | 102 | static bool distrust_firmware = 1; |
1da177e4 LT |
103 | module_param (distrust_firmware, bool, 0); |
104 | MODULE_PARM_DESC (distrust_firmware, | |
105 | "true to distrust firmware power/overcurrent setup"); | |
106 | ||
107 | /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ | |
90ab5ee9 | 108 | static bool no_handshake = 0; |
1da177e4 LT |
109 | module_param (no_handshake, bool, 0); |
110 | MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); | |
111 | ||
112 | /*-------------------------------------------------------------------------*/ | |
113 | ||
114 | /* | |
115 | * queue up an urb for anything except the root hub | |
116 | */ | |
117 | static int ohci_urb_enqueue ( | |
118 | struct usb_hcd *hcd, | |
1da177e4 | 119 | struct urb *urb, |
55016f10 | 120 | gfp_t mem_flags |
1da177e4 LT |
121 | ) { |
122 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
123 | struct ed *ed; | |
124 | urb_priv_t *urb_priv; | |
125 | unsigned int pipe = urb->pipe; | |
126 | int i, size = 0; | |
127 | unsigned long flags; | |
128 | int retval = 0; | |
dd9048af | 129 | |
1da177e4 | 130 | #ifdef OHCI_VERBOSE_DEBUG |
55d84968 | 131 | urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); |
1da177e4 | 132 | #endif |
dd9048af | 133 | |
1da177e4 | 134 | /* every endpoint has a ed, locate and maybe (re)initialize it */ |
e9df41c5 | 135 | if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) |
1da177e4 LT |
136 | return -ENOMEM; |
137 | ||
138 | /* for the private part of the URB we need the number of TDs (size) */ | |
139 | switch (ed->type) { | |
140 | case PIPE_CONTROL: | |
141 | /* td_submit_urb() doesn't yet handle these */ | |
142 | if (urb->transfer_buffer_length > 4096) | |
143 | return -EMSGSIZE; | |
144 | ||
145 | /* 1 TD for setup, 1 for ACK, plus ... */ | |
146 | size = 2; | |
147 | /* FALLTHROUGH */ | |
148 | // case PIPE_INTERRUPT: | |
149 | // case PIPE_BULK: | |
150 | default: | |
25985edc | 151 | /* one TD for every 4096 Bytes (can be up to 8K) */ |
1da177e4 LT |
152 | size += urb->transfer_buffer_length / 4096; |
153 | /* ... and for any remaining bytes ... */ | |
154 | if ((urb->transfer_buffer_length % 4096) != 0) | |
155 | size++; | |
156 | /* ... and maybe a zero length packet to wrap it up */ | |
157 | if (size == 0) | |
158 | size++; | |
159 | else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 | |
160 | && (urb->transfer_buffer_length | |
161 | % usb_maxpacket (urb->dev, pipe, | |
162 | usb_pipeout (pipe))) == 0) | |
163 | size++; | |
164 | break; | |
165 | case PIPE_ISOCHRONOUS: /* number of packets from URB */ | |
166 | size = urb->number_of_packets; | |
167 | break; | |
168 | } | |
169 | ||
170 | /* allocate the private part of the URB */ | |
dd00cc48 | 171 | urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), |
1da177e4 LT |
172 | mem_flags); |
173 | if (!urb_priv) | |
174 | return -ENOMEM; | |
1da177e4 LT |
175 | INIT_LIST_HEAD (&urb_priv->pending); |
176 | urb_priv->length = size; | |
dd9048af | 177 | urb_priv->ed = ed; |
1da177e4 LT |
178 | |
179 | /* allocate the TDs (deferring hash chain updates) */ | |
180 | for (i = 0; i < size; i++) { | |
181 | urb_priv->td [i] = td_alloc (ohci, mem_flags); | |
182 | if (!urb_priv->td [i]) { | |
183 | urb_priv->length = i; | |
184 | urb_free_priv (ohci, urb_priv); | |
185 | return -ENOMEM; | |
186 | } | |
dd9048af | 187 | } |
1da177e4 LT |
188 | |
189 | spin_lock_irqsave (&ohci->lock, flags); | |
190 | ||
191 | /* don't submit to a dead HC */ | |
541c7d43 | 192 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
8de98402 BH |
193 | retval = -ENODEV; |
194 | goto fail; | |
195 | } | |
b7463c71 | 196 | if (ohci->rh_state != OHCI_RH_RUNNING) { |
1da177e4 LT |
197 | retval = -ENODEV; |
198 | goto fail; | |
199 | } | |
e9df41c5 AS |
200 | retval = usb_hcd_link_urb_to_ep(hcd, urb); |
201 | if (retval) | |
1da177e4 | 202 | goto fail; |
1da177e4 LT |
203 | |
204 | /* schedule the ed if needed */ | |
205 | if (ed->state == ED_IDLE) { | |
206 | retval = ed_schedule (ohci, ed); | |
e9df41c5 AS |
207 | if (retval < 0) { |
208 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
209 | goto fail; | |
210 | } | |
1da177e4 LT |
211 | if (ed->type == PIPE_ISOCHRONOUS) { |
212 | u16 frame = ohci_frame_no(ohci); | |
213 | ||
214 | /* delay a few frames before the first TD */ | |
215 | frame += max_t (u16, 8, ed->interval); | |
216 | frame &= ~(ed->interval - 1); | |
217 | frame |= ed->branch; | |
218 | urb->start_frame = frame; | |
a8693424 | 219 | ed->last_iso = frame + ed->interval * (size - 1); |
6a41b4d3 AS |
220 | } |
221 | } else if (ed->type == PIPE_ISOCHRONOUS) { | |
e1944017 | 222 | u16 next = ohci_frame_no(ohci) + 1; |
6a41b4d3 | 223 | u16 frame = ed->last_iso + ed->interval; |
a8693424 | 224 | u16 length = ed->interval * (size - 1); |
6a41b4d3 AS |
225 | |
226 | /* Behind the scheduling threshold? */ | |
227 | if (unlikely(tick_before(frame, next))) { | |
228 | ||
a8693424 | 229 | /* URB_ISO_ASAP: Round up to the first available slot */ |
815fa7b9 | 230 | if (urb->transfer_flags & URB_ISO_ASAP) { |
6a41b4d3 AS |
231 | frame += (next - frame + ed->interval - 1) & |
232 | -ed->interval; | |
1da177e4 | 233 | |
6a41b4d3 | 234 | /* |
a8693424 AS |
235 | * Not ASAP: Use the next slot in the stream, |
236 | * no matter what. | |
1da177e4 | 237 | */ |
815fa7b9 | 238 | } else { |
815fa7b9 AS |
239 | /* |
240 | * Some OHCI hardware doesn't handle late TDs | |
241 | * correctly. After retiring them it proceeds | |
242 | * to the next ED instead of the next TD. | |
243 | * Therefore we have to omit the late TDs | |
244 | * entirely. | |
245 | */ | |
246 | urb_priv->td_cnt = DIV_ROUND_UP( | |
247 | (u16) (next - frame), | |
248 | ed->interval); | |
a8693424 AS |
249 | if (urb_priv->td_cnt >= urb_priv->length) { |
250 | ++urb_priv->td_cnt; /* Mark it */ | |
251 | ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n", | |
252 | urb, frame, length, | |
253 | next); | |
254 | } | |
6a41b4d3 | 255 | } |
1da177e4 | 256 | } |
6a41b4d3 | 257 | urb->start_frame = frame; |
a8693424 | 258 | ed->last_iso = frame + length; |
6a41b4d3 | 259 | } |
1da177e4 LT |
260 | |
261 | /* fill the TDs and link them to the ed; and | |
262 | * enable that part of the schedule, if needed | |
263 | * and update count of queued periodic urbs | |
264 | */ | |
265 | urb->hcpriv = urb_priv; | |
266 | td_submit_urb (ohci, urb); | |
267 | ||
1da177e4 LT |
268 | fail: |
269 | if (retval) | |
270 | urb_free_priv (ohci, urb_priv); | |
271 | spin_unlock_irqrestore (&ohci->lock, flags); | |
272 | return retval; | |
273 | } | |
274 | ||
275 | /* | |
55d84968 AS |
276 | * decouple the URB from the HC queues (TDs, urb_priv). |
277 | * reporting is always done | |
1da177e4 LT |
278 | * asynchronously, and we might be dealing with an urb that's |
279 | * partially transferred, or an ED with other urbs being unlinked. | |
280 | */ | |
e9df41c5 | 281 | static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
1da177e4 LT |
282 | { |
283 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
284 | unsigned long flags; | |
e9df41c5 | 285 | int rc; |
dd9048af | 286 | |
1da177e4 | 287 | #ifdef OHCI_VERBOSE_DEBUG |
55d84968 | 288 | urb_print(urb, "UNLINK", 1, status); |
dd9048af | 289 | #endif |
1da177e4 LT |
290 | |
291 | spin_lock_irqsave (&ohci->lock, flags); | |
e9df41c5 AS |
292 | rc = usb_hcd_check_unlink_urb(hcd, urb, status); |
293 | if (rc) { | |
294 | ; /* Do nothing */ | |
b7463c71 | 295 | } else if (ohci->rh_state == OHCI_RH_RUNNING) { |
1da177e4 LT |
296 | urb_priv_t *urb_priv; |
297 | ||
298 | /* Unless an IRQ completed the unlink while it was being | |
299 | * handed to us, flag it for unlink and giveback, and force | |
300 | * some upcoming INTR_SF to call finish_unlinks() | |
301 | */ | |
302 | urb_priv = urb->hcpriv; | |
303 | if (urb_priv) { | |
304 | if (urb_priv->ed->state == ED_OPER) | |
305 | start_ed_unlink (ohci, urb_priv->ed); | |
306 | } | |
307 | } else { | |
308 | /* | |
309 | * with HC dead, we won't respect hc queue pointers | |
310 | * any more ... just clean up every urb's memory. | |
311 | */ | |
312 | if (urb->hcpriv) | |
55d84968 | 313 | finish_urb(ohci, urb, status); |
1da177e4 LT |
314 | } |
315 | spin_unlock_irqrestore (&ohci->lock, flags); | |
e9df41c5 | 316 | return rc; |
1da177e4 LT |
317 | } |
318 | ||
319 | /*-------------------------------------------------------------------------*/ | |
320 | ||
321 | /* frees config/altsetting state for endpoints, | |
322 | * including ED memory, dummy TD, and bulk/intr data toggle | |
323 | */ | |
324 | ||
325 | static void | |
326 | ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) | |
327 | { | |
328 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
329 | unsigned long flags; | |
330 | struct ed *ed = ep->hcpriv; | |
331 | unsigned limit = 1000; | |
332 | ||
333 | /* ASSERT: any requests/urbs are being unlinked */ | |
334 | /* ASSERT: nobody can be submitting urbs for this any more */ | |
335 | ||
336 | if (!ed) | |
337 | return; | |
338 | ||
339 | rescan: | |
340 | spin_lock_irqsave (&ohci->lock, flags); | |
341 | ||
b7463c71 | 342 | if (ohci->rh_state != OHCI_RH_RUNNING) { |
1da177e4 LT |
343 | sanitize: |
344 | ed->state = ED_IDLE; | |
89a0fd18 MN |
345 | if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) |
346 | ohci->eds_scheduled--; | |
7d12e780 | 347 | finish_unlinks (ohci, 0); |
1da177e4 LT |
348 | } |
349 | ||
350 | switch (ed->state) { | |
351 | case ED_UNLINK: /* wait for hw to finish? */ | |
352 | /* major IRQ delivery trouble loses INTR_SF too... */ | |
353 | if (limit-- == 0) { | |
89a0fd18 MN |
354 | ohci_warn(ohci, "ED unlink timeout\n"); |
355 | if (quirk_zfmicro(ohci)) { | |
356 | ohci_warn(ohci, "Attempting ZF TD recovery\n"); | |
357 | ohci->ed_to_check = ed; | |
358 | ohci->zf_delay = 2; | |
359 | } | |
1da177e4 LT |
360 | goto sanitize; |
361 | } | |
362 | spin_unlock_irqrestore (&ohci->lock, flags); | |
22c43863 | 363 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
364 | goto rescan; |
365 | case ED_IDLE: /* fully unlinked */ | |
366 | if (list_empty (&ed->td_list)) { | |
367 | td_free (ohci, ed->dummy); | |
368 | ed_free (ohci, ed); | |
369 | break; | |
370 | } | |
371 | /* else FALL THROUGH */ | |
372 | default: | |
373 | /* caller was supposed to have unlinked any requests; | |
374 | * that's not our job. can't recover; must leak ed. | |
375 | */ | |
376 | ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", | |
377 | ed, ep->desc.bEndpointAddress, ed->state, | |
378 | list_empty (&ed->td_list) ? "" : " (has tds)"); | |
379 | td_free (ohci, ed->dummy); | |
380 | break; | |
381 | } | |
382 | ep->hcpriv = NULL; | |
383 | spin_unlock_irqrestore (&ohci->lock, flags); | |
1da177e4 LT |
384 | } |
385 | ||
386 | static int ohci_get_frame (struct usb_hcd *hcd) | |
387 | { | |
388 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
389 | ||
390 | return ohci_frame_no(ohci); | |
391 | } | |
392 | ||
393 | static void ohci_usb_reset (struct ohci_hcd *ohci) | |
394 | { | |
395 | ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); | |
396 | ohci->hc_control &= OHCI_CTRL_RWC; | |
397 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
b7463c71 | 398 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 LT |
399 | } |
400 | ||
64a21d02 | 401 | /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and |
f4df0e33 DB |
402 | * other cases where the next software may expect clean state from the |
403 | * "firmware". this is bus-neutral, unlike shutdown() methods. | |
404 | */ | |
64a21d02 AG |
405 | static void |
406 | ohci_shutdown (struct usb_hcd *hcd) | |
f4df0e33 DB |
407 | { |
408 | struct ohci_hcd *ohci; | |
409 | ||
64a21d02 | 410 | ohci = hcd_to_ohci (hcd); |
c6187597 | 411 | ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable); |
3df7169e | 412 | |
c6187597 AS |
413 | /* Software reset, after which the controller goes into SUSPEND */ |
414 | ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
415 | ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */ | |
416 | udelay(10); | |
3df7169e | 417 | |
c6187597 | 418 | ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval); |
f4df0e33 DB |
419 | } |
420 | ||
89a0fd18 MN |
421 | static int check_ed(struct ohci_hcd *ohci, struct ed *ed) |
422 | { | |
423 | return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 | |
424 | && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) | |
425 | == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) | |
426 | && !list_empty(&ed->td_list); | |
427 | } | |
428 | ||
429 | /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes | |
430 | * an interrupt TD but neglects to add it to the donelist. On systems with | |
431 | * this chipset, we need to periodically check the state of the queues to look | |
432 | * for such "lost" TDs. | |
433 | */ | |
434 | static void unlink_watchdog_func(unsigned long _ohci) | |
435 | { | |
da6fb570 | 436 | unsigned long flags; |
89a0fd18 MN |
437 | unsigned max; |
438 | unsigned seen_count = 0; | |
439 | unsigned i; | |
440 | struct ed **seen = NULL; | |
441 | struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; | |
442 | ||
443 | spin_lock_irqsave(&ohci->lock, flags); | |
444 | max = ohci->eds_scheduled; | |
445 | if (!max) | |
446 | goto done; | |
447 | ||
448 | if (ohci->ed_to_check) | |
449 | goto out; | |
450 | ||
451 | seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); | |
452 | if (!seen) | |
453 | goto out; | |
454 | ||
455 | for (i = 0; i < NUM_INTS; i++) { | |
456 | struct ed *ed = ohci->periodic[i]; | |
457 | ||
458 | while (ed) { | |
459 | unsigned temp; | |
460 | ||
461 | /* scan this branch of the periodic schedule tree */ | |
462 | for (temp = 0; temp < seen_count; temp++) { | |
463 | if (seen[temp] == ed) { | |
464 | /* we've checked it and what's after */ | |
465 | ed = NULL; | |
466 | break; | |
467 | } | |
468 | } | |
469 | if (!ed) | |
470 | break; | |
471 | seen[seen_count++] = ed; | |
472 | if (!check_ed(ohci, ed)) { | |
473 | ed = ed->ed_next; | |
474 | continue; | |
475 | } | |
476 | ||
477 | /* HC's TD list is empty, but HCD sees at least one | |
478 | * TD that's not been sent through the donelist. | |
479 | */ | |
480 | ohci->ed_to_check = ed; | |
481 | ohci->zf_delay = 2; | |
482 | ||
483 | /* The HC may wait until the next frame to report the | |
484 | * TD as done through the donelist and INTR_WDH. (We | |
485 | * just *assume* it's not a multi-TD interrupt URB; | |
486 | * those could defer the IRQ more than one frame, using | |
487 | * DI...) Check again after the next INTR_SF. | |
488 | */ | |
489 | ohci_writel(ohci, OHCI_INTR_SF, | |
490 | &ohci->regs->intrstatus); | |
491 | ohci_writel(ohci, OHCI_INTR_SF, | |
492 | &ohci->regs->intrenable); | |
493 | ||
494 | /* flush those writes */ | |
495 | (void) ohci_readl(ohci, &ohci->regs->control); | |
496 | ||
497 | goto out; | |
498 | } | |
499 | } | |
500 | out: | |
501 | kfree(seen); | |
502 | if (ohci->eds_scheduled) | |
9cebcdc7 | 503 | mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); |
89a0fd18 MN |
504 | done: |
505 | spin_unlock_irqrestore(&ohci->lock, flags); | |
506 | } | |
507 | ||
1da177e4 LT |
508 | /*-------------------------------------------------------------------------* |
509 | * HC functions | |
510 | *-------------------------------------------------------------------------*/ | |
511 | ||
512 | /* init memory, and kick BIOS/SMM off */ | |
513 | ||
514 | static int ohci_init (struct ohci_hcd *ohci) | |
515 | { | |
516 | int ret; | |
6a9062f3 | 517 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 518 | |
1133cd8a DB |
519 | if (distrust_firmware) |
520 | ohci->flags |= OHCI_QUIRK_HUB_POWER; | |
521 | ||
b7463c71 | 522 | ohci->rh_state = OHCI_RH_HALTED; |
6a9062f3 | 523 | ohci->regs = hcd->regs; |
1da177e4 | 524 | |
6a9062f3 DB |
525 | /* REVISIT this BIOS handshake is now moved into PCI "quirks", and |
526 | * was never needed for most non-PCI systems ... remove the code? | |
527 | */ | |
528 | ||
1da177e4 LT |
529 | #ifndef IR_DISABLE |
530 | /* SMM owns the HC? not for long! */ | |
531 | if (!no_handshake && ohci_readl (ohci, | |
532 | &ohci->regs->control) & OHCI_CTRL_IR) { | |
533 | u32 temp; | |
534 | ||
535 | ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); | |
536 | ||
537 | /* this timeout is arbitrary. we make it long, so systems | |
538 | * depending on usb keyboards may be usable even if the | |
539 | * BIOS/SMM code seems pretty broken. | |
540 | */ | |
541 | temp = 500; /* arbitrary: five seconds */ | |
542 | ||
543 | ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); | |
544 | ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); | |
545 | while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { | |
546 | msleep (10); | |
547 | if (--temp == 0) { | |
548 | ohci_err (ohci, "USB HC takeover failed!" | |
549 | " (BIOS/SMM bug)\n"); | |
550 | return -EBUSY; | |
551 | } | |
552 | } | |
553 | ohci_usb_reset (ohci); | |
554 | } | |
555 | #endif | |
556 | ||
557 | /* Disable HC interrupts */ | |
558 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); | |
6a9062f3 DB |
559 | |
560 | /* flush the writes, and save key bits like RWC */ | |
561 | if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) | |
562 | ohci->hc_control |= OHCI_CTRL_RWC; | |
1da177e4 | 563 | |
fdd13b36 DB |
564 | /* Read the number of ports unless overridden */ |
565 | if (ohci->num_ports == 0) | |
566 | ohci->num_ports = roothub_a(ohci) & RH_A_NDP; | |
567 | ||
1da177e4 LT |
568 | if (ohci->hcca) |
569 | return 0; | |
570 | ||
6a9062f3 | 571 | ohci->hcca = dma_alloc_coherent (hcd->self.controller, |
1da177e4 LT |
572 | sizeof *ohci->hcca, &ohci->hcca_dma, 0); |
573 | if (!ohci->hcca) | |
574 | return -ENOMEM; | |
575 | ||
576 | if ((ret = ohci_mem_init (ohci)) < 0) | |
6a9062f3 DB |
577 | ohci_stop (hcd); |
578 | else { | |
6a9062f3 DB |
579 | create_debug_files (ohci); |
580 | } | |
1da177e4 LT |
581 | |
582 | return ret; | |
1da177e4 LT |
583 | } |
584 | ||
585 | /*-------------------------------------------------------------------------*/ | |
586 | ||
587 | /* Start an OHCI controller, set the BUS operational | |
588 | * resets USB and controller | |
dd9048af | 589 | * enable interrupts |
1da177e4 LT |
590 | */ |
591 | static int ohci_run (struct ohci_hcd *ohci) | |
592 | { | |
96f90a8b | 593 | u32 mask, val; |
1da177e4 | 594 | int first = ohci->fminterval == 0; |
6a9062f3 | 595 | struct usb_hcd *hcd = ohci_to_hcd(ohci); |
1da177e4 | 596 | |
b7463c71 | 597 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 LT |
598 | |
599 | /* boot firmware should have set this up (5.1.1.3.1) */ | |
600 | if (first) { | |
601 | ||
96f90a8b HS |
602 | val = ohci_readl (ohci, &ohci->regs->fminterval); |
603 | ohci->fminterval = val & 0x3fff; | |
1da177e4 LT |
604 | if (ohci->fminterval != FI) |
605 | ohci_dbg (ohci, "fminterval delta %d\n", | |
606 | ohci->fminterval - FI); | |
607 | ohci->fminterval |= FSMP (ohci->fminterval) << 16; | |
608 | /* also: power/overcurrent flags in roothub.a */ | |
609 | } | |
610 | ||
6fd9086a AS |
611 | /* Reset USB nearly "by the book". RemoteWakeupConnected has |
612 | * to be checked in case boot firmware (BIOS/SMM/...) has set up | |
613 | * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). | |
614 | * If the bus glue detected wakeup capability then it should | |
bcca06ef | 615 | * already be enabled; if so we'll just enable it again. |
1da177e4 | 616 | */ |
bcca06ef AS |
617 | if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) |
618 | device_set_wakeup_capable(hcd->self.controller, 1); | |
1da177e4 LT |
619 | |
620 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
621 | case OHCI_USB_OPER: | |
96f90a8b | 622 | val = 0; |
1da177e4 LT |
623 | break; |
624 | case OHCI_USB_SUSPEND: | |
625 | case OHCI_USB_RESUME: | |
626 | ohci->hc_control &= OHCI_CTRL_RWC; | |
627 | ohci->hc_control |= OHCI_USB_RESUME; | |
96f90a8b | 628 | val = 10 /* msec wait */; |
1da177e4 LT |
629 | break; |
630 | // case OHCI_USB_RESET: | |
631 | default: | |
632 | ohci->hc_control &= OHCI_CTRL_RWC; | |
633 | ohci->hc_control |= OHCI_USB_RESET; | |
96f90a8b | 634 | val = 50 /* msec wait */; |
1da177e4 LT |
635 | break; |
636 | } | |
637 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
638 | // flush the writes | |
639 | (void) ohci_readl (ohci, &ohci->regs->control); | |
96f90a8b | 640 | msleep(val); |
383975d7 | 641 | |
1da177e4 LT |
642 | memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); |
643 | ||
644 | /* 2msec timelimit here means no irqs/preempt */ | |
645 | spin_lock_irq (&ohci->lock); | |
646 | ||
647 | retry: | |
648 | /* HC Reset requires max 10 us delay */ | |
649 | ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); | |
96f90a8b | 650 | val = 30; /* ... allow extra time */ |
1da177e4 | 651 | while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { |
96f90a8b | 652 | if (--val == 0) { |
1da177e4 LT |
653 | spin_unlock_irq (&ohci->lock); |
654 | ohci_err (ohci, "USB HC reset timed out!\n"); | |
655 | return -1; | |
656 | } | |
657 | udelay (1); | |
658 | } | |
659 | ||
660 | /* now we're in the SUSPEND state ... must go OPERATIONAL | |
661 | * within 2msec else HC enters RESUME | |
662 | * | |
663 | * ... but some hardware won't init fmInterval "by the book" | |
664 | * (SiS, OPTi ...), so reset again instead. SiS doesn't need | |
665 | * this if we write fmInterval after we're OPERATIONAL. | |
666 | * Unclear about ALi, ServerWorks, and others ... this could | |
667 | * easily be a longstanding bug in chip init on Linux. | |
668 | */ | |
669 | if (ohci->flags & OHCI_QUIRK_INITRESET) { | |
670 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
671 | // flush those writes | |
672 | (void) ohci_readl (ohci, &ohci->regs->control); | |
673 | } | |
674 | ||
675 | /* Tell the controller where the control and bulk lists are | |
676 | * The lists are empty now. */ | |
677 | ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); | |
678 | ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); | |
679 | ||
680 | /* a reset clears this */ | |
681 | ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); | |
682 | ||
683 | periodic_reinit (ohci); | |
684 | ||
685 | /* some OHCI implementations are finicky about how they init. | |
686 | * bogus values here mean not even enumeration could work. | |
687 | */ | |
688 | if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 | |
689 | || !ohci_readl (ohci, &ohci->regs->periodicstart)) { | |
690 | if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { | |
691 | ohci->flags |= OHCI_QUIRK_INITRESET; | |
692 | ohci_dbg (ohci, "enabling initreset quirk\n"); | |
693 | goto retry; | |
694 | } | |
695 | spin_unlock_irq (&ohci->lock); | |
696 | ohci_err (ohci, "init err (%08x %04x)\n", | |
697 | ohci_readl (ohci, &ohci->regs->fminterval), | |
698 | ohci_readl (ohci, &ohci->regs->periodicstart)); | |
699 | return -EOVERFLOW; | |
700 | } | |
701 | ||
d413984a | 702 | /* use rhsc irqs after khubd is fully initialized */ |
541c7d43 | 703 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
d413984a DB |
704 | hcd->uses_new_polling = 1; |
705 | ||
706 | /* start controller operations */ | |
1da177e4 | 707 | ohci->hc_control &= OHCI_CTRL_RWC; |
d413984a DB |
708 | ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; |
709 | ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); | |
b7463c71 | 710 | ohci->rh_state = OHCI_RH_RUNNING; |
1da177e4 LT |
711 | |
712 | /* wake on ConnectStatusChange, matching external hubs */ | |
713 | ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); | |
714 | ||
715 | /* Choose the interrupts we care about now, others later on demand */ | |
716 | mask = OHCI_INTR_INIT; | |
d413984a | 717 | ohci_writel (ohci, ~0, &ohci->regs->intrstatus); |
1da177e4 LT |
718 | ohci_writel (ohci, mask, &ohci->regs->intrenable); |
719 | ||
720 | /* handle root hub init quirks ... */ | |
96f90a8b HS |
721 | val = roothub_a (ohci); |
722 | val &= ~(RH_A_PSM | RH_A_OCPM); | |
1da177e4 LT |
723 | if (ohci->flags & OHCI_QUIRK_SUPERIO) { |
724 | /* NSC 87560 and maybe others */ | |
96f90a8b HS |
725 | val |= RH_A_NOCP; |
726 | val &= ~(RH_A_POTPGT | RH_A_NPS); | |
727 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1133cd8a DB |
728 | } else if ((ohci->flags & OHCI_QUIRK_AMD756) || |
729 | (ohci->flags & OHCI_QUIRK_HUB_POWER)) { | |
1da177e4 LT |
730 | /* hub power always on; required for AMD-756 and some |
731 | * Mac platforms. ganged overcurrent reporting, if any. | |
732 | */ | |
96f90a8b HS |
733 | val |= RH_A_NPS; |
734 | ohci_writel (ohci, val, &ohci->regs->roothub.a); | |
1da177e4 LT |
735 | } |
736 | ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); | |
96f90a8b | 737 | ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, |
1da177e4 LT |
738 | &ohci->regs->roothub.b); |
739 | // flush those writes | |
740 | (void) ohci_readl (ohci, &ohci->regs->control); | |
741 | ||
d413984a | 742 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; |
1da177e4 LT |
743 | spin_unlock_irq (&ohci->lock); |
744 | ||
745 | // POTPGT delay is bits 24-31, in 2 ms units. | |
96f90a8b | 746 | mdelay ((val >> 23) & 0x1fe); |
1da177e4 | 747 | |
89a0fd18 MN |
748 | if (quirk_zfmicro(ohci)) { |
749 | /* Create timer to watch for bad queue state on ZF Micro */ | |
750 | setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, | |
751 | (unsigned long) ohci); | |
752 | ||
753 | ohci->eds_scheduled = 0; | |
754 | ohci->ed_to_check = NULL; | |
755 | } | |
756 | ||
1da177e4 LT |
757 | ohci_dump (ohci, 1); |
758 | ||
1da177e4 LT |
759 | return 0; |
760 | } | |
761 | ||
95e44d44 MG |
762 | /* ohci_setup routine for generic controller initialization */ |
763 | ||
764 | int ohci_setup(struct usb_hcd *hcd) | |
765 | { | |
766 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | |
767 | ||
768 | ohci_hcd_init(ohci); | |
769 | ||
770 | return ohci_init(ohci); | |
771 | } | |
772 | EXPORT_SYMBOL_GPL(ohci_setup); | |
773 | ||
774 | /* ohci_start routine for generic controller start of all OHCI bus glue */ | |
775 | static int ohci_start(struct usb_hcd *hcd) | |
776 | { | |
777 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); | |
778 | int ret; | |
779 | ||
780 | ret = ohci_run(ohci); | |
781 | if (ret < 0) { | |
782 | ohci_err(ohci, "can't start\n"); | |
783 | ohci_stop(hcd); | |
784 | } | |
785 | return ret; | |
786 | } | |
787 | ||
1da177e4 LT |
788 | /*-------------------------------------------------------------------------*/ |
789 | ||
790 | /* an interrupt happens */ | |
791 | ||
7d12e780 | 792 | static irqreturn_t ohci_irq (struct usb_hcd *hcd) |
1da177e4 LT |
793 | { |
794 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
795 | struct ohci_regs __iomem *regs = ohci->regs; | |
89a0fd18 | 796 | int ints; |
1da177e4 | 797 | |
565227c0 BH |
798 | /* Read interrupt status (and flush pending writes). We ignore the |
799 | * optimization of checking the LSB of hcca->done_head; it doesn't | |
800 | * work on all systems (edge triggering for OHCI can be a factor). | |
89a0fd18 | 801 | */ |
565227c0 | 802 | ints = ohci_readl(ohci, ®s->intrstatus); |
1da177e4 | 803 | |
565227c0 BH |
804 | /* Check for an all 1's result which is a typical consequence |
805 | * of dead, unclocked, or unplugged (CardBus...) devices | |
806 | */ | |
807 | if (ints == ~(u32)0) { | |
b7463c71 | 808 | ohci->rh_state = OHCI_RH_HALTED; |
1da177e4 | 809 | ohci_dbg (ohci, "device removed!\n"); |
69fff59d | 810 | usb_hc_died(hcd); |
1da177e4 | 811 | return IRQ_HANDLED; |
565227c0 BH |
812 | } |
813 | ||
814 | /* We only care about interrupts that are enabled */ | |
815 | ints &= ohci_readl(ohci, ®s->intrenable); | |
1da177e4 LT |
816 | |
817 | /* interrupt for some other device? */ | |
b7463c71 | 818 | if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED)) |
1da177e4 | 819 | return IRQ_NOTMINE; |
d413984a | 820 | |
1da177e4 | 821 | if (ints & OHCI_INTR_UE) { |
1da177e4 | 822 | // e.g. due to PCI Master/Target Abort |
89a0fd18 | 823 | if (quirk_nec(ohci)) { |
d576bb9f MH |
824 | /* Workaround for a silicon bug in some NEC chips used |
825 | * in Apple's PowerBooks. Adapted from Darwin code. | |
826 | */ | |
827 | ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); | |
828 | ||
829 | ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); | |
830 | ||
831 | schedule_work (&ohci->nec_work); | |
832 | } else { | |
d576bb9f | 833 | ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); |
b7463c71 | 834 | ohci->rh_state = OHCI_RH_HALTED; |
69fff59d | 835 | usb_hc_died(hcd); |
d576bb9f | 836 | } |
1da177e4 LT |
837 | |
838 | ohci_dump (ohci, 1); | |
839 | ohci_usb_reset (ohci); | |
840 | } | |
841 | ||
583ceada AS |
842 | if (ints & OHCI_INTR_RHSC) { |
843 | ohci_vdbg(ohci, "rhsc\n"); | |
844 | ohci->next_statechange = jiffies + STATECHANGE_DELAY; | |
845 | ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, | |
846 | ®s->intrstatus); | |
052ac01a AS |
847 | |
848 | /* NOTE: Vendors didn't always make the same implementation | |
849 | * choices for RHSC. Many followed the spec; RHSC triggers | |
850 | * on an edge, like setting and maybe clearing a port status | |
851 | * change bit. With others it's level-triggered, active | |
852 | * until khubd clears all the port status change bits. We'll | |
853 | * always disable it here and rely on polling until khubd | |
854 | * re-enables it. | |
855 | */ | |
856 | ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); | |
583ceada AS |
857 | usb_hcd_poll_rh_status(hcd); |
858 | } | |
859 | ||
860 | /* For connect and disconnect events, we expect the controller | |
861 | * to turn on RHSC along with RD. But for remote wakeup events | |
862 | * this might not happen. | |
863 | */ | |
864 | else if (ints & OHCI_INTR_RD) { | |
865 | ohci_vdbg(ohci, "resume detect\n"); | |
866 | ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); | |
541c7d43 | 867 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
8d1a243b AS |
868 | if (ohci->autostop) { |
869 | spin_lock (&ohci->lock); | |
870 | ohci_rh_resume (ohci); | |
871 | spin_unlock (&ohci->lock); | |
872 | } else | |
f197b2c5 | 873 | usb_hcd_resume_root_hub(hcd); |
1da177e4 LT |
874 | } |
875 | ||
876 | if (ints & OHCI_INTR_WDH) { | |
1da177e4 | 877 | spin_lock (&ohci->lock); |
7d12e780 | 878 | dl_done_list (ohci); |
1da177e4 | 879 | spin_unlock (&ohci->lock); |
1da177e4 | 880 | } |
dd9048af | 881 | |
89a0fd18 MN |
882 | if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { |
883 | spin_lock(&ohci->lock); | |
884 | if (ohci->ed_to_check) { | |
885 | struct ed *ed = ohci->ed_to_check; | |
886 | ||
887 | if (check_ed(ohci, ed)) { | |
888 | /* HC thinks the TD list is empty; HCD knows | |
889 | * at least one TD is outstanding | |
890 | */ | |
891 | if (--ohci->zf_delay == 0) { | |
892 | struct td *td = list_entry( | |
893 | ed->td_list.next, | |
894 | struct td, td_list); | |
895 | ohci_warn(ohci, | |
896 | "Reclaiming orphan TD %p\n", | |
897 | td); | |
898 | takeback_td(ohci, td); | |
899 | ohci->ed_to_check = NULL; | |
900 | } | |
901 | } else | |
902 | ohci->ed_to_check = NULL; | |
903 | } | |
904 | spin_unlock(&ohci->lock); | |
905 | } | |
906 | ||
1da177e4 LT |
907 | /* could track INTR_SO to reduce available PCI/... bandwidth */ |
908 | ||
909 | /* handle any pending URB/ED unlinks, leaving INTR_SF enabled | |
910 | * when there's still unlinking to be done (next frame). | |
911 | */ | |
912 | spin_lock (&ohci->lock); | |
913 | if (ohci->ed_rm_list) | |
7d12e780 | 914 | finish_unlinks (ohci, ohci_frame_no(ohci)); |
89a0fd18 MN |
915 | if ((ints & OHCI_INTR_SF) != 0 |
916 | && !ohci->ed_rm_list | |
917 | && !ohci->ed_to_check | |
b7463c71 | 918 | && ohci->rh_state == OHCI_RH_RUNNING) |
dd9048af | 919 | ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); |
1da177e4 LT |
920 | spin_unlock (&ohci->lock); |
921 | ||
b7463c71 | 922 | if (ohci->rh_state == OHCI_RH_RUNNING) { |
1da177e4 | 923 | ohci_writel (ohci, ints, ®s->intrstatus); |
dd9048af | 924 | ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); |
1da177e4 LT |
925 | // flush those writes |
926 | (void) ohci_readl (ohci, &ohci->regs->control); | |
927 | } | |
928 | ||
929 | return IRQ_HANDLED; | |
930 | } | |
931 | ||
932 | /*-------------------------------------------------------------------------*/ | |
933 | ||
934 | static void ohci_stop (struct usb_hcd *hcd) | |
dd9048af | 935 | { |
1da177e4 LT |
936 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); |
937 | ||
1da177e4 LT |
938 | ohci_dump (ohci, 1); |
939 | ||
569ff2de | 940 | if (quirk_nec(ohci)) |
43829731 | 941 | flush_work(&ohci->nec_work); |
1da177e4 | 942 | |
1da177e4 | 943 | ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
435932f2 | 944 | ohci_usb_reset(ohci); |
71795c1d | 945 | free_irq(hcd->irq, hcd); |
cd70469d | 946 | hcd->irq = 0; |
71795c1d | 947 | |
89a0fd18 MN |
948 | if (quirk_zfmicro(ohci)) |
949 | del_timer(&ohci->unlink_watchdog); | |
ab1666c1 | 950 | if (quirk_amdiso(ohci)) |
ad93562b | 951 | usb_amd_dev_put(); |
89a0fd18 | 952 | |
1da177e4 LT |
953 | remove_debug_files (ohci); |
954 | ohci_mem_cleanup (ohci); | |
955 | if (ohci->hcca) { | |
dd9048af DB |
956 | dma_free_coherent (hcd->self.controller, |
957 | sizeof *ohci->hcca, | |
1da177e4 LT |
958 | ohci->hcca, ohci->hcca_dma); |
959 | ohci->hcca = NULL; | |
960 | ohci->hcca_dma = 0; | |
961 | } | |
962 | } | |
963 | ||
964 | /*-------------------------------------------------------------------------*/ | |
965 | ||
da6fb570 DB |
966 | #if defined(CONFIG_PM) || defined(CONFIG_PCI) |
967 | ||
1da177e4 | 968 | /* must not be called from interrupt context */ |
95e44d44 | 969 | int ohci_restart(struct ohci_hcd *ohci) |
1da177e4 LT |
970 | { |
971 | int temp; | |
972 | int i; | |
973 | struct urb_priv *priv; | |
1da177e4 | 974 | |
95e44d44 | 975 | ohci_init(ohci); |
1da177e4 | 976 | spin_lock_irq(&ohci->lock); |
b7463c71 | 977 | ohci->rh_state = OHCI_RH_HALTED; |
d576bb9f MH |
978 | |
979 | /* Recycle any "live" eds/tds (and urbs). */ | |
1da177e4 LT |
980 | if (!list_empty (&ohci->pending)) |
981 | ohci_dbg(ohci, "abort schedule...\n"); | |
982 | list_for_each_entry (priv, &ohci->pending, pending) { | |
983 | struct urb *urb = priv->td[0]->urb; | |
984 | struct ed *ed = priv->ed; | |
985 | ||
986 | switch (ed->state) { | |
987 | case ED_OPER: | |
988 | ed->state = ED_UNLINK; | |
989 | ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); | |
990 | ed_deschedule (ohci, ed); | |
991 | ||
992 | ed->ed_next = ohci->ed_rm_list; | |
993 | ed->ed_prev = NULL; | |
994 | ohci->ed_rm_list = ed; | |
995 | /* FALLTHROUGH */ | |
996 | case ED_UNLINK: | |
997 | break; | |
998 | default: | |
999 | ohci_dbg(ohci, "bogus ed %p state %d\n", | |
1000 | ed, ed->state); | |
1001 | } | |
1002 | ||
55d84968 AS |
1003 | if (!urb->unlinked) |
1004 | urb->unlinked = -ESHUTDOWN; | |
1da177e4 | 1005 | } |
7d12e780 | 1006 | finish_unlinks (ohci, 0); |
1da177e4 LT |
1007 | spin_unlock_irq(&ohci->lock); |
1008 | ||
1009 | /* paranoia, in case that didn't work: */ | |
1010 | ||
1011 | /* empty the interrupt branches */ | |
1012 | for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; | |
1013 | for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; | |
dd9048af | 1014 | |
1da177e4 LT |
1015 | /* no EDs to remove */ |
1016 | ohci->ed_rm_list = NULL; | |
1017 | ||
dd9048af | 1018 | /* empty control and bulk lists */ |
1da177e4 LT |
1019 | ohci->ed_controltail = NULL; |
1020 | ohci->ed_bulktail = NULL; | |
1021 | ||
1022 | if ((temp = ohci_run (ohci)) < 0) { | |
1023 | ohci_err (ohci, "can't restart, %d\n", temp); | |
1024 | return temp; | |
1da177e4 | 1025 | } |
383975d7 | 1026 | ohci_dbg(ohci, "restart complete\n"); |
1da177e4 LT |
1027 | return 0; |
1028 | } | |
95e44d44 | 1029 | EXPORT_SYMBOL_GPL(ohci_restart); |
d576bb9f | 1030 | |
da6fb570 DB |
1031 | #endif |
1032 | ||
cd1965db FF |
1033 | #ifdef CONFIG_PM |
1034 | ||
95e44d44 | 1035 | int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup) |
cd1965db FF |
1036 | { |
1037 | struct ohci_hcd *ohci = hcd_to_ohci (hcd); | |
1038 | unsigned long flags; | |
cd1965db | 1039 | |
d4ae47dc | 1040 | /* Disable irq emission and mark HW unaccessible. Use |
cd1965db FF |
1041 | * the spinlock to properly synchronize with possible pending |
1042 | * RH suspend or resume activity. | |
1043 | */ | |
1044 | spin_lock_irqsave (&ohci->lock, flags); | |
cd1965db FF |
1045 | ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); |
1046 | (void)ohci_readl(ohci, &ohci->regs->intrdisable); | |
1047 | ||
1048 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
cd1965db FF |
1049 | spin_unlock_irqrestore (&ohci->lock, flags); |
1050 | ||
ca1ad0ff | 1051 | return 0; |
cd1965db | 1052 | } |
95e44d44 | 1053 | EXPORT_SYMBOL_GPL(ohci_suspend); |
cd1965db FF |
1054 | |
1055 | ||
95e44d44 | 1056 | int ohci_resume(struct usb_hcd *hcd, bool hibernated) |
cd1965db | 1057 | { |
cfa49b4b FF |
1058 | struct ohci_hcd *ohci = hcd_to_ohci(hcd); |
1059 | int port; | |
1060 | bool need_reinit = false; | |
1061 | ||
cd1965db FF |
1062 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
1063 | ||
1064 | /* Make sure resume from hibernation re-enumerates everything */ | |
1065 | if (hibernated) | |
cfa49b4b FF |
1066 | ohci_usb_reset(ohci); |
1067 | ||
1068 | /* See if the controller is already running or has been reset */ | |
1069 | ohci->hc_control = ohci_readl(ohci, &ohci->regs->control); | |
1070 | if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) { | |
1071 | need_reinit = true; | |
1072 | } else { | |
1073 | switch (ohci->hc_control & OHCI_CTRL_HCFS) { | |
1074 | case OHCI_USB_OPER: | |
1075 | case OHCI_USB_RESET: | |
1076 | need_reinit = true; | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | /* If needed, reinitialize and suspend the root hub */ | |
1081 | if (need_reinit) { | |
1082 | spin_lock_irq(&ohci->lock); | |
1083 | ohci_rh_resume(ohci); | |
1084 | ohci_rh_suspend(ohci, 0); | |
1085 | spin_unlock_irq(&ohci->lock); | |
1086 | } | |
1087 | ||
1088 | /* Normally just turn on port power and enable interrupts */ | |
1089 | else { | |
1090 | ohci_dbg(ohci, "powerup ports\n"); | |
1091 | for (port = 0; port < ohci->num_ports; port++) | |
1092 | ohci_writel(ohci, RH_PS_PPS, | |
1093 | &ohci->regs->roothub.portstatus[port]); | |
1094 | ||
1095 | ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable); | |
1096 | ohci_readl(ohci, &ohci->regs->intrenable); | |
1097 | msleep(20); | |
1098 | } | |
1099 | ||
1100 | usb_hcd_resume_root_hub(hcd); | |
cd1965db | 1101 | |
cd1965db FF |
1102 | return 0; |
1103 | } | |
95e44d44 MG |
1104 | EXPORT_SYMBOL_GPL(ohci_resume); |
1105 | ||
1106 | #endif | |
1107 | ||
1108 | /*-------------------------------------------------------------------------*/ | |
1109 | ||
1110 | /* | |
1111 | * Generic structure: This gets copied for platform drivers so that | |
1112 | * individual entries can be overridden as needed. | |
1113 | */ | |
cd1965db | 1114 | |
95e44d44 MG |
1115 | static const struct hc_driver ohci_hc_driver = { |
1116 | .description = hcd_name, | |
1117 | .product_desc = "OHCI Host Controller", | |
1118 | .hcd_priv_size = sizeof(struct ohci_hcd), | |
1119 | ||
1120 | /* | |
1121 | * generic hardware linkage | |
1122 | */ | |
1123 | .irq = ohci_irq, | |
1124 | .flags = HCD_MEMORY | HCD_USB11, | |
1125 | ||
1126 | /* | |
1127 | * basic lifecycle operations | |
1128 | */ | |
1129 | .reset = ohci_setup, | |
1130 | .start = ohci_start, | |
1131 | .stop = ohci_stop, | |
1132 | .shutdown = ohci_shutdown, | |
1133 | ||
1134 | /* | |
1135 | * managing i/o requests and associated device resources | |
1136 | */ | |
1137 | .urb_enqueue = ohci_urb_enqueue, | |
1138 | .urb_dequeue = ohci_urb_dequeue, | |
1139 | .endpoint_disable = ohci_endpoint_disable, | |
1140 | ||
1141 | /* | |
1142 | * scheduling support | |
1143 | */ | |
1144 | .get_frame_number = ohci_get_frame, | |
1145 | ||
1146 | /* | |
1147 | * root hub support | |
1148 | */ | |
1149 | .hub_status_data = ohci_hub_status_data, | |
1150 | .hub_control = ohci_hub_control, | |
1151 | #ifdef CONFIG_PM | |
1152 | .bus_suspend = ohci_bus_suspend, | |
1153 | .bus_resume = ohci_bus_resume, | |
cd1965db | 1154 | #endif |
95e44d44 MG |
1155 | .start_port_reset = ohci_start_port_reset, |
1156 | }; | |
1157 | ||
1158 | void ohci_init_driver(struct hc_driver *drv, | |
1159 | const struct ohci_driver_overrides *over) | |
1160 | { | |
1161 | /* Copy the generic table to drv and then apply the overrides */ | |
1162 | *drv = ohci_hc_driver; | |
1163 | ||
c80ad6d1 KH |
1164 | if (over) { |
1165 | drv->product_desc = over->product_desc; | |
1166 | drv->hcd_priv_size += over->extra_priv_size; | |
1167 | if (over->reset) | |
1168 | drv->reset = over->reset; | |
1169 | } | |
95e44d44 MG |
1170 | } |
1171 | EXPORT_SYMBOL_GPL(ohci_init_driver); | |
cd1965db | 1172 | |
d576bb9f MH |
1173 | /*-------------------------------------------------------------------------*/ |
1174 | ||
1da177e4 | 1175 | MODULE_AUTHOR (DRIVER_AUTHOR); |
2b70f073 | 1176 | MODULE_DESCRIPTION(DRIVER_DESC); |
1da177e4 LT |
1177 | MODULE_LICENSE ("GPL"); |
1178 | ||
6381fad7 | 1179 | #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) |
1da177e4 | 1180 | #include "ohci-sa1111.c" |
5e16fabe | 1181 | #define SA1111_DRIVER ohci_hcd_sa1111_driver |
1da177e4 LT |
1182 | #endif |
1183 | ||
efe7daf2 SS |
1184 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX |
1185 | #include "ohci-da8xx.c" | |
8097804e | 1186 | #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver |
efe7daf2 SS |
1187 | #endif |
1188 | ||
495a678f SM |
1189 | #ifdef CONFIG_USB_OHCI_HCD_PPC_OF |
1190 | #include "ohci-ppc-of.c" | |
1191 | #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver | |
1192 | #endif | |
1193 | ||
6a6c957e GL |
1194 | #ifdef CONFIG_PPC_PS3 |
1195 | #include "ohci-ps3.c" | |
7a4eb7fd | 1196 | #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver |
6a6c957e GL |
1197 | #endif |
1198 | ||
f54aab6e MD |
1199 | #ifdef CONFIG_MFD_SM501 |
1200 | #include "ohci-sm501.c" | |
3ee38d8b | 1201 | #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver |
f54aab6e MD |
1202 | #endif |
1203 | ||
78c73414 DB |
1204 | #ifdef CONFIG_MFD_TC6393XB |
1205 | #include "ohci-tmio.c" | |
1206 | #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver | |
2249071b LPC |
1207 | #endif |
1208 | ||
1209 | #ifdef CONFIG_MACH_JZ4740 | |
1210 | #include "ohci-jz4740.c" | |
1211 | #define PLATFORM_DRIVER ohci_hcd_jz4740_driver | |
78c73414 DB |
1212 | #endif |
1213 | ||
1643accd DD |
1214 | #ifdef CONFIG_USB_OCTEON_OHCI |
1215 | #include "ohci-octeon.c" | |
1216 | #define PLATFORM_DRIVER ohci_octeon_driver | |
1217 | #endif | |
1218 | ||
47fc28bf CM |
1219 | #ifdef CONFIG_TILE_USB |
1220 | #include "ohci-tilegx.c" | |
1221 | #define PLATFORM_DRIVER ohci_hcd_tilegx_driver | |
1222 | #endif | |
1223 | ||
5e16fabe SM |
1224 | static int __init ohci_hcd_mod_init(void) |
1225 | { | |
1226 | int retval = 0; | |
5e16fabe SM |
1227 | |
1228 | if (usb_disabled()) | |
1229 | return -ENODEV; | |
1230 | ||
2b70f073 | 1231 | printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); |
5e16fabe SM |
1232 | pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, |
1233 | sizeof (struct ed), sizeof (struct td)); | |
9beeee65 | 1234 | set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe | 1235 | |
684c19e0 | 1236 | #ifdef DEBUG |
485f4f39 | 1237 | ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); |
684c19e0 TJ |
1238 | if (!ohci_debug_root) { |
1239 | retval = -ENOENT; | |
1240 | goto error_debug; | |
1241 | } | |
1242 | #endif | |
1243 | ||
6a6c957e | 1244 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd GL |
1245 | retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); |
1246 | if (retval < 0) | |
1247 | goto error_ps3; | |
6a6c957e GL |
1248 | #endif |
1249 | ||
5e16fabe SM |
1250 | #ifdef PLATFORM_DRIVER |
1251 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
1252 | if (retval < 0) | |
de44743b | 1253 | goto error_platform; |
5e16fabe SM |
1254 | #endif |
1255 | ||
495a678f | 1256 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1257 | retval = platform_driver_register(&OF_PLATFORM_DRIVER); |
495a678f | 1258 | if (retval < 0) |
de44743b | 1259 | goto error_of_platform; |
495a678f SM |
1260 | #endif |
1261 | ||
5e16fabe SM |
1262 | #ifdef SA1111_DRIVER |
1263 | retval = sa1111_driver_register(&SA1111_DRIVER); | |
1264 | if (retval < 0) | |
de44743b | 1265 | goto error_sa1111; |
5e16fabe SM |
1266 | #endif |
1267 | ||
3ee38d8b BD |
1268 | #ifdef SM501_OHCI_DRIVER |
1269 | retval = platform_driver_register(&SM501_OHCI_DRIVER); | |
1270 | if (retval < 0) | |
1271 | goto error_sm501; | |
1272 | #endif | |
1273 | ||
78c73414 DB |
1274 | #ifdef TMIO_OHCI_DRIVER |
1275 | retval = platform_driver_register(&TMIO_OHCI_DRIVER); | |
1276 | if (retval < 0) | |
1277 | goto error_tmio; | |
1278 | #endif | |
1279 | ||
8097804e AB |
1280 | #ifdef DAVINCI_PLATFORM_DRIVER |
1281 | retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER); | |
1282 | if (retval < 0) | |
1283 | goto error_davinci; | |
1284 | #endif | |
1285 | ||
5e16fabe SM |
1286 | return retval; |
1287 | ||
1288 | /* Error path */ | |
8097804e AB |
1289 | #ifdef DAVINCI_PLATFORM_DRIVER |
1290 | platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER); | |
1291 | error_davinci: | |
1292 | #endif | |
78c73414 DB |
1293 | #ifdef TMIO_OHCI_DRIVER |
1294 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1295 | error_tmio: | |
1296 | #endif | |
3ee38d8b | 1297 | #ifdef SM501_OHCI_DRIVER |
78c73414 | 1298 | platform_driver_unregister(&SM501_OHCI_DRIVER); |
3ee38d8b BD |
1299 | error_sm501: |
1300 | #endif | |
de44743b BH |
1301 | #ifdef SA1111_DRIVER |
1302 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1303 | error_sa1111: | |
5e16fabe | 1304 | #endif |
495a678f | 1305 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1306 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
de44743b | 1307 | error_of_platform: |
495a678f | 1308 | #endif |
8097804e AB |
1309 | #ifdef PLATFORM_DRIVER |
1310 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1311 | error_platform: | |
968b448b | 1312 | #endif |
6a6c957e | 1313 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1314 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1315 | error_ps3: |
5e16fabe | 1316 | #endif |
684c19e0 TJ |
1317 | #ifdef DEBUG |
1318 | debugfs_remove(ohci_debug_root); | |
1319 | ohci_debug_root = NULL; | |
1320 | error_debug: | |
1321 | #endif | |
1322 | ||
9beeee65 | 1323 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1324 | return retval; |
1325 | } | |
1326 | module_init(ohci_hcd_mod_init); | |
1327 | ||
1328 | static void __exit ohci_hcd_mod_exit(void) | |
1329 | { | |
8097804e AB |
1330 | #ifdef DAVINCI_PLATFORM_DRIVER |
1331 | platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER); | |
1332 | #endif | |
78c73414 DB |
1333 | #ifdef TMIO_OHCI_DRIVER |
1334 | platform_driver_unregister(&TMIO_OHCI_DRIVER); | |
1335 | #endif | |
3ee38d8b BD |
1336 | #ifdef SM501_OHCI_DRIVER |
1337 | platform_driver_unregister(&SM501_OHCI_DRIVER); | |
1338 | #endif | |
5e16fabe SM |
1339 | #ifdef SA1111_DRIVER |
1340 | sa1111_driver_unregister(&SA1111_DRIVER); | |
1341 | #endif | |
495a678f | 1342 | #ifdef OF_PLATFORM_DRIVER |
d35fb641 | 1343 | platform_driver_unregister(&OF_PLATFORM_DRIVER); |
495a678f | 1344 | #endif |
8097804e AB |
1345 | #ifdef PLATFORM_DRIVER |
1346 | platform_driver_unregister(&PLATFORM_DRIVER); | |
1347 | #endif | |
6a6c957e | 1348 | #ifdef PS3_SYSTEM_BUS_DRIVER |
7a4eb7fd | 1349 | ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); |
6a6c957e | 1350 | #endif |
684c19e0 TJ |
1351 | #ifdef DEBUG |
1352 | debugfs_remove(ohci_debug_root); | |
1353 | #endif | |
9beeee65 | 1354 | clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); |
5e16fabe SM |
1355 | } |
1356 | module_exit(ohci_hcd_mod_exit); | |
1357 |