[deliverable/linux.git] / drivers / usb / host / ohci-pxa27x.c

/*
 * OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
 * (C) Copyright 2002 Hewlett-Packard Company
 *
 * Bus Glue for pxa27x
 *
 * Written by Christopher Hoover <ch@hpl.hp.com>
 * Based on fragments of previous driver by Russell King et al.
 *
 * Modified for LH7A404 from ohci-sa1111.c
 *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
 *
 * Modified for pxa27x from ohci-lh7a404.c
 *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
 *
 * This file is licenced under the GPL.
 */

#include <linux/device.h>
#include <linux/signal.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <mach/ohci.h>
#include <mach/pxa3xx-u2d.h>

/*
 * UHC: USB Host Controller (OHCI-like) register definitions
 */
#define UHCREV		(0x0000) /* UHC HCI Spec Revision */
#define UHCHCON		(0x0004) /* UHC Host Control Register */
#define UHCCOMS		(0x0008) /* UHC Command Status Register */
#define UHCINTS		(0x000C) /* UHC Interrupt Status Register */
#define UHCINTE		(0x0010) /* UHC Interrupt Enable */
#define UHCINTD		(0x0014) /* UHC Interrupt Disable */
#define UHCHCCA		(0x0018) /* UHC Host Controller Comm. Area */
#define UHCPCED		(0x001C) /* UHC Period Current Endpt Descr */
#define UHCCHED		(0x0020) /* UHC Control Head Endpt Descr */
#define UHCCCED		(0x0024) /* UHC Control Current Endpt Descr */
#define UHCBHED		(0x0028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED		(0x002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD	(0x0030) /* UHC Done Head */
#define UHCFMI		(0x0034) /* UHC Frame Interval */
#define UHCFMR		(0x0038) /* UHC Frame Remaining */
#define UHCFMN		(0x003C) /* UHC Frame Number */
#define UHCPERS		(0x0040) /* UHC Periodic Start */
#define UHCLS		(0x0044) /* UHC Low Speed Threshold */

#define UHCRHDA		(0x0048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP	(1 << 12)	/* No over current protection */
#define UHCRHDA_OCPM	(1 << 11)	/* Over Current Protection Mode */
#define UHCRHDA_POTPGT(x) \
			(((x) & 0xff) << 24) /* Power On To Power Good Time */

#define UHCRHDB		(0x004C) /* UHC Root Hub Descriptor B */
#define UHCRHS		(0x0050) /* UHC Root Hub Status */
#define UHCRHPS1	(0x0054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2	(0x0058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3	(0x005C) /* UHC Root Hub Port 3 Status */

#define UHCSTAT		(0x0060) /* UHC Status Register */
#define UHCSTAT_UPS3	(1 << 16)	/* USB Power Sense Port3 */
#define UHCSTAT_SBMAI	(1 << 15)	/* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI	(1 << 14)	/* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI	(1 << 13)	/* USB Port Resume Interrupt */
#define UHCSTAT_UPS2	(1 << 12)	/* USB Power Sense Port 2 */
#define UHCSTAT_UPS1	(1 << 11)	/* USB Power Sense Port 1 */
#define UHCSTAT_HTA	(1 << 10)	/* HCI Target Abort */
#define UHCSTAT_HBA	(1 << 8)	/* HCI Buffer Active */
#define UHCSTAT_RWUE	(1 << 7)	/* HCI Remote Wake Up Event */

#define UHCHR           (0x0064) /* UHC Reset Register */
#define UHCHR_SSEP3	(1 << 11)	/* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2	(1 << 10)	/* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1	(1 << 9)	/* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL	(1 << 7)	/* Power control polarity low */
#define UHCHR_PSPL	(1 << 6)	/* Power sense polarity low */
#define UHCHR_SSE	(1 << 5)	/* Sleep Standby Enable */
#define UHCHR_UIT	(1 << 4)	/* USB Interrupt Test */
#define UHCHR_SSDC	(1 << 3)	/* Simulation Scale Down Clock */
#define UHCHR_CGR	(1 << 2)	/* Clock Generation Reset */
#define UHCHR_FHR	(1 << 1)	/* Force Host Controller Reset */
#define UHCHR_FSBIR	(1 << 0)	/* Force System Bus Iface Reset */

#define UHCHIE          (0x0068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE	(1 << 14)	/* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE	(1 << 13)	/* Port Resume IntEn */
#define UHCHIE_UPS2IE	(1 << 12)	/* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE	(1 << 11)	/* Power Sense Port1 IntEn */
#define UHCHIE_TAIE	(1 << 10)	/* HCI Interface Transfer Abort
					   Interrupt Enable*/
#define UHCHIE_HBAIE	(1 << 8)	/* HCI Buffer Active IntEn */
#define UHCHIE_RWIE	(1 << 7)	/* Remote Wake-up IntEn */

#define UHCHIT          (0x006C) /* UHC Interrupt Test register */

#define PXA_UHC_MAX_PORTNUM    3

struct pxa27x_ohci {
	/* must be 1st member here for hcd_to_ohci() to work */
	struct ohci_hcd ohci;

	struct device	*dev;
	struct clk	*clk;
	void __iomem	*mmio_base;
};

#define to_pxa27x_ohci(hcd)	(struct pxa27x_ohci *)hcd_to_ohci(hcd)

/*
  PMM_NPS_MODE -- PMM Non-power switching mode
      Ports are powered continuously.

  PMM_GLOBAL_MODE -- PMM global switching mode
      All ports are powered at the same time.

  PMM_PERPORT_MODE -- PMM per port switching mode
      Ports are powered individually.
 */
static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
{
	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
	uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);

	switch (mode) {
	case PMM_NPS_MODE:
		uhcrhda |= RH_A_NPS;
		break;
	case PMM_GLOBAL_MODE:
		uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
		break;
	case PMM_PERPORT_MODE:
		uhcrhda &= ~(RH_A_NPS);
		uhcrhda |= RH_A_PSM;

		/* Set port power control mask bits, only 3 ports. */
		uhcrhdb |= (0x7<<17);
		break;
	default:
		printk( KERN_ERR
			"Invalid mode %d, set to non-power switch mode.\n",
			mode );

		uhcrhda |= RH_A_NPS;
	}

	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
	__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
	return 0;
}

extern int usb_disabled(void);

/*-------------------------------------------------------------------------*/

static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
				   struct pxaohci_platform_data *inf)
{
	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);

	if (inf->flags & ENABLE_PORT1)
		uhchr &= ~UHCHR_SSEP1;

	if (inf->flags & ENABLE_PORT2)
		uhchr &= ~UHCHR_SSEP2;

	if (inf->flags & ENABLE_PORT3)
		uhchr &= ~UHCHR_SSEP3;

	if (inf->flags & POWER_CONTROL_LOW)
		uhchr |= UHCHR_PCPL;

	if (inf->flags & POWER_SENSE_LOW)
		uhchr |= UHCHR_PSPL;

	if (inf->flags & NO_OC_PROTECTION)
		uhcrhda |= UHCRHDA_NOCP;
	else
		uhcrhda &= ~UHCRHDA_NOCP;

	if (inf->flags & OC_MODE_PERPORT)
		uhcrhda |= UHCRHDA_OCPM;
	else
		uhcrhda &= ~UHCRHDA_OCPM;

	if (inf->power_on_delay) {
		uhcrhda &= ~UHCRHDA_POTPGT(0xff);
		uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	}

	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
}

static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
{
	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);

	__raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
	udelay(11);
	__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
}

#ifdef CONFIG_PXA27x
extern void pxa27x_clear_otgph(void);
#else
#define pxa27x_clear_otgph()	do {} while (0)
#endif

static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
	int retval = 0;
	struct pxaohci_platform_data *inf;
	uint32_t uhchr;

	inf = dev->platform_data;

	clk_enable(ohci->clk);

	pxa27x_reset_hc(ohci);

	uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
	__raw_writel(uhchr, ohci->mmio_base + UHCHR);

	while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
		cpu_relax();

	pxa27x_setup_hc(ohci, inf);

	if (inf->init)
		retval = inf->init(dev);

	if (retval < 0)
		return retval;

	if (cpu_is_pxa3xx())
		pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);

	uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);

	/* Clear any OTG Pin Hold */
	pxa27x_clear_otgph();
	return 0;
}

static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
	struct pxaohci_platform_data *inf;
	uint32_t uhccoms;

	inf = dev->platform_data;

	if (cpu_is_pxa3xx())
		pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);

	if (inf->exit)
		inf->exit(dev);

	pxa27x_reset_hc(ohci);

	/* Host Controller Reset */
	uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
	__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
	udelay(10);

	clk_disable(ohci->clk);
}


/*-------------------------------------------------------------------------*/

/* configure so an HC device and id are always provided */
/* always called with process context; sleeping is OK */


/**
 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
 * Context: !in_interrupt()
 *
 * Allocates basic resources for this USB host controller, and
 * then invokes the start() method for the HCD associated with it
 * through the hotplug entry's driver_data.
 *
 */
int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
{
	int retval, irq;
	struct usb_hcd *hcd;
	struct pxaohci_platform_data *inf;
	struct pxa27x_ohci *ohci;
	struct resource *r;
	struct clk *usb_clk;

	inf = pdev->dev.platform_data;

	if (!inf)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		pr_err("no resource of IORESOURCE_IRQ");
		return -ENXIO;
	}

	usb_clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(usb_clk))
		return PTR_ERR(usb_clk);

	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
	if (!hcd)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		pr_err("no resource of IORESOURCE_MEM");
		retval = -ENXIO;
		goto err1;
	}

	hcd->rsrc_start = r->start;
	hcd->rsrc_len = resource_size(r);

	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
		pr_debug("request_mem_region failed");
		retval = -EBUSY;
		goto err1;
	}

	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	if (!hcd->regs) {
		pr_debug("ioremap failed");
		retval = -ENOMEM;
		goto err2;
	}

	/* initialize "struct pxa27x_ohci" */
	ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
	ohci->dev = &pdev->dev;
	ohci->clk = usb_clk;
	ohci->mmio_base = (void __iomem *)hcd->regs;

	if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
		pr_debug("pxa27x_start_hc failed");
		goto err3;
	}

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(ohci, inf->port_mode);

	if (inf->power_budget)
		hcd->power_budget = inf->power_budget;

	ohci_hcd_init(hcd_to_ohci(hcd));

	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
	if (retval == 0)
		return retval;

	pxa27x_stop_hc(ohci, &pdev->dev);
 err3:
	iounmap(hcd->regs);
 err2:
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 err1:
	usb_put_hcd(hcd);
	clk_put(usb_clk);
	return retval;
}


/* may be called without controller electrically present */
/* may be called with controller, bus, and devices active */

/**
 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
 * @dev: USB Host Controller being removed
 * Context: !in_interrupt()
 *
 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
 * the HCD's stop() method.  It is always called from a thread
 * context, normally "rmmod", "apmd", or something similar.
 *
 */
void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
{
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);

	usb_remove_hcd(hcd);
	pxa27x_stop_hc(ohci, &pdev->dev);
	iounmap(hcd->regs);
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	usb_put_hcd(hcd);
	clk_put(ohci->clk);
}

/*-------------------------------------------------------------------------*/

static int __devinit
ohci_pxa27x_start (struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	int		ret;

	ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);

	/* The value of NDP in roothub_a is incorrect on this hardware */
	ohci->num_ports = 3;

	if ((ret = ohci_init(ohci)) < 0)
		return ret;

	if ((ret = ohci_run (ohci)) < 0) {
		err ("can't start %s", hcd->self.bus_name);
		ohci_stop (hcd);
		return ret;
	}

	return 0;
}

/*-------------------------------------------------------------------------*/

static const struct hc_driver ohci_pxa27x_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"PXA27x OHCI",
	.hcd_priv_size =	sizeof(struct pxa27x_ohci),

	/*
	 * generic hardware linkage
	 */
	.irq =			ohci_irq,
	.flags =		HCD_USB11 | HCD_MEMORY,

	/*
	 * basic lifecycle operations
	 */
	.start =		ohci_pxa27x_start,
	.stop =			ohci_stop,
	.shutdown =		ohci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ohci_urb_enqueue,
	.urb_dequeue =		ohci_urb_dequeue,
	.endpoint_disable =	ohci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ohci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ohci_hub_status_data,
	.hub_control =		ohci_hub_control,
#ifdef  CONFIG_PM
	.bus_suspend =		ohci_bus_suspend,
	.bus_resume =		ohci_bus_resume,
#endif
	.start_port_reset =	ohci_start_port_reset,
};

/*-------------------------------------------------------------------------*/

static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
{
	pr_debug ("In ohci_hcd_pxa27x_drv_probe");

	if (usb_disabled())
		return -ENODEV;

	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
}

static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);

	usb_hcd_pxa27x_remove(hcd, pdev);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

#ifdef CONFIG_PM
static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
{
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);

	if (time_before(jiffies, ohci->ohci.next_statechange))
		msleep(5);
	ohci->ohci.next_statechange = jiffies;

	pxa27x_stop_hc(ohci, dev);
	hcd->state = HC_STATE_SUSPENDED;

	return 0;
}

static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
{
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
	struct pxaohci_platform_data *inf = dev->platform_data;
	int status;

	if (time_before(jiffies, ohci->ohci.next_statechange))
		msleep(5);
	ohci->ohci.next_statechange = jiffies;

	if ((status = pxa27x_start_hc(ohci, dev)) < 0)
		return status;

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(ohci, inf->port_mode);

	ohci_finish_controller_resume(hcd);
	return 0;
}

static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
	.suspend	= ohci_hcd_pxa27x_drv_suspend,
	.resume		= ohci_hcd_pxa27x_drv_resume,
};
#endif

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:pxa27x-ohci");

static struct platform_driver ohci_hcd_pxa27x_driver = {
	.probe		= ohci_hcd_pxa27x_drv_probe,
	.remove		= ohci_hcd_pxa27x_drv_remove,
	.shutdown	= usb_hcd_platform_shutdown,
	.driver		= {
		.name	= "pxa27x-ohci",
		.owner	= THIS_MODULE,
#ifdef CONFIG_PM
		.pm	= &ohci_hcd_pxa27x_pm_ops,
#endif
	},
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* OHCI HCD (Host Controller Driver) for USB.
	3	*
	4	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
	5	* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
	6	* (C) Copyright 2002 Hewlett-Packard Company
	7	*
	8	* Bus Glue for pxa27x
	9	*
	10	* Written by Christopher Hoover <ch@hpl.hp.com>
	11	* Based on fragments of previous driver by Russell King et al.
	12	*
	13	* Modified for LH7A404 from ohci-sa1111.c
	14	* by Durgesh Pattamatta <pattamattad@sharpsec.com>
	15	*
	16	* Modified for pxa27x from ohci-lh7a404.c
	17	* by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
	18	*
	19	* This file is licenced under the GPL.
	20	*/
	21
	22	#include <linux/device.h>
4e57b681	23	#include <linux/signal.h>
d052d1be	24	#include <linux/platform_device.h>
a8bcf410	25	#include <linux/clk.h>
a09e64fb	26	#include <mach/ohci.h>
6dc3ae84	27	#include <mach/pxa3xx-u2d.h>
1da177e4	28
596050bc EM	29	/*
	30	* UHC: USB Host Controller (OHCI-like) register definitions
	31	*/
0c392ed9 EM	32	#define UHCREV (0x0000) /* UHC HCI Spec Revision */
	33	#define UHCHCON (0x0004) /* UHC Host Control Register */
	34	#define UHCCOMS (0x0008) /* UHC Command Status Register */
	35	#define UHCINTS (0x000C) /* UHC Interrupt Status Register */
	36	#define UHCINTE (0x0010) /* UHC Interrupt Enable */
	37	#define UHCINTD (0x0014) /* UHC Interrupt Disable */
	38	#define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
	39	#define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
	40	#define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
	41	#define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
	42	#define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
	43	#define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
	44	#define UHCDHEAD (0x0030) /* UHC Done Head */
	45	#define UHCFMI (0x0034) /* UHC Frame Interval */
	46	#define UHCFMR (0x0038) /* UHC Frame Remaining */
	47	#define UHCFMN (0x003C) /* UHC Frame Number */
	48	#define UHCPERS (0x0040) /* UHC Periodic Start */
	49	#define UHCLS (0x0044) /* UHC Low Speed Threshold */
	50
	51	#define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
596050bc EM	52	#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
	53	#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
	54	#define UHCRHDA_POTPGT(x) \
	55	(((x) & 0xff) << 24) /* Power On To Power Good Time */
	56
0c392ed9 EM	57	#define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
	58	#define UHCRHS (0x0050) /* UHC Root Hub Status */
	59	#define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
	60	#define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
	61	#define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
596050bc	62
0c392ed9	63	#define UHCSTAT (0x0060) /* UHC Status Register */
596050bc EM	64	#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
	65	#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
	66	#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
	67	#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
	68	#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
	69	#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
	70	#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
	71	#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
	72	#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
	73
0c392ed9	74	#define UHCHR (0x0064) /* UHC Reset Register */
596050bc EM	75	#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
	76	#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
	77	#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
	78	#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
	79	#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
	80	#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
	81	#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
	82	#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
	83	#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
	84	#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
	85	#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
	86
0c392ed9	87	#define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
596050bc EM	88	#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
	89	#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
	90	#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
	91	#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
	92	#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
	93	Interrupt Enable*/
	94	#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
	95	#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
	96
0c392ed9	97	#define UHCHIT (0x006C) /* UHC Interrupt Test register */
596050bc	98
1da177e4 LT	99	#define PXA_UHC_MAX_PORTNUM 3
1da177e4 LT	100
0c392ed9 EM	101	struct pxa27x_ohci {
	102	/* must be 1st member here for hcd_to_ohci() to work */
	103	struct ohci_hcd ohci;
1da177e4	104
0c392ed9 EM	105	struct device *dev;
	106	struct clk *clk;
	107	void __iomem *mmio_base;
	108	};
	109
	110	#define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd)
a8bcf410	111
1da177e4 LT	112	/*
	113	PMM_NPS_MODE -- PMM Non-power switching mode
	114	Ports are powered continuously.
	115
	116	PMM_GLOBAL_MODE -- PMM global switching mode
	117	All ports are powered at the same time.
	118
	119	PMM_PERPORT_MODE -- PMM per port switching mode
	120	Ports are powered individually.
	121	*/
0c392ed9	122	static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
1da177e4	123	{
0c392ed9 EM	124	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
	125	uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
	126
	127	switch (mode) {
1da177e4	128	case PMM_NPS_MODE:
0c392ed9	129	uhcrhda \|= RH_A_NPS;
dd9048af	130	break;
1da177e4	131	case PMM_GLOBAL_MODE:
0c392ed9	132	uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
1da177e4 LT	133	break;
1da177e4 LT	134	case PMM_PERPORT_MODE:
0c392ed9 EM	135	uhcrhda &= ~(RH_A_NPS);
0c392ed9 EM	136	uhcrhda \|= RH_A_PSM;
1da177e4 LT	137
1da177e4 LT	138	/* Set port power control mask bits, only 3 ports. */
0c392ed9	139	uhcrhdb \|= (0x7<<17);
1da177e4 LT	140	break;
	141	default:
	142	printk( KERN_ERR
dd9048af	143	"Invalid mode %d, set to non-power switch mode.\n",
1da177e4 LT	144	mode );
1da177e4 LT	145
0c392ed9	146	uhcrhda \|= RH_A_NPS;
1da177e4 LT	147	}
1da177e4 LT	148
0c392ed9 EM	149	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
0c392ed9 EM	150	__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
1da177e4 LT	151	return 0;
	152	}
	153
1da177e4 LT	154	extern int usb_disabled(void);
	155
	156	/-------------------------------------------------------------------------/
	157
0c392ed9 EM	158	static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
0c392ed9 EM	159	struct pxaohci_platform_data *inf)
097b5334	160	{
0c392ed9 EM	161	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
0c392ed9 EM	162	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
097b5334 EM	163
	164	if (inf->flags & ENABLE_PORT1)
	165	uhchr &= ~UHCHR_SSEP1;
	166
	167	if (inf->flags & ENABLE_PORT2)
	168	uhchr &= ~UHCHR_SSEP2;
	169
	170	if (inf->flags & ENABLE_PORT3)
	171	uhchr &= ~UHCHR_SSEP3;
	172
	173	if (inf->flags & POWER_CONTROL_LOW)
	174	uhchr \|= UHCHR_PCPL;
	175
	176	if (inf->flags & POWER_SENSE_LOW)
	177	uhchr \|= UHCHR_PSPL;
	178
	179	if (inf->flags & NO_OC_PROTECTION)
	180	uhcrhda \|= UHCRHDA_NOCP;
7b4361f0 AB	181	else
7b4361f0 AB	182	uhcrhda &= ~UHCRHDA_NOCP;
097b5334 EM	183
	184	if (inf->flags & OC_MODE_PERPORT)
	185	uhcrhda \|= UHCRHDA_OCPM;
7b4361f0 AB	186	else
7b4361f0 AB	187	uhcrhda &= ~UHCRHDA_OCPM;
097b5334 EM	188
	189	if (inf->power_on_delay) {
	190	uhcrhda &= ~UHCRHDA_POTPGT(0xff);
	191	uhcrhda \|= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	192	}
	193
0c392ed9 EM	194	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	195	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
	196	}
	197
	198	static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
	199	{
	200	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
	201
	202	__raw_writel(uhchr \| UHCHR_FHR, ohci->mmio_base + UHCHR);
	203	udelay(11);
	204	__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
097b5334 EM	205	}
097b5334 EM	206
59376cc3	207	#ifdef CONFIG_PXA27x
0cb0b0d3 EM	208	extern void pxa27x_clear_otgph(void);
	209	#else
	210	#define pxa27x_clear_otgph() do {} while (0)
	211	#endif
	212
0c392ed9	213	static int pxa27x_start_hc(struct pxa27x_ohci ohci, struct device dev)
1da177e4	214	{
81f280e2 RP	215	int retval = 0;
81f280e2 RP	216	struct pxaohci_platform_data *inf;
0c392ed9	217	uint32_t uhchr;
81f280e2 RP	218
	219	inf = dev->platform_data;
	220
0c392ed9	221	clk_enable(ohci->clk);
1da177e4	222
0c392ed9	223	pxa27x_reset_hc(ohci);
1da177e4	224
0c392ed9 EM	225	uhchr = __raw_readl(ohci->mmio_base + UHCHR) \| UHCHR_FSBIR;
	226	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	227
	228	while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
1da177e4 LT	229	cpu_relax();
1da177e4 LT	230
0c392ed9	231	pxa27x_setup_hc(ohci, inf);
097b5334	232
81f280e2 RP	233	if (inf->init)
81f280e2 RP	234	retval = inf->init(dev);
155faf5e	235
81f280e2 RP	236	if (retval < 0)
81f280e2 RP	237	return retval;
1da177e4	238
6dc3ae84 IG	239	if (cpu_is_pxa3xx())
	240	pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);
	241
0c392ed9 EM	242	uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
	243	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	244	__raw_writel(UHCHIE_UPRIE \| UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
155faf5e DB	245
155faf5e DB	246	/* Clear any OTG Pin Hold */
0cb0b0d3	247	pxa27x_clear_otgph();
81f280e2	248	return 0;
1da177e4 LT	249	}
1da177e4 LT	250
0c392ed9	251	static void pxa27x_stop_hc(struct pxa27x_ohci ohci, struct device dev)
1da177e4	252	{
81f280e2	253	struct pxaohci_platform_data *inf;
0c392ed9	254	uint32_t uhccoms;
81f280e2 RP	255
	256	inf = dev->platform_data;
	257
6dc3ae84 IG	258	if (cpu_is_pxa3xx())
	259	pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);
	260
81f280e2 RP	261	if (inf->exit)
	262	inf->exit(dev);
	263
0c392ed9	264	pxa27x_reset_hc(ohci);
1da177e4	265
0c392ed9 EM	266	/* Host Controller Reset */
	267	uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) \| 0x01;
	268	__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
1da177e4 LT	269	udelay(10);
1da177e4 LT	270
0c392ed9	271	clk_disable(ohci->clk);
1da177e4 LT	272	}
	273
	274
	275	/-------------------------------------------------------------------------/
	276
	277	/* configure so an HC device and id are always provided */
	278	/* always called with process context; sleeping is OK */
	279
	280
	281	/**
	282	* usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
	283	* Context: !in_interrupt()
	284	*
	285	* Allocates basic resources for this USB host controller, and
	286	* then invokes the start() method for the HCD associated with it
	287	* through the hotplug entry's driver_data.
	288	*
	289	*/
81f280e2	290	int usb_hcd_pxa27x_probe (const struct hc_driver driver, struct platform_device pdev)
1da177e4	291	{
84bab739	292	int retval, irq;
1da177e4	293	struct usb_hcd *hcd;
81f280e2	294	struct pxaohci_platform_data *inf;
0c392ed9	295	struct pxa27x_ohci *ohci;
84bab739	296	struct resource *r;
0c392ed9	297	struct clk *usb_clk;
81f280e2 RP	298
81f280e2 RP	299	inf = pdev->dev.platform_data;
1da177e4	300
81f280e2 RP	301	if (!inf)
	302	return -ENODEV;
	303
84bab739 EM	304	irq = platform_get_irq(pdev, 0);
	305	if (irq < 0) {
	306	pr_err("no resource of IORESOURCE_IRQ");
	307	return -ENXIO;
1da177e4 LT	308	}
1da177e4 LT	309
e0d8b13a	310	usb_clk = clk_get(&pdev->dev, NULL);
a8bcf410	311	if (IS_ERR(usb_clk))
	312	return PTR_ERR(usb_clk);
	313
81f280e2	314	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
1da177e4 LT	315	if (!hcd)
1da177e4 LT	316	return -ENOMEM;
84bab739 EM	317
	318	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	319	if (!r) {
	320	pr_err("no resource of IORESOURCE_MEM");
	321	retval = -ENXIO;
	322	goto err1;
	323	}
	324
	325	hcd->rsrc_start = r->start;
	326	hcd->rsrc_len = resource_size(r);
1da177e4 LT	327
	328	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
	329	pr_debug("request_mem_region failed");
	330	retval = -EBUSY;
	331	goto err1;
	332	}
	333
	334	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	335	if (!hcd->regs) {
	336	pr_debug("ioremap failed");
	337	retval = -ENOMEM;
	338	goto err2;
	339	}
	340
0c392ed9 EM	341	/* initialize "struct pxa27x_ohci" */
	342	ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
	343	ohci->dev = &pdev->dev;
	344	ohci->clk = usb_clk;
	345	ohci->mmio_base = (void __iomem *)hcd->regs;
	346
	347	if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
81f280e2 RP	348	pr_debug("pxa27x_start_hc failed");
	349	goto err3;
	350	}
1da177e4 LT	351
1da177e4 LT	352	/* Select Power Management Mode */
0c392ed9	353	pxa27x_ohci_select_pmm(ohci, inf->port_mode);
1da177e4	354
0c27c5d5 RP	355	if (inf->power_budget)
	356	hcd->power_budget = inf->power_budget;
	357
1da177e4 LT	358	ohci_hcd_init(hcd_to_ohci(hcd));
1da177e4 LT	359
84bab739	360	retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
1da177e4 LT	361	if (retval == 0)
	362	return retval;
	363
0c392ed9	364	pxa27x_stop_hc(ohci, &pdev->dev);
81f280e2	365	err3:
1da177e4 LT	366	iounmap(hcd->regs);
	367	err2:
	368	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	369	err1:
	370	usb_put_hcd(hcd);
a8bcf410	371	clk_put(usb_clk);
1da177e4 LT	372	return retval;
	373	}
	374
	375
	376	/* may be called without controller electrically present */
	377	/* may be called with controller, bus, and devices active */
	378
	379	/**
	380	* usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
	381	* @dev: USB Host Controller being removed
	382	* Context: !in_interrupt()
	383	*
	384	* Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
	385	* the HCD's stop() method. It is always called from a thread
	386	* context, normally "rmmod", "apmd", or something similar.
	387	*
	388	*/
81f280e2	389	void usb_hcd_pxa27x_remove (struct usb_hcd hcd, struct platform_device pdev)
1da177e4	390	{
0c392ed9 EM	391	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
0c392ed9 EM	392
1da177e4	393	usb_remove_hcd(hcd);
0c392ed9	394	pxa27x_stop_hc(ohci, &pdev->dev);
1da177e4 LT	395	iounmap(hcd->regs);
	396	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	397	usb_put_hcd(hcd);
0c392ed9	398	clk_put(ohci->clk);
1da177e4 LT	399	}
	400
	401	/-------------------------------------------------------------------------/
	402
	403	static int __devinit
	404	ohci_pxa27x_start (struct usb_hcd *hcd)
	405	{
	406	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	407	int ret;
	408
	409	ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
	410
fdd13b36 DB	411	/* The value of NDP in roothub_a is incorrect on this hardware */
	412	ohci->num_ports = 3;
	413
1da177e4 LT	414	if ((ret = ohci_init(ohci)) < 0)
	415	return ret;
	416
	417	if ((ret = ohci_run (ohci)) < 0) {
	418	err ("can't start %s", hcd->self.bus_name);
	419	ohci_stop (hcd);
	420	return ret;
	421	}
	422
	423	return 0;
	424	}
	425
	426	/-------------------------------------------------------------------------/
	427
	428	static const struct hc_driver ohci_pxa27x_hc_driver = {
	429	.description = hcd_name,
	430	.product_desc = "PXA27x OHCI",
0c392ed9	431	.hcd_priv_size = sizeof(struct pxa27x_ohci),
1da177e4 LT	432
	433	/*
	434	* generic hardware linkage
	435	*/
	436	.irq = ohci_irq,
	437	.flags = HCD_USB11 \| HCD_MEMORY,
	438
	439	/*
	440	* basic lifecycle operations
	441	*/
	442	.start = ohci_pxa27x_start,
	443	.stop = ohci_stop,
dd9048af	444	.shutdown = ohci_shutdown,
1da177e4 LT	445
	446	/*
	447	* managing i/o requests and associated device resources
	448	*/
	449	.urb_enqueue = ohci_urb_enqueue,
	450	.urb_dequeue = ohci_urb_dequeue,
	451	.endpoint_disable = ohci_endpoint_disable,
	452
	453	/*
	454	* scheduling support
	455	*/
	456	.get_frame_number = ohci_get_frame,
	457
	458	/*
	459	* root hub support
	460	*/
	461	.hub_status_data = ohci_hub_status_data,
	462	.hub_control = ohci_hub_control,
8ad7fe16	463	#ifdef CONFIG_PM
0c0382e3 AS	464	.bus_suspend = ohci_bus_suspend,
0c0382e3 AS	465	.bus_resume = ohci_bus_resume,
1da177e4	466	#endif
9293677a	467	.start_port_reset = ohci_start_port_reset,
1da177e4 LT	468	};
	469
	470	/-------------------------------------------------------------------------/
	471
3ae5eaec	472	static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
1da177e4	473	{
1da177e4 LT	474	pr_debug ("In ohci_hcd_pxa27x_drv_probe");
	475
	476	if (usb_disabled())
	477	return -ENODEV;
	478
81f280e2	479	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
1da177e4 LT	480	}
1da177e4 LT	481
3ae5eaec	482	static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
1da177e4	483	{
3ae5eaec	484	struct usb_hcd *hcd = platform_get_drvdata(pdev);
1da177e4 LT	485
1da177e4 LT	486	usb_hcd_pxa27x_remove(hcd, pdev);
a5e36d20	487	platform_set_drvdata(pdev, NULL);
1da177e4 LT	488	return 0;
	489	}
	490
b7f3f59b MR	491	#ifdef CONFIG_PM
b7f3f59b MR	492	static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
1da177e4	493	{
b7f3f59b	494	struct usb_hcd *hcd = dev_get_drvdata(dev);
0c392ed9	495	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
2e1dcc16	496
0c392ed9	497	if (time_before(jiffies, ohci->ohci.next_statechange))
2e1dcc16	498	msleep(5);
0c392ed9	499	ohci->ohci.next_statechange = jiffies;
2e1dcc16	500
b7f3f59b	501	pxa27x_stop_hc(ohci, dev);
a5e36d20	502	hcd->state = HC_STATE_SUSPENDED;
1da177e4 LT	503
	504	return 0;
	505	}
	506
b7f3f59b	507	static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
1da177e4	508	{
b7f3f59b	509	struct usb_hcd *hcd = dev_get_drvdata(dev);
0c392ed9	510	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
a75d048e	511	struct pxaohci_platform_data *inf = dev->platform_data;
2e1dcc16 RP	512	int status;
2e1dcc16 RP	513
0c392ed9	514	if (time_before(jiffies, ohci->ohci.next_statechange))
2e1dcc16	515	msleep(5);
0c392ed9	516	ohci->ohci.next_statechange = jiffies;
2e1dcc16	517
b7f3f59b	518	if ((status = pxa27x_start_hc(ohci, dev)) < 0)
2e1dcc16 RP	519	return status;
2e1dcc16 RP	520
a75d048e AB	521	/* Select Power Management Mode */
	522	pxa27x_ohci_select_pmm(ohci, inf->port_mode);
	523
43bbb7e0	524	ohci_finish_controller_resume(hcd);
1da177e4 LT	525	return 0;
1da177e4 LT	526	}
b7f3f59b	527
47145210	528	static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
b7f3f59b MR	529	.suspend = ohci_hcd_pxa27x_drv_suspend,
	530	.resume = ohci_hcd_pxa27x_drv_resume,
	531	};
2e1dcc16	532	#endif
1da177e4	533
f4fce61d KS	534	/* work with hotplug and coldplug */
f4fce61d KS	535	MODULE_ALIAS("platform:pxa27x-ohci");
1da177e4	536
3ae5eaec	537	static struct platform_driver ohci_hcd_pxa27x_driver = {
1da177e4 LT	538	.probe = ohci_hcd_pxa27x_drv_probe,
1da177e4 LT	539	.remove = ohci_hcd_pxa27x_drv_remove,
dd9048af	540	.shutdown = usb_hcd_platform_shutdown,
3ae5eaec RK	541	.driver = {
3ae5eaec RK	542	.name = "pxa27x-ohci",
f4fce61d	543	.owner = THIS_MODULE,
b7f3f59b MR	544	#ifdef CONFIG_PM
	545	.pm = &ohci_hcd_pxa27x_pm_ops,
	546	#endif
3ae5eaec	547	},
1da177e4 LT	548	};
1da177e4 LT	549