[deliverable/linux.git] / drivers / usb / host / ohci-pxa27x.c

/*
 * OHCI HCD (Host Controller Driver) for USB.
 *
 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
 * (C) Copyright 2002 Hewlett-Packard Company
 *
 * Bus Glue for pxa27x
 *
 * Written by Christopher Hoover <ch@hpl.hp.com>
 * Based on fragments of previous driver by Russell King et al.
 *
 * Modified for LH7A404 from ohci-sa1111.c
 *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
 *
 * Modified for pxa27x from ohci-lh7a404.c
 *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
 *
 * This file is licenced under the GPL.
 */

#include <linux/device.h>
#include <linux/signal.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of_platform.h>
#include <linux/of_gpio.h>
#include <mach/hardware.h>
#include <linux/platform_data/usb-ohci-pxa27x.h>
#include <linux/platform_data/usb-pxa3xx-ulpi.h>

/*
 * UHC: USB Host Controller (OHCI-like) register definitions
 */
#define UHCREV		(0x0000) /* UHC HCI Spec Revision */
#define UHCHCON		(0x0004) /* UHC Host Control Register */
#define UHCCOMS		(0x0008) /* UHC Command Status Register */
#define UHCINTS		(0x000C) /* UHC Interrupt Status Register */
#define UHCINTE		(0x0010) /* UHC Interrupt Enable */
#define UHCINTD		(0x0014) /* UHC Interrupt Disable */
#define UHCHCCA		(0x0018) /* UHC Host Controller Comm. Area */
#define UHCPCED		(0x001C) /* UHC Period Current Endpt Descr */
#define UHCCHED		(0x0020) /* UHC Control Head Endpt Descr */
#define UHCCCED		(0x0024) /* UHC Control Current Endpt Descr */
#define UHCBHED		(0x0028) /* UHC Bulk Head Endpt Descr */
#define UHCBCED		(0x002C) /* UHC Bulk Current Endpt Descr */
#define UHCDHEAD	(0x0030) /* UHC Done Head */
#define UHCFMI		(0x0034) /* UHC Frame Interval */
#define UHCFMR		(0x0038) /* UHC Frame Remaining */
#define UHCFMN		(0x003C) /* UHC Frame Number */
#define UHCPERS		(0x0040) /* UHC Periodic Start */
#define UHCLS		(0x0044) /* UHC Low Speed Threshold */

#define UHCRHDA		(0x0048) /* UHC Root Hub Descriptor A */
#define UHCRHDA_NOCP	(1 << 12)	/* No over current protection */
#define UHCRHDA_OCPM	(1 << 11)	/* Over Current Protection Mode */
#define UHCRHDA_POTPGT(x) \
			(((x) & 0xff) << 24) /* Power On To Power Good Time */

#define UHCRHDB		(0x004C) /* UHC Root Hub Descriptor B */
#define UHCRHS		(0x0050) /* UHC Root Hub Status */
#define UHCRHPS1	(0x0054) /* UHC Root Hub Port 1 Status */
#define UHCRHPS2	(0x0058) /* UHC Root Hub Port 2 Status */
#define UHCRHPS3	(0x005C) /* UHC Root Hub Port 3 Status */

#define UHCSTAT		(0x0060) /* UHC Status Register */
#define UHCSTAT_UPS3	(1 << 16)	/* USB Power Sense Port3 */
#define UHCSTAT_SBMAI	(1 << 15)	/* System Bus Master Abort Interrupt*/
#define UHCSTAT_SBTAI	(1 << 14)	/* System Bus Target Abort Interrupt*/
#define UHCSTAT_UPRI	(1 << 13)	/* USB Port Resume Interrupt */
#define UHCSTAT_UPS2	(1 << 12)	/* USB Power Sense Port 2 */
#define UHCSTAT_UPS1	(1 << 11)	/* USB Power Sense Port 1 */
#define UHCSTAT_HTA	(1 << 10)	/* HCI Target Abort */
#define UHCSTAT_HBA	(1 << 8)	/* HCI Buffer Active */
#define UHCSTAT_RWUE	(1 << 7)	/* HCI Remote Wake Up Event */

#define UHCHR           (0x0064) /* UHC Reset Register */
#define UHCHR_SSEP3	(1 << 11)	/* Sleep Standby Enable for Port3 */
#define UHCHR_SSEP2	(1 << 10)	/* Sleep Standby Enable for Port2 */
#define UHCHR_SSEP1	(1 << 9)	/* Sleep Standby Enable for Port1 */
#define UHCHR_PCPL	(1 << 7)	/* Power control polarity low */
#define UHCHR_PSPL	(1 << 6)	/* Power sense polarity low */
#define UHCHR_SSE	(1 << 5)	/* Sleep Standby Enable */
#define UHCHR_UIT	(1 << 4)	/* USB Interrupt Test */
#define UHCHR_SSDC	(1 << 3)	/* Simulation Scale Down Clock */
#define UHCHR_CGR	(1 << 2)	/* Clock Generation Reset */
#define UHCHR_FHR	(1 << 1)	/* Force Host Controller Reset */
#define UHCHR_FSBIR	(1 << 0)	/* Force System Bus Iface Reset */

#define UHCHIE          (0x0068) /* UHC Interrupt Enable Register*/
#define UHCHIE_UPS3IE	(1 << 14)	/* Power Sense Port3 IntEn */
#define UHCHIE_UPRIE	(1 << 13)	/* Port Resume IntEn */
#define UHCHIE_UPS2IE	(1 << 12)	/* Power Sense Port2 IntEn */
#define UHCHIE_UPS1IE	(1 << 11)	/* Power Sense Port1 IntEn */
#define UHCHIE_TAIE	(1 << 10)	/* HCI Interface Transfer Abort
					   Interrupt Enable*/
#define UHCHIE_HBAIE	(1 << 8)	/* HCI Buffer Active IntEn */
#define UHCHIE_RWIE	(1 << 7)	/* Remote Wake-up IntEn */

#define UHCHIT          (0x006C) /* UHC Interrupt Test register */

#define PXA_UHC_MAX_PORTNUM    3

struct pxa27x_ohci {
	/* must be 1st member here for hcd_to_ohci() to work */
	struct ohci_hcd ohci;

	struct device	*dev;
	struct clk	*clk;
	void __iomem	*mmio_base;
};

#define to_pxa27x_ohci(hcd)	(struct pxa27x_ohci *)hcd_to_ohci(hcd)

/*
  PMM_NPS_MODE -- PMM Non-power switching mode
      Ports are powered continuously.

  PMM_GLOBAL_MODE -- PMM global switching mode
      All ports are powered at the same time.

  PMM_PERPORT_MODE -- PMM per port switching mode
      Ports are powered individually.
 */
static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
{
	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
	uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);

	switch (mode) {
	case PMM_NPS_MODE:
		uhcrhda |= RH_A_NPS;
		break;
	case PMM_GLOBAL_MODE:
		uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
		break;
	case PMM_PERPORT_MODE:
		uhcrhda &= ~(RH_A_NPS);
		uhcrhda |= RH_A_PSM;

		/* Set port power control mask bits, only 3 ports. */
		uhcrhdb |= (0x7<<17);
		break;
	default:
		printk( KERN_ERR
			"Invalid mode %d, set to non-power switch mode.\n",
			mode );

		uhcrhda |= RH_A_NPS;
	}

	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
	__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
	return 0;
}

extern int usb_disabled(void);

/*-------------------------------------------------------------------------*/

static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
				   struct pxaohci_platform_data *inf)
{
	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);

	if (inf->flags & ENABLE_PORT1)
		uhchr &= ~UHCHR_SSEP1;

	if (inf->flags & ENABLE_PORT2)
		uhchr &= ~UHCHR_SSEP2;

	if (inf->flags & ENABLE_PORT3)
		uhchr &= ~UHCHR_SSEP3;

	if (inf->flags & POWER_CONTROL_LOW)
		uhchr |= UHCHR_PCPL;

	if (inf->flags & POWER_SENSE_LOW)
		uhchr |= UHCHR_PSPL;

	if (inf->flags & NO_OC_PROTECTION)
		uhcrhda |= UHCRHDA_NOCP;
	else
		uhcrhda &= ~UHCRHDA_NOCP;

	if (inf->flags & OC_MODE_PERPORT)
		uhcrhda |= UHCRHDA_OCPM;
	else
		uhcrhda &= ~UHCRHDA_OCPM;

	if (inf->power_on_delay) {
		uhcrhda &= ~UHCRHDA_POTPGT(0xff);
		uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	}

	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
}

static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
{
	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);

	__raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
	udelay(11);
	__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
}

#ifdef CONFIG_PXA27x
extern void pxa27x_clear_otgph(void);
#else
#define pxa27x_clear_otgph()	do {} while (0)
#endif

static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
	int retval = 0;
	struct pxaohci_platform_data *inf;
	uint32_t uhchr;

	inf = dev->platform_data;

	clk_prepare_enable(ohci->clk);

	pxa27x_reset_hc(ohci);

	uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
	__raw_writel(uhchr, ohci->mmio_base + UHCHR);

	while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
		cpu_relax();

	pxa27x_setup_hc(ohci, inf);

	if (inf->init)
		retval = inf->init(dev);

	if (retval < 0)
		return retval;

	if (cpu_is_pxa3xx())
		pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);

	uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);

	/* Clear any OTG Pin Hold */
	pxa27x_clear_otgph();
	return 0;
}

static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
	struct pxaohci_platform_data *inf;
	uint32_t uhccoms;

	inf = dev->platform_data;

	if (cpu_is_pxa3xx())
		pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);

	if (inf->exit)
		inf->exit(dev);

	pxa27x_reset_hc(ohci);

	/* Host Controller Reset */
	uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
	__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
	udelay(10);

	clk_disable_unprepare(ohci->clk);
}

#ifdef CONFIG_OF
static const struct of_device_id pxa_ohci_dt_ids[] = {
	{ .compatible = "marvell,pxa-ohci" },
	{ }
};

MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);

static u64 pxa_ohci_dma_mask = DMA_BIT_MASK(32);

static int ohci_pxa_of_init(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct pxaohci_platform_data *pdata;
	u32 tmp;

	if (!np)
		return 0;

	/* Right now device-tree probed devices don't get dma_mask set.
	 * Since shared usb code relies on it, set it here for now.
	 * Once we have dma capability bindings this can go away.
	 */
	if (!pdev->dev.dma_mask)
		pdev->dev.dma_mask = &pxa_ohci_dma_mask;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;

	if (of_get_property(np, "marvell,enable-port1", NULL))
		pdata->flags |= ENABLE_PORT1;
	if (of_get_property(np, "marvell,enable-port2", NULL))
		pdata->flags |= ENABLE_PORT2;
	if (of_get_property(np, "marvell,enable-port3", NULL))
		pdata->flags |= ENABLE_PORT3;
	if (of_get_property(np, "marvell,port-sense-low", NULL))
		pdata->flags |= POWER_SENSE_LOW;
	if (of_get_property(np, "marvell,power-control-low", NULL))
		pdata->flags |= POWER_CONTROL_LOW;
	if (of_get_property(np, "marvell,no-oc-protection", NULL))
		pdata->flags |= NO_OC_PROTECTION;
	if (of_get_property(np, "marvell,oc-mode-perport", NULL))
		pdata->flags |= OC_MODE_PERPORT;
	if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
		pdata->power_on_delay = tmp;
	if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
		pdata->port_mode = tmp;
	if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
		pdata->power_budget = tmp;

	pdev->dev.platform_data = pdata;

	return 0;
}
#else
static int ohci_pxa_of_init(struct platform_device *pdev)
{
	return 0;
}
#endif

/*-------------------------------------------------------------------------*/

/* configure so an HC device and id are always provided */
/* always called with process context; sleeping is OK */


/**
 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
 * Context: !in_interrupt()
 *
 * Allocates basic resources for this USB host controller, and
 * then invokes the start() method for the HCD associated with it
 * through the hotplug entry's driver_data.
 *
 */
int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
{
	int retval, irq;
	struct usb_hcd *hcd;
	struct pxaohci_platform_data *inf;
	struct pxa27x_ohci *ohci;
	struct resource *r;
	struct clk *usb_clk;

	retval = ohci_pxa_of_init(pdev);
	if (retval)
		return retval;

	inf = pdev->dev.platform_data;

	if (!inf)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		pr_err("no resource of IORESOURCE_IRQ");
		return -ENXIO;
	}

	usb_clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(usb_clk))
		return PTR_ERR(usb_clk);

	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
	if (!hcd) {
		retval = -ENOMEM;
		goto err0;
	}

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		pr_err("no resource of IORESOURCE_MEM");
		retval = -ENXIO;
		goto err1;
	}

	hcd->rsrc_start = r->start;
	hcd->rsrc_len = resource_size(r);

	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
		pr_debug("request_mem_region failed");
		retval = -EBUSY;
		goto err1;
	}

	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	if (!hcd->regs) {
		pr_debug("ioremap failed");
		retval = -ENOMEM;
		goto err2;
	}

	/* initialize "struct pxa27x_ohci" */
	ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
	ohci->dev = &pdev->dev;
	ohci->clk = usb_clk;
	ohci->mmio_base = (void __iomem *)hcd->regs;

	if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
		pr_debug("pxa27x_start_hc failed");
		goto err3;
	}

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(ohci, inf->port_mode);

	if (inf->power_budget)
		hcd->power_budget = inf->power_budget;

	ohci_hcd_init(hcd_to_ohci(hcd));

	retval = usb_add_hcd(hcd, irq, 0);
	if (retval == 0)
		return retval;

	pxa27x_stop_hc(ohci, &pdev->dev);
 err3:
	iounmap(hcd->regs);
 err2:
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 err1:
	usb_put_hcd(hcd);
 err0:
	clk_put(usb_clk);
	return retval;
}


/* may be called without controller electrically present */
/* may be called with controller, bus, and devices active */

/**
 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
 * @dev: USB Host Controller being removed
 * Context: !in_interrupt()
 *
 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
 * the HCD's stop() method.  It is always called from a thread
 * context, normally "rmmod", "apmd", or something similar.
 *
 */
void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
{
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);

	usb_remove_hcd(hcd);
	pxa27x_stop_hc(ohci, &pdev->dev);
	iounmap(hcd->regs);
	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	usb_put_hcd(hcd);
	clk_put(ohci->clk);
}

/*-------------------------------------------------------------------------*/

static int
ohci_pxa27x_start (struct usb_hcd *hcd)
{
	struct ohci_hcd	*ohci = hcd_to_ohci (hcd);
	int		ret;

	ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);

	/* The value of NDP in roothub_a is incorrect on this hardware */
	ohci->num_ports = 3;

	if ((ret = ohci_init(ohci)) < 0)
		return ret;

	if ((ret = ohci_run (ohci)) < 0) {
		dev_err(hcd->self.controller, "can't start %s",
			hcd->self.bus_name);
		ohci_stop (hcd);
		return ret;
	}

	return 0;
}

/*-------------------------------------------------------------------------*/

static const struct hc_driver ohci_pxa27x_hc_driver = {
	.description =		hcd_name,
	.product_desc =		"PXA27x OHCI",
	.hcd_priv_size =	sizeof(struct pxa27x_ohci),

	/*
	 * generic hardware linkage
	 */
	.irq =			ohci_irq,
	.flags =		HCD_USB11 | HCD_MEMORY,

	/*
	 * basic lifecycle operations
	 */
	.start =		ohci_pxa27x_start,
	.stop =			ohci_stop,
	.shutdown =		ohci_shutdown,

	/*
	 * managing i/o requests and associated device resources
	 */
	.urb_enqueue =		ohci_urb_enqueue,
	.urb_dequeue =		ohci_urb_dequeue,
	.endpoint_disable =	ohci_endpoint_disable,

	/*
	 * scheduling support
	 */
	.get_frame_number =	ohci_get_frame,

	/*
	 * root hub support
	 */
	.hub_status_data =	ohci_hub_status_data,
	.hub_control =		ohci_hub_control,
#ifdef  CONFIG_PM
	.bus_suspend =		ohci_bus_suspend,
	.bus_resume =		ohci_bus_resume,
#endif
	.start_port_reset =	ohci_start_port_reset,
};

/*-------------------------------------------------------------------------*/

static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
{
	pr_debug ("In ohci_hcd_pxa27x_drv_probe");

	if (usb_disabled())
		return -ENODEV;

	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
}

static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
{
	struct usb_hcd *hcd = platform_get_drvdata(pdev);

	usb_hcd_pxa27x_remove(hcd, pdev);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

#ifdef CONFIG_PM
static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
{
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);

	if (time_before(jiffies, ohci->ohci.next_statechange))
		msleep(5);
	ohci->ohci.next_statechange = jiffies;

	pxa27x_stop_hc(ohci, dev);
	return 0;
}

static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
{
	struct usb_hcd *hcd = dev_get_drvdata(dev);
	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
	struct pxaohci_platform_data *inf = dev->platform_data;
	int status;

	if (time_before(jiffies, ohci->ohci.next_statechange))
		msleep(5);
	ohci->ohci.next_statechange = jiffies;

	if ((status = pxa27x_start_hc(ohci, dev)) < 0)
		return status;

	/* Select Power Management Mode */
	pxa27x_ohci_select_pmm(ohci, inf->port_mode);

	ohci_resume(hcd, false);
	return 0;
}

static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
	.suspend	= ohci_hcd_pxa27x_drv_suspend,
	.resume		= ohci_hcd_pxa27x_drv_resume,
};
#endif

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:pxa27x-ohci");

static struct platform_driver ohci_hcd_pxa27x_driver = {
	.probe		= ohci_hcd_pxa27x_drv_probe,
	.remove		= ohci_hcd_pxa27x_drv_remove,
	.shutdown	= usb_hcd_platform_shutdown,
	.driver		= {
		.name	= "pxa27x-ohci",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(pxa_ohci_dt_ids),
#ifdef CONFIG_PM
		.pm	= &ohci_hcd_pxa27x_pm_ops,
#endif
	},
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* OHCI HCD (Host Controller Driver) for USB.
	3	*
	4	* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
	5	* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
	6	* (C) Copyright 2002 Hewlett-Packard Company
	7	*
	8	* Bus Glue for pxa27x
	9	*
	10	* Written by Christopher Hoover <ch@hpl.hp.com>
	11	* Based on fragments of previous driver by Russell King et al.
	12	*
	13	* Modified for LH7A404 from ohci-sa1111.c
	14	* by Durgesh Pattamatta <pattamattad@sharpsec.com>
	15	*
	16	* Modified for pxa27x from ohci-lh7a404.c
	17	* by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
	18	*
	19	* This file is licenced under the GPL.
	20	*/
	21
	22	#include <linux/device.h>
4e57b681	23	#include <linux/signal.h>
d052d1be	24	#include <linux/platform_device.h>
a8bcf410	25	#include <linux/clk.h>
1139b451 DM	26	#include <linux/of_platform.h>
1139b451 DM	27	#include <linux/of_gpio.h>
60b9bd8d	28	#include <mach/hardware.h>
293b2da1 AB	29	#include <linux/platform_data/usb-ohci-pxa27x.h>
293b2da1 AB	30	#include <linux/platform_data/usb-pxa3xx-ulpi.h>
1da177e4	31
596050bc EM	32	/*
	33	* UHC: USB Host Controller (OHCI-like) register definitions
	34	*/
0c392ed9 EM	35	#define UHCREV (0x0000) /* UHC HCI Spec Revision */
	36	#define UHCHCON (0x0004) /* UHC Host Control Register */
	37	#define UHCCOMS (0x0008) /* UHC Command Status Register */
	38	#define UHCINTS (0x000C) /* UHC Interrupt Status Register */
	39	#define UHCINTE (0x0010) /* UHC Interrupt Enable */
	40	#define UHCINTD (0x0014) /* UHC Interrupt Disable */
	41	#define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
	42	#define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
	43	#define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
	44	#define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
	45	#define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
	46	#define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
	47	#define UHCDHEAD (0x0030) /* UHC Done Head */
	48	#define UHCFMI (0x0034) /* UHC Frame Interval */
	49	#define UHCFMR (0x0038) /* UHC Frame Remaining */
	50	#define UHCFMN (0x003C) /* UHC Frame Number */
	51	#define UHCPERS (0x0040) /* UHC Periodic Start */
	52	#define UHCLS (0x0044) /* UHC Low Speed Threshold */
	53
	54	#define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
596050bc EM	55	#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
	56	#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
	57	#define UHCRHDA_POTPGT(x) \
	58	(((x) & 0xff) << 24) /* Power On To Power Good Time */
	59
0c392ed9 EM	60	#define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
	61	#define UHCRHS (0x0050) /* UHC Root Hub Status */
	62	#define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
	63	#define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
	64	#define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
596050bc	65
0c392ed9	66	#define UHCSTAT (0x0060) /* UHC Status Register */
596050bc EM	67	#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
	68	#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
	69	#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
	70	#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
	71	#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
	72	#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
	73	#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
	74	#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
	75	#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
	76
0c392ed9	77	#define UHCHR (0x0064) /* UHC Reset Register */
596050bc EM	78	#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
	79	#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
	80	#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
	81	#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
	82	#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
	83	#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
	84	#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
	85	#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
	86	#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
	87	#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
	88	#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
	89
0c392ed9	90	#define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
596050bc EM	91	#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
	92	#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
	93	#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
	94	#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
	95	#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
	96	Interrupt Enable*/
	97	#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
	98	#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
	99
0c392ed9	100	#define UHCHIT (0x006C) /* UHC Interrupt Test register */
596050bc	101
1da177e4 LT	102	#define PXA_UHC_MAX_PORTNUM 3
1da177e4 LT	103
0c392ed9 EM	104	struct pxa27x_ohci {
	105	/* must be 1st member here for hcd_to_ohci() to work */
	106	struct ohci_hcd ohci;
1da177e4	107
0c392ed9 EM	108	struct device *dev;
	109	struct clk *clk;
	110	void __iomem *mmio_base;
	111	};
	112
	113	#define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd)
a8bcf410	114
1da177e4 LT	115	/*
	116	PMM_NPS_MODE -- PMM Non-power switching mode
	117	Ports are powered continuously.
	118
	119	PMM_GLOBAL_MODE -- PMM global switching mode
	120	All ports are powered at the same time.
	121
	122	PMM_PERPORT_MODE -- PMM per port switching mode
	123	Ports are powered individually.
	124	*/
0c392ed9	125	static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
1da177e4	126	{
0c392ed9 EM	127	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
	128	uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
	129
	130	switch (mode) {
1da177e4	131	case PMM_NPS_MODE:
0c392ed9	132	uhcrhda \|= RH_A_NPS;
dd9048af	133	break;
1da177e4	134	case PMM_GLOBAL_MODE:
0c392ed9	135	uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
1da177e4 LT	136	break;
1da177e4 LT	137	case PMM_PERPORT_MODE:
0c392ed9 EM	138	uhcrhda &= ~(RH_A_NPS);
0c392ed9 EM	139	uhcrhda \|= RH_A_PSM;
1da177e4 LT	140
1da177e4 LT	141	/* Set port power control mask bits, only 3 ports. */
0c392ed9	142	uhcrhdb \|= (0x7<<17);
1da177e4 LT	143	break;
	144	default:
	145	printk( KERN_ERR
dd9048af	146	"Invalid mode %d, set to non-power switch mode.\n",
1da177e4 LT	147	mode );
1da177e4 LT	148
0c392ed9	149	uhcrhda \|= RH_A_NPS;
1da177e4 LT	150	}
1da177e4 LT	151
0c392ed9 EM	152	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
0c392ed9 EM	153	__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
1da177e4 LT	154	return 0;
	155	}
	156
1da177e4 LT	157	extern int usb_disabled(void);
	158
	159	/-------------------------------------------------------------------------/
	160
0c392ed9 EM	161	static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
0c392ed9 EM	162	struct pxaohci_platform_data *inf)
097b5334	163	{
0c392ed9 EM	164	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
0c392ed9 EM	165	uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
097b5334 EM	166
	167	if (inf->flags & ENABLE_PORT1)
	168	uhchr &= ~UHCHR_SSEP1;
	169
	170	if (inf->flags & ENABLE_PORT2)
	171	uhchr &= ~UHCHR_SSEP2;
	172
	173	if (inf->flags & ENABLE_PORT3)
	174	uhchr &= ~UHCHR_SSEP3;
	175
	176	if (inf->flags & POWER_CONTROL_LOW)
	177	uhchr \|= UHCHR_PCPL;
	178
	179	if (inf->flags & POWER_SENSE_LOW)
	180	uhchr \|= UHCHR_PSPL;
	181
	182	if (inf->flags & NO_OC_PROTECTION)
	183	uhcrhda \|= UHCRHDA_NOCP;
7b4361f0 AB	184	else
7b4361f0 AB	185	uhcrhda &= ~UHCRHDA_NOCP;
097b5334 EM	186
	187	if (inf->flags & OC_MODE_PERPORT)
	188	uhcrhda \|= UHCRHDA_OCPM;
7b4361f0 AB	189	else
7b4361f0 AB	190	uhcrhda &= ~UHCRHDA_OCPM;
097b5334 EM	191
	192	if (inf->power_on_delay) {
	193	uhcrhda &= ~UHCRHDA_POTPGT(0xff);
	194	uhcrhda \|= UHCRHDA_POTPGT(inf->power_on_delay / 2);
	195	}
	196
0c392ed9 EM	197	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	198	__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
	199	}
	200
	201	static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
	202	{
	203	uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
	204
	205	__raw_writel(uhchr \| UHCHR_FHR, ohci->mmio_base + UHCHR);
	206	udelay(11);
	207	__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
097b5334 EM	208	}
097b5334 EM	209
59376cc3	210	#ifdef CONFIG_PXA27x
0cb0b0d3 EM	211	extern void pxa27x_clear_otgph(void);
	212	#else
	213	#define pxa27x_clear_otgph() do {} while (0)
	214	#endif
	215
0c392ed9	216	static int pxa27x_start_hc(struct pxa27x_ohci ohci, struct device dev)
1da177e4	217	{
81f280e2 RP	218	int retval = 0;
81f280e2 RP	219	struct pxaohci_platform_data *inf;
0c392ed9	220	uint32_t uhchr;
81f280e2 RP	221
	222	inf = dev->platform_data;
	223
4bf34b8c	224	clk_prepare_enable(ohci->clk);
1da177e4	225
0c392ed9	226	pxa27x_reset_hc(ohci);
1da177e4	227
0c392ed9 EM	228	uhchr = __raw_readl(ohci->mmio_base + UHCHR) \| UHCHR_FSBIR;
	229	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	230
	231	while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
1da177e4 LT	232	cpu_relax();
1da177e4 LT	233
0c392ed9	234	pxa27x_setup_hc(ohci, inf);
097b5334	235
81f280e2 RP	236	if (inf->init)
81f280e2 RP	237	retval = inf->init(dev);
155faf5e	238
81f280e2 RP	239	if (retval < 0)
81f280e2 RP	240	return retval;
1da177e4	241
6dc3ae84 IG	242	if (cpu_is_pxa3xx())
	243	pxa3xx_u2d_start_hc(&ohci_to_hcd(&ohci->ohci)->self);
	244
0c392ed9 EM	245	uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
	246	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
	247	__raw_writel(UHCHIE_UPRIE \| UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
155faf5e DB	248
155faf5e DB	249	/* Clear any OTG Pin Hold */
0cb0b0d3	250	pxa27x_clear_otgph();
81f280e2	251	return 0;
1da177e4 LT	252	}
1da177e4 LT	253
0c392ed9	254	static void pxa27x_stop_hc(struct pxa27x_ohci ohci, struct device dev)
1da177e4	255	{
81f280e2	256	struct pxaohci_platform_data *inf;
0c392ed9	257	uint32_t uhccoms;
81f280e2 RP	258
	259	inf = dev->platform_data;
	260
6dc3ae84 IG	261	if (cpu_is_pxa3xx())
	262	pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);
	263
81f280e2 RP	264	if (inf->exit)
	265	inf->exit(dev);
	266
0c392ed9	267	pxa27x_reset_hc(ohci);
1da177e4	268
0c392ed9 EM	269	/* Host Controller Reset */
	270	uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) \| 0x01;
	271	__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
1da177e4 LT	272	udelay(10);
1da177e4 LT	273
4bf34b8c	274	clk_disable_unprepare(ohci->clk);
1da177e4 LT	275	}
1da177e4 LT	276
1139b451 DM	277	#ifdef CONFIG_OF
	278	static const struct of_device_id pxa_ohci_dt_ids[] = {
	279	{ .compatible = "marvell,pxa-ohci" },
	280	{ }
	281	};
	282
	283	MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
	284
	285	static u64 pxa_ohci_dma_mask = DMA_BIT_MASK(32);
	286
41ac7b3a	287	static int ohci_pxa_of_init(struct platform_device *pdev)
1139b451 DM	288	{
	289	struct device_node *np = pdev->dev.of_node;
	290	struct pxaohci_platform_data *pdata;
	291	u32 tmp;
	292
	293	if (!np)
	294	return 0;
	295
	296	/* Right now device-tree probed devices don't get dma_mask set.
	297	* Since shared usb code relies on it, set it here for now.
	298	* Once we have dma capability bindings this can go away.
	299	*/
	300	if (!pdev->dev.dma_mask)
	301	pdev->dev.dma_mask = &pxa_ohci_dma_mask;
	302
	303	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	304	if (!pdata)
	305	return -ENOMEM;
	306
	307	if (of_get_property(np, "marvell,enable-port1", NULL))
	308	pdata->flags \|= ENABLE_PORT1;
	309	if (of_get_property(np, "marvell,enable-port2", NULL))
	310	pdata->flags \|= ENABLE_PORT2;
	311	if (of_get_property(np, "marvell,enable-port3", NULL))
	312	pdata->flags \|= ENABLE_PORT3;
	313	if (of_get_property(np, "marvell,port-sense-low", NULL))
	314	pdata->flags \|= POWER_SENSE_LOW;
	315	if (of_get_property(np, "marvell,power-control-low", NULL))
	316	pdata->flags \|= POWER_CONTROL_LOW;
	317	if (of_get_property(np, "marvell,no-oc-protection", NULL))
	318	pdata->flags \|= NO_OC_PROTECTION;
	319	if (of_get_property(np, "marvell,oc-mode-perport", NULL))
	320	pdata->flags \|= OC_MODE_PERPORT;
	321	if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
	322	pdata->power_on_delay = tmp;
	323	if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
	324	pdata->port_mode = tmp;
	325	if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
	326	pdata->power_budget = tmp;
	327
	328	pdev->dev.platform_data = pdata;
	329
	330	return 0;
	331	}
	332	#else
41ac7b3a	333	static int ohci_pxa_of_init(struct platform_device *pdev)
1139b451 DM	334	{
	335	return 0;
	336	}
	337	#endif
1da177e4 LT	338
	339	/-------------------------------------------------------------------------/
	340
	341	/* configure so an HC device and id are always provided */
	342	/* always called with process context; sleeping is OK */
	343
	344
	345	/**
	346	* usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
	347	* Context: !in_interrupt()
	348	*
	349	* Allocates basic resources for this USB host controller, and
	350	* then invokes the start() method for the HCD associated with it
	351	* through the hotplug entry's driver_data.
	352	*
	353	*/
81f280e2	354	int usb_hcd_pxa27x_probe (const struct hc_driver driver, struct platform_device pdev)
1da177e4	355	{
84bab739	356	int retval, irq;
1da177e4	357	struct usb_hcd *hcd;
81f280e2	358	struct pxaohci_platform_data *inf;
0c392ed9	359	struct pxa27x_ohci *ohci;
84bab739	360	struct resource *r;
0c392ed9	361	struct clk *usb_clk;
81f280e2	362
1139b451 DM	363	retval = ohci_pxa_of_init(pdev);
	364	if (retval)
	365	return retval;
	366
81f280e2	367	inf = pdev->dev.platform_data;
1da177e4	368
81f280e2 RP	369	if (!inf)
	370	return -ENODEV;
	371
84bab739 EM	372	irq = platform_get_irq(pdev, 0);
	373	if (irq < 0) {
	374	pr_err("no resource of IORESOURCE_IRQ");
	375	return -ENXIO;
1da177e4 LT	376	}
1da177e4 LT	377
e0d8b13a	378	usb_clk = clk_get(&pdev->dev, NULL);
a8bcf410	379	if (IS_ERR(usb_clk))
	380	return PTR_ERR(usb_clk);
	381
81f280e2	382	hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
7febe2be JL	383	if (!hcd) {
	384	retval = -ENOMEM;
	385	goto err0;
	386	}
84bab739 EM	387
	388	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	389	if (!r) {
	390	pr_err("no resource of IORESOURCE_MEM");
	391	retval = -ENXIO;
	392	goto err1;
	393	}
	394
	395	hcd->rsrc_start = r->start;
	396	hcd->rsrc_len = resource_size(r);
1da177e4 LT	397
	398	if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
	399	pr_debug("request_mem_region failed");
	400	retval = -EBUSY;
	401	goto err1;
	402	}
	403
	404	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
	405	if (!hcd->regs) {
	406	pr_debug("ioremap failed");
	407	retval = -ENOMEM;
	408	goto err2;
	409	}
	410
0c392ed9 EM	411	/* initialize "struct pxa27x_ohci" */
	412	ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
	413	ohci->dev = &pdev->dev;
	414	ohci->clk = usb_clk;
	415	ohci->mmio_base = (void __iomem *)hcd->regs;
	416
	417	if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
81f280e2 RP	418	pr_debug("pxa27x_start_hc failed");
	419	goto err3;
	420	}
1da177e4 LT	421
1da177e4 LT	422	/* Select Power Management Mode */
0c392ed9	423	pxa27x_ohci_select_pmm(ohci, inf->port_mode);
1da177e4	424
0c27c5d5 RP	425	if (inf->power_budget)
	426	hcd->power_budget = inf->power_budget;
	427
1da177e4 LT	428	ohci_hcd_init(hcd_to_ohci(hcd));
1da177e4 LT	429
b5dd18d8	430	retval = usb_add_hcd(hcd, irq, 0);
1da177e4 LT	431	if (retval == 0)
	432	return retval;
	433
0c392ed9	434	pxa27x_stop_hc(ohci, &pdev->dev);
81f280e2	435	err3:
1da177e4 LT	436	iounmap(hcd->regs);
	437	err2:
	438	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	439	err1:
	440	usb_put_hcd(hcd);
7febe2be	441	err0:
a8bcf410	442	clk_put(usb_clk);
1da177e4 LT	443	return retval;
	444	}
	445
	446
	447	/* may be called without controller electrically present */
	448	/* may be called with controller, bus, and devices active */
	449
	450	/**
	451	* usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
	452	* @dev: USB Host Controller being removed
	453	* Context: !in_interrupt()
	454	*
	455	* Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
	456	* the HCD's stop() method. It is always called from a thread
	457	* context, normally "rmmod", "apmd", or something similar.
	458	*
	459	*/
81f280e2	460	void usb_hcd_pxa27x_remove (struct usb_hcd hcd, struct platform_device pdev)
1da177e4	461	{
0c392ed9 EM	462	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
0c392ed9 EM	463
1da177e4	464	usb_remove_hcd(hcd);
0c392ed9	465	pxa27x_stop_hc(ohci, &pdev->dev);
1da177e4 LT	466	iounmap(hcd->regs);
	467	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
	468	usb_put_hcd(hcd);
0c392ed9	469	clk_put(ohci->clk);
1da177e4 LT	470	}
	471
	472	/-------------------------------------------------------------------------/
	473
41ac7b3a	474	static int
1da177e4 LT	475	ohci_pxa27x_start (struct usb_hcd *hcd)
	476	{
	477	struct ohci_hcd *ohci = hcd_to_ohci (hcd);
	478	int ret;
	479
	480	ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
	481
fdd13b36 DB	482	/* The value of NDP in roothub_a is incorrect on this hardware */
	483	ohci->num_ports = 3;
	484
1da177e4 LT	485	if ((ret = ohci_init(ohci)) < 0)
	486	return ret;
	487
	488	if ((ret = ohci_run (ohci)) < 0) {
ade749a6 PG	489	dev_err(hcd->self.controller, "can't start %s",
ade749a6 PG	490	hcd->self.bus_name);
1da177e4 LT	491	ohci_stop (hcd);
	492	return ret;
	493	}
	494
	495	return 0;
	496	}
	497
	498	/-------------------------------------------------------------------------/
	499
	500	static const struct hc_driver ohci_pxa27x_hc_driver = {
	501	.description = hcd_name,
	502	.product_desc = "PXA27x OHCI",
0c392ed9	503	.hcd_priv_size = sizeof(struct pxa27x_ohci),
1da177e4 LT	504
	505	/*
	506	* generic hardware linkage
	507	*/
	508	.irq = ohci_irq,
	509	.flags = HCD_USB11 \| HCD_MEMORY,
	510
	511	/*
	512	* basic lifecycle operations
	513	*/
	514	.start = ohci_pxa27x_start,
	515	.stop = ohci_stop,
dd9048af	516	.shutdown = ohci_shutdown,
1da177e4 LT	517
	518	/*
	519	* managing i/o requests and associated device resources
	520	*/
	521	.urb_enqueue = ohci_urb_enqueue,
	522	.urb_dequeue = ohci_urb_dequeue,
	523	.endpoint_disable = ohci_endpoint_disable,
	524
	525	/*
	526	* scheduling support
	527	*/
	528	.get_frame_number = ohci_get_frame,
	529
	530	/*
	531	* root hub support
	532	*/
	533	.hub_status_data = ohci_hub_status_data,
	534	.hub_control = ohci_hub_control,
8ad7fe16	535	#ifdef CONFIG_PM
0c0382e3 AS	536	.bus_suspend = ohci_bus_suspend,
0c0382e3 AS	537	.bus_resume = ohci_bus_resume,
1da177e4	538	#endif
9293677a	539	.start_port_reset = ohci_start_port_reset,
1da177e4 LT	540	};
	541
	542	/-------------------------------------------------------------------------/
	543
3ae5eaec	544	static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
1da177e4	545	{
1da177e4 LT	546	pr_debug ("In ohci_hcd_pxa27x_drv_probe");
	547
	548	if (usb_disabled())
	549	return -ENODEV;
	550
81f280e2	551	return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
1da177e4 LT	552	}
1da177e4 LT	553
3ae5eaec	554	static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
1da177e4	555	{
3ae5eaec	556	struct usb_hcd *hcd = platform_get_drvdata(pdev);
1da177e4 LT	557
1da177e4 LT	558	usb_hcd_pxa27x_remove(hcd, pdev);
a5e36d20	559	platform_set_drvdata(pdev, NULL);
1da177e4 LT	560	return 0;
	561	}
	562
b7f3f59b MR	563	#ifdef CONFIG_PM
b7f3f59b MR	564	static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
1da177e4	565	{
b7f3f59b	566	struct usb_hcd *hcd = dev_get_drvdata(dev);
0c392ed9	567	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
2e1dcc16	568
0c392ed9	569	if (time_before(jiffies, ohci->ohci.next_statechange))
2e1dcc16	570	msleep(5);
0c392ed9	571	ohci->ohci.next_statechange = jiffies;
2e1dcc16	572
b7f3f59b	573	pxa27x_stop_hc(ohci, dev);
1da177e4 LT	574	return 0;
	575	}
	576
b7f3f59b	577	static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
1da177e4	578	{
b7f3f59b	579	struct usb_hcd *hcd = dev_get_drvdata(dev);
0c392ed9	580	struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
a75d048e	581	struct pxaohci_platform_data *inf = dev->platform_data;
2e1dcc16 RP	582	int status;
2e1dcc16 RP	583
0c392ed9	584	if (time_before(jiffies, ohci->ohci.next_statechange))
2e1dcc16	585	msleep(5);
0c392ed9	586	ohci->ohci.next_statechange = jiffies;
2e1dcc16	587
b7f3f59b	588	if ((status = pxa27x_start_hc(ohci, dev)) < 0)
2e1dcc16 RP	589	return status;
2e1dcc16 RP	590
a75d048e AB	591	/* Select Power Management Mode */
	592	pxa27x_ohci_select_pmm(ohci, inf->port_mode);
	593
cfa49b4b	594	ohci_resume(hcd, false);
1da177e4 LT	595	return 0;
1da177e4 LT	596	}
b7f3f59b	597
47145210	598	static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
b7f3f59b MR	599	.suspend = ohci_hcd_pxa27x_drv_suspend,
	600	.resume = ohci_hcd_pxa27x_drv_resume,
	601	};
2e1dcc16	602	#endif
1da177e4	603
f4fce61d KS	604	/* work with hotplug and coldplug */
f4fce61d KS	605	MODULE_ALIAS("platform:pxa27x-ohci");
1da177e4	606
3ae5eaec	607	static struct platform_driver ohci_hcd_pxa27x_driver = {
1da177e4 LT	608	.probe = ohci_hcd_pxa27x_drv_probe,
1da177e4 LT	609	.remove = ohci_hcd_pxa27x_drv_remove,
dd9048af	610	.shutdown = usb_hcd_platform_shutdown,
3ae5eaec RK	611	.driver = {
3ae5eaec RK	612	.name = "pxa27x-ohci",
f4fce61d	613	.owner = THIS_MODULE,
1139b451	614	.of_match_table = of_match_ptr(pxa_ohci_dt_ids),
b7f3f59b MR	615	#ifdef CONFIG_PM
	616	.pm = &ohci_hcd_pxa27x_pm_ops,
	617	#endif
3ae5eaec	618	},
1da177e4 LT	619	};
1da177e4 LT	620